From 3ab89d5be73b4c52336f3ea349e4314dbbe01def Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Tue, 25 Feb 2025 13:03:25 +0100
Subject: [PATCH] Add used language to `--preproc-resolve` output (#5795)

---
 src/V3PreShell.cpp                          | 2 +-
 test_regress/t/t_preproc_resolve.out        | 5 +++++
 test_regress/t/t_preproc_resolve.py         | 4 +++-
 test_regress/t/t_preproc_resolve_config.vlt | 8 ++++++++
 4 files changed, 17 insertions(+), 2 deletions(-)
 create mode 100644 test_regress/t/t_preproc_resolve_config.vlt

diff --git a/src/V3PreShell.cpp b/src/V3PreShell.cpp
index 6655c0786..c93c74371 100644
--- a/src/V3PreShell.cpp
+++ b/src/V3PreShell.cpp
@@ -95,7 +95,7 @@ protected:
         if (modfilename.empty()) return false;
 
         // Set language standard up front
-        if (!v3Global.opt.preprocOnly()) {
+        if (!v3Global.opt.preprocOnly() || v3Global.opt.preprocResolve()) {
             // Letting lex parse this saves us from having to specially en/decode
             // from the V3LangCode to the various Lex BEGIN states. The language
             // of this source file is updated here, in case there have been any
diff --git a/test_regress/t/t_preproc_resolve.out b/test_regress/t/t_preproc_resolve.out
index 7f76f5919..ca8171e87 100644
--- a/test_regress/t/t_preproc_resolve.out
+++ b/test_regress/t/t_preproc_resolve.out
@@ -1,3 +1,7 @@
+`begin_keywords "1800-2023"
+`verilator_config
+lint_off -rule NONSTD
+`begin_keywords "1800-2023"
 `timescale 1ns/1ps
 module top( 
    input logic clk,
@@ -10,6 +14,7 @@ module top(
       .out_signal(top_out)
    );
 endmodule
+`begin_keywords "1800-2023"
 `timescale 1ns/1ps
 module submod( 
    input logic clk,
diff --git a/test_regress/t/t_preproc_resolve.py b/test_regress/t/t_preproc_resolve.py
index d6f95780f..8cc950b99 100755
--- a/test_regress/t/t_preproc_resolve.py
+++ b/test_regress/t/t_preproc_resolve.py
@@ -16,7 +16,9 @@ stdout_filename = os.path.join(test.obj_dir, test.name + ".out")
 test.compile(
     # Override default flags
     v_flags=[''],
-    verilator_flags=["-E -P --preproc-resolve -y t/t_preproc_resolve"],
+    verilator_flags=[
+        "-E -P --preproc-resolve t/t_preproc_resolve_config.vlt -y t/t_preproc_resolve"
+    ],
     verilator_flags2=[''],
     verilator_flags3=[''],
     verilator_make_gmake=False,
diff --git a/test_regress/t/t_preproc_resolve_config.vlt b/test_regress/t/t_preproc_resolve_config.vlt
new file mode 100644
index 000000000..ed2310c9b
--- /dev/null
+++ b/test_regress/t/t_preproc_resolve_config.vlt
@@ -0,0 +1,8 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+`verilator_config
+lint_off -rule NONSTD