diff --git a/Changes b/Changes
index 40e5d200d..f112d1d1b 100644
--- a/Changes
+++ b/Changes
@@ -35,6 +35,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix number parsing with newline after radix, bug1340. [George Cuan]
 
+****  Fix string ?: conditional type resolution, bug1345. [Iztok Jeras]
+
 
 * Verilator 3.926 2018-08-22
 
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 97caa4cbb..addafab35 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -358,6 +358,8 @@ private:
 	    //  the expression includes the size of the output too.
 	    if (nodep->expr1p()->isDouble() || nodep->expr2p()->isDouble()) {
 		nodep->dtypeSetDouble();
+            } else if (nodep->expr1p()->isString() || nodep->expr2p()->isString()) {
+                nodep->dtypeSetString();
 	    } else {
                 int width  = std::max(nodep->expr1p()->width(),    nodep->expr2p()->width());
                 int mwidth = std::max(nodep->expr1p()->widthMin(), nodep->expr2p()->widthMin());
diff --git a/test_regress/t/t_trace_string.v b/test_regress/t/t_trace_string.v
index c72b05099..9f3fb8d83 100644
--- a/test_regress/t/t_trace_string.v
+++ b/test_regress/t/t_trace_string.v
@@ -3,7 +3,12 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2018 by Wilson Snyder.
 
-module t (/*AUTOARG*/);
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
 
    localparam string SVEC [0:7] = '{"zero", "one", "two", "three", "four", "five", "six", "seven"};
 
@@ -13,4 +18,28 @@ module t (/*AUTOARG*/);
       $finish;
    end
 
+   localparam string REGX [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
+                                      "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"};
+
+   function string regx (logic [5-1:0] r, bit abi=1'b0);
+      regx = abi ? REGX[r] : $sformatf("x%0d", r);
+   endfunction: regx
+
+   function string dis32 (logic [32-1:0] op);
+      casez (op)
+        32'b0000_0000_0000_0000_0000_0000_0001_0011: dis32 = $sformatf("nop");
+        32'b0000_0000_0000_0000_0100_0000_0011_0011: dis32 = $sformatf("-");
+        32'b????_????_????_????_?000_????_?110_0111: dis32 = $sformatf("jalr  %s, 0x%03x (%s)",
+                                                                       regx(op[5-1:0]), op[16-1:0], regx(op[5-1:0]));
+        default: dis32 = "illegal";
+      endcase
+   endfunction: dis32
+
+   always @(posedge clk) begin
+      for (int unsigned i=0; i<32; i++)
+        $display("REGX: %s", regx(i[4:0]));
+      $display("OP: %s", dis32(32'h00000000));
+      $finish();
+   end
+
 endmodule