diff --git a/Changes b/Changes
index 1757bb35b..d2038fcde 100644
--- a/Changes
+++ b/Changes
@@ -28,6 +28,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix wide array indices causing compile error.
 
+****  Better optimize Shift-And constructs.
+
 
 * Verilator 3.910 2017-09-07
 
diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 73d4043db..dc5862205 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -341,6 +341,33 @@ private:
 	replaceWChild(nodep, bip); VL_DANGLING(nodep);
 	return true;
     }
+    bool operandSelShiftLower(AstSel* nodep) {
+	// AND({a}, SHIFTR({b}, {c})) is often shorthand in C for Verilog {b}[{c} :+ {a}]
+	// becomes thought other optimizations
+	// SEL(SHIFTR({a},{b}),{lsb},{width}) -> SEL({a},{lsb+b},{width})
+	AstShiftR* shiftp = nodep->fromp()->castShiftR();
+	if (!(m_doV
+	      && shiftp
+	      && shiftp->rhsp()->castConst()
+	      && nodep->lsbp()->castConst()
+	      && nodep->widthp()->castConst()
+		)) return false;
+	AstNode* ap = shiftp->lhsp();
+	AstConst* bp = shiftp->rhsp()->castConst();
+	AstConst* lp = nodep->lsbp()->castConst();
+	if (bp->isWide() || bp->num().isFourState() || bp->num().isNegative()
+	    || lp->isWide() || lp->num().isFourState() || lp->num().isNegative()) return false;
+	int newLsb = lp->toSInt() + bp->toSInt();
+	if (newLsb + nodep->widthConst() > ap->width()) return false;
+	//
+	UINFO(9, "SEL(SHIFTR(a,b),l,w) -> SEL(a,l+b,w)\n");
+	if (debug()>=9) nodep->dumpTree(cout,"SEL(SH)-in:");
+	AstSel* newp = new AstSel(nodep->fileline(), ap->unlinkFrBack(), newLsb, nodep->widthConst());
+	newp->dtypeFrom(nodep);
+	if (debug()>=9) newp->dumpTree(cout,"SEL(SH)-ou:");
+	nodep->replaceWith(newp); VL_DANGLING(nodep);
+	return true;
+    }
 
     bool operandBiExtendConst(AstNodeBiop* nodep) {
 	// Loop unrolling favors standalone compares
@@ -2252,6 +2279,7 @@ private:
     TREEOPV("AstSel{$fromp.castSub, operandSelBiLower(nodep)}",	"DONE");
     TREEOPV("AstSel{$fromp.castXnor,operandSelBiLower(nodep)}",	"DONE");
     TREEOPV("AstSel{$fromp.castXor, operandSelBiLower(nodep)}",	"DONE");
+    TREEOPV("AstSel{$fromp.castShiftR, operandSelShiftLower(nodep)}",	"DONE");
     TREEOPC("AstSel{$fromp.castConst, $lsbp.castConst, $widthp.castConst, }",	"replaceConst(nodep)");
     TREEOPV("AstSel{$fromp.castConcat, $lsbp.castConst, $widthp.castConst, }",	"replaceSelConcat(nodep)");
     TREEOPV("AstSel{$fromp.castReplicate, $lsbp.castConst, $widthp.isOne, }",	"replaceSelReplicate(nodep)");
diff --git a/test_regress/t/t_math_shift_sel.pl b/test_regress/t/t_math_shift_sel.pl
new file mode 100755
index 000000000..f91289753
--- /dev/null
+++ b/test_regress/t/t_math_shift_sel.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_math_shift_sel.v b/test_regress/t/t_math_shift_sel.v
new file mode 100644
index 000000000..ecb39172f
--- /dev/null
+++ b/test_regress/t/t_math_shift_sel.v
@@ -0,0 +1,87 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [106:0]  in = {~crc[42:0], crc[63:0]};
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [7:0]		out1;			// From test of Test.v
+   wire [7:0]		out2;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out1			(out1[7:0]),
+	      .out2			(out2[7:0]),
+	      // Inputs
+	      .in			(in[106:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {48'h0, out1, out1};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= '0;
+      end
+      else if (cyc<10) begin
+	 sum <= '0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'hc746017202a24ecc
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out1, out2,
+   // Inputs
+   in
+   );
+
+   // Replace this module with the device under test.
+   //
+   // Change the code in the t module to apply values to the inputs and
+   // merge the output values into the result vector.
+
+   input [106:0]    in;
+   output [7:0]     out1, out2;
+
+   // verilator lint_off WIDTH
+   // Better written as onibble[99 +: 8]. Verilator will convert it.
+   wire [7:0] 	    out1 = (in >>> 99) & 255;
+   // verilator lint_on WIDTH
+   wire [7:0] 	    out2 = in[106:99];
+
+endmodule