diff --git a/test_regress/t/t_trace_saif_sc.out b/test_regress/t/t_trace_saif_sc.out new file mode 100755 index 000000000..e3e1d5179 --- /dev/null +++ b/test_regress/t/t_trace_saif_sc.out @@ -0,0 +1,82 @@ +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(DESIGN "t") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 1004) +(INSTANCE top + (INSTANCE t + (NET + (clk (T0 505) (T1 499) (TX 0) (TC 199)) + (cyc\[0\] (T0 504) (T1 500) (TX 0) (TC 100)) + (cyc\[1\] (T0 504) (T1 500) (TX 0) (TC 50)) + (cyc\[2\] (T0 520) (T1 484) (TX 0) (TC 25)) + (cyc\[3\] (T0 524) (T1 480) (TX 0) (TC 12)) + (cyc\[4\] (T0 524) (T1 480) (TX 0) (TC 6)) + (cyc\[5\] (T0 640) (T1 364) (TX 0) (TC 3)) + (cyc\[6\] (T0 640) (T1 364) (TX 0) (TC 1)) + (rstn (T0 110) (T1 894) (TX 0) (TC 1)) + (fst_parameter\[0\] (T0 0) (T1 1004) (TX 0) (TC 1)) + (fst_parameter\[1\] (T0 0) (T1 1004) (TX 0) (TC 1)) + (fst_parameter\[3\] (T0 0) (T1 1004) (TX 0) (TC 1)) + (fst_parameter\[4\] (T0 0) (T1 1004) (TX 0) (TC 1)) + (fst_parameter\[5\] (T0 0) (T1 1004) (TX 0) (TC 1)) + (fst_parameter\[6\] (T0 0) (T1 1004) (TX 0) (TC 1)) + (fst_lparam\[3\] (T0 0) (T1 1004) (TX 0) (TC 1)) + (fst_lparam\[6\] (T0 0) (T1 1004) (TX 0) (TC 1)) + (fst_lparam\[7\] (T0 0) (T1 1004) (TX 0) (TC 1)) + (fst_lparam\[8\] (T0 0) (T1 1004) (TX 0) (TC 1)) + (fst_supply1 (T0 0) (T1 1004) (TX 0) (TC 1)) + (fst_tri1 (T0 0) (T1 1004) (TX 0) (TC 1)) + (state\[0\] (T0 414) (T1 590) (TX 0) (TC 46)) + (state\[1\] (T0 540) (T1 464) (TX 0) (TC 45)) + (state\[2\] (T0 534) (T1 470) (TX 0) (TC 46)) + (state\[3\] (T0 544) (T1 460) (TX 0) (TC 44)) + (state\[4\] (T0 540) (T1 464) (TX 0) (TC 45)) + ) + (INSTANCE test + (NET + (clk (T0 505) (T1 499) (TX 0) (TC 199)) + (rstn (T0 110) (T1 894) (TX 0) (TC 1)) + (state\[0\] (T0 414) (T1 590) (TX 0) (TC 46)) + (state\[1\] (T0 540) (T1 464) (TX 0) (TC 45)) + (state\[2\] (T0 534) (T1 470) (TX 0) (TC 46)) + (state\[3\] (T0 544) (T1 460) (TX 0) (TC 44)) + (state\[4\] (T0 540) (T1 464) (TX 0) (TC 45)) + (state_w\[0\] (T0 534) (T1 470) (TX 0) (TC 46)) + (state_w\[1\] (T0 534) (T1 470) (TX 0) (TC 46)) + (state_w\[2\] (T0 434) (T1 570) (TX 0) (TC 46)) + (state_w\[3\] (T0 530) (T1 474) (TX 0) (TC 47)) + (state_w\[4\] (T0 424) (T1 580) (TX 0) (TC 48)) + (state_array[0]\[0\] (T0 414) (T1 590) (TX 0) (TC 46)) + (state_array[0]\[1\] (T0 540) (T1 464) (TX 0) (TC 45)) + (state_array[0]\[2\] (T0 534) (T1 470) (TX 0) (TC 46)) + (state_array[0]\[3\] (T0 544) (T1 460) (TX 0) (TC 44)) + (state_array[0]\[4\] (T0 540) (T1 464) (TX 0) (TC 45)) + (state_array[1]\[0\] (T0 420) (T1 584) (TX 0) (TC 47)) + (state_array[1]\[1\] (T0 534) (T1 470) (TX 0) (TC 46)) + (state_array[1]\[2\] (T0 534) (T1 470) (TX 0) (TC 46)) + (state_array[1]\[3\] (T0 540) (T1 464) (TX 0) (TC 45)) + (state_array[1]\[4\] (T0 534) (T1 470) (TX 0) (TC 46)) + (state_array[2]\[0\] (T0 424) (T1 580) (TX 0) (TC 48)) + (state_array[2]\[1\] (T0 534) (T1 470) (TX 0) (TC 46)) + (state_array[2]\[2\] (T0 534) (T1 470) (TX 0) (TC 46)) + (state_array[2]\[3\] (T0 534) (T1 470) (TX 0) (TC 46)) + (state_array[2]\[4\] (T0 530) (T1 474) (TX 0) (TC 47)) + ) + (INSTANCE unnamedblk1 + (NET + (i\[0\] (T0 10) (T1 994) (TX 0) (TC 1)) + (i\[1\] (T0 10) (T1 994) (TX 0) (TC 1)) + ) + ) + (INSTANCE unnamedblk2 + (NET + (i\[1\] (T0 120) (T1 884) (TX 0) (TC 1)) + ) + ) + ) + ) +) +) diff --git a/test_regress/t/t_trace_saif_sc.py b/test_regress/t/t_trace_saif_sc.py new file mode 100755 index 000000000..d8ff6413a --- /dev/null +++ b/test_regress/t/t_trace_saif_sc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=["--trace-saif --sc"]) + +test.execute() + +test.saif_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_saif_sc.v b/test_regress/t/t_trace_saif_sc.v new file mode 100644 index 000000000..52c148bd5 --- /dev/null +++ b/test_regress/t/t_trace_saif_sc.v @@ -0,0 +1,98 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + int cyc; + reg rstn; + + parameter real fst_gparam_real = 1.23; + localparam real fst_lparam_real = 4.56; + real fst_real = 1.23; + integer fst_integer; + bit fst_bit; + logic fst_logic; + int fst_int; + shortint fst_shortint; + longint fst_longint; + byte fst_byte; + + parameter fst_parameter = 123; + localparam fst_lparam = 456; + supply0 fst_supply0; + supply1 fst_supply1; + tri0 fst_tri0; + tri1 fst_tri1; + tri fst_tri; + wire fst_wire; + + logic [4:0] state; + + Test test (/*AUTOINST*/ + // Outputs + .state (state[4:0]), + // Inputs + .clk (clk), + .rstn (rstn)); + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + rstn <= ~'1; + end + else if (cyc<10) begin + rstn <= ~'1; + end + else if (cyc<90) begin + rstn <= ~'0; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + + +module Test ( + input clk, + input rstn, + output logic [4:0] state + ); + + logic [4:0] state_w; + logic [4:0] state_array [3]; + assign state = state_array[0]; + + always_comb begin + state_w[4] = state_array[2][0]; + state_w[3] = state_array[2][4]; + state_w[2] = state_array[2][3] ^ state_array[2][0]; + state_w[1] = state_array[2][2]; + state_w[0] = state_array[2][1]; + end + + always_ff @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 3; i++) + state_array[i] <= 'b1; + end + else begin + for (int i = 0; i < 2; i++) + state_array[i] <= state_array[i+1]; + state_array[2] <= state_w; + end + end + +endmodule