diff --git a/src/V3Number.cpp b/src/V3Number.cpp index f172e0001..dd7b662f4 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -139,6 +139,7 @@ V3Number::V3Number (FileLine* fileline, const char* sourcep) { this->opAdd(product,addend); if (product.bitsValue(width(), 4)) { // Overflowed m_fileline->v3error("Too many digits for "<v3error("As that number was unsized ('d...) it is limited to 32 bits (IEEE 2012 5.7.1)"); while (*(cp+1)) cp++; // Skip ahead so don't get multiple warnings } } diff --git a/test_regress/t/t_lint_unsized_bad.pl b/test_regress/t/t_lint_unsized_bad.pl new file mode 100755 index 000000000..cd621a77e --- /dev/null +++ b/test_regress/t/t_lint_unsized_bad.pl @@ -0,0 +1,25 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->{vlt} or $Self->skip("Verilator only test"); + +compile ( + v_flags2 => ["--lint-only"], + fails=>1, + verilator_make_gcc => 0, + make_top_shell => 0, + make_main => 0, + expect=> quotemeta( +qq{%Error: t/t_lint_unsized_bad.v:7: Too many digits for 32 bit number: 'd123456789123456789123456789 +%Error: t/t_lint_unsized_bad.v:7: As that number was unsized ('d...) it is limited to 32 bits (IEEE 2012 5.7.1) +}).'%Error: Exiting due to.*' + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_unsized_bad.v b/test_regress/t/t_lint_unsized_bad.v new file mode 100644 index 000000000..1157b47b9 --- /dev/null +++ b/test_regress/t/t_lint_unsized_bad.v @@ -0,0 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t; + bit [256:0] num = 'd123456789123456789123456789; +endmodule