diff --git a/test_regress/t/t_trace_dumpvars_dyn.cpp b/test_regress/t/t_trace_dumpvars_dyn.cpp
index 4123e95b7..b9f14a17f 100644
--- a/test_regress/t/t_trace_dumpvars_dyn.cpp
+++ b/test_regress/t/t_trace_dumpvars_dyn.cpp
@@ -15,6 +15,10 @@
 #include <verilated_vcd_c.h>
 #define TRACE_FILE_NAME "simx.vcd"
 #define TRACE_CLASS VerilatedVcdC
+#elif VM_TRACE_SAIF
+#include <verilated_saif_c.h>
+#define TRACE_FILE_NAME "simx.saif"
+#define TRACE_CLASS VerilatedSaifC
 #endif
 
 #include <memory>
@@ -35,9 +39,9 @@ int main(int argc, char** argv) {
 
     std::unique_ptr<TRACE_CLASS> tfp{new TRACE_CLASS};
 
-#if defined(T_TRACE_DUMPVARS_DYN_VCD_0) || defined(T_TRACE_DUMPVARS_DYN_FST_0)
+#if defined(T_TRACE_DUMPVARS_DYN_VCD_0) || defined(T_TRACE_DUMPVARS_DYN_FST_0) || defined(T_TRACE_DUMPVARS_DYN_SAIF_0)
     tfp->dumpvars(0, "");
-#elif defined(T_TRACE_DUMPVARS_DYN_VCD_1) || defined(T_TRACE_DUMPVARS_DYN_FST_1)
+#elif defined(T_TRACE_DUMPVARS_DYN_VCD_1) || defined(T_TRACE_DUMPVARS_DYN_FST_1) || defined(T_TRACE_DUMPVARS_DYN_SAIF_1)
     tfp->dumpvars(99, "t");  // This should not match "top."
     tfp->dumpvars(1, "top.t.cyc");  // A signal
     tfp->dumpvars(1, "top.t.sub1a");  // Scope
diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_0.out b/test_regress/t/t_trace_dumpvars_dyn_saif_0.out
new file mode 100644
index 000000000..bca4d4c6e
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_dyn_saif_0.out
@@ -0,0 +1,150 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "t")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 20)
+(INSTANCE top
+  (NET
+    (clk (T0 10) (T1 10) (TX 0) (TC 20))
+  )
+  (INSTANCE t
+    (NET
+      (clk (T0 10) (T1 10) (TX 0) (TC 20))
+      (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+      (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+      (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+      (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+    )
+    (INSTANCE sub1a
+      (NET
+        (ADD\[1\] (T0 0) (T1 20) (TX 0) (TC 1))
+        (ADD\[3\] (T0 0) (T1 20) (TX 0) (TC 1))
+        (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+        (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+        (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+        (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+        (value\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+        (value\[1\] (T0 9) (T1 11) (TX 0) (TC 6))
+        (value\[2\] (T0 11) (T1 9) (TX 0) (TC 3))
+        (value\[3\] (T0 9) (T1 11) (TX 0) (TC 2))
+        (value\[4\] (T0 11) (T1 9) (TX 0) (TC 1))
+      )
+      (INSTANCE sub2a
+        (NET
+          (ADD\[0\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[1\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[3\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+          (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+          (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+          (value\[0\] (T0 10) (T1 10) (TX 0) (TC 11))
+          (value\[1\] (T0 11) (T1 9) (TX 0) (TC 6))
+          (value\[2\] (T0 9) (T1 11) (TX 0) (TC 3))
+          (value\[3\] (T0 11) (T1 9) (TX 0) (TC 2))
+          (value\[4\] (T0 9) (T1 11) (TX 0) (TC 1))
+        )
+      )
+      (INSTANCE sub2b
+        (NET
+          (ADD\[2\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[3\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+          (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+          (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+          (value\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (value\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+          (value\[2\] (T0 8) (T1 12) (TX 0) (TC 3))
+          (value\[3\] (T0 13) (T1 7) (TX 0) (TC 2))
+          (value\[4\] (T0 7) (T1 13) (TX 0) (TC 1))
+        )
+      )
+      (INSTANCE sub2c
+        (NET
+          (ADD\[0\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[2\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[3\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+          (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+          (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+          (value\[0\] (T0 10) (T1 10) (TX 0) (TC 11))
+          (value\[1\] (T0 9) (T1 11) (TX 0) (TC 5))
+          (value\[2\] (T0 8) (T1 12) (TX 0) (TC 3))
+          (value\[3\] (T0 15) (T1 5) (TX 0) (TC 2))
+          (value\[4\] (T0 5) (T1 15) (TX 0) (TC 1))
+        )
+      )
+    )
+    (INSTANCE sub1b
+      (NET
+        (ADD\[2\] (T0 0) (T1 20) (TX 0) (TC 1))
+        (ADD\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+        (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+        (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+        (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+        (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+        (value\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+        (value\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+        (value\[2\] (T0 8) (T1 12) (TX 0) (TC 3))
+        (value\[3\] (T0 7) (T1 13) (TX 0) (TC 1))
+        (value\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+      )
+      (INSTANCE sub2a
+        (NET
+          (ADD\[0\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[2\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+          (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+          (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+          (value\[0\] (T0 10) (T1 10) (TX 0) (TC 11))
+          (value\[1\] (T0 9) (T1 11) (TX 0) (TC 5))
+          (value\[2\] (T0 8) (T1 12) (TX 0) (TC 3))
+          (value\[3\] (T0 5) (T1 15) (TX 0) (TC 1))
+          (value\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+        )
+      )
+      (INSTANCE sub2b
+        (NET
+          (ADD\[1\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[2\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+          (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+          (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+          (value\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (value\[1\] (T0 9) (T1 11) (TX 0) (TC 6))
+          (value\[2\] (T0 9) (T1 11) (TX 0) (TC 4))
+          (value\[3\] (T0 4) (T1 16) (TX 0) (TC 2))
+          (value\[4\] (T0 1) (T1 19) (TX 0) (TC 2))
+          (value\[5\] (T0 19) (T1 1) (TX 0) (TC 1))
+        )
+      )
+      (INSTANCE sub2c
+        (NET
+          (ADD\[0\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[1\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[2\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+          (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+          (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+          (value\[0\] (T0 10) (T1 10) (TX 0) (TC 11))
+          (value\[1\] (T0 11) (T1 9) (TX 0) (TC 6))
+          (value\[2\] (T0 11) (T1 9) (TX 0) (TC 4))
+          (value\[3\] (T0 4) (T1 16) (TX 0) (TC 2))
+          (value\[4\] (T0 3) (T1 17) (TX 0) (TC 2))
+          (value\[5\] (T0 17) (T1 3) (TX 0) (TC 1))
+        )
+      )
+    )
+  )
+)
+)
diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_0.py b/test_regress/t/t_trace_dumpvars_dyn_saif_0.py
new file mode 100755
index 000000000..44835a822
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_dyn_saif_0.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.pli_filename = "t/t_trace_dumpvars_dyn.cpp"
+test.top_filename = "t/t_trace_dumpvars_dyn.v"
+
+test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_1.out b/test_regress/t/t_trace_dumpvars_dyn_saif_1.out
new file mode 100644
index 000000000..b66f98844
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_dyn_saif_1.out
@@ -0,0 +1,113 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "t")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 20)
+(INSTANCE top
+  (NET
+  )
+  (INSTANCE t
+    (NET
+      (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+      (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+      (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+      (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+    )
+    (INSTANCE sub1a
+      (NET
+        (ADD\[1\] (T0 0) (T1 20) (TX 0) (TC 1))
+        (ADD\[3\] (T0 0) (T1 20) (TX 0) (TC 1))
+        (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+        (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+        (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+        (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+        (value\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+        (value\[1\] (T0 9) (T1 11) (TX 0) (TC 6))
+        (value\[2\] (T0 11) (T1 9) (TX 0) (TC 3))
+        (value\[3\] (T0 9) (T1 11) (TX 0) (TC 2))
+        (value\[4\] (T0 11) (T1 9) (TX 0) (TC 1))
+      )
+      (INSTANCE sub2a
+        (NET
+        )
+      )
+      (INSTANCE sub2b
+        (NET
+        )
+      )
+      (INSTANCE sub2c
+        (NET
+        )
+      )
+    )
+    (INSTANCE sub1b
+      (NET
+        (ADD\[2\] (T0 0) (T1 20) (TX 0) (TC 1))
+        (ADD\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+        (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+        (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+        (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+        (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+        (value\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+        (value\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+        (value\[2\] (T0 8) (T1 12) (TX 0) (TC 3))
+        (value\[3\] (T0 7) (T1 13) (TX 0) (TC 1))
+        (value\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+      )
+      (INSTANCE sub2a
+        (NET
+          (ADD\[0\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[2\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+          (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+          (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+          (value\[0\] (T0 10) (T1 10) (TX 0) (TC 11))
+          (value\[1\] (T0 9) (T1 11) (TX 0) (TC 5))
+          (value\[2\] (T0 8) (T1 12) (TX 0) (TC 3))
+          (value\[3\] (T0 5) (T1 15) (TX 0) (TC 1))
+          (value\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+        )
+      )
+      (INSTANCE sub2b
+        (NET
+          (ADD\[1\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[2\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+          (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+          (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+          (value\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (value\[1\] (T0 9) (T1 11) (TX 0) (TC 6))
+          (value\[2\] (T0 9) (T1 11) (TX 0) (TC 4))
+          (value\[3\] (T0 4) (T1 16) (TX 0) (TC 2))
+          (value\[4\] (T0 1) (T1 19) (TX 0) (TC 2))
+          (value\[5\] (T0 19) (T1 1) (TX 0) (TC 1))
+        )
+      )
+      (INSTANCE sub2c
+        (NET
+          (ADD\[0\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[1\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[2\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (ADD\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+          (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+          (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+          (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+          (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+          (value\[0\] (T0 10) (T1 10) (TX 0) (TC 11))
+          (value\[1\] (T0 11) (T1 9) (TX 0) (TC 6))
+          (value\[2\] (T0 11) (T1 9) (TX 0) (TC 4))
+          (value\[3\] (T0 4) (T1 16) (TX 0) (TC 2))
+          (value\[4\] (T0 3) (T1 17) (TX 0) (TC 2))
+          (value\[5\] (T0 17) (T1 3) (TX 0) (TC 1))
+        )
+      )
+    )
+  )
+)
+)
diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_1.py b/test_regress/t/t_trace_dumpvars_dyn_saif_1.py
new file mode 100755
index 000000000..44835a822
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_dyn_saif_1.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.pli_filename = "t/t_trace_dumpvars_dyn.cpp"
+test.top_filename = "t/t_trace_dumpvars_dyn.v"
+
+test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()