diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp
index 288a576ec..e8ff6e06d 100644
--- a/src/V3EmitCMake.cpp
+++ b/src/V3EmitCMake.cpp
@@ -169,11 +169,6 @@ class CMakeEmitter final {
             global.emplace_back("${VERILATOR_ROOT}/include/" + v3Global.opt.traceSourceBase()
                                 + "_c.cpp");
             if (v3Global.opt.systemC()) {
-                if (v3Global.opt.traceFormat() != TraceFormat::VCD) {
-                    v3warn(E_UNSUPPORTED,
-                           "Unsupported: This trace format is not supported in SystemC, "
-                           "use VCD format.");
-                }
                 global.emplace_back("${VERILATOR_ROOT}/include/" + v3Global.opt.traceSourceLang()
                                     + ".cpp");
             }
diff --git a/test_regress/t/t_trace_fst_sc_cmake.out b/test_regress/t/t_trace_fst_sc_cmake.out
new file mode 100644
index 000000000..3fe026e70
--- /dev/null
+++ b/test_regress/t/t_trace_fst_sc_cmake.out
@@ -0,0 +1,1824 @@
+$date
+	Thu Apr  1 14:28:55 2021
+
+$end
+$version
+	fstWriter
+$end
+$timescale
+	1ps
+$end
+$scope module top $end
+$scope module t $end
+$var wire 1 ! clk $end
+$var int 32 " cyc $end
+$var logic 1 # rstn $end
+$var real_parameter 64 $ fst_gparam_real $end
+$var real_parameter 64 % fst_lparam_real $end
+$var real 64 $ fst_real $end
+$var integer 32 & fst_integer $end
+$var bit 1 ' fst_bit $end
+$var logic 1 ( fst_logic $end
+$var int 32 ) fst_int $end
+$var shortint 16 * fst_shortint $end
+$var longint 64 + fst_longint $end
+$var byte 8 , fst_byte $end
+$var parameter 32 - fst_parameter $end
+$var parameter 32 . fst_lparam $end
+$var supply0 1 / fst_supply0 $end
+$var supply1 1 0 fst_supply1 $end
+$var tri0 1 1 fst_tri0 $end
+$var tri1 1 2 fst_tri1 $end
+$var tri 1 3 fst_tri $end
+$var wire 1 4 fst_wire $end
+$var logic 5 5 state $end
+$scope module test $end
+$var wire 1 ! clk $end
+$var wire 1 # rstn $end
+$var wire 5 5 state $end
+$var logic 5 6 state_w $end
+$var logic 5 7 state_array(0) $end
+$var logic 5 8 state_array(1) $end
+$var logic 5 9 state_array(2) $end
+$scope module unnamedblk2 $end
+$var int 32 : i $end
+$upscope $end
+$scope module unnamedblk1 $end
+$var int 32 ; i $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
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diff --git a/test_regress/t/t_trace_fst_sc_cmake.pl b/test_regress/t/t_trace_fst_sc_cmake.pl
new file mode 100755
index 000000000..9764d6bf0
--- /dev/null
+++ b/test_regress/t/t_trace_fst_sc_cmake.pl
@@ -0,0 +1,31 @@
+#!/usr/bin/env perl
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+
+scenarios(vlt_all => 1);
+
+if (!$Self->have_sc) {
+    skip("No SystemC installed");
+}
+else {
+    compile(
+        verilator_flags2 => ["--trace-fst --sc"],
+        verilator_make_gmake => 0,
+        verilator_make_cmake => 1,
+    );
+
+    execute(
+        check_finished => 1,
+    );
+
+    fst_identical($Self->trace_filename, $Self->{golden_filename});
+}
+ok(1);
+1;
diff --git a/test_regress/t/t_trace_fst_sc_cmake.v b/test_regress/t/t_trace_fst_sc_cmake.v
new file mode 100644
index 000000000..52c148bd5
--- /dev/null
+++ b/test_regress/t/t_trace_fst_sc_cmake.v
@@ -0,0 +1,98 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   int   cyc;
+   reg   rstn;
+
+   parameter real  fst_gparam_real = 1.23;
+   localparam real fst_lparam_real = 4.56;
+   real            fst_real = 1.23;
+   integer         fst_integer;
+   bit             fst_bit;
+   logic           fst_logic;
+   int             fst_int;
+   shortint        fst_shortint;
+   longint         fst_longint;
+   byte            fst_byte;
+
+   parameter       fst_parameter = 123;
+   localparam      fst_lparam = 456;
+   supply0         fst_supply0;
+   supply1         fst_supply1;
+   tri0            fst_tri0;
+   tri1            fst_tri1;
+   tri             fst_tri;
+   wire            fst_wire;
+
+   logic [4:0] state;
+
+   Test test (/*AUTOINST*/
+              // Outputs
+              .state                    (state[4:0]),
+              // Inputs
+              .clk                      (clk),
+              .rstn                     (rstn));
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==0) begin
+         // Setup
+         rstn <= ~'1;
+      end
+      else if (cyc<10) begin
+         rstn <= ~'1;
+      end
+      else if (cyc<90) begin
+         rstn <= ~'0;
+      end
+      else if (cyc==99) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+
+module Test (
+          input              clk,
+          input              rstn,
+          output logic [4:0] state
+          );
+
+   logic [4:0]               state_w;
+   logic [4:0]               state_array [3];
+   assign state = state_array[0];
+
+   always_comb begin
+      state_w[4] = state_array[2][0];
+      state_w[3] = state_array[2][4];
+      state_w[2] = state_array[2][3] ^ state_array[2][0];
+      state_w[1] = state_array[2][2];
+      state_w[0] = state_array[2][1];
+   end
+
+   always_ff @(posedge clk or negedge rstn) begin
+      if (!rstn) begin
+         for (int i = 0; i < 3; i++)
+           state_array[i] <= 'b1;
+      end
+      else begin
+         for (int i = 0; i < 2; i++)
+           state_array[i] <= state_array[i+1];
+         state_array[2] <= state_w;
+      end
+   end
+
+endmodule