diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index 5d844725c..e26272673 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -551,6 +551,32 @@ private:
         cleanFileline(nodep);
         iterateChildren(nodep);
     }
+    void visit(AstDot* nodep) override {
+        cleanFileline(nodep);
+        iterateChildren(nodep);
+        if (VN_IS(nodep->lhsp(), ParseRef) && nodep->lhsp()->name() == "super"
+            && VN_IS(nodep->rhsp(), New)) {
+            // Look for other statements until hit function start
+            AstNode* scanp = nodep;
+            // Skip over the New's statement
+            for (; scanp && !VN_IS(scanp, StmtExpr); scanp = scanp->backp()) {}
+            if (VN_IS(scanp, StmtExpr)) {  // Ignore warnign if something not understood
+                scanp = scanp->backp();
+                for (; scanp; scanp = scanp->backp()) {
+                    if (VN_IS(scanp, NodeStmt) || VN_IS(scanp, NodeModule)
+                        || VN_IS(scanp, NodeFTask))
+                        break;
+                }
+                if (!VN_IS(scanp, NodeFTask)) {
+                    nodep->rhsp()->v3error(
+                        "'super.new' not first statement in new function (IEEE 1800-2017 8.15)\n"
+                        << nodep->rhsp()->warnContextPrimary() << scanp->warnOther()
+                        << "... Location of earlier statement\n"
+                        << scanp->warnContextSecondary());
+                }
+            }
+        }
+    }
     void visit(AstPrintTimeScale* nodep) override {
         // Inlining may change hierarchy, so just save timescale where needed
         cleanFileline(nodep);
diff --git a/test_regress/t/t_class_super_new.pl b/test_regress/t/t_class_super_new.pl
index bf4e4ce9f..aabcde63e 100755
--- a/test_regress/t/t_class_super_new.pl
+++ b/test_regress/t/t_class_super_new.pl
@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2020 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,7 +10,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-compile();
+compile(
+    );
 
 execute(
     check_finished => 1,
diff --git a/test_regress/t/t_class_super_new_bad_nfirst.out b/test_regress/t/t_class_super_new_bad_nfirst.out
new file mode 100644
index 000000000..28662df24
--- /dev/null
+++ b/test_regress/t/t_class_super_new_bad_nfirst.out
@@ -0,0 +1,7 @@
+%Error: t/t_class_super_new_bad_nfirst.v:18:13: 'super.new' not first statement in new function (IEEE 1800-2017 8.15)
+   18 |       super.new(imemberc);   
+      |             ^~~
+        t/t_class_super_new_bad_nfirst.v:17:16: ... Location of earlier statement
+   17 |       imemberc = 10;
+      |                ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_class_super_new_bad_nfirst.pl b/test_regress/t/t_class_super_new_bad_nfirst.pl
new file mode 100755
index 000000000..8b81d9f75
--- /dev/null
+++ b/test_regress/t/t_class_super_new_bad_nfirst.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+compile(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_super_new_bad_nfirst.v b/test_regress/t/t_class_super_new_bad_nfirst.v
new file mode 100644
index 000000000..8e1197305
--- /dev/null
+++ b/test_regress/t/t_class_super_new_bad_nfirst.v
@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class Base;
+   int imemberb;
+   function new(int adder);
+      imemberb = 5 + adder;
+   endfunction
+endclass
+
+class Cls extends Base;
+   int imemberc;
+   function new();
+      imemberc = 10;
+      super.new(imemberc);  // BAD not first
+   endfunction
+endclass
+
+module t (/*AUTOARG*/);
+   initial begin
+      Cls   c;
+      c = new;
+      if (c.imemberc != 10) $stop;
+      if (c.imemberb != 5) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule