diff --git a/test_regress/t/t_lint_implicit_port.v b/test_regress/t/t_lint_implicit_port.v
index d3f76bce5..637e5c6c6 100644
--- a/test_regress/t/t_lint_implicit_port.v
+++ b/test_regress/t/t_lint_implicit_port.v
@@ -12,12 +12,12 @@ module t (/*AUTOARG*/
    logic oe;
 
    read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) );
-   set  s (.clk(clk), .enable(implicit_write));
+   sets s (.clk(clk), .enable(implicit_write));
    read u (.clk(clk), .data(~implicit_also));
 
 endmodule
 
-module set (
+module sets (
    input  clk,
    output enable
    );