From 3381d656c761b5aad75887bc721125d2fe4185a8 Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Wed, 13 May 2026 14:15:32 +0200
Subject: [PATCH] Support calling interface functions without parens (#7584)

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 src/V3Width.cpp                             | 10 +++++++
 test_regress/t/t_interface_func_no_paren.py | 18 ++++++++++++
 test_regress/t/t_interface_func_no_paren.v  | 32 +++++++++++++++++++++
 3 files changed, 60 insertions(+)
 create mode 100755 test_regress/t/t_interface_func_no_paren.py
 create mode 100644 test_regress/t/t_interface_func_no_paren.v

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 5aedf9202..1adcf43b9 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3762,6 +3762,16 @@ class WidthVisitor final : public VNVisitor {
                         return;
                     }
                 }
+                if (AstNodeFTask* const ftaskp = VN_CAST(foundp, NodeFTask)) {
+                    AstMethodCall* const newp = new AstMethodCall{
+                        nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name()};
+                    newp->taskp(ftaskp);
+                    newp->dtypep(ftaskp->dtypep());
+                    nodep->replaceWith(newp);
+                    VL_DO_DANGLING(pushDeletep(nodep), nodep);
+                    userIterate(newp, m_vup);
+                    return;
+                }
                 UINFO(1, "found object " << foundp);
                 nodep->v3fatalSrc("MemberSel of non-variable\n"
                                   << nodep->warnContextPrimary() << '\n'
diff --git a/test_regress/t/t_interface_func_no_paren.py b/test_regress/t/t_interface_func_no_paren.py
new file mode 100755
index 000000000..8a938befd
--- /dev/null
+++ b/test_regress/t/t_interface_func_no_paren.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_interface_func_no_paren.v b/test_regress/t/t_interface_func_no_paren.v
new file mode 100644
index 000000000..71f083515
--- /dev/null
+++ b/test_regress/t/t_interface_func_no_paren.v
@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+interface intf;
+  int status;
+  function int get_status;
+    return status;
+  endfunction
+endinterface
+
+class cls;
+  virtual intf i;
+  function int get_status;
+    return i.get_status;
+  endfunction
+endclass
+
+module t;
+  intf intf();
+  cls c;
+  initial begin
+    intf.status = 'hdeadbeef;
+    c = new();
+    c.i = intf;
+    if (c.get_status !== 'hdeadbeef) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule