diff --git a/Changes b/Changes
index e7ac03f55..3709efc64 100644
--- a/Changes
+++ b/Changes
@@ -15,6 +15,8 @@ Verilator 5.045 devel
 
 * Remove deprecated `--xml-only`.
 * Remove deprecated `--make cmake`.
+* Fix MULTIDRIVEN with task and default driver (#4045) (#6858). [em2machine]
+* Fix dynamic array elements passed to ref argument (#6877). [Ryszard Rozak, Antmicro Ltd.]
 
 
 Verilator 5.044 2026-01-01
diff --git a/README.rst b/README.rst
index dd12d8728..2dac2e8bb 100644
--- a/README.rst
+++ b/README.rst
@@ -67,11 +67,10 @@ executable performs the design simulation. Verilator also supports linking
 Verilated generated libraries, optionally encrypted, into other simulators.
 
 Verilator may not be the best choice if you are expecting a full-featured
-replacement for a closed-source Verilog simulator, need SDF annotation,
-mixed-signal simulation, or are doing a quick class project (we recommend
-`Icarus Verilog`_ for classwork). However, if you are looking for a path to
-migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
-designs, Verilator is the tool for you.
+replacement for a closed-source Verilog simulator, need SDF annotation, or
+mixed-signal simulation. However, if you are looking for a path to migrate
+SystemVerilog to C++/SystemC, or want high-speed simulation of designs,
+Verilator is the tool for you.
 
 
 Performance