From 323f01935098699ff54436502c0680765bd4a993 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 8 Apr 2012 18:13:42 -0400
Subject: [PATCH] Tests: Add t_interface, bug481.  Merge from JERAS/test_sv.

---
 test_regress/t/t_interface.pl  |  20 ++++
 test_regress/t/t_interface.v   | 169 +++++++++++++++++++++++++++++++++
 test_regress/t/t_param_type.pl |   2 +-
 3 files changed, 190 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_interface.pl
 create mode 100644 test_regress/t/t_interface.v

diff --git a/test_regress/t/t_interface.pl b/test_regress/t/t_interface.pl
new file mode 100755
index 000000000..5277b6ecb
--- /dev/null
+++ b/test_regress/t/t_interface.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug102");
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface.v b/test_regress/t/t_interface.v
new file mode 100644
index 000000000..8dd7d9d25
--- /dev/null
+++ b/test_regress/t/t_interface.v
@@ -0,0 +1,169 @@
+// DESCRIPTION: Verilator: SystemVerilog interface test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Iztok Jeras.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   logic   rst = 1'b1;  // reset
+   integer rst_cnt = 0;
+
+   // reset is removed after a delay
+   always @ (posedge clk)
+   begin
+      rst_cnt <= rst_cnt + 1;
+      rst     <= rst_cnt <= 3;
+   end
+
+   // counters
+   int cnt;
+   int cnt_src;
+   int cnt_drn;
+
+   // add all counters
+   assign cnt = cnt_src + cnt_drn + inf.cnt;
+
+   // finish report
+   always @ (posedge clk)
+   if (cnt == 3*16) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   // interface instance
+   handshake inf (
+      .clk (clk),
+      .rst (rst)
+   );
+
+   // source instance
+   source #(
+      .RW  (8),
+      .RP  (8'b11100001)
+   ) source (
+      .clk  (clk),
+      .rst  (rst),
+      .inf  (inf),
+      .cnt  (cnt_src)
+   );
+
+   // drain instance
+   drain #(
+      .RW  (8),
+      .RP  (8'b11010100)
+   ) drain (
+      .clk  (clk),
+      .rst  (rst),
+      .inf  (inf),
+      .cnt  (cnt_drn)
+   );
+
+endmodule : t
+
+
+// interface definition
+interface handshake #(
+   parameter int unsigned WC = 32
+)(
+   input logic clk,
+   input logic rst
+);
+
+   // modport signals
+   logic req;  // request
+   logic grt;  // grant
+   logic inc;  // increment
+
+   // local signals
+   integer cnt;  // counter
+
+   // source
+   modport src (
+      output req,
+      input  grt
+   );
+
+   // drain
+   modport drn (
+      input  req,
+      output grt
+   );
+
+   // incremet condition
+   assign inc = req & grt;
+
+   // local logic (counter)
+   always @ (posedge clk, posedge rst)
+   if (rst) cnt <= '0;
+   else     cnt <= cnt + inc;
+
+endinterface : handshake
+
+
+// source module
+module source #(
+   // random generator parameters
+   parameter int unsigned RW=1,   // LFSR width
+   parameter bit [RW-1:0] RP='0,  // LFSR polinom
+   parameter bit [RW-1:0] RR='1   // LFSR reset state
+)(
+   input logic    clk,
+   input logic    rst,
+   handshake.src  inf,
+   output integer cnt
+);
+
+   // LFSR
+   logic [RW-1:0] rnd;
+
+   // LFSR in Galois form
+   always @ (posedge clk, posedge rst)
+   if (rst) rnd <= RR;
+   else     rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
+
+   // counter
+   always @ (posedge clk, posedge rst)
+   if (rst) cnt <= 32'd0;
+   else     cnt <= cnt + (inf.req & inf.grt);
+
+   // request signal
+   assign inf.req = rnd[0];
+
+endmodule : source
+
+
+// drain module
+module drain #(
+   // random generator parameters
+   parameter int unsigned RW=1,   // LFSR width
+   parameter bit [RW-1:0] RP='0,  // LFSR polinom
+   parameter bit [RW-1:0] RR='1   // LFSR reset state
+)(
+   input logic    clk,
+   input logic    rst,
+   handshake.drn  inf,
+   output integer cnt
+);
+
+   // LFSR
+   logic [RW-1:0] rnd;
+
+   // LFSR in Galois form
+   always @ (posedge clk, posedge rst)
+   if (rst) rnd <= RR;
+   else     rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
+
+   // counter
+   always @ (posedge clk, posedge rst)
+   if (rst) cnt <= 32'd0;
+   else     cnt <= cnt + (inf.req & inf.grt);
+
+   // grant signal
+   assign inf.grt = rnd[0];
+
+endmodule : drain
diff --git a/test_regress/t/t_param_type.pl b/test_regress/t/t_param_type.pl
index 813e1c5a0..ea02c60a4 100755
--- a/test_regress/t/t_param_type.pl
+++ b/test_regress/t/t_param_type.pl
@@ -7,7 +7,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 
-$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug480");
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug376");
 
 compile (
 	 );