diff --git a/include/verilated.cpp b/include/verilated.cpp
index cb1ad5481..8733c4367 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -207,7 +207,8 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, boo
     vluint32_t vn[VL_MULS_MAX_WORDS+1]; // v normalized
 
     // Zero for ease of debugging and to save having to zero for shifts
-    for (int i=0; i<words; i++) { un[i]=vn[i]=0; }
+    // Note +1 as loop will use extra word
+    for (int i=0; i<words+1; i++) { un[i]=vn[i]=0; }
 
     // Algorithm requires divisor MSB to be set
     // Copy and shift to normalize divisor so MSB of vn[vw-1] is set
diff --git a/test_regress/t/t_math_vgen.v b/test_regress/t/t_math_vgen.v
index fe4f43c98..fc98f93c6 100644
--- a/test_regress/t/t_math_vgen.v
+++ b/test_regress/t/t_math_vgen.v
@@ -282,6 +282,16 @@ module t (/*AUTOARG*/
 
    //============================================================
 
+   reg signed [ 83:  0] W0024                     ; //=84'h0000000000000e1fe9094
+   reg signed [ 83:  0] W0025                     ; //=84'h0f66afffffffe308b3d7c
+   always @(posedge clk) begin
+      W0024 <= 84'h0000000000000e1fe9094;
+      W0025 <= 84'h0f66afffffffe308b3d7c;
+      if ((W0024 % W0025) != 84'sh0000000000000e1fe9094) if (check) $stop;
+   end
+
+   //============================================================
+
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;