From 32019d2bc45d21ef2394b49078b51d3f1521d51c Mon Sep 17 00:00:00 2001
From: Aleksander Kiryk <akiryk@antmicro.com>
Date: Thu, 29 Jun 2023 15:21:49 +0200
Subject: [PATCH] Fix state update for always processes (#4311)

---
 src/V3Timing.cpp                 |  2 ++
 test_regress/t/t_process_task.pl | 23 ++++++++++++++++++++++
 test_regress/t/t_process_task.v  | 33 ++++++++++++++++++++++++++++++++
 3 files changed, 58 insertions(+)
 create mode 100755 test_regress/t/t_process_task.pl
 create mode 100644 test_regress/t/t_process_task.v

diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp
index d7f27eba7..08fa6919b 100644
--- a/src/V3Timing.cpp
+++ b/src/V3Timing.cpp
@@ -594,6 +594,8 @@ private:
     }
     void visit(AstAlways* nodep) override {
         if (nodep->user1SetOnce()) return;
+        VL_RESTORER(m_procp);
+        m_procp = nodep;
         iterateChildren(nodep);
         if (!nodep->user2()) return;
         if (nodep->user2() == T_PROC) nodep->setNeedProcess();
diff --git a/test_regress/t/t_process_task.pl b/test_regress/t/t_process_task.pl
new file mode 100755
index 000000000..123e2f4fd
--- /dev/null
+++ b/test_regress/t/t_process_task.pl
@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    v_flags2 => ["--exe --main --timing"],
+    make_main => 0,
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_process_task.v b/test_regress/t/t_process_task.v
new file mode 100644
index 000000000..5701b47b3
--- /dev/null
+++ b/test_regress/t/t_process_task.v
@@ -0,0 +1,33 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t();
+   std::process proc;
+   logic clk = 0;
+   logic b = 0;
+
+   always #1 clk = ~clk;
+
+   task kill_me_after_1ns();
+      fork
+         #1 proc.kill();
+         #3 begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+         end
+      join_none
+   endtask
+
+   always @(posedge clk) begin
+      if (!b) begin
+         proc = std::process::self();
+         kill_me_after_1ns();
+         b = 1;
+      end else begin
+         $stop;
+      end
+   end
+endmodule