diff --git a/test_regress/t/t_param_public.pl b/test_regress/t/t_param_public.pl
new file mode 100755
index 000000000..f91289753
--- /dev/null
+++ b/test_regress/t/t_param_public.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_param_public.v b/test_regress/t/t_param_public.v
new file mode 100644
index 000000000..045c95287
--- /dev/null
+++ b/test_regress/t/t_param_public.v
@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+//bug505
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   a #(1) a1 ();
+   b #(2) b2 ();
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module a;
+   parameter ONE /*verilator public*/ = 22;
+   initial if (ONE != 1) $stop;
+`ifdef VERILATOR
+   initial if ($c32("ONE") != 1) $stop;
+`endif
+endmodule
+
+module b #(
+	   parameter TWO /*verilator public*/ = 22
+	   );
+   initial if (TWO != 2) $stop;
+`ifdef VERILATOR
+   initial if ($c32("TWO") != 2) $stop;
+`endif
+endmodule