diff --git a/Changes b/Changes index 71fe31bf2..75d3f2c04 100644 --- a/Changes +++ b/Changes @@ -16,6 +16,7 @@ Verilator 5.039 devel * Add ENUMITEMWIDTH error, and apply to X-extended and ranged values. * Add NOEFFECT warning, replacing previous `foreach` error. * Add SPECIFYIGN warning for specify constructs that were previously silently ignored. +* Add PARAMNODEFAULT error, for parameters without defaults. * Add enum base data type, wire data type, and I/O versus data declaration checking per IEEE. * Add error on missing forward declarations (#6206). [Alex Solomatnikov] * Add error when trying to assign class object to variable of non-class types (#6237). [Igor Zaworski, Antmicro Ltd.] diff --git a/docs/gen/ex_PARAMNODEFAULT_faulty.rst b/docs/gen/ex_PARAMNODEFAULT_faulty.rst new file mode 100644 index 000000000..e5eab758c --- /dev/null +++ b/docs/gen/ex_PARAMNODEFAULT_faulty.rst @@ -0,0 +1,7 @@ +.. comment: generated by t_lint_paramnodefault_bad +.. code-block:: sv + :linenos: + :emphasize-lines: 2 + + module sub; + parameter NODEF; //<--- Warning diff --git a/docs/gen/ex_PARAMNODEFAULT_msg.rst b/docs/gen/ex_PARAMNODEFAULT_msg.rst new file mode 100644 index 000000000..d1fa62f7c --- /dev/null +++ b/docs/gen/ex_PARAMNODEFAULT_msg.rst @@ -0,0 +1,6 @@ +.. comment: generated by t_lint_paramnodefault_bad +.. code-block:: + + %Error-PARAMNODEFAULT: example.v:1:13 Parameter without default requires ANSI-style parameter list (IEEE 1800-2023 6.20.1): 'NODEF' + 8 | parameter NODEF; + | ^~~~~ diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index 9e6d534be..22e61d582 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -1378,6 +1378,27 @@ List Of Warnings simulate correctly. +.. option:: PARAMNODEFAULT + + An error that a parameter is being declared that has no default value, + and this is being done in a non-ANSI block while this is only legal in + ANSI-style `#(...)` declarations. IEEE 1800-2023 6.20.1 requires this + error, but some simulators accept this syntax. + + Faulty example: + + .. include:: ../../docs/gen/ex_PARAMNODEFAULT_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_PARAMNODEFAULT_msg.rst + + To fix the issue, move to an ANSI-style declaration. + + Suppressing this error will only suppress the IEEE-required check; it + will simulate correctly. + + .. option:: PINCONNECTEMPTY .. TODO better example diff --git a/src/V3Error.h b/src/V3Error.h index 4e2eadb64..ebb8e3fa5 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -129,6 +129,7 @@ public: NOLATCH, // No latch detected in always_latch block NONSTD, // Non-standard feature present in other sims NULLPORT, // Null port detected in module definition + PARAMNODEFAULT, // Parameter without default PINCONNECTEMPTY,// Cell pin connected by name with empty reference PINMISSING, // Cell pin not specified PINNOCONNECT, // Cell pin not connected @@ -210,15 +211,16 @@ public: "IGNOREDRETURN", "IMPERFECTSCH", "IMPLICIT", "IMPLICITSTATIC", "IMPORTSTAR", "IMPURE", "INCABSPATH", "INFINITELOOP", "INITIALDLY", "INSECURE", "LATCH", "LITENDIAN", "MINTYPMAXDLY", "MISINDENT", "MODDUP", "MODMISSING", "MULTIDRIVEN", "MULTITOP", - "NEWERSTD", "NOEFFECT", "NOLATCH", "NONSTD", "NULLPORT", "PINCONNECTEMPTY", - "PINMISSING", "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", "PREPROCZERO", "PROCASSINIT", - "PROCASSWIRE", "PROFOUTOFDATE", "PROTECTED", "RANDC", "REALCVT", "REDEFMACRO", - "RISEFALLDLY", "SELRANGE", "SHORTREAL", "SIDEEFFECT", "SPECIFYIGN", "SPLITVAR", - "STATICVAR", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET", "TICKCOUNT", "TIMESCALEMOD", - "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNOPTTHREADS", "UNPACKED", "UNSIGNED", - "UNUSEDGENVAR", "UNUSEDLOOP", "UNUSEDPARAM", "UNUSEDSIGNAL", "USERERROR", "USERFATAL", - "USERINFO", "USERWARN", "VARHIDDEN", "WAITCONST", "WIDTH", "WIDTHCONCAT", - "WIDTHEXPAND", "WIDTHTRUNC", "WIDTHXZEXPAND", "ZERODLY", "ZEROREPL", " MAX"}; + "NEWERSTD", "NOEFFECT", "NOLATCH", "NONSTD", "NULLPORT", "PARAMNODEFAULT", + "PINCONNECTEMPTY", "PINMISSING", "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", + "PREPROCZERO", "PROCASSINIT", "PROCASSWIRE", "PROFOUTOFDATE", "PROTECTED", "RANDC", + "REALCVT", "REDEFMACRO", "RISEFALLDLY", "SELRANGE", "SHORTREAL", "SIDEEFFECT", + "SPECIFYIGN", "SPLITVAR", "STATICVAR", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET", + "TICKCOUNT", "TIMESCALEMOD", "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNOPTTHREADS", + "UNPACKED", "UNSIGNED", "UNUSEDGENVAR", "UNUSEDLOOP", "UNUSEDPARAM", "UNUSEDSIGNAL", + "USERERROR", "USERFATAL", "USERINFO", "USERWARN", "VARHIDDEN", "WAITCONST", "WIDTH", + "WIDTHCONCAT", "WIDTHEXPAND", "WIDTHTRUNC", "WIDTHXZEXPAND", "ZERODLY", "ZEROREPL", + " MAX"}; return names[m_e]; } // Warnings that default to off @@ -246,8 +248,8 @@ public: return (m_e == ASSIGNIN || m_e == BADSTDPRAGMA || m_e == BADVLTPRAGMA || m_e == BLKANDNBLK || m_e == BLKLOOPINIT || m_e == CONTASSREG || m_e == ENCAPSULATED || m_e == ENDLABEL || m_e == ENUMITEMWIDTH || m_e == ENUMVALUE || m_e == IMPURE - || m_e == MODMISSING || m_e == PINNOTFOUND || m_e == PKGNODECL - || m_e == PROCASSWIRE || m_e == ZEROREPL // Says IEEE + || m_e == MODMISSING || m_e == PARAMNODEFAULT || m_e == PINNOTFOUND + || m_e == PKGNODECL || m_e == PROCASSWIRE || m_e == ZEROREPL // Says IEEE ); } // Warnings to mention manual diff --git a/src/verilog.y b/src/verilog.y index ce6933289..8f1242b03 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -3276,7 +3276,11 @@ param_assignment: // ==IEEE: param_assignment // // constant_param_expression: '$' is in expr id/*new-parameter*/ variable_dimensionListE sigAttrListE exprOrDataTypeEqE { $$ = VARDONEA($1, *$1, $2, $3); - if ($4) $$->valuep($4); } + if ($4) $$->valuep($4); + else if (!GRAMMARP->m_pinAnsi) + $$->v3warn(PARAMNODEFAULT, "Parameter without default requires" + " ANSI-style parameter list (IEEE 1800-2023 6.20.1): " + << $$->prettyNameQ()); } ; list_of_param_assignments: // ==IEEE: list_of_param_assignments diff --git a/test_regress/t/t_lint_paramnodefault.py b/test_regress/t/t_lint_paramnodefault.py new file mode 100755 index 000000000..bedf95356 --- /dev/null +++ b/test_regress/t/t_lint_paramnodefault.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['-Wno-PARAMNODEFAULT']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lint_paramnodefault.v b/test_regress/t/t_lint_paramnodefault.v new file mode 100644 index 000000000..dcc4e23fa --- /dev/null +++ b/test_regress/t/t_lint_paramnodefault.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module sub; + parameter NODEF; //<--- Warning + initial begin + if (NODEF != 6) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module t; + sub #(6) sub(); +endmodule diff --git a/test_regress/t/t_lint_paramnodefault_bad.out b/test_regress/t/t_lint_paramnodefault_bad.out new file mode 100644 index 000000000..8ea5c9b84 --- /dev/null +++ b/test_regress/t/t_lint_paramnodefault_bad.out @@ -0,0 +1,5 @@ +%Error-PARAMNODEFAULT: t/t_lint_paramnodefault.v:8:13: Parameter without default requires ANSI-style parameter list (IEEE 1800-2023 6.20.1): 'NODEF' + 8 | parameter NODEF; + | ^~~~~ + ... For error description see https://verilator.org/warn/PARAMNODEFAULT?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_lint_paramnodefault_bad.py b/test_regress/t/t_lint_paramnodefault_bad.py new file mode 100755 index 000000000..a39dc08aa --- /dev/null +++ b/test_regress/t/t_lint_paramnodefault_bad.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = 't/t_lint_paramnodefault.v' + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename=root + "/docs/gen/ex_PARAMNODEFAULT_faulty.rst", + lines="7-8") + +test.extract(in_filename=test.golden_filename, + out_filename=root + "/docs/gen/ex_PARAMNODEFAULT_msg.rst", + lines="1-3") + +test.passes() diff --git a/test_regress/t/t_param_pattern2.v b/test_regress/t/t_param_pattern2.v index 672b40fd2..2bd1731c8 100644 --- a/test_regress/t/t_param_pattern2.v +++ b/test_regress/t/t_param_pattern2.v @@ -4,8 +4,9 @@ // without warranty, 2021 by Ryszard Rozak. // SPDX-License-Identifier: CC0-1.0 -module dut(output int x); - parameter int P [5]; +module dut + #(parameter int P [5]) + (output int x); assign x = P[2]; endmodule diff --git a/test_regress/t/t_strength_equal_strength.v b/test_regress/t/t_strength_equal_strength.v index fbbe8bdf1..eb834bc33 100644 --- a/test_regress/t/t_strength_equal_strength.v +++ b/test_regress/t/t_strength_equal_strength.v @@ -4,8 +4,9 @@ // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 -interface inter (input logic cond, output wire a); - parameter W; +interface inter + #(parameter W) + (input logic cond, output wire a); // Example: wire (weak0, weak1) [W-1:0] b = '1; assign (strong0, strong1) b = cond ? 'b0 : 'bz;