diff --git a/src/verilog.l b/src/verilog.l index 222171770..6796cb811 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -687,7 +687,6 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} { /* Generic unsupported warnings */ - "1step" { FL; return y1STEP; } "above" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; } "abs" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; } "absdelay" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; } diff --git a/src/verilog.y b/src/verilog.y index bbe9b7aef..1abe0b82c 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1026,7 +1026,7 @@ description: // ==IEEE: description | yaT_UNCONNECTED_PULL0 { PARSEP->unconnectedDrive(VOptionBool::OPT_FALSE); } | yaT_UNCONNECTED_PULL1 { PARSEP->unconnectedDrive(VOptionBool::OPT_TRUE); } | vltItem { } - | error { } + | error { } // LCOV_EXCL_LINE ; timeunits_declaration: // ==IEEE: timeunits_declaration @@ -2124,8 +2124,8 @@ struct_unionDecl: // IEEE: part of data_type struct_union_memberListEnd: // IEEE: { struct_union_member } '}' struct_union_memberList '}' { $$ = $1; } // - | struct_union_memberList error '}' { $$ = $1; } - | error '}' { $$ = nullptr; } + | struct_union_memberList error '}' { $$ = $1; } // LCOV_EXCL_LINE + | error '}' { $$ = nullptr; } // LCOV_EXCL_LINE ; struct_union_memberList: // IEEE: { struct_union_member } @@ -2133,8 +2133,8 @@ struct_union_memberList: // IEEE: { struct_union_member } | struct_union_memberList struct_union_member { $$ = addNextNull($1, $2); } // - | struct_union_memberList error ';' { $$ = $1; } - | error ';' { $$ = nullptr; } + | struct_union_memberList error ';' { $$ = $1; } // LCOV_EXCL_LINE + | error ';' { $$ = nullptr; } // LCOV_EXCL_LINE ; struct_union_member: // ==IEEE: struct_union_member @@ -2514,7 +2514,7 @@ type_declaration: // ==IEEE: type_declaration | yTYPEDEF yCLASS idAny ';' { $$ = GRAMMARP->createTypedefFwd($3, *$3, VFwdType::CLASS); } | yTYPEDEF yINTERFACE yCLASS idAny ';' { $$ = GRAMMARP->createTypedefFwd($4, *$4, VFwdType::INTERFACE_CLASS); } // - | yTYPEDEF error idAny ';' { $$ = GRAMMARP->createTypedefFwd($3, *$3, VFwdType::NONE); } + | yTYPEDEF error idAny ';' { $$ = GRAMMARP->createTypedefFwd($3, *$3, VFwdType::NONE); } // LCOV_EXCL_LINE ; dtypeAttrListE: @@ -2616,7 +2616,7 @@ module_common_item: // ==IEEE: module_common_item | severity_system_task { $$ = $1; } | sigAttrScope { $$ = nullptr; } // - | error ';' { $$ = nullptr; } + | error ';' { $$ = nullptr; } // LCOV_EXCL_LINE ; always_construct: // IEEE: == always_construct @@ -3444,8 +3444,8 @@ block_item_declarationList: // IEEE: [ block_item_declaration ] block_item_declaration { $$ = $1; } | block_item_declarationList block_item_declaration { $$ = addNextNull($1, $2); } // - | block_item_declarationList error ';' { $$ = $1; } - | error ';' { $$ = nullptr; } + | block_item_declarationList error ';' { $$ = $1; } // LCOV_EXCL_LINE + | error ';' { $$ = nullptr; } // LCOV_EXCL_LINE ; block_item_declaration: // ==IEEE: block_item_declaration @@ -3458,7 +3458,7 @@ stmtList: stmtBlock { $$ = $1; } | stmtList stmtBlock { $$ = addNextNull($1, $2); } // - | stmtList error ';' { $$ = $1; } + | stmtList error ';' { $$ = $1; } // LCOV_EXCL_LINE ; stmt: // IEEE: statement_or_null == function_statement_or_null @@ -5823,7 +5823,7 @@ junkToSemiList: junkToSemi: BISONPRE_NOT(';',yD_SETUPHOLD,yENDMODULE,yENDSPECIFY,ySPECPARAM) { } - | error {} + | error { } // LCOV_EXCL_LINE ; //************************************************ @@ -6775,7 +6775,7 @@ coverage_spec_or_option: // ==IEEE: coverage_spec_or_option cover_point { $$ = $1; } | cover_cross { $$ = $1; } | coverage_option ';' { $$ = $1; } - | error { $$ = nullptr; } + | error { $$ = nullptr; } // LCOV_EXCL_LINE ; coverage_option: // ==IEEE: coverage_option @@ -6818,16 +6818,16 @@ bins_or_empty: // ==IEEE: bins_or_empty | '{' '}' { $$ = nullptr; } | ';' { $$ = nullptr; } // - | '{' bins_or_optionsList error '}' { $$ = $2; } - | '{' error '}' { $$ = nullptr; } + | '{' bins_or_optionsList error '}' { $$ = $2; } // LCOV_EXCL_LINE + | '{' error '}' { $$ = nullptr; } // LCOV_EXCL_LINE ; bins_or_optionsList: // IEEE: { bins_or_options ';' } bins_or_options ';' { $$ = $1; } | bins_or_optionsList bins_or_options ';' { $$ = addNextNull($1, $2); } // - | bins_or_optionsList error ';' { $$ = $1; } - | error ';' { $$ = nullptr; } + | bins_or_optionsList error ';' { $$ = $1; } // LCOV_EXCL_LINE + | error ';' { $$ = nullptr; } // LCOV_EXCL_LINE ; bins_or_options: // ==IEEE: bins_or_options @@ -6933,8 +6933,8 @@ cross_body: // ==IEEE: cross_body | '{' cross_body_itemList '}' { $$ = $2; } | ';' { $$ = nullptr; } // - | '{' cross_body_itemList error '}' { $$ = $2; } - | '{' error '}' { $$ = nullptr; } + | '{' cross_body_itemList error '}' { $$ = $2; } // LCOV_EXCL_LINE + | '{' error '}' { $$ = nullptr; } // LCOV_EXCL_LINE ; cross_body_itemList: // IEEE: part of cross_body @@ -6950,7 +6950,7 @@ cross_body_item: // ==IEEE: cross_body_item // // IEEE: bins_selection | bins_keyword idAny/*new-bin_identifier*/ '=' select_expression iffE ';' { $$ = nullptr; BBCOVERIGN($1, "Ignoring unsupported: coverage cross bin"); DEL($4, $5); } - | error ';' { $$ = nullptr; } + | error ';' { $$ = nullptr; } // LCOV_EXCL_LINE ; select_expression: // ==IEEE: select_expression @@ -7462,8 +7462,8 @@ localNextId: // local:: class_itemListEnd: yENDCLASS { $$ = nullptr; } | class_itemList yENDCLASS { $$ = $1; } - | error yENDCLASS { $$ = nullptr; } - | class_itemList error yENDCLASS { $$ = $1; } + | error yENDCLASS { $$ = nullptr; } // LCOV_EXCL_LINE + | class_itemList error yENDCLASS { $$ = $1; } // LCOV_EXCL_LINE ; class_itemList: @@ -7492,7 +7492,7 @@ class_item: // ==IEEE: class_item // // Verilator specific | vlScBlock { $$ = $1; } // - | error ';' { $$ = nullptr; } + | error ';' { $$ = nullptr; } // LCOV_EXCL_LINE ; class_method: // ==IEEE: class_method @@ -7582,8 +7582,8 @@ constraint_block: // ==IEEE: constraint_block '{' '}' { $$ = nullptr; } | '{' constraint_block_itemList '}' { $$ = $2; } // - | '{' error '}' { $$ = nullptr; } - | '{' constraint_block_itemList error '}' { $$ = $2; } + | '{' error '}' { $$ = nullptr; } // LCOV_EXCL_LINE + | '{' constraint_block_itemList error '}' { $$ = $2; } // LCOV_EXCL_LINE ; constraint_block_itemList: // IEEE: { constraint_block_item } @@ -7642,15 +7642,15 @@ constraint_expression: // ==IEEE: constraint_expression $$ = newp; } // | error ';' - { $$ = nullptr; } + { $$ = nullptr; } // LCOV_EXCL_LINE ; constraint_set: // ==IEEE: constraint_set constraint_expression { $$ = $1; } | '{' constraint_expressionList '}' { $$ = $2; } // - | '{' error '}' { $$ = nullptr; } - | '{' constraint_expressionList error '}' { $$ = $2; } + | '{' error '}' { $$ = nullptr; } // LCOV_EXCL_LINE + | '{' constraint_expressionList error '}' { $$ = $2; } // LCOV_EXCL_LINE ; dist_list: // ==IEEE: dist_list @@ -7769,7 +7769,7 @@ config_rule_statement: // == IEEE: config_rule_statement | yCELL configCell use_clause ';' { $$ = new AstConfigRule{$1, $2, $3, true}; } | error ';' - { $$ = nullptr; } + { $$ = nullptr; } // LCOV_EXCL_LINE ; inst_name: // == IEEE: inst_name diff --git a/test_regress/t/t_assert_always_unsup.out b/test_regress/t/t_assert_always_unsup.out index 2e537171c..f33c70fe2 100644 --- a/test_regress/t/t_assert_always_unsup.out +++ b/test_regress/t/t_assert_always_unsup.out @@ -8,19 +8,9 @@ %Error-UNSUPPORTED: t/t_assert_always_unsup.v:29:7: Unsupported: eventually[] (in property expression) 29 | eventually [2:5] a; | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_always_unsup.v:33:7: Unsupported: s_eventually[] (in property expression) - 33 | s_eventually [2:5] a; - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_always_unsup.v:37:14: Unsupported: s_eventually[] (in property expression) - 37 | always s_eventually [2:5] a; - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_always_unsup.v:37:7: Unsupported: always (in property expression) - 37 | always s_eventually [2:5] a; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_assert_always_unsup.v:41:20: Unsupported: always[] (in property expression) - 41 | s_eventually always [2:5] a; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_assert_always_unsup.v:41:7: Unsupported: s_eventually (in property expression) - 41 | s_eventually always [2:5] a; - | ^~~~~~~~~~~~ -%Error: Exiting due to +%Error: t/t_assert_always_unsup.v:33:20: syntax error, unexpected ']', expecting ':' + 33 | eventually [2] a; + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Cannot continue + ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_assert_always_unsup.v b/test_regress/t/t_assert_always_unsup.v index f273e5493..5e46e676c 100644 --- a/test_regress/t/t_assert_always_unsup.v +++ b/test_regress/t/t_assert_always_unsup.v @@ -29,6 +29,10 @@ module t (/*AUTOARG*/ eventually [2:5] a; endproperty + property p_evc; + eventually [2] a; + endproperty + property p_s_ev; s_eventually [2:5] a; endproperty diff --git a/test_regress/t/t_assert_comp_bad.out b/test_regress/t/t_assert_comp_bad.out index 29fd238ca..120d18bba 100644 --- a/test_regress/t/t_assert_comp_bad.out +++ b/test_regress/t/t_assert_comp_bad.out @@ -42,6 +42,10 @@ ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Warning-USERFATAL: t/t_assert_comp_bad.v:22:5: Elaboration system task message (IEEE 1800-2023 20.11) : ... note: In instance 't' - 22 | $fatal; + 22 | $fatal(0); + | ^~~~~~ +%Warning-USERFATAL: t/t_assert_comp_bad.v:23:5: Elaboration system task message (IEEE 1800-2023 20.11) + : ... note: In instance 't' + 23 | $fatal; | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_comp_bad.v b/test_regress/t/t_assert_comp_bad.v index 03a26d0cd..f8a4fac4e 100644 --- a/test_regress/t/t_assert_comp_bad.v +++ b/test_regress/t/t_assert_comp_bad.v @@ -19,6 +19,7 @@ module t; $error; $error("User elaboration-time error"); $fatal(0, "User elaboration-time fatal"); + $fatal(0); $fatal; end diff --git a/test_regress/t/t_case_genx_bad.v b/test_regress/t/t_case_genx_bad.v index 00ab51afc..c5d045979 100644 --- a/test_regress/t/t_case_genx_bad.v +++ b/test_regress/t/t_case_genx_bad.v @@ -12,7 +12,7 @@ module t; case (P) 32'b0: initial begin end 32'b1xxx: initial begin end - default: initial begin end + default initial begin end // No ':' to cover parser endcase endgenerate diff --git a/test_regress/t/t_case_inside.v b/test_regress/t/t_case_inside.v index f33993e3c..2db42cd2b 100644 --- a/test_regress/t/t_case_inside.v +++ b/test_regress/t/t_case_inside.v @@ -55,12 +55,12 @@ module sub (/*AUTOARG*/ always @* begin case (in[3:0]) inside - default: {out1,out2} = {1'b0,5'h0F}; // Note not last item + default {out1,out2} = {1'b0,5'h0F}; // Note not last item, no : to cover parser 4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01}; 4'h4: {out1,out2} = {1'b1,5'h04}; - [4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match + [4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match 4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08}; - [4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C}; + [4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C}; endcase end diff --git a/test_regress/t/t_covergroup_unsup.out b/test_regress/t/t_covergroup_unsup.out index 4ab822b34..5b5988b9c 100644 --- a/test_regress/t/t_covergroup_unsup.out +++ b/test_regress/t/t_covergroup_unsup.out @@ -244,10 +244,16 @@ 129 | { wildcard bins wbts = ( 1, 2 ); } | ^~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:130:33: Ignoring unsupported: covergroup value range - 130 | { bins bts2 = ( 2, 3 ), ( [5:6] ) ; } + 130 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:130:44: Ignoring unsupported: covergroup value range + 130 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:130:59: Ignoring unsupported: covergroup value range + 130 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } + | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:130:19: Ignoring unsupported: cover bin trans list - 130 | { bins bts2 = ( 2, 3 ), ( [5:6] ) ; } + 130 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:132:27: Ignoring unsupported: cover trans set '=>' 132 | { bins bts2 = ( 1,5 => 6,7 ) ; } diff --git a/test_regress/t/t_covergroup_unsup.v b/test_regress/t/t_covergroup_unsup.v index a68f1e5df..a8215c20b 100644 --- a/test_regress/t/t_covergroup_unsup.v +++ b/test_regress/t/t_covergroup_unsup.v @@ -127,7 +127,7 @@ module t (/*AUTOARG*/ { bins bts = ( 1, 2 ); } { wildcard bins wbts = ( 1, 2 ); } - { bins bts2 = ( 2, 3 ), ( [5:6] ) ; } + { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } { bins bts2 = ( 1,5 => 6,7 ) ; } { bins bts2 = ( 3 [*5] ) ; } diff --git a/test_regress/t/t_dist_warn_coverage.py b/test_regress/t/t_dist_warn_coverage.py index cb64be81d..e784f4287 100755 --- a/test_regress/t/t_dist_warn_coverage.py +++ b/test_regress/t/t_dist_warn_coverage.py @@ -71,8 +71,6 @@ for s in [ 'Unsupported tristate port expression: ', 'Unsupported: $bits for queue', 'Unsupported: &&& expression', - 'Unsupported: +%- range', - 'Unsupported: +/- range', 'Unsupported: 4-state numbers in this context', 'Unsupported: Bind with instance list', 'Unsupported: Concatenation to form ', diff --git a/test_regress/t/t_inside_tolerance_unsup.out b/test_regress/t/t_inside_tolerance_unsup.out new file mode 100644 index 000000000..2b74e6bc7 --- /dev/null +++ b/test_regress/t/t_inside_tolerance_unsup.out @@ -0,0 +1,26 @@ +%Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:18:23: Unsupported: +/- range + 18 | do if ((r inside {[1492 +/- 2]}) !== (1'b1)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",18, (r inside {[1492 +/- 2]}), (1'b1), "r inside {[1492 +/- 2]}", "1'b1"); $stop; end while(0);; + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:18:160: Unsupported: +/- range + 18 | do if ((r inside {[1492 +/- 2]}) !== (1'b1)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",18, (r inside {[1492 +/- 2]}), (1'b1), "r inside {[1492 +/- 2]}", "1'b1"); $stop; end while(0);; + | ^ +%Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:19:23: Unsupported: +/- range + 19 | do if ((r inside {[1482 +/- 2]}) !== (1'b0)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",19, (r inside {[1482 +/- 2]}), (1'b0), "r inside {[1482 +/- 2]}", "1'b0"); $stop; end while(0);; + | ^ +%Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:19:160: Unsupported: +/- range + 19 | do if ((r inside {[1482 +/- 2]}) !== (1'b0)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",19, (r inside {[1482 +/- 2]}), (1'b0), "r inside {[1482 +/- 2]}", "1'b0"); $stop; end while(0);; + | ^ +%Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:20:23: Unsupported: +%- range + 20 | do if ((r inside {[1490 +%- 10]}) !== (1'b1)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",20, (r inside {[1490 +%- 10]}), (1'b1), "r inside {[1490 +%- 10]}", "1'b1"); $stop; end while(0);; + | ^ +%Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:20:161: Unsupported: +%- range + 20 | do if ((r inside {[1490 +%- 10]}) !== (1'b1)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",20, (r inside {[1490 +%- 10]}), (1'b1), "r inside {[1490 +%- 10]}", "1'b1"); $stop; end while(0);; + | ^ +%Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:21:23: Unsupported: +%- range + 21 | do if ((r inside {[1090 +%- 10]}) !== (1'b0)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",21, (r inside {[1090 +%- 10]}), (1'b0), "r inside {[1090 +%- 10]}", "1'b0"); $stop; end while(0);; + | ^ +%Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:21:161: Unsupported: +%- range + 21 | do if ((r inside {[1090 +%- 10]}) !== (1'b0)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",21, (r inside {[1090 +%- 10]}), (1'b0), "r inside {[1090 +%- 10]}", "1'b0"); $stop; end while(0);; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_inside_tolerance_unsup.py b/test_regress/t/t_inside_tolerance_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inside_tolerance_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inside_tolerance_unsup.v b/test_regress/t/t_inside_tolerance_unsup.v new file mode 100644 index 000000000..60cdf5b97 --- /dev/null +++ b/test_regress/t/t_inside_tolerance_unsup.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +module t; + real r; + bit b; + + initial begin + r = 1492.4; + `checkh(r inside {[1492 +/- 2]}, 1'b1); + `checkh(r inside {[1482 +/- 2]}, 1'b0); + `checkh(r inside {[1490 +%- 10]}, 1'b1); + `checkh(r inside {[1090 +%- 10]}, 1'b0); + end + +endmodule diff --git a/test_regress/t/t_mod_macromodule.py b/test_regress/t/t_mod_macromodule.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_mod_macromodule.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_mod_macromodule.v b/test_regress/t/t_mod_macromodule.v new file mode 100644 index 000000000..710246901 --- /dev/null +++ b/test_regress/t/t_mod_macromodule.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +macromodule t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_sequence_sexpr_unsup.out b/test_regress/t/t_sequence_sexpr_unsup.out index 5a73a5851..c43956dfe 100644 --- a/test_regress/t/t_sequence_sexpr_unsup.out +++ b/test_regress/t/t_sequence_sexpr_unsup.out @@ -144,101 +144,110 @@ 90 | a ## [+] b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:93:4: Unsupported: sequence - 93 | sequence s_booleanabbrev_brastar_int; + 93 | sequence s_booleanabbrev_brastar; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:9: Unsupported: [*] boolean abbrev expression - 94 | a [* 1 ]; + 94 | a [*]; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:9: Unsupported: boolean abbrev (in sequence expression) + 94 | a [*]; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:12: Unsupported: boolean abbrev (in sequence expression) - 94 | a [* 1 ]; - | ^ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:96:4: Unsupported: sequence - 96 | sequence s_booleanabbrev_brastar; + 96 | sequence s_booleanabbrev_brastar_int; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:9: Unsupported: [*] boolean abbrev expression - 97 | a [*]; + 97 | a [* 1 ]; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:9: Unsupported: boolean abbrev (in sequence expression) - 97 | a [*]; - | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:99:4: Unsupported: sequence - 99 | sequence s_booleanabbrev_plus; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:9: Unsupported: [+] boolean abbrev expression - 100 | a [+]; - | ^~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:9: Unsupported: boolean abbrev (in sequence expression) - 100 | a [+]; - | ^~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:102:4: Unsupported: sequence - 102 | sequence s_booleanabbrev_eq; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:9: Unsupported: [= boolean abbrev expression - 103 | a [= 1]; - | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:12: Unsupported: boolean abbrev (in sequence expression) - 103 | a [= 1]; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:12: Unsupported: boolean abbrev (in sequence expression) + 97 | a [* 1 ]; | ^ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:99:4: Unsupported: sequence + 99 | sequence s_booleanabbrev_brastar_range; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:9: Unsupported: [*] boolean abbrev expression + 100 | a [* 1 : 2]; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:12: Unsupported: boolean abbrev (in sequence expression) + 100 | a [* 1 : 2]; + | ^ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:102:4: Unsupported: sequence + 102 | sequence s_booleanabbrev_plus; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:9: Unsupported: [+] boolean abbrev expression + 103 | a [+]; + | ^~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:9: Unsupported: boolean abbrev (in sequence expression) + 103 | a [+]; + | ^~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:105:4: Unsupported: sequence - 105 | sequence s_booleanabbrev_eq_range; + 105 | sequence s_booleanabbrev_eq; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:106:9: Unsupported: [= boolean abbrev expression - 106 | a [= 1:2]; + 106 | a [= 1]; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:106:12: Unsupported: boolean abbrev (in sequence expression) - 106 | a [= 1:2]; + 106 | a [= 1]; | ^ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:108:4: Unsupported: sequence - 108 | sequence s_booleanabbrev_minusgt; + 108 | sequence s_booleanabbrev_eq_range; | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:9: Unsupported: [-> boolean abbrev expression - 109 | a [-> 1]; - | ^~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:13: Unsupported: boolean abbrev (in sequence expression) - 109 | a [-> 1]; - | ^ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:9: Unsupported: [= boolean abbrev expression + 109 | a [= 1:2]; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:12: Unsupported: boolean abbrev (in sequence expression) + 109 | a [= 1:2]; + | ^ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:111:4: Unsupported: sequence - 111 | sequence s_booleanabbrev_minusgt_range; + 111 | sequence s_booleanabbrev_minusgt; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:112:9: Unsupported: [-> boolean abbrev expression - 112 | a [-> 1:2]; + 112 | a [-> 1]; | ^~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:112:13: Unsupported: boolean abbrev (in sequence expression) - 112 | a [-> 1:2]; + 112 | a [-> 1]; | ^ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:115:4: Unsupported: sequence - 115 | sequence p_arg_seqence(sequence inseq); +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:114:4: Unsupported: sequence + 114 | sequence s_booleanabbrev_minusgt_range; | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:115:27: Unsupported: sequence argument data type - 115 | sequence p_arg_seqence(sequence inseq); +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:115:9: Unsupported: [-> boolean abbrev expression + 115 | a [-> 1:2]; + | ^~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:115:13: Unsupported: boolean abbrev (in sequence expression) + 115 | a [-> 1:2]; + | ^ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:118:4: Unsupported: sequence + 118 | sequence p_arg_seqence(sequence inseq); + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:118:27: Unsupported: sequence argument data type + 118 | sequence p_arg_seqence(sequence inseq); | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:119:4: Unsupported: sequence - 119 | sequence s_firstmatch_a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:120:7: Unsupported: first_match (in sequence expression) - 120 | first_match (a); - | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:122:4: Unsupported: sequence - 122 | sequence s_firstmatch_ab; + 122 | sequence s_firstmatch_a; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:123:7: Unsupported: first_match (in sequence expression) - 123 | first_match (a, res0 = 1); + 123 | first_match (a); | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:125:4: Unsupported: sequence - 125 | sequence s_firstmatch_abc; + 125 | sequence s_firstmatch_ab; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:126:7: Unsupported: first_match (in sequence expression) - 126 | first_match (a, res0 = 1, res1 = 2); + 126 | first_match (a, res0 = 1); | ^~~~~~~~~~~ -%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:129:10: Ignoring unsupported: cover sequence - 129 | cover sequence (s_a) $display(""); +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:128:4: Unsupported: sequence + 128 | sequence s_firstmatch_abc; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:129:7: Unsupported: first_match (in sequence expression) + 129 | first_match (a, res0 = 1, res1 = 2); + | ^~~~~~~~~~~ +%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:132:10: Ignoring unsupported: cover sequence + 132 | cover sequence (s_a) $display(""); | ^~~~~~~~ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. -%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:130:10: Ignoring unsupported: cover sequence - 130 | cover sequence (@(posedge a) disable iff (b) s_a) $display(""); +%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:133:10: Ignoring unsupported: cover sequence + 133 | cover sequence (@(posedge a) disable iff (b) s_a) $display(""); | ^~~~~~~~ -%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:131:10: Ignoring unsupported: cover sequence - 131 | cover sequence (disable iff (b) s_a) $display(""); +%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:134:10: Ignoring unsupported: cover sequence + 134 | cover sequence (disable iff (b) s_a) $display(""); | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_sequence_sexpr_unsup.v b/test_regress/t/t_sequence_sexpr_unsup.v index da3b99ec2..2503f7cf8 100644 --- a/test_regress/t/t_sequence_sexpr_unsup.v +++ b/test_regress/t/t_sequence_sexpr_unsup.v @@ -90,11 +90,14 @@ module t (/*AUTOARG*/ a ## [+] b; endsequence + sequence s_booleanabbrev_brastar; + a [*]; + endsequence sequence s_booleanabbrev_brastar_int; a [* 1 ]; endsequence - sequence s_booleanabbrev_brastar; - a [*]; + sequence s_booleanabbrev_brastar_range; + a [* 1 : 2]; endsequence sequence s_booleanabbrev_plus; a [+]; diff --git a/test_regress/t/t_specparam.v b/test_regress/t/t_specparam.v index 67ab38219..3dc782844 100644 --- a/test_regress/t/t_specparam.v +++ b/test_regress/t/t_specparam.v @@ -11,6 +11,7 @@ module t; // verilator lint_off MINTYPMAXDLY specparam Tmintypmax = 1.0:1.1:1.2; specparam PATHPULSE$a$b = (3.0:3.1:3.2, 4.0:4.1:4.2); + specparam PATHPULSE$a$c = (3.0:3.1:3.2); specparam randomize = 1; // Special parser corner-case endspecify @@ -33,6 +34,7 @@ module t; `ifdef VERILATOR if (Tmintypmax != 1.1) $stop; if (PATHPULSE$a$b != 3.1) $stop; + if (PATHPULSE$a$c != 3.1) $stop; `endif if (Tranged != 4'b1011) $stop; if (Tmod34 != 3.4) $stop; diff --git a/test_regress/t/t_strength_assignments_constants.py b/test_regress/t/t_strength_assignments_constants.py index c30c310ba..43be79be3 100755 --- a/test_regress/t/t_strength_assignments_constants.py +++ b/test_regress/t/t_strength_assignments_constants.py @@ -11,10 +11,8 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile() +test.compile(verilator_flags2=["--language 1364-2005"]) test.execute() -test.lint(verilator_flags2=["--language 1364-2005"]) - test.passes() diff --git a/test_regress/t/t_strength_assignments_constants.v b/test_regress/t/t_strength_assignments_constants.v index 1f0164e07..f2d6f36e9 100644 --- a/test_regress/t/t_strength_assignments_constants.v +++ b/test_regress/t/t_strength_assignments_constants.v @@ -5,34 +5,37 @@ // SPDX-License-Identifier: CC0-1.0 module t; - wire a; - assign (weak0, weak1) a = 1; - assign (weak0, supply1) a = 1; - assign (strong0, strong1) a = 0; + wire a; + assign (weak0, weak1) a = 1; + assign (weak0, supply1) a = 1; + assign (strong0, strong1) a = 0; - wire (weak0, weak1) b = 1; - assign (strong0, strong1) b = 0; + wire (weak0, weak1) b = 1; + assign (strong0, strong1) b = 0; - wire [1:0] c; - assign (weak0, supply1) c = 2'b11; - assign (supply0, pull1) c = 2'b11; - assign (strong0, strong1) c = 0; + wire [1:0] c; + assign (weak0, supply1) c = 2'b11; + assign (supply0, pull1) c = 2'b11; + assign (strong0, strong1) c = 0; - supply0 d; - assign (strong0, strong1) d = 1; + wire [1:0] cr; + assign (supply1, weak0) cr = 2'b11; + assign (pull1, supply0) cr = 2'b11; + assign (strong1, strong0) cr = 0; - wire (supply0, supply1) e = 1'bz; - assign (weak0, weak1) e = 1; + supply0 d; + assign (strong0, strong1) d = 1; - always begin - if (a && !b && c === 2'b11 && !d && e) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("Error: a = %b, b = %b, c = %b, d = %b, e = %b ", a, b, c, d, e); - $write("expected: a = 1, b = 0, c = 11, d = 0, e = 1\n"); - $stop; - end - end + wire (supply0, supply1) e = 1'bz; + assign (weak0, weak1) e = 1; + + always begin + if (a !== 1'b1) $stop; + if (b !== 1'b0) $stop; + if (c !== 2'b11) $stop; + if (cr !== 2'b11) $stop; + if (e !== 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule