From 2fff92fe7814fe1d83eba3d86acc5c44991773d6 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 29 Jun 2019 08:12:00 -0400
Subject: [PATCH] Tests: Add array MDA test.

---
 test_regress/t/t_array_mda.pl | 20 +++++++++
 test_regress/t/t_array_mda.v  | 76 +++++++++++++++++++++++++++++++++++
 2 files changed, 96 insertions(+)
 create mode 100755 test_regress/t/t_array_mda.pl
 create mode 100644 test_regress/t/t_array_mda.v

diff --git a/test_regress/t/t_array_mda.pl b/test_regress/t/t_array_mda.pl
new file mode 100755
index 000000000..6b3b15be5
--- /dev/null
+++ b/test_regress/t/t_array_mda.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_array_mda.v b/test_regress/t/t_array_mda.v
new file mode 100644
index 000000000..899714d5d
--- /dev/null
+++ b/test_regress/t/t_array_mda.v
@@ -0,0 +1,76 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer      cyc=0;
+   reg [63:0]   crc;
+   reg [63:0]   sum;
+
+   // msg2946
+   int A [7][1], B [8][1];
+   int a    [1], b    [1];
+   always_ff @(posedge clk) begin
+`ifdef verilator  // msg2946
+ `define WORK_AROUND
+`endif
+`ifdef WORK_AROUND
+      a <= A[0];
+      b <= B[crc[2:0]];
+`else
+      a <= A[crc[2:0]];
+      b <= B[0];
+`endif
+   end
+   wire [63:0] result = {a[0], b[0]};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
+         sum <= '0;
+         A[0][0] <= 32'h1_0;
+         A[1][0] <= 32'h1_1;
+         A[2][0] <= 32'h1_2;
+         A[3][0] <= 32'h1_3;
+         A[4][0] <= 32'h1_4;
+         A[5][0] <= 32'h1_5;
+         A[6][0] <= 32'h1_6;
+         B[0][0] <= 32'h2_0;
+         B[1][0] <= 32'h2_1;
+         B[2][0] <= 32'h2_2;
+         B[3][0] <= 32'h2_3;
+         B[4][0] <= 32'h2_4;
+         B[5][0] <= 32'h2_5;
+         B[6][0] <= 32'h2_6;
+         B[7][0] <= 32'h2_7;
+      end
+      else if (cyc<10) begin
+         sum <= '0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+         $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'had01cfb7e84da129
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule