diff --git a/test_regress/t/t_castdyn.out b/test_regress/t/t_castdyn.out index 8f9e32b5e..14761e02a 100644 --- a/test_regress/t/t_castdyn.out +++ b/test_regress/t/t_castdyn.out @@ -1,9 +1,29 @@ -%Error-UNSUPPORTED: t/t_castdyn.v:12:11: Unsupported: $cast. Suggest try static cast. +%Error-UNSUPPORTED: t/t_castdyn.v:28:11: Unsupported: $cast. Suggest try static cast. : ... In instance t - 12 | i = $cast(a, b); + 28 | i = $cast(ao, a); | ^~~~~ -%Error-UNSUPPORTED: t/t_castdyn.v:14:7: Unsupported: $cast. Suggest try static cast. +%Error-UNSUPPORTED: t/t_castdyn.v:32:7: Unsupported: $cast. Suggest try static cast. : ... In instance t - 14 | $cast(a, b); + 32 | $cast(ao, a); | ^~~~~ +%Error-UNSUPPORTED: t/t_castdyn.v:35:11: Unsupported: $cast. Suggest try static cast. + : ... In instance t + 35 | i = $cast(ao, 2.1 * 3.7); + | ^~~~~ +%Error-UNSUPPORTED: t/t_castdyn.v:39:11: Unsupported: $cast. Suggest try static cast. + : ... In instance t + 39 | i = $cast(bo, null); + | ^~~~~ +%Error-UNSUPPORTED: t/t_castdyn.v:45:11: Unsupported: $cast. Suggest try static cast. + : ... In instance t + 45 | i = $cast(bao, b); + | ^~~~~ +%Error-UNSUPPORTED: t/t_castdyn.v:51:11: Unsupported: $cast. Suggest try static cast. + : ... In instance t + 51 | i = $cast(bbo, b); + | ^~~~~ +%Error-UNSUPPORTED: t/t_castdyn.v:57:11: Unsupported: $cast. Suggest try static cast. + : ... In instance t + 57 | i = $cast(bao, b); + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_castdyn.v b/test_regress/t/t_castdyn.v index 3fd235e82..2d788ca51 100644 --- a/test_regress/t/t_castdyn.v +++ b/test_regress/t/t_castdyn.v @@ -4,14 +4,59 @@ // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +class Base; +endclass +class BasedA extends Base; +endclass +class BasedB extends Base; +endclass + module t (/*AUTOARG*/); int i; int a; - int b; + int ao; + + Base b; + Base bo; + BasedA ba; + BasedA bao; + BasedB bb; + BasedB bbo; + initial begin - i = $cast(a, b); + a = 1234; + i = $cast(ao, a); if (i != 1) $stop; - $cast(a, b); + if (ao != 1234) $stop; + a = 12345; + $cast(ao, a); + if (ao != 12345) $stop; + + i = $cast(ao, 2.1 * 3.7); + if (i != 1) $stop; + if (ao != 8) $stop; + + i = $cast(bo, null); + if (i != 1) $stop; + if (bo != null) $stop; + + ba = new; + b = ba; + i = $cast(bao, b); + if (i != 1) $stop; + if (b != ba) $stop; + + bb = new; + b = bb; + i = $cast(bbo, b); + if (i != 1) $stop; + if (b != bb) $stop; + + bb = new; + b = b; + i = $cast(bao, b); + if (i != 0) $stop; + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_castdyn_bad.out b/test_regress/t/t_castdyn_bad.out new file mode 100644 index 000000000..030a8b1ac --- /dev/null +++ b/test_regress/t/t_castdyn_bad.out @@ -0,0 +1,9 @@ +%Error-UNSUPPORTED: t/t_castdyn_bad.v:20:11: Unsupported: $cast. Suggest try static cast. + : ... In instance t + 20 | i = $cast(c, b); + | ^~~~~ +%Error-UNSUPPORTED: t/t_castdyn_bad.v:23:7: Unsupported: $cast. Suggest try static cast. + : ... In instance t + 23 | $cast(c, b); + | ^~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_castdyn_bad.pl b/test_regress/t/t_castdyn_bad.pl new file mode 100755 index 000000000..2ad4a887d --- /dev/null +++ b/test_regress/t/t_castdyn_bad.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +execute( + check_finished => 1, + ) if !$Self->{vlt_all}; + +ok(1); +1; diff --git a/test_regress/t/t_castdyn_bad.v b/test_regress/t/t_castdyn_bad.v new file mode 100644 index 000000000..37fe1ec74 --- /dev/null +++ b/test_regress/t/t_castdyn_bad.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class Base; +endclass +class C; +endclass + +module t (/*AUTOARG*/); + int i; + + Base b; + C c; + + initial begin + b = new; + i = $cast(c, b); + if (i != 0) $stop; + + $cast(c, b); // Bad at runtime + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule