From 2f01775ba92e9dd6fa9fe7693b2d73339a3b3454 Mon Sep 17 00:00:00 2001 From: Artur Bieniek Date: Thu, 18 Jun 2026 14:30:52 +0200 Subject: [PATCH] Fix unstable --vltmt test Signed-off-by: Artur Bieniek --- test_regress/t/t_assert_iff_clk.py | 3 +-- test_regress/t/t_assert_iff_clk.v | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/test_regress/t/t_assert_iff_clk.py b/test_regress/t/t_assert_iff_clk.py index fd4b2dc44..35e44000c 100755 --- a/test_regress/t/t_assert_iff_clk.py +++ b/test_regress/t/t_assert_iff_clk.py @@ -9,8 +9,7 @@ import vltest_bootstrap -# Issue #7781 unstable with --vltmt -test.scenarios('simulator_st') +test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_assert_iff_clk.v b/test_regress/t/t_assert_iff_clk.v index 3dfb3458b..73c8b82b5 100644 --- a/test_regress/t/t_assert_iff_clk.v +++ b/test_regress/t/t_assert_iff_clk.v @@ -32,7 +32,7 @@ module t ( assert property (@(posedge clk) disable iff (cyc < 5) 1 ##1 0) else post_temporal_fail++; - always @(posedge clk) begin + always @(negedge clk) begin cyc <= cyc + 1; rst <= cyc < 4; x <= cyc < 4;