diff --git a/Changes b/Changes index 170c22ef6..0c3d0057f 100644 --- a/Changes +++ b/Changes @@ -23,6 +23,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix tracing of package variables and real arrays. +**** Fix tracing of packed arrays without --trace-structs, bug742. [Jie Xu] + **** Fix missing coverage line on else-if, bug727. [Sharad Bagri] **** Fix modport function import not-found error. diff --git a/src/V3Ast.h b/src/V3Ast.h index 88ee7ba64..32399dab9 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -615,7 +615,9 @@ struct VNumRange { int hiMaxSelect() const { return (lo()<0 ? hi()-lo() : hi()); } // Maximum value a [] select may index bool representableByWidth() const // Could be represented by just width=1, or [width-1:0] { return (!m_ranged || (m_lo==0 && m_hi>=1 && !m_littleEndian)); } + void dump(ostream& str) const { if (ranged()) str<<"["<AstNodeDType::dumpSmall(str); if (castPackArrayDType()) str<<"p"; else str<<"u"; - str<<"["<AstNodeDType::dump(str); - str<<" ["<AstNode::dump(str); @@ -855,7 +855,7 @@ void AstPackageImport::dump(ostream& str) { void AstSel::dump(ostream& str) { this->AstNode::dump(str); if (declRange().ranged()) { - str<<" decl["<addStmtsp(nodep); } - void addTraceDecl(const VNumRange& arrayRange) { + void addTraceDecl(const VNumRange& arrayRange, + int widthOverride) { // If !=0, is packed struct/array where basicp size misreflects one element VNumRange bitRange; AstBasicDType* bdtypep = m_traValuep->dtypep()->basicp(); - if (bdtypep) bitRange = bdtypep->nrange(); + if (widthOverride) bitRange = VNumRange(widthOverride-1,0,false); + else if (bdtypep) bitRange = bdtypep->nrange(); AstTraceDecl* declp = new AstTraceDecl(m_traVscp->fileline(), m_traShowname, m_traValuep, bitRange, arrayRange); + UINFO(9,"Decl "< v3Global.opt.outputSplitCTrace()) { @@ -199,7 +202,7 @@ private: && m_traVscp->dtypep()->skipRefp() == nodep) { // Nothing above this array // Simple 1-D array, use exising V3EmitC runtime loop rather than unrolling // This will put "(index)" at end of signal name for us - addTraceDecl(nodep->declRange()); + addTraceDecl(nodep->declRange(), 0); } else { // Unroll now, as have no other method to get right signal names AstNodeDType* subtypep = nodep->subDTypep()->skipRefp(); @@ -225,7 +228,7 @@ private: if (!v3Global.opt.traceStructs()) { // Everything downstream is packed, so deal with as one trace unit // This may not be the nicest for user presentation, but is a much faster way to trace - addTraceDecl(VNumRange()); + addTraceDecl(VNumRange(), nodep->width()); } else { AstNodeDType* subtypep = nodep->subDTypep()->skipRefp(); for (int i=nodep->lsb(); i<=nodep->msb(); ++i) { @@ -250,7 +253,7 @@ private: if (nodep->packed() && !v3Global.opt.traceStructs()) { // Everything downstream is packed, so deal with as one trace unit // This may not be the nicest for user presentation, but is a much faster way to trace - addTraceDecl(VNumRange()); + addTraceDecl(VNumRange(), nodep->width()); } else { if (!nodep->packed()) { addIgnore("Unsupported: Unpacked struct/union"); @@ -282,7 +285,7 @@ private: if (nodep->keyword()==AstBasicDTypeKwd::STRING) { addIgnore("Unsupported: strings"); } else { - addTraceDecl(VNumRange()); + addTraceDecl(VNumRange(), 0); } } } diff --git a/test_regress/t/t_trace_complex.out b/test_regress/t/t_trace_complex.out index 9dde10fbb..ea1006e99 100644 --- a/test_regress/t/t_trace_complex.out +++ b/test_regress/t/t_trace_complex.out @@ -1,45 +1,46 @@ $version Generated by VerilatedVcd $end -$date Fri Mar 14 20:31:17 2014 +$date Tue Apr 15 19:42:28 2014 $end $timescale 1ns $end $scope module top $end - $var wire 1 7 clk $end + $var wire 1 9 clk $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end $scope module v $end - $var wire 1 7 clk $end + $var wire 1 9 clk $end $var wire 32 $ cyc [31:0] $end - $var real 64 1 v_arr_real(0) $end - $var real 64 3 v_arr_real(1) $end - $var wire 2 ( v_arrp [2:1] $end - $var wire 2 ) v_arrp_arrp [2:1] $end - $var wire 2 * v_arrp_strp [1:0] $end - $var wire 1 8 v_arru(1) $end - $var wire 1 9 v_arru(2) $end - $var wire 2 + v_arru_arrp(3) [2:1] $end - $var wire 2 , v_arru_arrp(4) [2:1] $end - $var wire 1 : v_arru_arru(3)(1) $end - $var wire 1 ; v_arru_arru(3)(2) $end - $var wire 1 < v_arru_arru(4)(1) $end - $var wire 1 = v_arru_arru(4)(2) $end - $var wire 2 - v_arru_strp(3) [1:0] $end - $var wire 2 . v_arru_strp(4) [1:0] $end - $var real 64 / v_real $end - $var wire 2 % v_strp [1:0] $end - $var wire 4 & v_strp_strp [3:0] $end - $var wire 2 ' v_unip_strp [1:0] $end + $var real 64 3 v_arr_real(0) $end + $var real 64 5 v_arr_real(1) $end + $var wire 2 * v_arrp [2:1] $end + $var wire 4 + v_arrp_arrp [3:0] $end + $var wire 4 , v_arrp_strp [3:0] $end + $var wire 1 : v_arru(1) $end + $var wire 1 ; v_arru(2) $end + $var wire 2 - v_arru_arrp(3) [2:1] $end + $var wire 2 . v_arru_arrp(4) [2:1] $end + $var wire 1 < v_arru_arru(3)(1) $end + $var wire 1 = v_arru_arru(3)(2) $end + $var wire 1 > v_arru_arru(4)(1) $end + $var wire 1 ? v_arru_arru(4)(2) $end + $var wire 2 / v_arru_strp(3) [1:0] $end + $var wire 2 0 v_arru_strp(4) [1:0] $end + $var real 64 1 v_real $end + $var wire 64 % v_str32x2 [63:0] $end + $var wire 2 ' v_strp [1:0] $end + $var wire 4 ( v_strp_strp [3:0] $end + $var wire 2 ) v_unip_strp [1:0] $end $scope module p2 $end - $var wire 32 > PARAM [31:0] $end + $var wire 32 @ PARAM [31:0] $end $upscope $end $scope module p3 $end - $var wire 32 ? PARAM [31:0] $end + $var wire 32 A PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 5 b [31:0] $end + $var wire 32 7 b [31:0] $end $scope module unnamedblk2 $end - $var wire 32 6 a [31:0] $end + $var wire 32 8 a [31:0] $end $upscope $end $upscope $end $upscope $end @@ -50,135 +51,142 @@ $enddefinitions $end #0 1# b00000000000000000000000000000000 $ -b00 % -b0000 & +b0000000000000000000000000000000000000000000000000000000011111111 % b00 ' -b00 ( -b0000 ) -b0000 * -b00 + -b00 , +b0000 ( +b00 ) +b00 * +b0000 + +b0000 , b00 - b00 . -r0 / +b00 / +b00 0 r0 1 r0 3 -b00000000000000000000000000000000 5 -b00000000000000000000000000000000 6 -07 -08 +r0 5 +b00000000000000000000000000000000 7 +b00000000000000000000000000000000 8 09 0: 0; 0< 0= -b00000000000000000000000000000010 > -b00000000000000000000000000000011 ? +0> +0? +b00000000000000000000000000000010 @ +b00000000000000000000000000000011 A #10 b00000000000000000000000000000001 $ -b11 % -b1111 & +b0000000000000000000000000000000100000000000000000000000011111110 % b11 ' -b11 ( -b1111 ) -b1111 * -b11 + -b11 , +b1111 ( +b11 ) +b11 * +b1111 + +b1111 , b11 - b11 . -r0.1 / -r0.2 1 -r0.3 3 -b00000000000000000000000000000101 5 -b00000000000000000000000000000101 6 -17 +b11 / +b11 0 +r0.1 1 +r0.2 3 +r0.3 5 +b00000000000000000000000000000101 7 +b00000000000000000000000000000101 8 +19 #15 -07 +09 #20 b00000000000000000000000000000010 $ -b00 % -b0000 & +b0000000000000000000000000000001000000000000000000000000011111101 % b00 ' -b00 ( -b0000 ) -b0000 * -b00 + -b00 , +b0000 ( +b00 ) +b00 * +b0000 + +b0000 , b00 - b00 . -r0.2 / -r0.4 1 -r0.6 3 -17 +b00 / +b00 0 +r0.2 1 +r0.4 3 +r0.6 5 +19 #25 -07 +09 #30 b00000000000000000000000000000011 $ -b11 % -b1111 & +b0000000000000000000000000000001100000000000000000000000011111100 % b11 ' -b11 ( -b1111 ) -b1111 * -b11 + -b11 , +b1111 ( +b11 ) +b11 * +b1111 + +b1111 , b11 - b11 . -r0.3 / -r0.6000000000000001 1 -r0.8999999999999999 3 -17 +b11 / +b11 0 +r0.3 1 +r0.6000000000000001 3 +r0.8999999999999999 5 +19 #35 -07 +09 #40 b00000000000000000000000000000100 $ -b00 % -b0000 & +b0000000000000000000000000000010000000000000000000000000011111011 % b00 ' -b00 ( -b0000 ) -b0000 * -b00 + -b00 , +b0000 ( +b00 ) +b00 * +b0000 + +b0000 , b00 - b00 . -r0.4 / -r0.8 1 -r1.2 3 -17 +b00 / +b00 0 +r0.4 1 +r0.8 3 +r1.2 5 +19 #45 -07 +09 #50 b00000000000000000000000000000101 $ -b11 % -b1111 & +b0000000000000000000000000000010100000000000000000000000011111010 % b11 ' -b11 ( -b1111 ) -b1111 * -b11 + -b11 , +b1111 ( +b11 ) +b11 * +b1111 + +b1111 , b11 - b11 . -r0.5 / -r1 1 -r1.5 3 -17 +b11 / +b11 0 +r0.5 1 +r1 3 +r1.5 5 +19 #55 -07 +09 #60 b00000000000000000000000000000110 $ -b00 % -b0000 & +b0000000000000000000000000000011000000000000000000000000011111001 % b00 ' -b00 ( -b0000 ) -b0000 * -b00 + -b00 , +b0000 ( +b00 ) +b00 * +b0000 + +b0000 , b00 - b00 . -r0.6 / -r1.2 1 -r1.8 3 -17 +b00 / +b00 0 +r0.6 1 +r1.2 3 +r1.8 5 +19 diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v index c57e440a8..da3fd399f 100644 --- a/test_regress/t/t_trace_complex.v +++ b/test_regress/t/t_trace_complex.v @@ -49,6 +49,13 @@ module t (clk); real v_arr_real [2]; string v_string; + typedef struct packed { + logic [31:0] data; + } str32_t; + str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0 + initial v_str32x2[0] = 32'hff; + initial v_str32x2[1] = 0; + p #(.PARAM(2)) p2 (); p #(.PARAM(3)) p3 (); @@ -72,6 +79,8 @@ module t (clk); v_arru_arru[a][b] = ~v_arru_arru[a][b]; end end + v_str32x2[0] <= v_str32x2[0] - 1; + v_str32x2[1] <= v_str32x2[1] + 1; if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_trace_complex_params.out b/test_regress/t/t_trace_complex_params.out index a55094151..850d62d35 100644 --- a/test_regress/t/t_trace_complex_params.out +++ b/test_regress/t/t_trace_complex_params.out @@ -1,45 +1,46 @@ $version Generated by VerilatedVcd $end -$date Fri Mar 14 20:32:05 2014 +$date Tue Apr 15 19:42:37 2014 $end $timescale 1ns $end $scope module top $end - $var wire 1 7 clk $end + $var wire 1 9 clk $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end $scope module v $end - $var wire 1 7 clk $end + $var wire 1 9 clk $end $var wire 32 $ cyc [31:0] $end - $var real 64 1 v_arr_real(0) $end - $var real 64 3 v_arr_real(1) $end - $var wire 2 ( v_arrp [2:1] $end - $var wire 2 ) v_arrp_arrp [2:1] $end - $var wire 2 * v_arrp_strp [1:0] $end - $var wire 1 8 v_arru(1) $end - $var wire 1 9 v_arru(2) $end - $var wire 2 + v_arru_arrp(3) [2:1] $end - $var wire 2 , v_arru_arrp(4) [2:1] $end - $var wire 1 : v_arru_arru(3)(1) $end - $var wire 1 ; v_arru_arru(3)(2) $end - $var wire 1 < v_arru_arru(4)(1) $end - $var wire 1 = v_arru_arru(4)(2) $end - $var wire 2 - v_arru_strp(3) [1:0] $end - $var wire 2 . v_arru_strp(4) [1:0] $end - $var real 64 / v_real $end - $var wire 2 % v_strp [1:0] $end - $var wire 4 & v_strp_strp [3:0] $end - $var wire 2 ' v_unip_strp [1:0] $end + $var real 64 3 v_arr_real(0) $end + $var real 64 5 v_arr_real(1) $end + $var wire 2 * v_arrp [2:1] $end + $var wire 4 + v_arrp_arrp [3:0] $end + $var wire 4 , v_arrp_strp [3:0] $end + $var wire 1 : v_arru(1) $end + $var wire 1 ; v_arru(2) $end + $var wire 2 - v_arru_arrp(3) [2:1] $end + $var wire 2 . v_arru_arrp(4) [2:1] $end + $var wire 1 < v_arru_arru(3)(1) $end + $var wire 1 = v_arru_arru(3)(2) $end + $var wire 1 > v_arru_arru(4)(1) $end + $var wire 1 ? v_arru_arru(4)(2) $end + $var wire 2 / v_arru_strp(3) [1:0] $end + $var wire 2 0 v_arru_strp(4) [1:0] $end + $var real 64 1 v_real $end + $var wire 64 % v_str32x2 [63:0] $end + $var wire 2 ' v_strp [1:0] $end + $var wire 4 ( v_strp_strp [3:0] $end + $var wire 2 ) v_unip_strp [1:0] $end $scope module p2 $end - $var wire 32 > PARAM [31:0] $end + $var wire 32 @ PARAM [31:0] $end $upscope $end $scope module p3 $end - $var wire 32 ? PARAM [31:0] $end + $var wire 32 A PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 5 b [31:0] $end + $var wire 32 7 b [31:0] $end $scope module unnamedblk2 $end - $var wire 32 6 a [31:0] $end + $var wire 32 8 a [31:0] $end $upscope $end $upscope $end $upscope $end @@ -50,135 +51,142 @@ $enddefinitions $end #0 1# b00000000000000000000000000000000 $ -b00 % -b0000 & +b0000000000000000000000000000000000000000000000000000000011111111 % b00 ' -b00 ( -b0000 ) -b0000 * -b00 + -b00 , +b0000 ( +b00 ) +b00 * +b0000 + +b0000 , b00 - b00 . -r0 / +b00 / +b00 0 r0 1 r0 3 -b00000000000000000000000000000000 5 -b00000000000000000000000000000000 6 -07 -08 +r0 5 +b00000000000000000000000000000000 7 +b00000000000000000000000000000000 8 09 0: 0; 0< 0= -b00000000000000000000000000000010 > -b00000000000000000000000000000011 ? +0> +0? +b00000000000000000000000000000010 @ +b00000000000000000000000000000011 A #10 b00000000000000000000000000000001 $ -b11 % -b1111 & +b0000000000000000000000000000000100000000000000000000000011111110 % b11 ' -b11 ( -b1111 ) -b1111 * -b11 + -b11 , +b1111 ( +b11 ) +b11 * +b1111 + +b1111 , b11 - b11 . -r0.1 / -r0.2 1 -r0.3 3 -b00000000000000000000000000000101 5 -b00000000000000000000000000000101 6 -17 +b11 / +b11 0 +r0.1 1 +r0.2 3 +r0.3 5 +b00000000000000000000000000000101 7 +b00000000000000000000000000000101 8 +19 #15 -07 +09 #20 b00000000000000000000000000000010 $ -b00 % -b0000 & +b0000000000000000000000000000001000000000000000000000000011111101 % b00 ' -b00 ( -b0000 ) -b0000 * -b00 + -b00 , +b0000 ( +b00 ) +b00 * +b0000 + +b0000 , b00 - b00 . -r0.2 / -r0.4 1 -r0.6 3 -17 +b00 / +b00 0 +r0.2 1 +r0.4 3 +r0.6 5 +19 #25 -07 +09 #30 b00000000000000000000000000000011 $ -b11 % -b1111 & +b0000000000000000000000000000001100000000000000000000000011111100 % b11 ' -b11 ( -b1111 ) -b1111 * -b11 + -b11 , +b1111 ( +b11 ) +b11 * +b1111 + +b1111 , b11 - b11 . -r0.3 / -r0.6000000000000001 1 -r0.8999999999999999 3 -17 +b11 / +b11 0 +r0.3 1 +r0.6000000000000001 3 +r0.8999999999999999 5 +19 #35 -07 +09 #40 b00000000000000000000000000000100 $ -b00 % -b0000 & +b0000000000000000000000000000010000000000000000000000000011111011 % b00 ' -b00 ( -b0000 ) -b0000 * -b00 + -b00 , +b0000 ( +b00 ) +b00 * +b0000 + +b0000 , b00 - b00 . -r0.4 / -r0.8 1 -r1.2 3 -17 +b00 / +b00 0 +r0.4 1 +r0.8 3 +r1.2 5 +19 #45 -07 +09 #50 b00000000000000000000000000000101 $ -b11 % -b1111 & +b0000000000000000000000000000010100000000000000000000000011111010 % b11 ' -b11 ( -b1111 ) -b1111 * -b11 + -b11 , +b1111 ( +b11 ) +b11 * +b1111 + +b1111 , b11 - b11 . -r0.5 / -r1 1 -r1.5 3 -17 +b11 / +b11 0 +r0.5 1 +r1 3 +r1.5 5 +19 #55 -07 +09 #60 b00000000000000000000000000000110 $ -b00 % -b0000 & +b0000000000000000000000000000011000000000000000000000000011111001 % b00 ' -b00 ( -b0000 ) -b0000 * -b00 + -b00 , +b0000 ( +b00 ) +b00 * +b0000 + +b0000 , b00 - b00 . -r0.6 / -r1.2 1 -r1.8 3 -17 +b00 / +b00 0 +r0.6 1 +r1.2 3 +r1.8 5 +19 diff --git a/test_regress/t/t_trace_complex_structs.out b/test_regress/t/t_trace_complex_structs.out index 850a29c03..f1274bc1b 100644 --- a/test_regress/t/t_trace_complex_structs.out +++ b/test_regress/t/t_trace_complex_structs.out @@ -1,74 +1,80 @@ $version Generated by VerilatedVcd $end -$date Fri Mar 14 20:32:11 2014 +$date Tue Apr 15 12:58:17 2014 $end $timescale 1ns $end $scope module top $end - $var wire 1 B clk $end + $var wire 1 D clk $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end $scope module v $end - $var wire 1 B clk $end + $var wire 1 D clk $end $var wire 32 $ cyc [31:0] $end - $var real 64 < v_arr_real(0) $end - $var real 64 > v_arr_real(1) $end - $var wire 2 - v_arrp [2:1] $end - $var wire 2 . v_arrp_arrp(3) [1:0] $end - $var wire 2 / v_arrp_arrp(4) [1:0] $end - $var wire 1 C v_arru(1) $end - $var wire 1 D v_arru(2) $end - $var wire 2 4 v_arru_arrp(3) [2:1] $end - $var wire 2 5 v_arru_arrp(4) [2:1] $end - $var wire 1 E v_arru_arru(3)(1) $end - $var wire 1 F v_arru_arru(3)(2) $end - $var wire 1 G v_arru_arru(4)(1) $end - $var wire 1 H v_arru_arru(4)(2) $end - $var real 64 : v_real $end + $var real 64 > v_arr_real(0) $end + $var real 64 @ v_arr_real(1) $end + $var wire 2 / v_arrp [2:1] $end + $var wire 2 0 v_arrp_arrp(3) [1:0] $end + $var wire 2 1 v_arrp_arrp(4) [1:0] $end + $var wire 1 E v_arru(1) $end + $var wire 1 F v_arru(2) $end + $var wire 2 6 v_arru_arrp(3) [2:1] $end + $var wire 2 7 v_arru_arrp(4) [2:1] $end + $var wire 1 G v_arru_arru(3)(1) $end + $var wire 1 H v_arru_arru(3)(2) $end + $var wire 1 I v_arru_arru(4)(1) $end + $var wire 1 J v_arru_arru(4)(2) $end + $var real 64 < v_real $end $scope module unnamedblk1 $end - $var wire 32 @ b [31:0] $end + $var wire 32 B b [31:0] $end $scope module unnamedblk2 $end - $var wire 32 A a [31:0] $end + $var wire 32 C a [31:0] $end $upscope $end $upscope $end $scope module v_arrp_strp(3) $end - $var wire 1 1 b0 $end - $var wire 1 0 b1 $end - $upscope $end - $scope module v_arrp_strp(4) $end $var wire 1 3 b0 $end $var wire 1 2 b1 $end $upscope $end - $scope module v_arru_strp(3) $end - $var wire 1 7 b0 $end - $var wire 1 6 b1 $end + $scope module v_arrp_strp(4) $end + $var wire 1 5 b0 $end + $var wire 1 4 b1 $end $upscope $end - $scope module v_arru_strp(4) $end + $scope module v_arru_strp(3) $end $var wire 1 9 b0 $end $var wire 1 8 b1 $end $upscope $end + $scope module v_arru_strp(4) $end + $var wire 1 ; b0 $end + $var wire 1 : b1 $end + $upscope $end + $scope module v_str32x2(0) $end + $var wire 32 % data [31:0] $end + $upscope $end + $scope module v_str32x2(1) $end + $var wire 32 & data [31:0] $end + $upscope $end $scope module v_strp $end - $var wire 1 & b0 $end - $var wire 1 % b1 $end + $var wire 1 ( b0 $end + $var wire 1 ' b1 $end $upscope $end $scope module v_strp_strp $end $scope module x0 $end - $var wire 1 * b0 $end - $var wire 1 ) b1 $end + $var wire 1 , b0 $end + $var wire 1 + b1 $end $upscope $end $scope module x1 $end - $var wire 1 ( b0 $end - $var wire 1 ' b1 $end + $var wire 1 * b0 $end + $var wire 1 ) b1 $end $upscope $end $upscope $end $scope module v_unip_strp $end $scope module x0 $end - $var wire 1 , b0 $end - $var wire 1 + b1 $end + $var wire 1 . b0 $end + $var wire 1 - b1 $end $upscope $end $scope module x1 $end - $var wire 1 , b0 $end - $var wire 1 + b1 $end + $var wire 1 . b0 $end + $var wire 1 - b1 $end $upscope $end $upscope $end $upscope $end @@ -79,210 +85,224 @@ $enddefinitions $end #0 1# b00000000000000000000000000000000 $ -0% -0& +b00000000000000000000000011111111 % +b00000000000000000000000000000000 & 0' 0( 0) 0* 0+ 0, -b00 - -b00 . +0- +0. b00 / -00 -01 +b00 0 +b00 1 02 03 -b00 4 -b00 5 -06 -07 +04 +05 +b00 6 +b00 7 08 09 -r0 : +0: +0; r0 < r0 > -b00000000000000000000000000000000 @ -b00000000000000000000000000000000 A -0B -0C +r0 @ +b00000000000000000000000000000000 B +b00000000000000000000000000000000 C 0D 0E 0F 0G 0H +0I +0J #10 b00000000000000000000000000000001 $ -1% -1& +b00000000000000000000000011111110 % +b00000000000000000000000000000001 & 1' 1( 1) 1* 1+ 1, -b11 - -b11 . +1- +1. b11 / -10 -11 +b11 0 +b11 1 12 13 -b11 4 -b11 5 -16 -17 +14 +15 +b11 6 +b11 7 18 19 -r0.1 : -r0.2 < -r0.3 > -b00000000000000000000000000000101 @ -b00000000000000000000000000000101 A -1B +1: +1; +r0.1 < +r0.2 > +r0.3 @ +b00000000000000000000000000000101 B +b00000000000000000000000000000101 C +1D #15 -0B +0D #20 b00000000000000000000000000000010 $ -0% -0& +b00000000000000000000000011111101 % +b00000000000000000000000000000010 & 0' 0( 0) 0* 0+ 0, -b00 - -b00 . +0- +0. b00 / -00 -01 +b00 0 +b00 1 02 03 -b00 4 -b00 5 -06 -07 +04 +05 +b00 6 +b00 7 08 09 -r0.2 : -r0.4 < -r0.6 > -1B +0: +0; +r0.2 < +r0.4 > +r0.6 @ +1D #25 -0B +0D #30 b00000000000000000000000000000011 $ -1% -1& +b00000000000000000000000011111100 % +b00000000000000000000000000000011 & 1' 1( 1) 1* 1+ 1, -b11 - -b11 . +1- +1. b11 / -10 -11 +b11 0 +b11 1 12 13 -b11 4 -b11 5 -16 -17 +14 +15 +b11 6 +b11 7 18 19 -r0.3 : -r0.6000000000000001 < -r0.8999999999999999 > -1B +1: +1; +r0.3 < +r0.6000000000000001 > +r0.8999999999999999 @ +1D #35 -0B +0D #40 b00000000000000000000000000000100 $ -0% -0& +b00000000000000000000000011111011 % +b00000000000000000000000000000100 & 0' 0( 0) 0* 0+ 0, -b00 - -b00 . +0- +0. b00 / -00 -01 +b00 0 +b00 1 02 03 -b00 4 -b00 5 -06 -07 +04 +05 +b00 6 +b00 7 08 09 -r0.4 : -r0.8 < -r1.2 > -1B +0: +0; +r0.4 < +r0.8 > +r1.2 @ +1D #45 -0B +0D #50 b00000000000000000000000000000101 $ -1% -1& +b00000000000000000000000011111010 % +b00000000000000000000000000000101 & 1' 1( 1) 1* 1+ 1, -b11 - -b11 . +1- +1. b11 / -10 -11 +b11 0 +b11 1 12 13 -b11 4 -b11 5 -16 -17 +14 +15 +b11 6 +b11 7 18 19 -r0.5 : -r1 < -r1.5 > -1B +1: +1; +r0.5 < +r1 > +r1.5 @ +1D #55 -0B +0D #60 b00000000000000000000000000000110 $ -0% -0& +b00000000000000000000000011111001 % +b00000000000000000000000000000110 & 0' 0( 0) 0* 0+ 0, -b00 - -b00 . +0- +0. b00 / -00 -01 +b00 0 +b00 1 02 03 -b00 4 -b00 5 -06 -07 +04 +05 +b00 6 +b00 7 08 09 -r0.6 : -r1.2 < -r1.8 > -1B +0: +0; +r0.6 < +r1.2 > +r1.8 @ +1D