diff --git a/src/V3Link.cpp b/src/V3Link.cpp
index e7d2e2f18..aaa456f78 100644
--- a/src/V3Link.cpp
+++ b/src/V3Link.cpp
@@ -467,6 +467,9 @@ private:
 		nodep->iterateChildren(*this);
 		m_cellVarsp = NULL;
 	    }
+	    else if (m_idState==ID_PARAM) {
+		nodep->iterateChildren(*this);
+	    }
 	}
 	// Parent module inherits child's publicity
 	// This is done bottom up in the LinkBotupVisitor stage
@@ -509,14 +512,15 @@ private:
 	    if (nodep->op2p()) pinImplicitExprRecurse(nodep->op2p());
 	    if (nodep->op3p()) pinImplicitExprRecurse(nodep->op3p());
 	    if (nodep->op4p()) pinImplicitExprRecurse(nodep->op4p());
+	    if (nodep->nextp()) pinImplicitExprRecurse(nodep->nextp());
 	}
     }
 
     virtual void visit(AstPin* nodep, AstNUser*) {
 	// Pin: Link to submodule's pin
-	// ONLY CALLED by AstCell during ID_RESOLVE state
-	if (!m_cellVarsp) nodep->v3fatalSrc("Pin not under cell?\n");
+	// ONLY CALLED by AstCell during ID_RESOLVE and ID_PARAM state
 	if (m_idState==ID_RESOLVE && !nodep->modVarp()) {
+	    if (!m_cellVarsp) nodep->v3fatalSrc("Pin not under cell?\n");
 	    AstVar* refp = m_cellVarsp->findIdFlat(nodep->name())->castVar();
 	    if (!refp) {
 		nodep->v3error("Pin not found: "<<nodep->prettyName());
@@ -525,13 +529,12 @@ private:
 	    } else {
 		nodep->modVarp(refp);
 	    }
+	    nodep->iterateChildren(*this);
 	}
-	// Deal with implicit definitions
-	if (m_idState==ID_RESOLVE && nodep->modVarp()
-	    && !nodep->svImplicit()) {   // SV 19.11.3: .name pins don't allow implicit decls
+	// Deal with implicit definitions - do before ID_RESOLVE stage as may be referenced above declaration
+	if (m_idState==ID_PARAM && !nodep->svImplicit()) {   // SV 19.11.3: .name pins don't allow implicit decls
 	    pinImplicitExprRecurse(nodep->exprp());
 	}
-	nodep->iterateChildren(*this);
     }
 
     virtual void visit(AstAssignW* nodep, AstNUser*) {
diff --git a/test_regress/t/t_gate_implicit.pl b/test_regress/t/t_gate_implicit.pl
new file mode 100755
index 000000000..7058e622f
--- /dev/null
+++ b/test_regress/t/t_gate_implicit.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gate_implicit.v b/test_regress/t/t_gate_implicit.v
new file mode 100644
index 000000000..5220f5c5e
--- /dev/null
+++ b/test_regress/t/t_gate_implicit.v
@@ -0,0 +1,80 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire			RBL2;			// From t of Test.v
+   // End of automatics
+
+   wire 		RWL1 = crc[2];
+   wire 		RWL2 = crc[3];
+
+   Test t (/*AUTOINST*/
+	   // Outputs
+	   .RBL2			(RBL2),
+	   // Inputs
+	   .RWL1			(RWL1),
+	   .RWL2			(RWL2));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {63'h0, RBL2};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'hb6d6b86aa20a882a
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (
+   output RBL2,
+   input  RWL1, RWL2);
+
+   // verilator lint_off IMPLICIT
+   not    I1 (RWL2_n, RWL2);
+   bufif1 I2 (RBL2, n3, 1'b1);
+   Mxor   I3 (n3, RWL1, RWL2_n);
+   // verilator lint_on IMPLICIT
+
+endmodule
+
+module Mxor (output out, input a, b);
+   assign out = (a ^ b);
+endmodule
+