diff --git a/Changes b/Changes index 36d045c6d..196c59353 100644 --- a/Changes +++ b/Changes @@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 3.921 devel +** Support IEEE 1800-2017 as default language. + *** Support trig functions ($sin() etc), bug1281. [Patrick Stewart] *** Support calling system functions as tasks, bug1285. [Joel Holdsworth] diff --git a/bin/verilator b/bin/verilator index eed2f9a31..7cbe723f9 100755 --- a/bin/verilator +++ b/bin/verilator @@ -259,6 +259,7 @@ descriptions in the next sections for more information. +1800-2005ext+ Use SystemVerilog 2005 with file extension +1800-2009ext+ Use SystemVerilog 2009 with file extension +1800-2012ext+ Use SystemVerilog 2012 with file extension + +1800-2017ext+ Use SystemVerilog 2017 with file extension --assert Enable all assertions --autoflush Flush streams after all $displays --bbox-sys Blackbox unknown $system calls @@ -345,7 +346,7 @@ descriptions in the next sections for more information. --stats Create statistics file --stats-vars Provide statistics on variables -sv Enable SystemVerilog parsing - +systemverilogext+ Synonym for +1800-2012ext+ + +systemverilogext+ Synonym for +1800-2017ext+ --top-module Name of top level input module --trace Enable waveform creation --trace-depth Depth of tracing @@ -412,6 +413,8 @@ with the --exe option. =item +1800-2012ext+I +=item +1800-2017ext+I + Specifies the language standard to be used with a specific filename extension, I. @@ -661,7 +664,7 @@ produce more detailed messages. Select the language to be used by default when first processing each Verilog file. The language value must be "1364-1995", "1364-2001", -"1364-2005", "1800-2005", "1800-2009" or "1800-2012". +"1364-2005", "1800-2005", "1800-2009", "1800-2012" or "1800-2017". Any language associated with a particular file extension (see the various +Iext+ options) will be used in preference to the language specified @@ -674,7 +677,7 @@ legacy mixed language designs, the various +Iext+ options should be used. If no language is specified, either by this flag or +Iext+ options, -then the latest SystemVerilog language (IEEE 1800-2012) is used. +then the latest SystemVerilog language (IEEE 1800-2017) is used. =item +define+I=I @@ -1152,7 +1155,7 @@ compatibility with other simulators. =item +systemverilogext+I -A synonym for C<+1800-2012ext+>I. +A synonym for C<+1800-2017ext+>I. =item --top-module I @@ -2216,6 +2219,11 @@ Verilator currently has some support for SystemVerilog synthesis constructs. As SystemVerilog features enter common usage they are added; please file a bug if a feature you need is missing. +=head2 SystemVerilog 2017 (IEEE 1800-2017) Support + +Verilator supports the 2017 "for" loop constructs, and several minor +cleanups made in 1800-2017. + =head2 Verilog AMS Support Verilator implements a very small subset of Verilog AMS (Verilog Analog and diff --git a/include/vltstd/svdpi.h b/include/vltstd/svdpi.h index 69597926d..f77630af7 100644 --- a/include/vltstd/svdpi.h +++ b/include/vltstd/svdpi.h @@ -7,7 +7,7 @@ * This file contains the constant definitions, structure definitions, * and routine declarations used by SystemVerilog DPI. * - * This file is from the SystemVerilog IEEE 1800-2012 Annex I. + * This file is from the SystemVerilog IEEE 1800-2017 Annex I. */ #ifndef INCLUDED_SVDPI @@ -117,7 +117,7 @@ typedef uint32_t svBitVecVal; /* * Return implementation version information string ("1800-2005" or "SV3.1a"). */ -XXTERN const char* svDpiVersion(); +XXTERN const char* svDpiVersion( void ); /* a handle to a scope (an instance of a module or interface) */ XXTERN typedef void* svScope; @@ -241,28 +241,28 @@ XXTERN void svGetLogicArrElem2VecVal(svLogicVecVal* d, const svOpenArrayHandle s XXTERN void svGetLogicArrElem3VecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1, int indx2, int indx3); -XXTERN svBit svGetBitArrElem(const svOpenArrayHandle s, int indx1, ...); -XXTERN svBit svGetBitArrElem1(const svOpenArrayHandle s, int indx1); -XXTERN svBit svGetBitArrElem2(const svOpenArrayHandle s, int indx1, int indx2); -XXTERN svBit svGetBitArrElem3(const svOpenArrayHandle s, int indx1, int indx2, +XXTERN svBit svGetBitArrElem(const svOpenArrayHandle s, int indx1, ...); +XXTERN svBit svGetBitArrElem1(const svOpenArrayHandle s, int indx1); +XXTERN svBit svGetBitArrElem2(const svOpenArrayHandle s, int indx1, int indx2); +XXTERN svBit svGetBitArrElem3(const svOpenArrayHandle s, int indx1, int indx2, int indx3); -XXTERN svLogic svGetLogicArrElem(const svOpenArrayHandle s, int indx1, ...); -XXTERN svLogic svGetLogicArrElem1(const svOpenArrayHandle s, int indx1); -XXTERN svLogic svGetLogicArrElem2(const svOpenArrayHandle s, int indx1, int indx2); -XXTERN svLogic svGetLogicArrElem3(const svOpenArrayHandle s, int indx1, int indx2, +XXTERN svLogic svGetLogicArrElem(const svOpenArrayHandle s, int indx1, ...); +XXTERN svLogic svGetLogicArrElem1(const svOpenArrayHandle s, int indx1); +XXTERN svLogic svGetLogicArrElem2(const svOpenArrayHandle s, int indx1, int indx2); +XXTERN svLogic svGetLogicArrElem3(const svOpenArrayHandle s, int indx1, int indx2, int indx3); -XXTERN void svPutLogicArrElem(const svOpenArrayHandle d, svLogic value, int indx1, +XXTERN void svPutLogicArrElem(const svOpenArrayHandle d, svLogic value, int indx1, ...); -XXTERN void svPutLogicArrElem1(const svOpenArrayHandle d, svLogic value, int indx1); -XXTERN void svPutLogicArrElem2(const svOpenArrayHandle d, svLogic value, int indx1, +XXTERN void svPutLogicArrElem1(const svOpenArrayHandle d, svLogic value, int indx1); +XXTERN void svPutLogicArrElem2(const svOpenArrayHandle d, svLogic value, int indx1, int indx2); -XXTERN void svPutLogicArrElem3(const svOpenArrayHandle d, svLogic value, int indx1, +XXTERN void svPutLogicArrElem3(const svOpenArrayHandle d, svLogic value, int indx1, int indx2, int indx3); -XXTERN void svPutBitArrElem(const svOpenArrayHandle d, svBit value, int indx1, ...); -XXTERN void svPutBitArrElem1(const svOpenArrayHandle d, svBit value, int indx1); -XXTERN void svPutBitArrElem2(const svOpenArrayHandle d, svBit value, int indx1, +XXTERN void svPutBitArrElem(const svOpenArrayHandle d, svBit value, int indx1, ...); +XXTERN void svPutBitArrElem1(const svOpenArrayHandle d, svBit value, int indx1); +XXTERN void svPutBitArrElem2(const svOpenArrayHandle d, svBit value, int indx1, int indx2); -XXTERN void svPutBitArrElem3(const svOpenArrayHandle d, svBit value, int indx1, +XXTERN void svPutBitArrElem3(const svOpenArrayHandle d, svBit value, int indx1, int indx2, int indx3); /* Functions for working with DPI context */ @@ -273,7 +273,7 @@ XXTERN void svPutBitArrElem3(const svOpenArrayHandle d, svBit value, int indx1 * is the scope of the function's declaration site, not call site. * Returns NULL if called from C code that is *not* an imported function. */ -XXTERN svScope svGetScope(); +XXTERN svScope svGetScope( void ); /* * Set context for subsequent export function execution. @@ -337,7 +337,7 @@ XXTERN int svGetCallerInfo(const char** fileName, int *lineNumber); * Returns 1 if the current execution thread is in the disabled state. * Disable protocol must be adhered to if in the disabled state. */ -XXTERN int svIsDisabledState(); +XXTERN int svIsDisabledState( void ); /* * Imported functions call this API function during disable processing to @@ -345,7 +345,7 @@ XXTERN int svIsDisabledState(); * This function must be called before returning from an imported function that is * in the disabled state. */ -XXTERN void svAckDisabledState(); +XXTERN void svAckDisabledState( void ); /* ********************************************************** diff --git a/include/vltstd/vpi_user.h b/include/vltstd/vpi_user.h index c7a901b30..bc830c014 100644 --- a/include/vltstd/vpi_user.h +++ b/include/vltstd/vpi_user.h @@ -1,7 +1,7 @@ /******************************************************************************* * vpi_user.h * - * IEEE Std 1800-2012 Programming Language Interface (PLI) + * IEEE Std 1800-2017 Programming Language Interface (PLI) * * This file contains the constant definitions, structure definitions, and * routine declarations used by the SystemVerilog Verification Procedural @@ -251,7 +251,7 @@ typedef PLI_UINT32 *vpiHandle; #define vpiModPathOut 96 /* output terminal of a module path */ #define vpiOperand 97 /* operand of expression */ #define vpiPortInst 98 /* connected port instance */ -#define vpiProcess 99 /* process in module */ +#define vpiProcess 99 /* process in module, program or interface */ #define vpiVariables 100 /* variables in module */ #define vpiUse 101 /* usage */ @@ -978,7 +978,7 @@ XXTERN vpiHandle vpi_handle_by_multi_index PROTO_PARAMS((vpiHandle obj, /****************************** GLOBAL VARIABLES ******************************/ -PLI_VEXTERN PLI_DLLESPEC void (*vlog_startup_routines[])(); +PLI_VEXTERN PLI_DLLESPEC void (*vlog_startup_routines[])( void ); /* array of function pointers, last pointer should be null */ diff --git a/src/V3LangCode.h b/src/V3LangCode.h index 839447b25..e2cfd3ae0 100644 --- a/src/V3LangCode.h +++ b/src/V3LangCode.h @@ -42,6 +42,7 @@ public: L1800_2005, L1800_2009, L1800_2012, + L1800_2017, // ***Add new elements below also*** _ENUM_END }; @@ -54,12 +55,14 @@ public: "1364-2005", "1800-2005", "1800-2009", - "1800-2012" + "1800-2012", + "1800-2017" }; return names[m_e]; }; - static V3LangCode mostRecent() { return V3LangCode(L1800_2012); } - bool systemVerilog() const { return m_e == L1800_2005 || m_e == L1800_2009 || m_e == L1800_2012; } + static V3LangCode mostRecent() { return V3LangCode(L1800_2017); } + bool systemVerilog() const { return m_e == L1800_2005 || m_e == L1800_2009 + || m_e == L1800_2012 || m_e == L1800_2017; } bool legal() const { return m_e != L_ERROR; } // enum en m_e; diff --git a/src/V3Number.cpp b/src/V3Number.cpp index 7734ad92f..66467524a 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -142,7 +142,7 @@ V3Number::V3Number (FileLine* fileline, const char* sourcep) { if (!m_sized) { static int warned = false; if (!warned++) { - m_fileline->v3error("As that number was unsized ('d...) it is limited to 32 bits (IEEE 2012 5.7.1)"); + m_fileline->v3error("As that number was unsized ('d...) it is limited to 32 bits (IEEE 2017 5.7.1)"); } } while (*(cp+1)) cp++; // Skip ahead so don't get multiple warnings diff --git a/src/V3Options.cpp b/src/V3Options.cpp index aba146712..ea96e798f 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -604,7 +604,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char else if ( !strncmp (sw, "+incdir+", 8)) { addIncDirUser (parseFileArg(optdir, string (sw+strlen("+incdir+")))); } - else if (parseLangExt(sw, "+systemverilogext+", V3LangCode::L1800_2012) + else if (parseLangExt(sw, "+systemverilogext+", V3LangCode::L1800_2017) || parseLangExt(sw, "+verilog1995ext+", V3LangCode::L1364_1995) || parseLangExt(sw, "+verilog2001ext+", V3LangCode::L1364_2001) || parseLangExt(sw, "+1364-1995ext+", V3LangCode::L1364_1995) @@ -612,7 +612,8 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char || parseLangExt(sw, "+1364-2005ext+", V3LangCode::L1364_2005) || parseLangExt(sw, "+1800-2005ext+", V3LangCode::L1800_2005) || parseLangExt(sw, "+1800-2009ext+", V3LangCode::L1800_2009) - || parseLangExt(sw, "+1800-2012ext+", V3LangCode::L1800_2012)) { + || parseLangExt(sw, "+1800-2012ext+", V3LangCode::L1800_2012) + || parseLangExt(sw, "+1800-2017ext+", V3LangCode::L1800_2017)) { // Nothing to do here - all done in the test } diff --git a/src/V3Task.cpp b/src/V3Task.cpp index e5f339bfd..bd99f3133 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -928,7 +928,7 @@ private: && portp->dtypep()->basicp() && portp->dtypep()->basicp()->keyword().isDpiUnreturnable()) { portp->v3error("DPI function may not return type "<basicp()->prettyTypeName() - <<" (IEEE 2012 35.5.5)"); + <<" (IEEE 2017 35.5.5)"); } portp->unlinkFrBack(); rtnvarp = portp; diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 5a2227965..39bf904eb 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -446,7 +446,7 @@ private: if (!constp) { nodep->v3error("Replication value isn't a constant."); return; } uint32_t times = constp->toUInt(); if (times==0 && !nodep->backp()->castConcat()) { // Concat Visitor will clean it up. - nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 2012 11.4.12.1)"); times=1; + nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 2017 11.4.12.1)"); times=1; } if (nodep->lhsp()->isString()) { AstNode* newp = new AstReplicateN(nodep->fileline(),nodep->lhsp()->unlinkFrBack(), @@ -477,7 +477,7 @@ private: if (!constp) { nodep->v3error("Replication value isn't a constant."); return; } uint32_t times = constp->toUInt(); if (times==0 && !nodep->backp()->castConcat()) { // Concat Visitor will clean it up. - nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 2012 11.4.12.1)"); + nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 2017 11.4.12.1)"); } nodep->dtypeSetString(); } @@ -1298,7 +1298,7 @@ private: } if (!itemp->valuep()) { if (num.isEqZero() && itemp != nodep->itemsp()) - itemp->v3error("Enum value illegally wrapped around (IEEE 2012 6.19)"); + itemp->v3error("Enum value illegally wrapped around (IEEE 2017 6.19)"); if (!nodep->dtypep()->basicp() && !nodep->dtypep()->basicp()->keyword().isIntNumeric()) { itemp->v3error("Enum names without values only allowed on numeric types"); diff --git a/src/verilog.l b/src/verilog.l index dc2ff7fca..5702b7461 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -32,7 +32,7 @@ extern void yyerror(const char*); extern void yyerrorf(const char* format, ...); -#define STATE_VERILOG_RECENT S12 // State name for most recent Verilog Version +#define STATE_VERILOG_RECENT S17 // State name for most recent Verilog Version #define PARSEP V3ParseImp::parsep() #define SYMP PARSEP->symp() @@ -126,7 +126,7 @@ void yyerror(const char* errmsg) { static int warned = false; if (!warned++) { PARSEP->fileline()->v3error("Perhaps '"+*PARSEP->prevBisonVal().strp - +"' is a package which needs to be predeclared? (IEEE 2012 26.3)"); + +"' is a package which needs to be predeclared? (IEEE 2017 26.3)"); } } } @@ -154,7 +154,7 @@ void yyerrorf(const char* format, ...) { %a 15000 %o 25000 -%s V95 V01 V05 S05 S09 S12 +%s V95 V01 V05 S05 S09 S12 S17 %s STRING ATTRMODE TABLE %s VA5 SAX VLT %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR @@ -200,7 +200,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Verilog 1995 */ -{ +{ {ws} { } /* otherwise ignore white-space */ {crnl} { NEXTLINE(); } /* Count line numbers */ /* Extensions to Verilog set, some specified by PSL */ @@ -390,7 +390,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Verilog 2001 */ -{ +{ /* System Tasks */ "$signed" { FL; return yD_SIGNED; } "$unsigned" { FL; return yD_UNSIGNED; } @@ -421,13 +421,13 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Verilog 2005 */ -{ +{ /* Keywords */ "uwire" { FL; return yWIRE; } } /* System Verilog 2005 */ -{ +{ /* System Tasks */ "$bits" { FL; return yD_BITS; } "$clog2" { FL; return yD_CLOG2; } @@ -552,7 +552,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* SystemVerilog 2009 */ -{ +{ /* Keywords */ "global" { FL; return yGLOBAL__LEX; } "unique0" { FL; return yUNIQUE0; } @@ -581,7 +581,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* System Verilog 2012 */ -{ +{ /* Keywords */ "implements" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); } "interconnect" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); } @@ -589,8 +589,11 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "soft" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); } } + /* System Verilog 2017 */ + /* No new keywords */ + /* Default PLI rule */ -{ +{ "$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext,yyleng); yylval.strp = PARSEP->newString(AstNode::encodeName(str)); // Lookup unencoded name including the $, to avoid hitting normal signals @@ -697,7 +700,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Meta comments */ /* Converted from //{cmt}verilator ...{cmt} by preprocessor */ -{ +{ "/*verilator"{ws}*"*/" {} /* Ignore empty comments, may be `endif // verilator */ "/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; } "/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; } @@ -735,7 +738,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Single character operator thingies */ -{ +{ "{" { FL; return yytext[0]; } "}" { FL; return yytext[0]; } "!" { FL; return yytext[0]; } @@ -769,7 +772,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Operators and multi-character symbols */ /* Verilog 1995 Operators */ -{ +{ "&&" { FL; return yP_ANDAND; } "||" { FL; return yP_OROR; } "<=" { FL; return yP_LTE; } @@ -791,7 +794,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Verilog 2001 Operators */ -{ +{ "<<<" { FL; return yP_SLEFT; } ">>>" { FL; return yP_SSRIGHT; } "**" { FL; return yP_POW; } @@ -804,7 +807,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* SystemVerilog Operators */ -{ +{ "'" { FL; return yP_TICK; } "'{" { FL; return yP_TICKBRA; } "==?" { FL; return yP_WILDEQUAL; } @@ -838,7 +841,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Identifiers and numbers */ -{ +{ {escid} { FL; yylval.strp = PARSEP->newString (AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash return yaID__LEX; @@ -911,7 +914,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Attributes */ /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */ -{ +{ "(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */ } @@ -928,7 +931,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Preprocessor */ /* Common for all SYSC header states */ /* OPTIMIZE: we return one per line, make it one for the entire block */ -{ +{ "`accelerate" { } // Verilog-XL compatibility "`autoexpand_vectornets" { } // Verilog-XL compatibility "`celldefine" { PARSEP->inCellDefine(true); } @@ -972,6 +975,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); } "`begin_keywords"[ \t]*\"1800-2009\" { yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); } "`begin_keywords"[ \t]*\"1800-2012\" { yy_push_state(S12); PARSEP->pushBeginKeywords(YY_START); } + "`begin_keywords"[ \t]*\"1800-2017\" { yy_push_state(S17); PARSEP->pushBeginKeywords(YY_START); } "`begin_keywords"[ \t]*\"1800[+]VAMS\" { yy_push_state(SAX); PARSEP->pushBeginKeywords(YY_START); } /*Latest SV*/ "`end_keywords" { yy_pop_state(); if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); } @@ -1003,7 +1007,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Default rules - leave last */ -{ +{ "`"[a-zA-Z_0-9]+ { FL; yyerrorf("Define or directive not defined: %s",yytext); } "//"[^\n]* { } /* throw away single line comments */ . { FL; return yytext[0]; } /* return single char ops. */ diff --git a/src/verilog.y b/src/verilog.y index 3b76f6fdc..d30a5e484 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -743,7 +743,6 @@ package_or_generate_item_declaration: // ==IEEE: package_or_generate_item | local_parameter_declaration ';' { $$ = $1; } | parameter_declaration ';' { $$ = $1; } //UNSUP covergroup_declaration { $$ = $1; } - //UNSUP overload_declaration { $$ = $1; } //UNSUP assertion_item_declaration { $$ = $1; } | ';' { $$ = NULL; } ; @@ -2275,7 +2274,6 @@ block_item_declaration: // ==IEEE: block_item_declaration data_declaration { $$ = $1; } | local_parameter_declaration ';' { $$ = $1; } | parameter_declaration ';' { $$ = $1; } - //UNSUP overload_declaration { $$ = $1; } //UNSUP let_declaration { $$ = $1; } ; @@ -2374,8 +2372,7 @@ statement_item: // IEEE: statement_item | yREPEAT '(' expr ')' stmtBlock { $$ = new AstRepeat($1,$3,$5);} | yWHILE '(' expr ')' stmtBlock { $$ = new AstWhile($1,$3,$5);} // // for's first ';' is in for_initalization - | yFOR '(' for_initialization expr ';' for_stepE ')' stmtBlock - { $$ = new AstBegin($1,"",$3); $3->addNext(new AstWhile($1, $4,$8,$6)); } + | statementFor { $$ = $1; } | yDO stmtBlock yWHILE '(' expr ')' ';' { $$ = $2->cloneTree(true); $$->addNext(new AstWhile($1,$5,$2));} // // IEEE says array_identifier here, but dotted accepted in VMM and 1800-2009 | yFOREACH '(' idClassForeach '[' loop_variables ']' ')' stmtBlock { $$ = new AstForeach($1,$3,$5,$8); } @@ -2423,6 +2420,15 @@ statement_item: // IEEE: statement_item | error ';' { $$ = NULL; } ; +statementFor: // IEEE: part of statement + yFOR '(' for_initialization expr ';' for_stepE ')' stmtBlock + { $$ = new AstBegin($1,"",$3); + $$->addStmtsp(new AstWhile($1, $4,$8,$6)); } + | yFOR '(' for_initialization ';' for_stepE ')' stmtBlock + { $$ = new AstBegin($1,"",$3); + $$->addStmtsp(new AstWhile($1, new AstConst($1,AstConst::LogicTrue()),$7,$5)); } + ; + statementVerilatorPragmas: yVL_COVERAGE_BLOCK_OFF { $$ = new AstPragma($1,AstPragmaType::COVERAGE_BLOCK_OFF); } ; @@ -2597,6 +2603,7 @@ for_initialization: // ==IEEE: for_initialization + for_variable_declarat $$ = VARDONEA($2,*$2,NULL,NULL); $$->addNext(new AstAssign($3,new AstVarRef($3,*$2,true),$4));} | varRefBase '=' expr ';' { $$ = new AstAssign($2,$1,$3); } + | ';' { $$ = NULL; } //UNSUP: List of initializations ; @@ -3120,7 +3127,7 @@ expr: // IEEE: part of expression/constant_expression/primary // // // IEEE: "... hierarchical_identifier select" see below // - // // IEEE: empty_queue + // // IEEE: empty_queue (IEEE 1800-2017 empty_unpacked_array_concatenation) //UNSUP '{' '}' // // // IEEE: concatenation/constant_concatenation diff --git a/test_regress/t/t_dpi_logic_bad.pl b/test_regress/t/t_dpi_logic_bad.pl index 29ff03c2d..69732372e 100755 --- a/test_regress/t/t_dpi_logic_bad.pl +++ b/test_regress/t/t_dpi_logic_bad.pl @@ -11,7 +11,7 @@ compile ( v_flags2 => ["--lint-only"], fails=>$Self->{v3}, expect=> -'%Error: t/t_dpi_logic_bad.v:\d+: DPI function may not return type BASICDTYPE \'logic\' \(IEEE 2012 35.5.5\) +'%Error: t/t_dpi_logic_bad.v:\d+: DPI function may not return type BASICDTYPE \'logic\' \(IEEE 2017 35.5.5\) %Error: Exiting due to .*' ); diff --git a/test_regress/t/t_for_loop.v b/test_regress/t/t_for_loop.v index dd4b4d6d8..8d8c4acc5 100644 --- a/test_regress/t/t_for_loop.v +++ b/test_regress/t/t_for_loop.v @@ -78,6 +78,22 @@ module t (/*AUTOARG*/ if (i !== -1) $stop; if (loops !== 17) $stop; // + // 1800-2017 optionals init/expr/incr + loops = 0; + i = 0; + for (; i<10; ++i) ++loops; + if (loops !== 10) $stop; + // + loops = 0; + i = 0; + for (i=0; i<10; ) begin ++loops; ++i; end + if (loops !== 10) $stop; + // + loops = 0; + i = 0; + for (; ; ++i) begin ++loops; break; end + if (loops !== 1) $stop; + // $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_lint_pkg_colon_bad.pl b/test_regress/t/t_lint_pkg_colon_bad.pl index decc210b4..862dec3bc 100755 --- a/test_regress/t/t_lint_pkg_colon_bad.pl +++ b/test_regress/t/t_lint_pkg_colon_bad.pl @@ -17,7 +17,7 @@ compile ( make_main => 0, expect=> quotemeta( qq{%Error: t/t_lint_pkg_colon_bad.v:6: syntax error, unexpected ::, expecting ')' or ',' -%Error: t/t_lint_pkg_colon_bad.v:6: Perhaps 'mispkg' is a package which needs to be predeclared? (IEEE 2012 26.3) +%Error: t/t_lint_pkg_colon_bad.v:6: Perhaps 'mispkg' is a package which needs to be predeclared? (IEEE 2017 26.3) %Error: t/t_lint_pkg_colon_bad.v:7: syntax error, unexpected ::, expecting ',' or ';' }).'%Error: Exiting due to.*' ); diff --git a/test_regress/t/t_lint_unsized_bad.pl b/test_regress/t/t_lint_unsized_bad.pl index cd621a77e..f9b683e90 100755 --- a/test_regress/t/t_lint_unsized_bad.pl +++ b/test_regress/t/t_lint_unsized_bad.pl @@ -17,7 +17,7 @@ compile ( make_main => 0, expect=> quotemeta( qq{%Error: t/t_lint_unsized_bad.v:7: Too many digits for 32 bit number: 'd123456789123456789123456789 -%Error: t/t_lint_unsized_bad.v:7: As that number was unsized ('d...) it is limited to 32 bits (IEEE 2012 5.7.1) +%Error: t/t_lint_unsized_bad.v:7: As that number was unsized ('d...) it is limited to 32 bits (IEEE 2017 5.7.1) }).'%Error: Exiting due to.*' ); diff --git a/test_regress/t/t_math_arith.v b/test_regress/t/t_math_arith.v index f39fa0376..b79aeea1a 100644 --- a/test_regress/t/t_math_arith.v +++ b/test_regress/t/t_math_arith.v @@ -129,7 +129,7 @@ module t (/*AUTOARG*/ if (bug764_p11 !== 4'b000x) $stop; if (~& bug764_p11 !== 1'b1) $stop; //verilator lint_on WIDTH - // However IEEE says for constants in 2012 5.7.1 that smaller-sizes do extend + // However IEEE 2017 5.7.1 says for constants that smaller-sizes do extend if (4'bx !== 4'bxxxx) $stop; if (4'bz !== 4'bzzzz) $stop; if (4'b1 !== 4'b0001) $stop; diff --git a/test_regress/t/t_preproc_kwd.v b/test_regress/t/t_preproc_kwd.v index 85fb878e1..f62e5124e 100644 --- a/test_regress/t/t_preproc_kwd.v +++ b/test_regress/t/t_preproc_kwd.v @@ -14,8 +14,10 @@ module t (/*AUTOARG*/ v05 v05 (); s05 s05 (); s09 s09 (); - a23 a23 (); s12 s12 (); + s17 s17 (); + + a23 a23 (); initial begin $finish; @@ -60,6 +62,14 @@ module s12; endmodule `end_keywords +`begin_keywords "1800-2017" +module s17; + final begin + $write("*-* All Finished *-*\n"); + end +endmodule +`end_keywords + `begin_keywords "VAMS-2.3" module a23; real foo; initial foo = sqrt(2.0); diff --git a/test_regress/t/t_xml_first.out b/test_regress/t/t_xml_first.out index 4548b237c..a8c29db29 100644 --- a/test_regress/t/t_xml_first.out +++ b/test_regress/t/t_xml_first.out @@ -2,11 +2,11 @@ - - - - - + + + + + diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out index 0bde73392..0edec2e4a 100644 --- a/test_regress/t/t_xml_tag.out +++ b/test_regress/t/t_xml_tag.out @@ -2,11 +2,11 @@ - - - - - + + + + +