diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 8a73837ac..30d88d6a8 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1020,7 +1020,8 @@ class LinkDotFindVisitor : public AstNVisitor {
                         nodep->v3error("Duplicate declaration of signal: "
                                        <<nodep->prettyNameQ()<<endl
                                        <<(ansiWarn
-                                          ? nodep->warnMore()+"... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)\n"
+                                          ? nodep->warnMore() + "... note: ANSI ports must have"
+                                          " type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n"
                                           : "")
                                        <<nodep->warnContextPrimary()<<endl
                                        <<findvarp->warnOther()<<"... Location of original declaration"<<endl
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 5bf498ae0..00a043c68 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -127,7 +127,7 @@ void V3Number::V3NumberCreate(AstNode* nodep, const char* sourcep, FileLine* fl)
             if (atoi(widthn.c_str()) < 0 || atoi(widthn.c_str()) > v3Global.opt.maxNumWidth()) {
                 // atoi might convert large number to negative, so can't tell which
                 v3error("Unsupported: Width of number exceeds implementation limit: "
-                        << sourcep << "  (IEEE 2017 6.9.1)");
+                        << sourcep << "  (IEEE 1800-2017 6.9.1)");
                 width(v3Global.opt.maxNumWidth(), true);
             } else {
                 width(atoi(widthn.c_str()), true);
@@ -198,7 +198,7 @@ void V3Number::V3NumberCreate(AstNode* nodep, const char* sourcep, FileLine* fl)
                                 <<std::endl
                                 <<((!m_sized && !warned++)
                                    ? (V3Error::warnMore()+"... As that number was unsized"
-                                      +" ('d...) it is limited to 32 bits (IEEE 2017 5.7.1)\n"
+                                      +" ('d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n"
                                       + V3Error::warnMore()+"... Suggest adding a size to it.")
                                    : ""));
                         while (*(cp+1)) cp++;  // Skip ahead so don't get multiple warnings
diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp
index 51796dba2..f49464eae 100644
--- a/src/V3PreProc.cpp
+++ b/src/V3PreProc.cpp
@@ -339,7 +339,8 @@ void V3PreProcImp::define(FileLine* fl, const string& name, const string& value,
                           const string& params, bool cmdline) {
     UINFO(4,"DEFINE '"<<name<<"' as '"<<value<<"' params '"<<params<<"'"<<endl);
     if (!V3LanguageWords::isKeyword(string("`") + name).empty()) {
-        fl->v3error("Attempting to define built-in directive: '`"<<name<<"' (IEEE 2017 22.5.1)");
+        fl->v3error("Attempting to define built-in directive: '`"
+                    << name << "' (IEEE 1800-2017 22.5.1)");
     } else {
         if (defExists(name)) {
             if (!(defValue(name) == value
diff --git a/src/V3Task.cpp b/src/V3Task.cpp
index 133d8a4bf..72cb3c9e4 100644
--- a/src/V3Task.cpp
+++ b/src/V3Task.cpp
@@ -933,7 +933,7 @@ private:
                 && portp->dtypep()->basicp()->keyword().isDpiUnreturnable()) {
                 portp->v3error("DPI function may not return type "
                                <<portp->basicp()->prettyTypeName()
-                               <<" (IEEE 2017 35.5.5)");
+                               <<" (IEEE 1800-2017 35.5.5)");
             }
             portp->unlinkFrBack();
             rtnvarp = portp;
@@ -1183,7 +1183,7 @@ private:
         } else {
             if (nodep->taskp()->isFunction()) {
                 nodep->v3warn(IGNOREDRETURN,
-                              "Ignoring return value of non-void function (IEEE 2017 13.4.1)");
+                              "Ignoring return value of non-void function (IEEE 1800-2017 13.4.1)");
             }
             // outvscp maybe non-NULL if calling a function in a taskref,
             // but if so we want to simply ignore the function result
diff --git a/src/V3Undriven.cpp b/src/V3Undriven.cpp
index 59c85dc9c..571b57a98 100644
--- a/src/V3Undriven.cpp
+++ b/src/V3Undriven.cpp
@@ -338,14 +338,13 @@ private:
                 && !nodep->varp()->isDeclTyped()
                 && !nodep->varp()->isFuncLocal()) {
                 nodep->v3warn(PROCASSWIRE, "Procedural assignment to wire, perhaps intended var"
-                              " (IEEE 2017 6.5): "
-                              +nodep->prettyNameQ());
+                              << " (IEEE 1800-2017 6.5): " << nodep->prettyNameQ());
             }
             if (m_inContAssign && !nodep->varp()->varType().isContAssignable()
                 && !nodep->fileline()->language().systemVerilog()) {
                 nodep->v3warn(CONTASSREG, "Continuous assignment to reg, perhaps intended wire"
-                              " (IEEE 2005 6.1; Verilog only, legal in SV): "
-                              +nodep->prettyNameQ());
+                              << " (IEEE 1364-2005 6.1; Verilog only, legal in SV): "
+                              << nodep->prettyNameQ());
             }
         }
         for (int usr=1; usr<(m_alwaysCombp?3:2); ++usr) {
diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp
index 8888aed55..25408ef5b 100644
--- a/src/V3Unroll.cpp
+++ b/src/V3Unroll.cpp
@@ -125,7 +125,7 @@ private:
             nodep->v3error("Non-genvar used in generate for: "<<m_forVarp->prettyNameQ()<<endl);
         }
         else if (!VN_IS(nodep, GenFor) && m_forVarp->isGenVar()) {
-            nodep->v3error("Genvar not legal in non-generate for (IEEE 2017 27.4): "
+            nodep->v3error("Genvar not legal in non-generate for (IEEE 1800-2017 27.4): "
                            << m_forVarp->prettyNameQ() << endl
                            << nodep->warnMore()
                            << "... Suggest move for loop upwards to generate-level scope.");
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index d29b0a75d..8c18da24c 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -548,7 +548,7 @@ private:
             if (!constp) { nodep->v3error("Replication value isn't a constant."); return; }
             uint32_t times = constp->toUInt();
             if (times==0 && !VN_IS(nodep->backp(), Concat)) {  // Concat Visitor will clean it up.
-                nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 2017 11.4.12.1)");
+                nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)");
                 times = 1;
             }
             if (nodep->lhsp()->isString()) {
@@ -581,7 +581,7 @@ private:
             if (!constp) { nodep->v3error("Replication value isn't a constant."); return; }
             uint32_t times = constp->toUInt();
             if (times==0 && !VN_IS(nodep->backp(), Concat)) {  // Concat Visitor will clean it up.
-                nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 2017 11.4.12.1)");
+                nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)");
             }
             nodep->dtypeSetString();
         }
@@ -943,10 +943,10 @@ private:
                 V3Const::constifyParamsEdit(nodep->ticksp());  // ticksp may change
                 const AstConst* constp = VN_CAST(nodep->ticksp(), Const);
                 if (!constp || constp->toSInt() < 1) {
-                    nodep->v3error("$past tick value must be constant (IEEE 2017 16.9.3)");
+                    nodep->v3error("$past tick value must be constant (IEEE 1800-2017 16.9.3)");
                     nodep->ticksp()->unlinkFrBack()->deleteTree();
                 } else if (constp->toSInt() < 1) {
-                    constp->v3error("$past tick value must be >= 1 (IEEE 2017 16.9.3)");
+                    constp->v3error("$past tick value must be >= 1 (IEEE 1800-2017 16.9.3)");
                     nodep->ticksp()->unlinkFrBack()->deleteTree();
                 } else {
                     if (constp->toSInt() > 10) {
@@ -1588,9 +1588,9 @@ private:
             }
             if (!itemp->valuep()) {
                 if (num.isEqZero() && itemp != nodep->itemsp())
-                    itemp->v3error("Enum value illegally wrapped around (IEEE 2017 6.19)");
+                    itemp->v3error("Enum value illegally wrapped around (IEEE 1800-2017 6.19)");
                 if (num.isFourState())
-                    itemp->v3error("Enum value that is unassigned cannot follow value with X/Zs (IEEE 2017 6.19)");
+                    itemp->v3error("Enum value that is unassigned cannot follow value with X/Zs (IEEE 1800-2017 6.19)");
                 if (!nodep->dtypep()->basicp()
                     && !nodep->dtypep()->basicp()->keyword().isIntNumeric()) {
                     itemp->v3error("Enum names without values only allowed on numeric types");
@@ -1602,7 +1602,7 @@ private:
             AstConst* constp = VN_CAST(itemp->valuep(), Const);
             if (constp->num().isFourState() && nodep->dtypep()->basicp()
                 && !nodep->dtypep()->basicp()->isFourstate())
-                itemp->v3error("Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 2017 6.19)");
+                itemp->v3error("Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 1800-2017 6.19)");
             num.opAssign(constp->num());
             // Look for duplicates
             if (inits.find(num) != inits.end()) {  // IEEE says illegal
@@ -2984,7 +2984,7 @@ private:
             if (!adtypep->keyDTypep()->skipRefp()->basicp()
                 || !adtypep->keyDTypep()->skipRefp()->basicp()->keyword().isIntNumeric()) {
                 nodep->memp()->v3error(nodep->verilogKwd()
-                                       << " address/key must be integral (IEEE 21.4.1)");
+                                       << " address/key must be integral (IEEE 1800-2017 21.4.1)");
             }
         } else if (AstUnpackArrayDType* adtypep
                    = VN_CAST(nodep->memp()->dtypep()->skipRefp(), UnpackArrayDType)) {
diff --git a/src/verilog.l b/src/verilog.l
index a442fe34e..fca5a2266 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -72,10 +72,10 @@ void yyerror(const char* errmsg) {
         && PARSEP->curBisonVal().token == yP_COLONCOLON) {
         static int warned = false;
         if (!warned++) {
-            std::cerr<<PARSEP->fileline()->warnMore()
-                     <<("... Perhaps '"+*PARSEP->prevBisonVal().strp
-                        +"' is a package which needs to be predeclared? (IEEE 2017 26.3)")
-                     <<std::endl;
+            std::cerr << PARSEP->fileline()->warnMore()
+                      << ("... Perhaps '" + *PARSEP->prevBisonVal().strp
+                          + "' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)")
+                      << std::endl;
         }
     }
 }
diff --git a/src/verilog.y b/src/verilog.y
index 6503dc0e4..7052e8e17 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -4500,7 +4500,7 @@ simple_immediate_assertion_statement<nodep>:	// ==IEEE: simple_immediate_asserti
 
 final_zero:			// IEEE: part of deferred_immediate_assertion_statement
 		'#' yaINTNUM
-			{ if ($2->isNeqZero()) { $<fl>2->v3error("Deferred assertions must use '#0' (IEEE 2017 16.4)"); } }
+			{ if ($2->isNeqZero()) { $<fl>2->v3error("Deferred assertions must use '#0' (IEEE 1800-2017 16.4)"); } }
 	//			// 1800-2012:
 	|	yFINAL							{ }
 	;
@@ -5362,7 +5362,7 @@ classExtendsE<nodep>:		// IEEE: part of class_declaration
 classExtendsList<nodep>:	// IEEE: part of class_declaration
 		classExtendsOne				{ $$ = $1; }
 	|	classExtendsList ',' classExtendsOne
-			{ $$ = $3; BBUNSUP($3, "Multiple inheritance illegal on non-interface classes (IEEE 8.13)"
+			{ $$ = $3; BBUNSUP($3, "Multiple inheritance illegal on non-interface classes (IEEE 1800-2017 8.13)"
 					       ", and unsupported for interface classes."); }
 	;
 
diff --git a/test_regress/t/t_dpi_logic_bad.out b/test_regress/t/t_dpi_logic_bad.out
index bb5c4444a..3d701665c 100644
--- a/test_regress/t/t_dpi_logic_bad.out
+++ b/test_regress/t/t_dpi_logic_bad.out
@@ -1,4 +1,4 @@
-%Error: t/t_dpi_logic_bad.v:11: DPI function may not return type BASICDTYPE 'logic' (IEEE 2017 35.5.5)
+%Error: t/t_dpi_logic_bad.v:11: DPI function may not return type BASICDTYPE 'logic' (IEEE 1800-2017 35.5.5)
    import "DPI-C" dpii_fa_bit = function logic [2:0] oth_f_int1(input time i);
                                                      ^~~~~~~~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_enum_x_bad.out b/test_regress/t/t_enum_x_bad.out
index 5fd3bc732..0f6ffbf24 100644
--- a/test_regress/t/t_enum_x_bad.out
+++ b/test_regress/t/t_enum_x_bad.out
@@ -1,8 +1,8 @@
-%Error: t/t_enum_x_bad.v:8: Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 2017 6.19)
+%Error: t/t_enum_x_bad.v:8: Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 1800-2017 6.19)
                           : ... In instance t
    enum bit [1:0] { BADX = 2'b1x } BAD1;
                     ^~~~
-%Error: t/t_enum_x_bad.v:11: Enum value that is unassigned cannot follow value with X/Zs (IEEE 2017 6.19)
+%Error: t/t_enum_x_bad.v:11: Enum value that is unassigned cannot follow value with X/Zs (IEEE 1800-2017 6.19)
                            : ... In instance t
                       e1
                       ^~
diff --git a/test_regress/t/t_func_void_bad.out b/test_regress/t/t_func_void_bad.out
index ba40b25a7..b98f258c6 100644
--- a/test_regress/t/t_func_void_bad.out
+++ b/test_regress/t/t_func_void_bad.out
@@ -1,4 +1,4 @@
-%Warning-IGNOREDRETURN: t/t_func_void_bad.v:25: Ignoring return value of non-void function (IEEE 2017 13.4.1)
+%Warning-IGNOREDRETURN: t/t_func_void_bad.v:25: Ignoring return value of non-void function (IEEE 1800-2017 13.4.1)
       f1(20);
       ^~
                         ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message.
diff --git a/test_regress/t/t_fuzz_negwidth_bad.out b/test_regress/t/t_fuzz_negwidth_bad.out
index c9637baf3..ac8d41a77 100644
--- a/test_regress/t/t_fuzz_negwidth_bad.out
+++ b/test_regress/t/t_fuzz_negwidth_bad.out
@@ -1,4 +1,4 @@
-%Error: t/t_fuzz_negwidth_bad.v:8: Unsupported: Width of number exceeds implementation limit: 1231232312312312'd1  (IEEE 2017 6.9.1)
+%Error: t/t_fuzz_negwidth_bad.v:8: Unsupported: Width of number exceeds implementation limit: 1231232312312312'd1  (IEEE 1800-2017 6.9.1)
 int c = 1231232312312312'd1;
         ^~~~~~~~~~~~~~~~~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_genvar_for_bad.out b/test_regress/t/t_genvar_for_bad.out
index bc1e2f800..33409bfd1 100644
--- a/test_regress/t/t_genvar_for_bad.out
+++ b/test_regress/t/t_genvar_for_bad.out
@@ -1,4 +1,4 @@
-%Error: t/t_genvar_for_bad.v:22: Genvar not legal in non-generate for (IEEE 2017 27.4): 't.i'
+%Error: t/t_genvar_for_bad.v:22: Genvar not legal in non-generate for (IEEE 1800-2017 27.4): 't.i'
                                : ... Suggest move for loop upwards to generate-level scope.
          for (i=0; i<N; i=i+1) begin
          ^~~
diff --git a/test_regress/t/t_lint_always_comb_bad.out b/test_regress/t/t_lint_always_comb_bad.out
index 9007f1e3a..cf3700947 100644
--- a/test_regress/t/t_lint_always_comb_bad.out
+++ b/test_regress/t/t_lint_always_comb_bad.out
@@ -1,8 +1,8 @@
-%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'temp1'
+%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1'
                                                  : ... In instance t
         temp1 = 'h0;
         ^~~~~
-%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:30: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'temp1'
+%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:30: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1'
                                                  : ... In instance t
         temp1 = (temp1_d1r - 'h1);
         ^~~~~
@@ -11,7 +11,7 @@
       mid = (temp1_d1r == 'h0);   
       ^~~
                        ... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message.
-%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:45: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'temp1_d1r'
+%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:45: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1_d1r'
                                                  : ... In instance t
       temp1_d1r <= temp1;
       ^~~~~~~~~
diff --git a/test_regress/t/t_lint_pkg_colon_bad.out b/test_regress/t/t_lint_pkg_colon_bad.out
index 483b9b58b..3ba969bcd 100644
--- a/test_regress/t/t_lint_pkg_colon_bad.out
+++ b/test_regress/t/t_lint_pkg_colon_bad.out
@@ -1,7 +1,7 @@
 %Error: t/t_lint_pkg_colon_bad.v:6: syntax error, unexpected ::, expecting ')' or ','
 module t (input mispkg::foo_t a);
                       ^~
-                                  : ... Perhaps 'mispkg' is a package which needs to be predeclared? (IEEE 2017 26.3)
+                                  : ... Perhaps 'mispkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)
 %Error: t/t_lint_pkg_colon_bad.v:7: syntax error, unexpected ::, expecting ',' or ';'
    reg mispkgb::bar_t b;
               ^~
diff --git a/test_regress/t/t_lint_unsized_bad.out b/test_regress/t/t_lint_unsized_bad.out
index ce16f29e9..11b16446c 100644
--- a/test_regress/t/t_lint_unsized_bad.out
+++ b/test_regress/t/t_lint_unsized_bad.out
@@ -1,5 +1,5 @@
 %Error: t/t_lint_unsized_bad.v:7: Too many digits for 32 bit number: 'd123456789123456789123456789
-        ... As that number was unsized ('d...) it is limited to 32 bits (IEEE 2017 5.7.1)
+        ... As that number was unsized ('d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)
         ... Suggest adding a size to it.
    bit [256:0] num = 'd123456789123456789123456789;
                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/test_regress/t/t_past_bad.out b/test_regress/t/t_past_bad.out
index 677f765d4..d6ac044d4 100644
--- a/test_regress/t/t_past_bad.out
+++ b/test_regress/t/t_past_bad.out
@@ -1,4 +1,4 @@
-%Error: t/t_past_bad.v:11: $past tick value must be constant (IEEE 2017 16.9.3)
+%Error: t/t_past_bad.v:11: $past tick value must be constant (IEEE 1800-2017 16.9.3)
                          : ... In instance t
       if ($past(d, 0)) $stop;   
           ^~~~~
diff --git a/test_regress/t/t_pp_defkwd_bad.out b/test_regress/t/t_pp_defkwd_bad.out
index 860e2a8c4..f64b09e20 100644
--- a/test_regress/t/t_pp_defkwd_bad.out
+++ b/test_regress/t/t_pp_defkwd_bad.out
@@ -1,2 +1,2 @@
-%Error: t/t_pp_defkwd_bad.v:7: Attempting to define built-in directive: '`define' (IEEE 2017 22.5.1)
+%Error: t/t_pp_defkwd_bad.v:7: Attempting to define built-in directive: '`define' (IEEE 1800-2017 22.5.1)
 %Error: Exiting due to
diff --git a/test_regress/t/t_sys_readmem_assoc_bad.out b/test_regress/t/t_sys_readmem_assoc_bad.out
index 724b24250..42a2644f4 100644
--- a/test_regress/t/t_sys_readmem_assoc_bad.out
+++ b/test_regress/t/t_sys_readmem_assoc_bad.out
@@ -1,4 +1,4 @@
-%Error: t/t_sys_readmem_assoc_bad.v:12: $readmemb address/key must be integral (IEEE 21.4.1)
+%Error: t/t_sys_readmem_assoc_bad.v:12: $readmemb address/key must be integral (IEEE 1800-2017 21.4.1)
                                       : ... In instance t
       $readmemb("not", assoc_bad_key);
                        ^~~~~~~~~~~~~
diff --git a/test_regress/t/t_var_dup2_bad.out b/test_regress/t/t_var_dup2_bad.out
index 78044c27d..2b8ad7717 100644
--- a/test_regress/t/t_var_dup2_bad.out
+++ b/test_regress/t/t_var_dup2_bad.out
@@ -1,5 +1,5 @@
 %Error: t/t_var_dup2_bad.v:12: Duplicate declaration of signal: 'bad_o_w'
-                             : ... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)
+                             : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)
    wire bad_o_w;
         ^~~~~~~
         t/t_var_dup2_bad.v:9: ... Location of original declaration
diff --git a/test_regress/t/t_var_dup_bad.out b/test_regress/t/t_var_dup_bad.out
index 4ef6a902d..727573ca7 100644
--- a/test_regress/t/t_var_dup_bad.out
+++ b/test_regress/t/t_var_dup_bad.out
@@ -47,7 +47,7 @@
    output bad_reout_port
           ^~~~~~~~~~~~~~
 %Error: t/t_var_dup_bad.v:72: Duplicate declaration of signal: 'bad_rewire'
-                            : ... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)
+                            : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)
    wire bad_rewire;
         ^~~~~~~~~~
         t/t_var_dup_bad.v:69: ... Location of original declaration
diff --git a/test_regress/t/t_wire_beh1364_bad.out b/test_regress/t/t_wire_beh1364_bad.out
index b8587e157..9f8606a6a 100644
--- a/test_regress/t/t_wire_beh1364_bad.out
+++ b/test_regress/t/t_wire_beh1364_bad.out
@@ -1,20 +1,20 @@
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w'
                                              : ... In instance t
       w = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o'
                                              : ... In instance t
       o = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa'
                                              : ... In instance t
       oa = '0;   
       ^~
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'wo'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'wo'
                                              : ... In instance t
       wo = '0;   
       ^~
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'woa'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'woa'
                                              : ... In instance t
       woa = '0;   
       ^~~
diff --git a/test_regress/t/t_wire_beh1800_bad.out b/test_regress/t/t_wire_beh1800_bad.out
index 296b99738..0d07bcd89 100644
--- a/test_regress/t/t_wire_beh1800_bad.out
+++ b/test_regress/t/t_wire_beh1800_bad.out
@@ -1,20 +1,20 @@
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w'
                                              : ... In instance t
       w = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o'
                                              : ... In instance t
       o = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa'
                                              : ... In instance t
       oa = '0;   
       ^~
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'wo'
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'wo'
                                              : ... In instance t
       wo = '0;   
       ^~
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'woa'
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'woa'
                                              : ... In instance t
       woa = '0;   
       ^~~
diff --git a/test_regress/t/t_wire_behp1364_bad.out b/test_regress/t/t_wire_behp1364_bad.out
index f0f1af40a..824dd2350 100644
--- a/test_regress/t/t_wire_behp1364_bad.out
+++ b/test_regress/t/t_wire_behp1364_bad.out
@@ -1,12 +1,12 @@
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w'
                                               : ... In instance t
       w = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o'
                                               : ... In instance t
       o = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa'
                                               : ... In instance t
       oa = '0;   
       ^~
diff --git a/test_regress/t/t_wire_behp1800_bad.out b/test_regress/t/t_wire_behp1800_bad.out
index 4db8bea6a..70434db94 100644
--- a/test_regress/t/t_wire_behp1800_bad.out
+++ b/test_regress/t/t_wire_behp1800_bad.out
@@ -1,12 +1,12 @@
-%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w'
                                               : ... In instance t
       w = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o'
                                               : ... In instance t
       o = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa'
                                               : ... In instance t
       oa = '0;   
       ^~