diff --git a/.codacy.yml b/.codacy.yml index 409c852ee..7ce1f8db5 100644 --- a/.codacy.yml +++ b/.codacy.yml @@ -1,6 +1,6 @@ --- exclude_paths: - - '.github/**' - - 'ci/build_verilator.sh' - - 'include/vltstd/**' - - 'nodist/fastcov.py' + - ".github/**" + - "ci/build_verilator.sh" + - "include/vltstd/**" + - "nodist/fastcov.py" diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json index c2235983d..c0ab75ebf 100644 --- a/.devcontainer/devcontainer.json +++ b/.devcontainer/devcontainer.json @@ -1,7 +1,7 @@ { - "name": "Verilator Build Environment", + "name": "Verilator Build Environment", - "build": { + "build": { "dockerfile": "../ci/docker/buildenv/Dockerfile" } diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index dc0bcd800..43a16129d 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -1,3 +1,4 @@ +--- # DESCRIPTION: Github actions config # This name is key to badges in README.rst, so we use the name build # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @@ -9,7 +10,7 @@ on: pull_request: workflow_dispatch: schedule: - - cron: '0 0 * * 0' # weekly + - cron: '0 0 * * 0' # weekly env: CI_OS_NAME: linux @@ -35,14 +36,14 @@ jobs: strategy: fail-fast: false matrix: - os: [ubuntu-22.04, ubuntu-20.04] + os: [ubuntu-24.04, ubuntu-22.04, ubuntu-20.04] compiler: - - { cc: clang, cxx: clang++ } - - { cc: gcc, cxx: g++ } + - {cc: clang, cxx: clang++} + - {cc: gcc, cxx: g++} include: # Build GCC 10 on ubuntu-20.04 - os: ubuntu-20.04 - compiler: { cc: gcc-10, cxx: g++-10 } + compiler: {cc: gcc-10, cxx: g++-10} runs-on: ${{ matrix.os }} name: Build | ${{ matrix.os }} | ${{ matrix.compiler.cc }} env: @@ -51,41 +52,40 @@ jobs: CC: ${{ matrix.compiler.cc }} CXX: ${{ matrix.compiler.cxx }} CACHE_BASE_KEY: build-${{ matrix.os }}-${{ matrix.compiler.cc }} - CCACHE_MAXSIZE: 1000M # Per build matrix entry (* 5 = 5000M in total) + CCACHE_MAXSIZE: 1000M # Per build matrix entry (* 5 = 5000M in total) VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ matrix.os }}-${{ matrix.compiler.cc }}.tar.gz steps: - - name: Checkout - uses: actions/checkout@v4 - with: - path: repo + - name: Checkout + uses: actions/checkout@v4 + with: + path: repo - - name: Cache $CCACHE_DIR - uses: actions/cache@v4 - env: - CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache - with: - path: ${{ env.CCACHE_DIR }} - key: ${{ env.CACHE_KEY }}-${{ github.sha }} - restore-keys: | - ${{ env.CACHE_KEY }}- + - name: Cache $CCACHE_DIR + uses: actions/cache@v4 + env: + CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache + with: + path: ${{ env.CCACHE_DIR }} + key: ${{ env.CACHE_KEY }}-${{ github.sha }} + restore-keys: | + ${{ env.CACHE_KEY }}- - - name: Install packages for build - run: ./ci/ci-install.bash + - name: Install packages for build + run: ./ci/ci-install.bash - - name: Build - run: ./ci/ci-script.bash + - name: Build + run: ./ci/ci-script.bash - - name: Tar up repository - working-directory: ${{ github.workspace }} - run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo - - - name: Upload tar archive - uses: actions/upload-artifact@v4 - with: - path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }} - name: ${{ env.VERILATOR_ARCHIVE }} + - name: Tar up repository + working-directory: ${{ github.workspace }} + run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo + - name: Upload tar archive + uses: actions/upload-artifact@v4 + with: + path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }} + name: ${{ env.VERILATOR_ARCHIVE }} test: needs: build @@ -94,25 +94,25 @@ jobs: matrix: os: [ubuntu-22.04, ubuntu-20.04] compiler: - - { cc: clang, cxx: clang++ } - - { cc: gcc, cxx: g++ } + - {cc: clang, cxx: clang++} + - {cc: gcc, cxx: g++} reloc: [0] suite: [dist-vlt-0, dist-vlt-1, dist-vlt-2, dist-vlt-3, vltmt-0, vltmt-1] include: - # Test with GCC 10 on ubuntu-20.04 - - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, suite: dist-vlt-0} - - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, suite: dist-vlt-1} - - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, suite: dist-vlt-2} - - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, suite: dist-vlt-3} - - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, suite: vltmt-0} - - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, suite: vltmt-1} - # Test relocated installation - on most common platform only - - {os: ubuntu-22.04, compiler: { cc: gcc, cxx: g++ }, reloc: 1, suite: dist-vlt-0} - - {os: ubuntu-22.04, compiler: { cc: gcc, cxx: g++ }, reloc: 1, suite: dist-vlt-1} - - {os: ubuntu-22.04, compiler: { cc: gcc, cxx: g++ }, reloc: 1, suite: dist-vlt-2} - - {os: ubuntu-22.04, compiler: { cc: gcc, cxx: g++ }, reloc: 1, suite: dist-vlt-3} - - {os: ubuntu-22.04, compiler: { cc: gcc, cxx: g++ }, reloc: 1, suite: vltmt-0} - - {os: ubuntu-22.04, compiler: { cc: gcc, cxx: g++ }, reloc: 1, suite: vltmt-1} + # Test with GCC 10 on ubuntu-20.04, also test relocation + - {os: ubuntu-20.04, compiler: {cc: gcc-10, cxx: g++-10}, reloc: 1, suite: dist-vlt-0} + - {os: ubuntu-20.04, compiler: {cc: gcc-10, cxx: g++-10}, reloc: 1, suite: dist-vlt-1} + - {os: ubuntu-20.04, compiler: {cc: gcc-10, cxx: g++-10}, reloc: 1, suite: dist-vlt-2} + - {os: ubuntu-20.04, compiler: {cc: gcc-10, cxx: g++-10}, reloc: 1, suite: dist-vlt-3} + - {os: ubuntu-20.04, compiler: {cc: gcc-10, cxx: g++-10}, reloc: 1, suite: vltmt-0} + - {os: ubuntu-20.04, compiler: {cc: gcc-10, cxx: g++-10}, reloc: 1, suite: vltmt-1} + # Ubuntu 24.04 only on GCC; not passing on clang yet + - {os: ubuntu-24.04, compiler: {cc: gcc, cxx: g++}, suite: dist-vlt-0} + - {os: ubuntu-24.04, compiler: {cc: gcc, cxx: g++}, suite: dist-vlt-1} + - {os: ubuntu-24.04, compiler: {cc: gcc, cxx: g++}, suite: dist-vlt-2} + - {os: ubuntu-24.04, compiler: {cc: gcc, cxx: g++}, suite: dist-vlt-3} + - {os: ubuntu-24.04, compiler: {cc: gcc, cxx: g++}, suite: vltmt-0} + - {os: ubuntu-24.04, compiler: {cc: gcc, cxx: g++}, suite: vltmt-1} runs-on: ${{ matrix.os }} name: Test | ${{ matrix.os }} | ${{ matrix.compiler.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} env: @@ -122,37 +122,37 @@ jobs: CC: ${{ matrix.compiler.cc }} CXX: ${{ matrix.compiler.cxx }} CACHE_BASE_KEY: test-${{ matrix.os }}-${{ matrix.compiler.cc }}-${{ matrix.reloc }}-${{ matrix.suite }} - CCACHE_MAXSIZE: 100M # Per build per suite (* 5 * 5 = 2500M in total) + CCACHE_MAXSIZE: 100M # Per build per suite (* 5 * 5 = 2500M in total) VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ matrix.os }}-${{ matrix.compiler.cc }}.tar.gz steps: - - name: Download tar archive - uses: actions/download-artifact@v4 - with: - name: ${{ env.VERILATOR_ARCHIVE }} - path: ${{ github.workspace }} + - name: Download tar archive + uses: actions/download-artifact@v4 + with: + name: ${{ env.VERILATOR_ARCHIVE }} + path: ${{ github.workspace }} - - name: Unpack tar archive - working-directory: ${{ github.workspace }} - run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }} + - name: Unpack tar archive + working-directory: ${{ github.workspace }} + run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }} - - name: Cache $CCACHE_DIR - uses: actions/cache@v4 - env: - CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache2 - with: - path: ${{ env.CCACHE_DIR }} - key: ${{ env.CACHE_KEY }}-${{ github.sha }} - restore-keys: | - ${{ env.CACHE_KEY }}- + - name: Cache $CCACHE_DIR + uses: actions/cache@v4 + env: + CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache2 + with: + path: ${{ env.CCACHE_DIR }} + key: ${{ env.CACHE_KEY }}-${{ github.sha }} + restore-keys: | + ${{ env.CACHE_KEY }}- - - name: Install test dependencies - run: ./ci/ci-install.bash + - name: Install test dependencies + run: ./ci/ci-install.bash - - name: Test - env: - TESTS: ${{ matrix.suite }} - run: ./ci/ci-script.bash + - name: Test + env: + TESTS: ${{ matrix.suite }} + run: ./ci/ci-script.bash lint-py: runs-on: ubuntu-22.04 @@ -161,21 +161,21 @@ jobs: CI_BUILD_STAGE_NAME: build CI_RUNS_ON: ubuntu-22.04 steps: - - name: Checkout - uses: actions/checkout@v4 - with: - path: repo + - name: Checkout + uses: actions/checkout@v4 + with: + path: repo - - name: Install packages for build - run: ./ci/ci-install.bash + - name: Install packages for build + run: ./ci/ci-install.bash # We use specific version numbers, otherwise a Python package # update may add a warning and break our build - - name: Install packages for lint - run: sudo pip3 install pylint==3.0.2 ruff==0.1.3 clang sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe ruff + - name: Install packages for lint + run: sudo pip3 install pylint==3.0.2 ruff==0.1.3 clang sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe ruff - - name: Configure - run: autoconf && ./configure --enable-longtests --enable-ccwarn + - name: Configure + run: autoconf && ./configure --enable-longtests --enable-ccwarn - - name: Lint - run: make -k lint-py + - name: Lint + run: make -k lint-py diff --git a/.github/workflows/contributor.yml b/.github/workflows/contributor.yml index 7904a333b..6485aaf48 100644 --- a/.github/workflows/contributor.yml +++ b/.github/workflows/contributor.yml @@ -1,17 +1,16 @@ +--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - +# name: Contributor Agreement - on: push: pull_request: workflow_dispatch: - jobs: Test: name: "'docs/CONTRIBUTORS' was signed" runs-on: ubuntu-22.04 steps: - - uses: actions/checkout@v4 - - run: test_regress/t/t_dist_contributors.pl + - uses: actions/checkout@v4 + - run: test_regress/t/t_dist_contributors.py diff --git a/.github/workflows/coverage.yml b/.github/workflows/coverage.yml index 5315418ef..5fb56e65a 100644 --- a/.github/workflows/coverage.yml +++ b/.github/workflows/coverage.yml @@ -1,3 +1,4 @@ +--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @@ -6,7 +7,7 @@ name: coverage on: workflow_dispatch: schedule: - - cron: '0 0 * * 0' # weekly + - cron: '0 0 * * 0' # weekly env: CI_OS_NAME: linux @@ -21,7 +22,6 @@ defaults: jobs: - Build: runs-on: ubuntu-22.04 env: @@ -29,49 +29,36 @@ jobs: CI_RUNS_ON: ubuntu-22.04 steps: - - name: Checkout - uses: actions/checkout@v4 - with: - path: repo + - name: Checkout + uses: actions/checkout@v4 + with: + path: repo - - name: Install packages for build - run: ./ci/ci-install.bash + - name: Install packages for build + run: ./ci/ci-install.bash - - name: Build - run: ./ci/ci-script.bash + - name: Build + run: ./ci/ci-script.bash - - name: Tar up repository - working-directory: ${{ github.workspace }} - run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo - - - name: Upload tar archive - uses: actions/upload-artifact@v4 - with: - path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }} - name: ${{ env.VERILATOR_ARCHIVE }} + - name: Tar up repository + working-directory: ${{ github.workspace }} + run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo + - name: Upload tar archive + uses: actions/upload-artifact@v4 + with: + path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }} + name: ${{ env.VERILATOR_ARCHIVE }} Test: needs: Build strategy: fail-fast: false matrix: - test: - - vlt- - - vltmt- - num: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 + test: [vlt-, vltmt-] + num: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9] include: - - { test: dist, num: '' } + - {test: dist, num: ''} runs-on: ubuntu-22.04 name: test-${{ matrix.test }}${{ matrix.num }} env: @@ -79,27 +66,27 @@ jobs: CI_RUNS_ON: ubuntu-22.04 steps: - - name: Download tar archive - uses: actions/download-artifact@v4 - with: - name: ${{ env.VERILATOR_ARCHIVE }} - path: ${{ github.workspace }} + - name: Download tar archive + uses: actions/download-artifact@v4 + with: + name: ${{ env.VERILATOR_ARCHIVE }} + path: ${{ github.workspace }} - - name: Unpack tar archive - working-directory: ${{ github.workspace }} - run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }} + - name: Unpack tar archive + working-directory: ${{ github.workspace }} + run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }} - - name: Install test dependencies - run: ./ci/ci-install.bash + - name: Install test dependencies + run: ./ci/ci-install.bash - - name: Test - env: - TESTS: coverage-${{ matrix.test }}${{ matrix.num }} - run: ./ci/ci-script.bash + - name: Test + env: + TESTS: coverage-${{ matrix.test }}${{ matrix.num }} + run: ./ci/ci-script.bash - - name: Upload coverage data to Codecov - env: - CODECOV_TOKEN: ${{ secrets.CODECOV_TOKEN }} - run: | - find . -name '*.gcno' -exec rm {} \; - ./ci/codecov -v upload-process -Z --sha ${{ github.sha }} -f nodist/obj_dir/coverage/app_total.info + - name: Upload coverage data to Codecov + env: + CODECOV_TOKEN: ${{ secrets.CODECOV_TOKEN }} + run: | + find . -name '*.gcno' -exec rm {} \; + ./ci/codecov -v upload-process -Z --sha ${{ github.sha }} -f nodist/obj_dir/coverage/app_total.info diff --git a/.github/workflows/docker.yml b/.github/workflows/docker.yml index 7a55fa921..574d77b35 100644 --- a/.github/workflows/docker.yml +++ b/.github/workflows/docker.yml @@ -1,3 +1,4 @@ +--- # Build and push verilator docker image when tags are pushed to the repository. # The following variable(s) must be configured in the github repository: # DOCKER_HUB_NAMESPACE: docker hub namespace. @@ -8,7 +9,7 @@ name: Build Verilator Container on: push: - tags: [ 'v*' ] + tags: ['v*'] workflow_dispatch: inputs: manual_tag: @@ -34,52 +35,52 @@ jobs: # - "ci/docker/buildenv:verilator-buildenv" steps: - - name: Checkout - uses: actions/checkout@v4 + - name: Checkout + uses: actions/checkout@v4 - - name: Extract context variables - run: | - echo "${{ matrix.contexts }}" | sed -r 's/(.*):.*/build_context=\1/' >> "$GITHUB_ENV" - echo "${{ matrix.contexts }}" | sed -r 's/.*:(.*)/image_name=\1/' >> "$GITHUB_ENV" - echo "git_tag=${GITHUB_REF#refs/*/}" >> "$GITHUB_ENV" + - name: Extract context variables + run: | + echo "${{ matrix.contexts }}" | sed -r 's/(.*):.*/build_context=\1/' >> "$GITHUB_ENV" + echo "${{ matrix.contexts }}" | sed -r 's/.*:(.*)/image_name=\1/' >> "$GITHUB_ENV" + echo "git_tag=${GITHUB_REF#refs/*/}" >> "$GITHUB_ENV" - - name: Use manual tag - if: ${{ inputs.manual_tag }} - run: | - echo "git_tag=${{ inputs.manual_tag }}" >> "$GITHUB_ENV" + - name: Use manual tag + if: ${{ inputs.manual_tag }} + run: | + echo "git_tag=${{ inputs.manual_tag }}" >> "$GITHUB_ENV" - - name: Docker meta - id: docker_meta - uses: docker/metadata-action@v4 - with: - images: | - ${{ vars.DOCKER_HUB_NAMESPACE }}/${{ env.image_name }} - tags: | - type=match,pattern=(v.*),group=1,enable=${{ startsWith(github.ref, 'refs/tags/v') }} - type=raw,value=${{ inputs.manual_tag }},enable=${{ inputs.manual_tag != '' }} - type=raw,value=latest,enable=${{ inputs.add_latest_tag == true }} + - name: Docker meta + id: docker_meta + uses: docker/metadata-action@v4 + with: + images: | + ${{ vars.DOCKER_HUB_NAMESPACE }}/${{ env.image_name }} + tags: | + type=match,pattern=(v.*),group=1,enable=${{ startsWith(github.ref, 'refs/tags/v') }} + type=raw,value=${{ inputs.manual_tag }},enable=${{ inputs.manual_tag != '' }} + type=raw,value=latest,enable=${{ inputs.add_latest_tag == true }} - - name: Set up QEMU - uses: docker/setup-qemu-action@v2 + - name: Set up QEMU + uses: docker/setup-qemu-action@v2 - - name: Set up Docker Buildx - uses: docker/setup-buildx-action@v2 - with: + - name: Set up Docker Buildx + uses: docker/setup-buildx-action@v2 + with: buildkitd-flags: --debug - - name: Login to Docker Hub - uses: docker/login-action@v2 - with: - username: ${{ secrets.DOCKER_HUB_USER }} - password: ${{ secrets.DOCKER_HUB_ACCESS_TOKEN }} + - name: Login to Docker Hub + uses: docker/login-action@v2 + with: + username: ${{ secrets.DOCKER_HUB_USER }} + password: ${{ secrets.DOCKER_HUB_ACCESS_TOKEN }} - - name: Build and Push to Docker - uses: docker/build-push-action@v4 - if: startsWith(github.ref, 'refs/tags/v') - with: - context: ${{ env.build_context }} - build-args: SOURCE_COMMIT=${{ env.git_tag }} - platforms: linux/arm64,linux/amd64 - push: ${{ !env.ACT && startsWith(github.ref, 'refs/tags/v') }} - tags: ${{ steps.docker_meta.outputs.tags }} - labels: ${{ steps.docker_meta.outputs.labels }} + - name: Build and Push to Docker + uses: docker/build-push-action@v4 + if: startsWith(github.ref, 'refs/tags/v') + with: + context: ${{ env.build_context }} + build-args: SOURCE_COMMIT=${{ env.git_tag }} + platforms: linux/arm64,linux/amd64 + push: ${{ !env.ACT && startsWith(github.ref, 'refs/tags/v') }} + tags: ${{ steps.docker_meta.outputs.tags }} + labels: ${{ steps.docker_meta.outputs.labels }} diff --git a/.github/workflows/format.yml b/.github/workflows/format.yml index 6a498715d..4fbd884c5 100644 --- a/.github/workflows/format.yml +++ b/.github/workflows/format.yml @@ -1,13 +1,12 @@ +--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - +# name: format - on: push: pull_request_target: workflow_dispatch: - jobs: format: runs-on: ubuntu-22.04 diff --git a/.github/workflows/msbuild.yml b/.github/workflows/msbuild.yml index 95c5ceee1..b7e5677c6 100644 --- a/.github/workflows/msbuild.yml +++ b/.github/workflows/msbuild.yml @@ -1,55 +1,50 @@ +--- # DESCRIPTION: Github actions config # This name is key to badges in README.rst, so we use the name build # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - +# name: msbuild - on: push: pull_request: workflow_dispatch: schedule: - - cron: '0 0 * * 0' # weekly - + - cron: 0 0 * * 0 # weekly env: CI_OS_NAME: win CI_COMMIT: ${{ github.sha }} CCACHE_COMPRESS: 1 CCACHE_DIR: ${{ github.workspace }}/.ccache CCACHE_LIMIT_MULTIPLE: 0.95 - defaults: run: working-directory: repo - concurrency: group: ${{ github.workflow }}-${{ github.event_name == 'pull_request' && github.ref || github.run_id }} cancel-in-progress: true - jobs: - - windows: + windows: name: run on windows runs-on: windows-latest steps: - - uses: actions/checkout@v4 - with: - path: repo - - name: Cache $CCACHE_DIR - uses: actions/cache@v4 - with: - path: ${{ env.CCACHE_DIR }} - key: msbuild-msvc-cmake - - name: compile - env: - WIN_FLEX_BISON: ${{ github.workspace }}/.ccache - run: ./ci/ci-win-compile.ps1 - - name: test build - run: ./ci/ci-win-test.ps1 - - name: Zip up repository - run: Compress-Archive -LiteralPath install -DestinationPath verilator.zip - - name: Upload zip archive - uses: actions/upload-artifact@v4 - with: - path: ${{ github.workspace }}/repo/verilator.zip - name: verilator-win.zip + - uses: actions/checkout@v4 + with: + path: repo + - name: Cache $CCACHE_DIR + uses: actions/cache@v4 + with: + path: ${{ env.CCACHE_DIR }} + key: msbuild-msvc-cmake + - name: compile + env: + WIN_FLEX_BISON: ${{ github.workspace }}/.ccache + run: ./ci/ci-win-compile.ps1 + - name: test build + run: ./ci/ci-win-test.ps1 + - name: Zip up repository + run: Compress-Archive -LiteralPath install -DestinationPath verilator.zip + - name: Upload zip archive + uses: actions/upload-artifact@v4 + with: + path: ${{ github.workspace }}/repo/verilator.zip + name: verilator-win.zip diff --git a/.gitignore b/.gitignore index f3325984e..f627ea0f6 100644 --- a/.gitignore +++ b/.gitignore @@ -29,14 +29,15 @@ dddrun* doxygen-doc gdbrun* gmon.out -ncverilog.history internals.txt +ncverilog.history +nohup.out +verilator-config-version.cmake +verilator-config.cmake +verilator.pc verilator.txt verilator_bin* verilator_coverage_bin* -verilator.pc -verilator-config.cmake -verilator-config-version.cmake **/__pycache__/* **/_build/* **/obj_dir/* diff --git a/.pre-commit-hooks.yaml b/.pre-commit-hooks.yaml new file mode 100644 index 000000000..9722691b3 --- /dev/null +++ b/.pre-commit-hooks.yaml @@ -0,0 +1,8 @@ +--- +- id: verilator + name: verilator-lint + description: Runs verilator Docker image to lint (System) Verilog designs + args: [--lint-only] + language: docker_image + entry: verilator/verilator:latest + types_or: [verilog, system-verilog] diff --git a/.style.yapf b/.style.yapf new file mode 100644 index 000000000..4f7cc6964 --- /dev/null +++ b/.style.yapf @@ -0,0 +1,4 @@ +[style] +based_on_style = pep8 +column_limit = 99 +#split_before_arithmetic_operator=True diff --git a/CMakeLists.txt b/CMakeLists.txt index fd18d6147..59ae991b5 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -14,37 +14,44 @@ cmake_minimum_required(VERSION 3.15) cmake_policy(SET CMP0091 NEW) # Use MSVC_RUNTIME_LIBRARY to select the runtime -project(Verilator - VERSION 5.028 +project( + Verilator + VERSION 5.030 HOMEPAGE_URL https://verilator.org LANGUAGES CXX ) -option(DEBUG_AND_RELEASE_AND_COVERAGE - "Builds both the debug and release binaries, overriding CMAKE_BUILD_TYPE. Not supported under MSBuild.") +option( + DEBUG_AND_RELEASE_AND_COVERAGE + "Builds both the debug and release binaries, overriding CMAKE_BUILD_TYPE. Not supported under MSBuild." +) find_package(Python3 COMPONENTS Interpreter) set(PYTHON3 ${Python3_EXECUTABLE}) -set(CMAKE_INSTALL_DATADIR ${CMAKE_INSTALL_PREFIX}) +# See also CMake built-in; CMAKE_INSTALL_PREFIX is applied by the install command. +set(CMAKE_INSTALL_DATADIR .) include(GNUInstallDirs) include(CMakePackageConfigHelpers) include(CheckStructHasMember) include(ExternalProject) include(FindThreads) -if (NOT WIN32) +if(NOT WIN32) message(WARNING "CMake support on Linux/OSX is experimental.") endif() -if (WIN32) - if (DEFINED ENV{WIN_FLEX_BISON}) +if(WIN32) + if(DEFINED ENV{WIN_FLEX_BISON}) set(WIN_FLEX_BISON "$ENV{WIN_FLEX_BISON}") endif() - if (EXISTS ${WIN_FLEX_BISON}) + if(EXISTS ${WIN_FLEX_BISON}) list(APPEND CMAKE_PREFIX_PATH ${WIN_FLEX_BISON}) endif() - if (NOT WIN_FLEX_BISON) - message(FATAL_ERROR "Please install https://github.com/lexxmark/winflexbison and set WIN_FLEX_BISON environment variable. Please use install cmake target after a successful build.") + if(NOT WIN_FLEX_BISON) + message( + FATAL_ERROR + "Please install https://github.com/lexxmark/winflexbison and set WIN_FLEX_BISON environment variable. Please use install cmake target after a successful build." + ) endif() set(CMAKE_CXX_STANDARD 20) endif() @@ -52,20 +59,25 @@ endif() set(OBJCACHE "" CACHE STRING "Path for ccache, auto-detected if empty") option(OBJCACHE_ENABLED "Compile Verilator with ccache" ON) -if (OBJCACHE_ENABLED) - if (OBJCACHE STREQUAL "") +if(OBJCACHE_ENABLED) + if(OBJCACHE STREQUAL "") find_program(OBJCACHE_PATH ccache) - if (OBJCACHE_PATH STREQUAL "OBJCACHE_PATH-NOTFOUND") + if(OBJCACHE_PATH STREQUAL "OBJCACHE_PATH-NOTFOUND") set(OBJCACHE_PATH "") endif() else() set(OBJCACHE_PATH "${OBJCACHE}") endif() - if (NOT OBJCACHE_PATH STREQUAL "") - execute_process(COMMAND "${OBJCACHE_PATH}" --version - OUTPUT_VARIABLE objcache_version) + if(NOT OBJCACHE_PATH STREQUAL "") + execute_process( + COMMAND "${OBJCACHE_PATH}" --version + OUTPUT_VARIABLE objcache_version + ) string(REGEX MATCH "[^\n\r]+" objcache_version "${objcache_version}") - message(STATUS "Found ccache: ${OBJCACHE_PATH} (\"${objcache_version}\")") + message( + STATUS + "Found ccache: ${OBJCACHE_PATH} (\"${objcache_version}\")" + ) set(CMAKE_CXX_COMPILER_LAUNCHER "${OBJCACHE_PATH}") endif() endif() @@ -76,8 +88,8 @@ find_package(FLEX) # Build #set_property(GLOBAL PROPERTY JOB_POOLS one_job=1) -if (DEBUG_AND_RELEASE_AND_COVERAGE) - if (CMAKE_GENERATOR MATCHES "^Visual Studio ") +if(DEBUG_AND_RELEASE_AND_COVERAGE) + if(CMAKE_GENERATOR MATCHES "^Visual Studio ") error("%Error: The DEBUG_AND_RELEASE_AND_COVERAGE option is not supported in MSBuild-based builds.") endif() set(saved_build_type ${CMAKE_BUILD_TYPE}) @@ -102,22 +114,39 @@ set(AR ${CMAKE_AR}) configure_file(include/verilated_config.h.in include/verilated_config.h @ONLY) configure_file(include/verilated.mk.in include/verilated.mk @ONLY) -install(FILES ${CMAKE_CURRENT_BINARY_DIR}/include/verilated_config.h DESTINATION ${CMAKE_INSTALL_PREFIX}/include) -install(FILES ${CMAKE_CURRENT_BINARY_DIR}/include/verilated.mk DESTINATION ${CMAKE_INSTALL_PREFIX}/include) - -configure_package_config_file(verilator-config.cmake.in verilator-config.cmake - INSTALL_DESTINATION ${CMAKE_INSTALL_PREFIX} +install( + FILES ${CMAKE_CURRENT_BINARY_DIR}/include/verilated_config.h + DESTINATION include +) +install( + FILES ${CMAKE_CURRENT_BINARY_DIR}/include/verilated.mk + DESTINATION include ) -install(FILES ${CMAKE_CURRENT_BINARY_DIR}/verilator-config.cmake DESTINATION ${CMAKE_INSTALL_PREFIX}) - -configure_package_config_file(verilator-config-version.cmake.in verilator-config-version.cmake - INSTALL_DESTINATION ${CMAKE_INSTALL_PREFIX} +configure_package_config_file( + verilator-config.cmake.in + verilator-config.cmake + INSTALL_DESTINATION . ) -install(FILES ${CMAKE_CURRENT_BINARY_DIR}/verilator-config-version.cmake DESTINATION ${CMAKE_INSTALL_PREFIX}) +install( + FILES ${CMAKE_CURRENT_BINARY_DIR}/verilator-config.cmake + DESTINATION . +) -foreach (program +configure_package_config_file( + verilator-config-version.cmake.in + verilator-config-version.cmake + INSTALL_DESTINATION . +) + +install( + FILES ${CMAKE_CURRENT_BINARY_DIR}/verilator-config-version.cmake + DESTINATION . +) + +foreach( + program verilator verilator_gantt verilator_ccache_report @@ -128,13 +157,19 @@ foreach (program install(PROGRAMS bin/${program} TYPE BIN) endforeach() -install(DIRECTORY examples TYPE DATA FILES_MATCHING +install( + DIRECTORY examples + TYPE DATA + FILES_MATCHING PATTERN "examples/*/*.[chv]*" PATTERN "examples/*/Makefile*" PATTERN "examples/*/CMakeLists.txt" ) -install(DIRECTORY include TYPE DATA FILES_MATCHING +install( + DIRECTORY include + TYPE DATA + FILES_MATCHING PATTERN "include/verilated_config.h" PATTERN "include/*.[chv]" PATTERN "include/*.cpp" diff --git a/Changes b/Changes index 5dbc67208..ad9894665 100644 --- a/Changes +++ b/Changes @@ -8,6 +8,103 @@ The changes in each Verilator version are described below. The contributors that suggested a given feature are shown in []. Thanks! +Verilator 5.030 2024-10-27 +========================== + +**Major:** + +* Add `-output-groups` to build with concatenated .cpp files (#5257). [Mariusz Glebocki] +* Self-tests have been converted to Python, run `{test_name}.py` instead of `{test_name}.pl`. + +**Minor:** + +* Change .vlt config files to be read before .v files (#5185). [David Moberg] +* Change to use maximum for cover point aggregation (#5402). [Andrew Nolte] +* Change `--main` and `--binary` to use a TOP hierarchy name of "" (#5482). +* Change install of public executables into bindir instead of pkgdatadir (#5140) (#5544). [Geza Lore] +* Support IEEE-compliant intra-assign delays (#3711) (#5441). [Krzysztof Bieganski, Antmicro Ltd.] +* Support `wor`, `trior`, `wand`, `triand` (#5386) (#5496). [Zhou Shen] +* Support unconstrained randomization for unions (#5395) (#5396). [Yilou Wang] +* Support basic constrained queue randomization (#5413). [Arkadiusz Kozdra, Antmicro Ltd.] +* Support packed/unpacked and dynamic array unconstrained randomization (#5414) (#5415). [Yilou Wang] +* Support appending to queue via `[]` (#5421). [Krzysztof Bieganski, Antmicro Ltd.] +* Support named event locals (#5422). [Krzysztof Bieganski, Antmicro Ltd.] +* Support basic `dist` constraints (#5431). [Arkadiusz Kozdra, Antmicro Ltd.] +* Support unpacked array constrained randomization (#5437) (#5489). [Yilou Wang] +* Support inside array constraints (#5448). [Arkadiusz Kozdra, Antmicro Ltd.] +* Support DPI imports and exports with double underscores (#5481). +* Support ccache when compiling Verilated files with cmake. +* Support `local` and `protected` on `typedef` (#5460). +* Support unconstrained randomization for associative array and queue (#5515). [Yilou Wang] +* Support `rand` dynamic arrays of objects (#5557) (#5564). [Ryszard Rozak, Antmicro Ltd.] +* Add error on misused genvar (#408). [Alex Solomatnikov] +* Add error on instances without parenthesis. +* Add Docker pre-commit hook (#5238) (#5452). [Chris Bachhuber] +* Add partial coverage symbol and branch data in lcov info files (#5388). [Andrew Nolte] +* Add method to check if there are VPI callbacks of the given type (#5399). [Kaleb Barrett] +* Remove warning on unsized numbers exceeding 32-bits. +* Improve Verilation thread pool (#5161). [Bartłomiej Chmiel, Antmicro Ltd.] +* Improve performance of V3VariableOrder with parallelism (#5406). [Bartłomiej Chmiel, Antmicro Ltd.] +* Improve parser error handling (#5493). [Arkadiusz Kozdra, Antmicro Ltd.] +* Improve process trigger performance (#5483). [Geza Lore] +* Fix suppression of WIDTH* warnings when immediately under a size cast (#3417). +* Fix `$fatal` to not be affected by `+verilator+error+limit` (#5135). [Gökçe Aydos] +* Fix equivalence checking when replacing type parameters (#5213) (#5255). [Han Qi] +* Fix display with multiple string formats (#5311). [Luiza de Melo] +* Fix performance of V3Trace when many activity blocks (#5372). [Deniz Güzel] +* Fix REALCVT warning on integral timescale conversions (#5378). [Liam Braun] +* Fix multidimensional function return value selects (#5382). [Gökçe Aydos] +* Fix internal error in out-of-range select (#5393) (#5443). [Geza Lore] +* Fix dot fallback finding wrong symbols (#5394). [Arkadiusz Kozdra, Antmicro Ltd.] +* Fix infinite recursion due to recursive functions/tasks (#5398). [Krzysztof Bieganski, Antmicro Ltd.] +* Fix V3Randomize compile error on old GCC (#5403) (#5417). [Krzysztof Bieganski, Antmicro Ltd.] +* Fix extra events in traces (#5405). +* Fix empty `foreach` in `if` in constraints (#5408). [Krzysztof Bieganski, Antmicro Ltd.] +* Fix queue `[$-i]` select as reference argument (#5411). [Krzysztof Bieganski, Antmicro Ltd.] +* Fix `pre`/`post_randomize` on `randomize() with` (#5412). [Krzysztof Bieganski, Antmicro Ltd.] +* Fix capturing params in `randomize() with` (#5416) (#5418). [Krzysztof Bieganski, Antmicro Ltd.] +* Fix `sformatf` internal error on initial automatics (#5423). [Todd Strader] +* Fix clearing trigger of events with no sensitivity trees (#5426). [Arkadiusz Kozdra, Antmicro Ltd.] +* Fix driving clocking block in reactive region (#5430). [Krzysztof Bieganski, Antmicro Ltd.] +* Fix associative array next/prev/first/last mis-propagating constants (#5435). [Ethan Sifferman] +* Fix randomize treated as std::randomize in classes (#5436). [Arkadiusz Kozdra, Antmicro Ltd.] +* Fix `foreach` colliding index names (#5444). [Arkadiusz Kozdra, Antmicro Ltd.] +* Fix fault on defparam with UNSUPPORTED ignored (#5450). [Luiza de Melo] +* Fix class reference with pin that is a class reference (#5454). +* Fix not reporting class reference with extra parameters (#5467). +* Fix user-type parameter overlap (#5469). [Todd Strader] +* Fix tracing when name() is empty (#5470). [Sam Shahrestani] +* Fix timing mode not exiting on empty events (#5472). +* Fix coverage counts missing due to table optimization (#5473) (#5474). [Vito Gamberini] +* Fix `--binary` with .cpp PLI filenames under relative directory paths. +* Fix extra dot in coverage point hierarchy when using name()=''. +* Fix short-circuiting with associative array access (#5484). [Ethan Sifferman] +* Fix short-circuiting on method calls (#5486). [Ethan Sifferman] +* Fix exponential concatenate performance (#5488). [Arkadiusz Kozdra, Antmicro Ltd.] +* Fix V3Table trying to generate 'x' bits in the lookup table. (#5491). [Geza Lore] +* Fix randomize with foreach constraints (#5492). [Arkadiusz Kozdra, Antmicro Ltd.] +* Fix explicit CMAKE_INSTALL_PREFIX usages (#5500). [Fabian Keßler] +* Fix configure inserting absolute paths for Python and Perl (#5504) (#5505). [Nathan Graybeal] +* Fix pattern initialization with typedef key (#5512). [Eugene Feinberg] +* Fix `-j` option without argument in hierarchical Verilation (#5514). [Ryszard Rozak, Antmicro Ltd.] +* Fix `foreach` with 2-D queues and dynamic arrays (#5525) (#5529). [Yilou Wang] +* Fix struct array assignment (#5455) (#5537). [Yilou Wang] +* Fix copy constructor of classes that use std::process (#5528). [Ryszard Rozak, Antmicro Ltd.] +* Fix foreach on associative array (#5530). [Yilou Wang] +* Fix multi-range indices assignment (#5534) (#5547). [Yilou Wang] +* Fix static function wrappers (#5536). [Ryszard Rozak, Antmicro Ltd.] +* Fix assignments of concatenation to queues and dynamic arrays (#5540). [Ryszard Rozak, Antmicro Ltd.] +* Fix container reduction methods (#5542). [Krzysztof Boroński] +* Fix complex user type problem with `--x-assign` (#5543). [Todd Strader] +* Fix long module names crashing string handling (#5546). [Filip Badáň] +* Fix array trace splitting (#5549). [Todd Strader] +* Fix queue element access (#5551). [Ryszard Rozak, Antmicro Ltd.] +* Fix struct literal on pattern assignment (#5552) (#5559). [Todd Strader] +* Fix build on gcc when using the Spack wrapper (#5555). [Eric Müller] +* Fix enum name method (#5563). [Todd Strader] +* Fix `$countbits` in assert with non-tristates (#5566). [Shou-Li Hsu] + + Verilator 5.028 2024-08-21 ========================== @@ -208,9 +305,10 @@ Verilator 5.024 2024-04-05 * Fix preprocessor to respect strings in joins (#5007). * Fix tracing class parameters (#5014). * Fix memory leaks (#5016). [Geza Lore] -* Fix $readmem with missing newline (#5019). [Josse Van Delm] +* Fix `$readmem` with missing newline (#5019). [Josse Van Delm] * Fix internal error on missing pattern key (#5023). * Fix tracing replicated hierarchical models (#5027). +* Fix false LIFETIME warning on `repeat` in `fork-join` (#5456). Verilator 5.022 2024-02-24 @@ -549,7 +647,7 @@ Verilator 5.012 2023-06-13 * Fix wide structure VL_TOSTRING_W generation (#4188) (#4189). [Aylon Chaim Porat] * Fix references to members of parameterized base classes (#4196). [Ryszard Rozak, Antmicro Ltd] * Fix tracing undefined alignment (#4201) (#4288) [John Wehle] -* Fix class specific same methods for AstVarScope, AstVar, and AstScope (#4203) (#4250). [John Wehle] +* Fix class-specific same methods for AstVarScope, AstVar, and AstScope (#4203) (#4250). [John Wehle] * Fix dotted references in parameterized classes (#4206). [Ryszard Rozak, Antmicro Ltd] * Fix bit selections under parameterized classes (#4210). [Ryszard Rozak, Antmicro Ltd] * Fix duplicate std:: declaration with -I (#4215). [Harald Pretl] diff --git a/Makefile.in b/Makefile.in index ad2cd2c6c..025294225 100644 --- a/Makefile.in +++ b/Makefile.in @@ -52,6 +52,7 @@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_DATA = @INSTALL_DATA@ MAKEINFO = makeinfo POD2TEXT = pod2text +PYTHON3 = @PYTHON3@ MKINSTALLDIRS = $(SHELL) $(srcdir)/src/mkinstalldirs # Version (for docs/guide/conf.py) @@ -76,7 +77,7 @@ datadir = @datadir@ # Directory in which to install documentation info files. infodir = @infodir@ -# Directory in which to install package specific files +# Directory in which to install package-specific files # Generally ${prefix}/share/verilator pkgdatadir = @pkgdatadir@ @@ -96,6 +97,7 @@ PACKAGE_VERSION = @PACKAGE_VERSION@ #### End of system configuration section. #### ###################################################################### +# Main build targets .SUFFIXES: @@ -146,6 +148,9 @@ verilator_exe verilator_bin$(EXEEXT) verilator_bin_dbg$(EXEEXT) verilator_covera @echo "making verilator in src" $(MAKE) -C src $(OBJCACHE_JOBS) +###################################################################### +# Tests + .PHONY:msg_test msg_test: all_nomsg @echo "Build complete!" @@ -156,7 +161,7 @@ msg_test: all_nomsg .PHONY: test ifeq ($(CFG_WITH_LONGTESTS),yes) # Local... Else don't burden users test: smoke-test test_regress -# examples is part of test_regress's test_regress/t/t_a2_examples.pl +# examples is part of test_regress's test_regress/t/t_a2_examples.py # (because that allows it to run in parallel with other test_regress's) else test: smoke-test examples @@ -168,8 +173,8 @@ endif @echo smoke-test: all_nomsg - test_regress/t/t_a1_first_cc.pl - test_regress/t/t_a2_first_sc.pl + test_regress/t/t_a1_first_cc.py + test_regress/t/t_a2_first_sc.py test_regress: all_nomsg $(MAKE) -C test_regress @@ -183,6 +188,9 @@ examples: all_nomsg $(MAKE) -C $$p VERILATOR_ROOT=`pwd` || exit 10; \ done +###################################################################### +# Docs + .PHONY: docs docs: info @@ -204,6 +212,20 @@ verilator.html: verilator.pdf: Makefile $(MAKE) -C docs verilator.pdf +TAGFILES=${srcdir}/*/*.cpp ${srcdir}/*/*.h ${srcdir}/*/*.in \ + ${srcdir}/*.in ${srcdir}/*.pod + +TAGS: $(TAGFILES) + etags $(TAGFILES) + +.PHONY: doxygen + +doxygen: + $(MAKE) -C docs doxygen + +###################################################################### +# Install + # Public executables intended to be invoked directly by the user # Don't put wildcards in these variables, it might cause an uninstall of other stuff VL_INST_PUBLIC_SCRIPT_FILES = verilator \ @@ -244,11 +266,15 @@ mkbindirs: installbin: | mkbindirs cd $(srcdir)/bin; \ for p in $(VL_INST_PUBLIC_SCRIPT_FILES) ; do \ - $(INSTALL_PROGRAM) $$p $(DESTDIR)$(pkgdatadir)/bin/$$p; \ + $(INSTALL_PROGRAM) $$p $(DESTDIR)$(bindir)/$$p; \ done + perl -p -i -e 'use File::Spec;' \ + -e' $$path = File::Spec->abs2rel("$(realpath $(DESTDIR)$(pkgdatadir))", "$(realpath $(DESTDIR)$(bindir))");' \ + -e 's/my \$$verilator_pkgdatadir_relpath = .*/my \$$verilator_pkgdatadir_relpath = "$$path";/g' \ + -- "$(DESTDIR)/$(bindir)/verilator" cd bin; \ for p in $(VL_INST_PUBLIC_BIN_FILES) ; do \ - $(INSTALL_PROGRAM) $$p $(DESTDIR)$(pkgdatadir)/bin/$$p; \ + $(INSTALL_PROGRAM) $$p $(DESTDIR)$(bindir)/$$p; \ done cd $(srcdir)/bin; \ for p in $(VL_INST_PRIVATE_SCRIPT_FILES) ; do \ @@ -258,11 +284,11 @@ installbin: | mkbindirs installredirect: installbin | mkbindirs cp ${srcdir}/bin/redirect ${srcdir}/bin/redirect.tmp perl -p -i -e 'use File::Spec;' \ - -e' $$path = File::Spec->abs2rel("$(realpath $(DESTDIR)$(pkgdatadir)/bin)", "$(realpath $(DESTDIR)$(bindir))");' \ + -e' $$path = File::Spec->abs2rel("$(realpath $(DESTDIR)$(bindir))", "$(realpath $(DESTDIR)$(pkgdatadir)/bin)");' \ -e 's/RELPATH.*/"$$path";/g' -- "${srcdir}/bin/redirect.tmp" cd $(srcdir)/bin; \ for p in $(VL_INST_PUBLIC_SCRIPT_FILES) $(VL_INST_PUBLIC_BIN_FILES) ; do \ - $(INSTALL_PROGRAM) redirect.tmp $(DESTDIR)$(bindir)/$$p; \ + $(INSTALL_PROGRAM) redirect.tmp $(DESTDIR)$(pkgdatadir)/bin/$$p; \ done rm ${srcdir}/bin/redirect.tmp @@ -344,6 +370,19 @@ install-all: installbin installredirect installman installdata install-msg install-here: installman info +install-msg: + @echo + @echo "Installed binaries to $(DESTDIR)$(bindir)/verilator" + @echo "Installed man to $(DESTDIR)$(mandir)/man1" + @echo "Installed examples to $(DESTDIR)$(pkgdatadir)/examples" + @echo + @echo "For documentation see 'man verilator' or 'verilator --help'" + @echo "For forums and to report bugs see https://verilator.org" + @echo + +###################################################################### +# Format/Lint + # Use --xml flag to see the cppcheck code to use for suppression CPPCHECK1_CPP = $(wildcard $(srcdir)/include/*.cpp) CPPCHECK2_CPP = $(wildcard $(srcdir)/examples/*/*.cpp) @@ -411,7 +450,8 @@ analyzer-include: -rm -rf examples/*/obj* scan-build $(MAKE) -k examples -format: clang-format yapf format-pl-exec +format: + $(MAKE) -j 4 clang-format yapf format-exec CLANGFORMAT = clang-format-14 CLANGFORMAT_FLAGS = -i @@ -422,6 +462,20 @@ clang-format: || echo "*** You are not using clang-format-14, indents may differ from master's ***" $(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES) +YAMLFIX = YAMLFIX_WHITELINES=1 YAMLFIX_LINE_LENGTH=130 YAMLFIX_preserve_quotes=true yamlfix + +yamlfix: + $(YAMLFIX) . + +# CMake files +CMAKE_FILES = \ + CMakeLists.txt \ + examples/*/CMakeLists.txt \ + src/CMakeLists.txt \ + test_regress/CMakeLists.txt \ + *.cmake.in \ + +# Python programs, subject to format and lint PY_PROGRAMS = \ bin/verilator_ccache_report \ bin/verilator_difftree \ @@ -440,6 +494,7 @@ PY_PROGRAMS = \ src/flexfix \ src/vlcovgen \ src/.gdbinit.py \ + test_regress/*.py \ test_regress/t/*.pf \ nodist/clang_check_attributes \ nodist/code_coverage \ @@ -449,44 +504,53 @@ PY_PROGRAMS = \ nodist/install_test \ nodist/log_changes \ +# Python files, subject to format but not lint PY_FILES = \ $(PY_PROGRAMS) \ nodist/code_coverage.dat \ + test_regress/t/*.py \ + +# Python files, test_regress tests +PY_TEST_FILES = \ + test_regress/t/*.py \ YAPF = yapf3 -YAPF_FLAGS = -i +YAPF_FLAGS = -i --parallel yapf: $(YAPF) $(YAPF_FLAGS) $(PY_FILES) +GERSEMI = gersemi +GERSEMI_FLAGS = -i + +format-cmake: + $(GERSEMI) $(GERSEMI_FLAGS) $(CMAKE_FILES) + PYLINT = pylint -PYLINT_FLAGS = --score=n --disable=R0801 +PYLINT_FLAGS = --recursive=n --score=n --disable=R0801 +PYLINT_TEST_FLAGS = $(PYLINT_FLAGS) --disable=C0103,C0114,C0116,C0209,C0411,C0413,C0301,R0801,R0912,R0915,R0916,R1702,W0511,W0621 RUFF = ruff RUFF_FLAGS = check --ignore=E402,E501,E701 # "make -k" so can see all tool result errors lint-py: - $(MAKE) -k lint-py-pylint lint-py-ruff + $(MAKE) -k lint-py-pylint lint-py-pylint-tests lint-py-ruff lint-py-pylint: $(PYLINT) $(PYLINT_FLAGS) $(PY_PROGRAMS) +lint-py-pylint-tests: + $(PYLINT) $(PYLINT_TEST_FLAGS) $(PY_TEST_FILES) | $(PYTHON3) nodist/lint_py_test_filter + lint-py-ruff: $(RUFF) $(RUFF_FLAGS) $(PY_PROGRAMS) -format-pl-exec: - -chmod a+x test_regress/t/*.pl +format-exec: + -chmod a+x test_regress/t/*.py -install-msg: - @echo - @echo "Installed binaries to $(DESTDIR)$(bindir)/verilator" - @echo "Installed man to $(DESTDIR)$(mandir)/man1" - @echo "Installed examples to $(DESTDIR)$(pkgdatadir)/examples" - @echo - @echo "For documentation see 'man verilator' or 'verilator --help'" - @echo "For forums and to report bugs see https://verilator.org" - @echo +###################################################################### +# Configure IN_WILD := ${srcdir}/*.in ${srcdir}/*/*.in @@ -507,6 +571,9 @@ else autoconf endif +###################################################################### +# Clean + maintainer-clean:: @echo "This command is intended for maintainers to use;" @echo "rebuilding the deleted files requires autoconf." @@ -537,17 +604,6 @@ distclean maintainer-clean:: rm -f bin/verilator_bin* bin/verilator_coverage_bin* rm -f include/verilated.mk include/verilated_config.h -TAGFILES=${srcdir}/*/*.cpp ${srcdir}/*/*.h ${srcdir}/*/*.in \ - ${srcdir}/*.in ${srcdir}/*.pod - -TAGS: $(TAGFILES) - etags $(TAGFILES) - -.PHONY: doxygen - -doxygen: - $(MAKE) -C docs doxygen - ###################################################################### # Distributions diff --git a/bin/verilator b/bin/verilator index 453138e1b..1ca6d3b8c 100755 --- a/bin/verilator +++ b/bin/verilator @@ -69,7 +69,9 @@ if (! GetOptions( pod2usage(-exitstatus => 2, -verbose => 0); } -my $verilator_root = realpath("$RealBin/.."); +# WARNING: $verilator_pkgdatadir_relpath is substituted during Verilator 'make install' +my $verilator_pkgdatadir_relpath = ".."; +my $verilator_root = realpath("$RealBin/$verilator_pkgdatadir_relpath"); if (defined $ENV{VERILATOR_ROOT}) { if ((!-d $ENV{VERILATOR_ROOT}) || $verilator_root ne realpath($ENV{VERILATOR_ROOT})) { warn "%Error: verilator: VERILATOR_ROOT is set to inconsistent path. Suggest leaving it unset.\n"; @@ -405,6 +407,7 @@ detailed descriptions of these arguments. -O3 High-performance optimizations -O Selectable optimizations -o Name of final executable + --output-groups Group .cpp files into larger ones --output-split Split .cpp files into pieces --output-split-cfuncs Split model functions --output-split-ctrace Split tracing functions diff --git a/bin/verilator_ccache_report b/bin/verilator_ccache_report index 43c4543f9..92355a898 100755 --- a/bin/verilator_ccache_report +++ b/bin/verilator_ccache_report @@ -16,8 +16,7 @@ parser = argparse.ArgumentParser( For documentation see https://verilator.org/guide/latest/exe_verilator_ccache_report.html""", - epilog= - """Copyright 2002-2024 by Wilson Snyder. This program is free software; you + epilog="""Copyright 2002-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. @@ -67,30 +66,23 @@ else: wnames = max(len(_) for _ in results) + 1 wresults = max(len(_) for _ in results.values()) + 1 for k in sorted(results.keys()): - args.o.write("{:{wnames}} : {:{wresults}} : {}s\n".format( - k, - results[k], - elapsed[k].total_seconds(), - wnames=wnames, - wresults=wresults)) + args.o.write("{:{wnames}} : {:{wresults}} : {}s\n".format(k, + results[k], + elapsed[k].total_seconds(), + wnames=wnames, + wresults=wresults)) args.o.write("\nSummary:\n") counts = collections.Counter(_ for _ in results.values()) total = sum(counts.values()) for k in sorted(counts.keys()): c = counts[k] - args.o.write("{:{width}}| {} ({:.2%})\n".format(k, - c, - c / total, - width=wresults)) + args.o.write("{:{width}}| {} ({:.2%})\n".format(k, c, c / total, width=wresults)) args.o.write("\nLongest:\n") - longest = sorted(list(elapsed.items()), - key=lambda kv: -kv[1].total_seconds()) + longest = sorted(list(elapsed.items()), key=lambda kv: -kv[1].total_seconds()) for i, (k, v) in enumerate(longest): - args.o.write("{:{width}}| {}s\n".format(k, - v.total_seconds(), - width=wnames)) + args.o.write("{:{width}}| {}s\n".format(k, v.total_seconds(), width=wnames)) if i > 4: break diff --git a/bin/verilator_difftree b/bin/verilator_difftree index 9bc590213..1b77e3832 100755 --- a/bin/verilator_difftree +++ b/bin/verilator_difftree @@ -47,8 +47,7 @@ def diff_dir(a, b): diff_file(a, b) anyfile = True if not anyfile: - sys.stderr.write( - "%Warning: No .tree files found that have similar base names\n") + sys.stderr.write("%Warning: No .tree files found that have similar base names\n") def diff_file(a, b): @@ -109,18 +108,14 @@ parser = argparse.ArgumentParser( Verilator_difftree is used for debugging Verilator tree output files. It performs a diff between two files, or all files common between two directories, ignoring irrelevant pointer differences.""", - epilog= - """Copyright 2005-2024 by Wilson Snyder. This program is free software; you + epilog="""Copyright 2005-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") -parser.add_argument('--debug', - action='store_const', - const=9, - help='enable debug') +parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('--no-lineno', action='store_false', help='do not show differences in line numbering') diff --git a/bin/verilator_gantt b/bin/verilator_gantt index 8f0c166e1..40450d299 100755 --- a/bin/verilator_gantt +++ b/bin/verilator_gantt @@ -15,11 +15,7 @@ LongestVcdStrValueLength = 0 Threads = collections.defaultdict(lambda: []) # List of records per thread id Mtasks = collections.defaultdict(lambda: {'elapsed': 0, 'end': 0}) Cpus = collections.defaultdict(lambda: {'mtask_time': 0}) -Global = { - 'args': {}, - 'cpuinfo': collections.defaultdict(lambda: {}), - 'stats': {} -} +Global = {'args': {}, 'cpuinfo': collections.defaultdict(lambda: {}), 'stats': {}} ElapsedTime = None # total elapsed time ExecGraphTime = 0 # total elapsed time excuting an exec graph ExecGraphIntervals = [] # list of (start, end) pairs @@ -31,8 +27,7 @@ def read_data(filename): with open(filename, "r", encoding="utf8") as fh: re_thread = re.compile(r'^VLPROFTHREAD (\d+)$') re_record = re.compile(r'^VLPROFEXEC (\S+) (\d+)(.*)$') - re_payload_mtaskBegin = re.compile( - r'id (\d+) predictStart (\d+) cpu (\d+)') + re_payload_mtaskBegin = re.compile(r'id (\d+) predictStart (\d+) cpu (\d+)') re_payload_mtaskEnd = re.compile(r'id (\d+) predictCost (\d+)') re_arg1 = re.compile(r'VLPROF arg\s+(\S+)\+([0-9.]*)\s*') @@ -57,8 +52,7 @@ def read_data(filename): tick = int(tick) payload = payload.strip() if kind == "SECTION_PUSH": - LongestVcdStrValueLength = max(LongestVcdStrValueLength, - len(payload)) + LongestVcdStrValueLength = max(LongestVcdStrValueLength, len(payload)) SectionStack.append(payload) Sections.append((tick, tuple(SectionStack))) elif kind == "SECTION_POP": @@ -66,15 +60,13 @@ def read_data(filename): SectionStack.pop() Sections.append((tick, tuple(SectionStack))) elif kind == "MTASK_BEGIN": - mtask, predict_start, ecpu = re_payload_mtaskBegin.match( - payload).groups() + mtask, predict_start, ecpu = re_payload_mtaskBegin.match(payload).groups() mtask = int(mtask) predict_start = int(predict_start) ecpu = int(ecpu) mTaskThread[mtask] = thread records = Threads[thread] - assert not records or records[-1]['start'] <= records[-1][ - 'end'] <= tick + assert not records or records[-1]['start'] <= records[-1]['end'] <= tick records.append({ 'start': tick, 'mtask': mtask, @@ -85,8 +77,7 @@ def read_data(filename): Mtasks[mtask]['thread'] = thread Mtasks[mtask]['predict_start'] = predict_start elif kind == "MTASK_END": - mtask, predict_cost = re_payload_mtaskEnd.match( - payload).groups() + mtask, predict_cost = re_payload_mtaskEnd.match(payload).groups() mtask = int(mtask) predict_cost = int(predict_cost) begin = Mtasks[mtask]['begin'] @@ -163,8 +154,7 @@ def report(): print("\nSummary:") print(" Total elapsed time = {} rdtsc ticks".format(ElapsedTime)) - print(" Parallelized code = {:.2%} of elapsed time".format( - ExecGraphTime / ElapsedTime)) + print(" Parallelized code = {:.2%} of elapsed time".format(ExecGraphTime / ElapsedTime)) print(" Total threads = %d" % nthreads) print(" Total CPUs used = %d" % ncpus) print(" Total mtasks = %d" % len(Mtasks)) @@ -176,15 +166,12 @@ def report(): if nthreads > ncpus: print() - print("%%Warning: There were fewer CPUs (%d) than threads (%d)." % - (ncpus, nthreads)) + print("%%Warning: There were fewer CPUs (%d) than threads (%d)." % (ncpus, nthreads)) print(" : See docs on use of numactl.") else: if 'cpu_socket_cores_warning' in Global: print() - print( - "%Warning: Multiple threads scheduled on same hyperthreaded core." - ) + print("%Warning: Multiple threads scheduled on same hyperthreaded core.") print(" : See docs on use of numactl.") if 'cpu_sockets_warning' in Global: print() @@ -228,8 +215,7 @@ def report_mtasks(): serialTime = ElapsedTime - ExecGraphTime def subReport(elapsed, work): - print(" Thread utilization = {:7.2%}".format(work / - (elapsed * nthreads))) + print(" Thread utilization = {:7.2%}".format(work / (elapsed * nthreads))) print(" Speedup = {:6.3}x".format(work / elapsed)) print("\nParallelized code, measured:") @@ -256,8 +242,7 @@ def report_mtasks(): if Mtasks[mtask]['elapsed'] > 0: if Mtasks[mtask]['predict_cost'] == 0: Mtasks[mtask]['predict_cost'] = 1 # don't log(0) below - p2e_ratio = math.log(Mtasks[mtask]['predict_cost'] / - Mtasks[mtask]['elapsed']) + p2e_ratio = math.log(Mtasks[mtask]['predict_cost'] / Mtasks[mtask]['elapsed']) p2e_ratios.append(p2e_ratio) if p2e_ratio > max_p2e: @@ -269,18 +254,14 @@ def report_mtasks(): print("\nMTask statistics:") print(" Longest mtask id = {}".format(long_mtask)) - print(" Longest mtask time = {:.2%} of time elapsed in parallelized code". - format(long_mtask_time / ExecGraphTime)) + print(" Longest mtask time = {:.2%} of time elapsed in parallelized code".format( + long_mtask_time / ExecGraphTime)) print(" min log(p2e) = %0.3f" % min_p2e, end="") - print(" from mtask %d (predict %d," % - (min_mtask, Mtasks[min_mtask]['predict_cost']), - end="") + print(" from mtask %d (predict %d," % (min_mtask, Mtasks[min_mtask]['predict_cost']), end="") print(" elapsed %d)" % Mtasks[min_mtask]['elapsed']) print(" max log(p2e) = %0.3f" % max_p2e, end="") - print(" from mtask %d (predict %d," % - (max_mtask, Mtasks[max_mtask]['predict_cost']), - end="") + print(" from mtask %d (predict %d," % (max_mtask, Mtasks[max_mtask]['predict_cost']), end="") print(" elapsed %d)" % Mtasks[max_mtask]['elapsed']) stddev = statistics.pstdev(p2e_ratios) @@ -315,8 +296,8 @@ def report_cpus(): model = cpuinfo['model_name'] print(" {:3d} | {:7.2%} / {:16d} | {:>6s} | {:>4s} | {}".format( - cpu, Cpus[cpu]['mtask_time'] / ElapsedTime, - Cpus[cpu]['mtask_time'], socket, core, model)) + cpu, Cpus[cpu]['mtask_time'] / ElapsedTime, Cpus[cpu]['mtask_time'], socket, core, + model)) if len(Global['cpu_sockets']) > 1: Global['cpu_sockets_warning'] = True @@ -366,8 +347,8 @@ def report_sections(): def printTree(prefix, name, entries, tree): print(" {:7.2%} | {:7.2%} | {:8} | {:10.2f} | {}".format( - treeSum(tree) / ElapsedTime, tree[0] / ElapsedTime, tree[2], - tree[2] / entries, prefix + name)) + treeSum(tree) / ElapsedTime, tree[0] / ElapsedTime, tree[2], tree[2] / entries, + prefix + name)) for k in sorted(tree[1], key=lambda _: -treeSum(tree[1][_])): printTree(prefix + " ", k, tree[2], tree[1][k]) @@ -438,10 +419,8 @@ def write_vcd(filename): addValue(code, start, mtask) addValue(code, end, None) - tStart = sorted(_['start'] for records in Threads.values() - for _ in records) - tEnd = sorted(_['end'] for records in Threads.values() - for _ in records) + tStart = sorted(_['start'] for records in Threads.values() for _ in records) + tEnd = sorted(_['end'] for records in Threads.values() for _ in records) # Predicted graph for start, end in ExecGraphIntervals: @@ -455,11 +434,10 @@ def write_vcd(filename): # Predict mtasks that fill the time the execution occupied for mtask in Mtasks: thread = Mtasks[mtask]['thread'] - pred_scaled_start = start + int( - Mtasks[mtask]['predict_start'] * measured_scaling) + pred_scaled_start = start + int(Mtasks[mtask]['predict_start'] * measured_scaling) pred_scaled_end = start + int( - (Mtasks[mtask]['predict_start'] + - Mtasks[mtask]['predict_cost']) * measured_scaling) + (Mtasks[mtask]['predict_start'] + Mtasks[mtask]['predict_cost']) * + measured_scaling) if pred_scaled_start == pred_scaled_end: continue @@ -545,8 +523,7 @@ Verilator_gantt creates a visual representation to help analyze Verilator For documentation see https://verilator.org/guide/latest/exe_verilator_gantt.html""", - epilog= - """Copyright 2018-2024 by Wilson Snyder. This program is free software; you + epilog="""Copyright 2018-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. @@ -554,12 +531,8 @@ Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_true', help='enable debug') -parser.add_argument('--no-vcd', - help='disable creating vcd', - action='store_true') -parser.add_argument('--vcd', - help='filename for vcd outpue', - default='profile_exec.vcd') +parser.add_argument('--no-vcd', help='disable creating vcd', action='store_true') +parser.add_argument('--vcd', help='filename for vcd outpue', default='profile_exec.vcd') parser.add_argument('filename', help='input profile_exec.dat filename to process', default='profile_exec.dat') diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index e5487f127..51ed57a58 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -34,9 +34,8 @@ def profcfunc(filename): # Older gprofs have no call column for single-call functions # %time cumesec selfsec {stuff} name - match = re.match( - r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$', - line) + match = re.match(r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$', + line) if match: pct = float(match.group(1)) sec = float(match.group(2)) @@ -136,19 +135,15 @@ def profcfunc(filename): design_width = 1 for func, func_item in vfuncs.items(): - if design_width < len(func_item['design']): - design_width = len(func_item['design']) + design_width = max(design_width, len(func_item['design'])) print("Verilog code profile:") print(" These are split into three categories:") print(" C++: Time in non-Verilated C++ code") print(" Prof: Time in profile overhead") - print(" VBlock: Time attributable to a block in a" + - " Verilog file and line") - print(" VCommon: Time in a Verilated module," + - " due to all parts of the design") - print(" VLib: Time in Verilated common libraries," + - " called by the Verilated code") + print(" VBlock: Time attributable to a block in a" + " Verilog file and line") + print(" VCommon: Time in a Verilated module," + " due to all parts of the design") + print(" VLib: Time in Verilated common libraries," + " called by the Verilated code") print() print(" % cumulative self ") @@ -156,13 +151,11 @@ def profcfunc(filename): "s type filename and line number") % "design") cume = 0 - for func in sorted(vfuncs.keys(), - key=lambda f: vfuncs[f]['sec'], - reverse=True): + for func in sorted(vfuncs.keys(), key=lambda f: vfuncs[f]['sec'], reverse=True): cume += vfuncs[func]['sec'] print(("%6.2f %9.2f %8.2f %10d %-" + str(design_width) + "s %s") % - (vfuncs[func]['pct'], cume, vfuncs[func]['sec'], - vfuncs[func]['calls'], vfuncs[func]['design'], func)) + (vfuncs[func]['pct'], cume, vfuncs[func]['sec'], vfuncs[func]['calls'], + vfuncs[func]['design'], func)) ###################################################################### @@ -180,18 +173,14 @@ in each Verilog block. For documentation see https://verilator.org/guide/latest/exe_verilator_profcfunc.html""", - epilog= - """Copyright 2002-2024 by Wilson Snyder. This program is free software; you + epilog="""Copyright 2002-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") -parser.add_argument('--debug', - action='store_const', - const=9, - help='enable debug') +parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('filename', help='input gprof output to process') Args = parser.parse_args() diff --git a/ci/ci-install.bash b/ci/ci-install.bash index 723dcb586..37a4feaed 100755 --- a/ci/ci-install.bash +++ b/ci/ci-install.bash @@ -60,17 +60,14 @@ if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then sudo apt-get install libgoogle-perftools-dev || sudo apt-get install libgoogle-perftools-dev fi - if [ "$CI_RUNS_ON" = "ubuntu-20.04" ] || [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then + if [ "$CI_RUNS_ON" = "ubuntu-20.04" ] || [ "$CI_RUNS_ON" = "ubuntu-22.04" ] || [ "$CI_RUNS_ON" = "ubuntu-24.04" ]; then sudo apt-get install libsystemc libsystemc-dev || sudo apt-get install libsystemc libsystemc-dev fi - if [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then + if [ "$CI_RUNS_ON" = "ubuntu-22.04" ] || [ "$CI_RUNS_ON" = "ubuntu-24.04" ]; then sudo apt-get install bear mold || sudo apt-get install bear mold fi - if [ "$COVERAGE" = 1 ]; then - yes yes | sudo cpan -fi Parallel::Forker - fi elif [ "$CI_OS_NAME" = "osx" ]; then brew update brew install ccache perl gperftools @@ -94,12 +91,12 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then # libfl-dev needed for internal coverage's test runs sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3 || sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3 - # Required for test_regress/t/t_dist_attributes.pl - if [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then + # Required for test_regress/t/t_dist_attributes.py + if [ "$CI_RUNS_ON" = "ubuntu-22.04" ] || [ "$CI_RUNS_ON" = "ubuntu-24.04" ]; then sudo apt-get install python3-clang mold || sudo apt-get install python3-clang mold fi - if [ "$CI_RUNS_ON" = "ubuntu-20.04" ] || [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then + if [ "$CI_RUNS_ON" = "ubuntu-20.04" ] || [ "$CI_RUNS_ON" = "ubuntu-22.04" ] || [ "$CI_RUNS_ON" = "ubuntu-24.04" ]; then sudo apt-get install libsystemc-dev || sudo apt-get install libsystemc-dev fi @@ -114,10 +111,6 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then fatal "Unknown os: '$CI_OS_NAME'" fi # Common installs - if [ "$CI_RUNS_ON" != "ubuntu-14.04" ]; then - CI_CPAN_REPO=https://cpan.org - fi - yes yes | sudo cpan -M $CI_CPAN_REPO -fi Parallel::Forker install-vcddiff # Workaround -fsanitize=address crash sudo sysctl -w vm.mmap_rnd_bits=28 diff --git a/ci/ci-script.bash b/ci/ci-script.bash index bee825161..4bdf9910e 100755 --- a/ci/ci-script.bash +++ b/ci/ci-script.bash @@ -33,6 +33,7 @@ elif [ "$CI_OS_NAME" = "freebsd" ]; then else fatal "Unknown os: '$CI_OS_NAME'" fi +NPROC=$(expr $NPROC '+' 1) if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then ############################################################################## @@ -61,6 +62,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then # Run tests export VERILATOR_TEST_NO_CONTRIBUTORS=1 # Separate workflow check + export VERILATOR_TEST_NO_LINT_PY=1 # Separate workflow check if [ "$CI_OS_NAME" = "osx" ]; then export VERILATOR_TEST_NO_GDB=1 # Pain to get GDB to work on OS X @@ -85,7 +87,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then fi # Run sanitize on Ubuntu 22.04 only - [ "$CI_RUNS_ON" = 'ubuntu-22.04' ] && sanitize='--sanitize' || sanitize='' + ( [ "$CI_RUNS_ON" = 'ubuntu-22.04' ] || [ "$CI_RUNS_ON" = 'ubuntu-24.04' ] ) && sanitize='--sanitize' || sanitize='' TEST_REGRESS=test_regress if [ "$CI_RELOC" == 1 ]; then @@ -193,6 +195,8 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then ;; esac + # To see load average (1 minute, 5 minute, 15 minute) + uptime # 22.04: ccache -s -v ccache -s diff --git a/ci/ci-win-compile.ps1 b/ci/ci-win-compile.ps1 index d5a469fd4..1cc694248 100644 --- a/ci/ci-win-compile.ps1 +++ b/ci/ci-win-compile.ps1 @@ -11,14 +11,14 @@ Set-PSDebug -Trace 1 if (-Not (Test-Path $PWD/../.ccache/win_bison.exe)) { - git clone --depth 1 https://github.com/lexxmark/winflexbison - cd winflexbison - mkdir build - cd build - cmake .. --install-prefix $PWD/../../../.ccache - cmake --build . --config Release -j 3 - cmake --install . --prefix $PWD/../../../.ccache - cd ../.. + git clone --depth 1 https://github.com/lexxmark/winflexbison + cd winflexbison + mkdir build + cd build + cmake .. --install-prefix $PWD/../../../.ccache + cmake --build . --config Release -j 3 + cmake --install . --prefix $PWD/../../../.ccache + cd ../.. } mkdir build diff --git a/ci/docker/buildenv/Dockerfile b/ci/docker/buildenv/Dockerfile index 88e39b85f..7e13feca8 100644 --- a/ci/docker/buildenv/Dockerfile +++ b/ci/docker/buildenv/Dockerfile @@ -51,8 +51,6 @@ RUN apt-get update \ WORKDIR /tmp -RUN cpan install -fi Parallel::Forker - RUN git clone https://github.com/veripool/vcddiff.git && \ make -C vcddiff && \ cp -p vcddiff/vcddiff /usr/local/bin/vcddiff && \ diff --git a/ci/docker/buildenv/README.rst b/ci/docker/buildenv/README.rst index 1bb317e47..2f04bb732 100644 --- a/ci/docker/buildenv/README.rst +++ b/ci/docker/buildenv/README.rst @@ -1,6 +1,8 @@ .. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +.. _Verilator Build Docker Container: + Verilator Build Docker Container ================================ diff --git a/codecov.yml b/codecov.yml index c03de64cb..bd2ee7f52 100644 --- a/codecov.yml +++ b/codecov.yml @@ -1,3 +1,4 @@ +--- # DESCRIPTION: codecov.io config # # Copyright 2020-2024 by Wilson Snyder. This program is free software; you @@ -8,31 +9,28 @@ #################### # Validate: # curl --data-binary @codecov.yml https://codecov.io/validate - +# codecov: - require_ci_to_pass: no - + require_ci_to_pass: false coverage: precision: 2 round: down - range: "50...100" + range: 50...100 ignore: - - "ci" - - "docs" - - "examples" - - "include/gtkwave" - - "include/vltstd" - - "test_regress" - + - "ci" # + - "docs" # + - "examples" # + - "include/gtkwave" # + - "include/vltstd" # + - "test_regress" # parsers: gcov: branch_detection: - conditional: yes - loop: yes - method: no - macro: no - + conditional: true + loop: true + method: false + macro: false comment: layout: "reach,diff,flags,tree" behavior: default - require_changes: yes + require_changes: true diff --git a/configure.ac b/configure.ac index 9eef95873..6d01254b4 100644 --- a/configure.ac +++ b/configure.ac @@ -10,7 +10,7 @@ # Then 'make maintainer-dist' #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) -AC_INIT([Verilator],[5.028 2024-08-21], +AC_INIT([Verilator],[5.030 2024-10-27], [https://verilator.org], [verilator],[https://verilator.org]) @@ -29,6 +29,9 @@ AC_DEFINE_UNQUOTED([PACKAGE_VERSION_STRING_CHAR], [Package version as a number]) AC_SUBST(PACKAGE_VERSION_STRING_CHAR) +###################################################################### +## Arguments/flag checking + # Ignore automake flags passed by Ubuntu builds AC_ARG_ENABLE([dependency-tracking], [AS_HELP_STRING([--disable-dependency-tracking], [ignored])]) @@ -156,6 +159,11 @@ AC_ARG_WITH([solver], AC_SUBST(CFG_WITH_SOLVER) AC_MSG_RESULT($CFG_WITH_SOLVER) +###################################################################### +## Compiler checks + +AC_MSG_RESULT([compiler CXX inbound is set to... $CXX]) + # Compiler flags (ensure they are not empty to avoid configure defaults) CFLAGS="$CFLAGS " CPPFLAGS="$CPPFLAGS " @@ -182,24 +190,26 @@ if test "x$AR" = "x" ; then AC_MSG_ERROR([Cannot find "ar" in your PATH, please install it]) fi -AC_PATH_PROG(PERL,perl) +AC_CHECK_PROG(PERL,perl,perl) if test "x$PERL" = "x" ; then AC_MSG_ERROR([Cannot find "perl" in your PATH, please install it]) fi -AC_PATH_PROG(PYTHON3,python3) +AC_CHECK_PROG(PYTHON3,python3,python3) if test "x$PYTHON3" = "x" ; then AC_MSG_ERROR([Cannot find "python3" in your PATH, please install it]) fi +python3_version=$($PYTHON3 --version | head -1) +AC_MSG_RESULT([$PYTHON3 --version = $python3_version]) -AC_PATH_PROG(LEX,flex) +AC_CHECK_PROG(LEX,flex,flex) if test "x$LEX" = "x" ; then AC_MSG_ERROR([Cannot find "flex" in your PATH, please install it]) fi flex_version=$($LEX --version | head -1) AC_MSG_RESULT([$LEX --version = $flex_version]) -AC_PATH_PROG(YACC,bison) +AC_CHECK_PROG(YACC,bison,bison) if test "x$YACC" = "x" ; then AC_MSG_ERROR([Cannot find "bison" in your PATH, please install it]) fi @@ -623,6 +633,9 @@ AC_SUBST(HAVE_SYSTEMC) # Checks for system services +###################################################################### +## Output + # Other install directories pkgdatadir=${datadir}/verilator AC_SUBST(pkgdatadir) diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index f9d18dc8a..dae6f4082 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -7,6 +7,7 @@ Adam Bagley Adrian Sampson Adrien Le Masle Ahmed El-Mahmoudy +Aidan McNay Aleksander Kiryk Alex Chadwick Alex Solomatnikov @@ -44,9 +45,12 @@ Drew Ranck Drew Taussig Driss Hafdi Edgar E. Iglesias +Eric Müller Eric Rippey Ethan Sifferman Eyck Jentzsch +Furqan Nadir +Fabian Keßler Fan Shupei february cozzocrea Felix Neumärker @@ -64,6 +68,7 @@ Graham Rushton Guokai Chen Gus Smith Gustav Svensk +Han Qi Harald Heckmann Hennadii Chernyshchyk Howard Su @@ -148,6 +153,7 @@ Mladen Slijepcevic Morten Borup Petersen Mostafa Gamal Nandu Raj +Nathan Graybeal Nathan Kohagen Nathan Myers Nolan Poe @@ -215,6 +221,7 @@ Wilson Snyder Xi Zhang Yan Xu Yangyu Chen +Yilou Wang Yinan Xu Yoda Lee Yossi Nivin diff --git a/docs/Makefile b/docs/Makefile index 70ebe1da3..78e39fae8 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -23,7 +23,7 @@ SPHINXBUILD ?= sphinx-build SOURCEDIR = guide BUILDDIR = _build -SPHINXOPTS ?= -c guide +SPHINXOPTS ?= -c guide -j 4 ifneq ($(VERILATOR_ANALYTICS_ID),) SPHINXOPTS += -D html_theme_options.analytics_id=$(VERILATOR_ANALYTICS_ID) endif diff --git a/docs/bin/vl_sphinx_extract b/docs/bin/vl_sphinx_extract index 6762d7886..75a7585bf 100755 --- a/docs/bin/vl_sphinx_extract +++ b/docs/bin/vl_sphinx_extract @@ -23,9 +23,7 @@ class VlSphinxExtract: outname = match.group(1) print("Writing %s" % outname) fhw = open(outname, "w", encoding="utf8") # pylint: disable=consider-using-with - fhw.write( - ".. comment: generated by vl_sphinx_extract from " + - filename + "\n") + fhw.write(".. comment: generated by vl_sphinx_extract from " + filename + "\n") fhw.write(".. code-block::\n") elif re.match(r'^[=a-zA-Z0-9_]', line): fhw = None @@ -39,18 +37,14 @@ parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Read a file and extract documentation data.""", - epilog= - """ Copyright 2021-2024 by Wilson Snyder. This package is free software; + epilog=""" Copyright 2021-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") -parser.add_argument('--debug', - action='store_const', - const=9, - help='enable debug') +parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('path', help='path to extract from') Args = parser.parse_args() diff --git a/docs/bin/vl_sphinx_fix b/docs/bin/vl_sphinx_fix index 51eda1c4c..d0e607a48 100755 --- a/docs/bin/vl_sphinx_fix +++ b/docs/bin/vl_sphinx_fix @@ -18,8 +18,7 @@ class VlSphinxFix: if os.path.isdir(path): for basefile in os.listdir(path): file = os.path.join(path, basefile) - if ((basefile != ".") and (basefile != "..") - and basefile not in self.SkipBasenames + if ((basefile != ".") and (basefile != "..") and basefile not in self.SkipBasenames and not os.path.islink(file)): self.process(file) elif re.search(r'\.(html|tex)$', path): @@ -54,18 +53,14 @@ parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Post-process Sphinx HTML.""", - epilog= - """ Copyright 2021-2024 by Wilson Snyder. This package is free software; + epilog=""" Copyright 2021-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") -parser.add_argument('--debug', - action='store_const', - const=9, - help='enable debug') +parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('path', help='path to edit') Args = parser.parse_args() diff --git a/docs/gen/ex_MULTIDRIVEN_msg.rst b/docs/gen/ex_MULTIDRIVEN_msg.rst index d8697a4a5..a2b090f34 100644 --- a/docs/gen/ex_MULTIDRIVEN_msg.rst +++ b/docs/gen/ex_MULTIDRIVEN_msg.rst @@ -1,6 +1,6 @@ .. comment: generated by t_lint_multidriven_bad .. code-block:: - %Warning-MULTIDRIVEN: example.v:1:22 Signal has multiple driving blocks with different clocking: 't.mem' + %Warning-MULTIDRIVEN: example.v:1:22 Signal has multiple driving blocks with different clocking: 'out2' example.v:1:7 ... Location of first driving block example.v:1:7 ... Location of other driving block diff --git a/docs/guide/conf.py b/docs/guide/conf.py index 12fd0db39..a01718c9e 100644 --- a/docs/guide/conf.py +++ b/docs/guide/conf.py @@ -23,8 +23,7 @@ def get_vlt_version(): filename = "../../Makefile" with open(filename, "r", encoding="utf8") as fh: for line in fh: - match = re.search(r"PACKAGE_VERSION *= *([a-z0-9.]+) +([-0-9]+)", - line) + match = re.search(r"PACKAGE_VERSION *= *([a-z0-9.]+) +([-0-9]+)", line) if match: return match.group(1), match.group(2) match = re.search(r"PACKAGE_VERSION *= *([a-z0-9.]+) +devel", line) @@ -75,8 +74,7 @@ extensions = [] # directories to ignore when looking for source files. # This pattern also affects html_static_path and html_extra_path. exclude_patterns = [ - '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst', 'gen/ex_*', - 'CONTRIBUTING.rst' + '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst', 'gen/ex_*', 'CONTRIBUTING.rst' ] # Warn about refs diff --git a/docs/guide/contributing.rst b/docs/guide/contributing.rst index d8f6dc35e..056a3e375 100644 --- a/docs/guide/contributing.rst +++ b/docs/guide/contributing.rst @@ -23,24 +23,24 @@ Next, try the :vlopt:`--debug` option. This will enable additional internal assertions, and may help identify the problem. Finally, reduce your code to the smallest possible routine that exhibits -the bug. Even better, create a test in the :file:`test_regress/t` -directory, as follows: +the bug (see: :ref:`Minimizing bug-inducing code`). Even better, create +a test in the :file:`test_regress/t` directory, as follows: .. code-block:: bash cd test_regress - cp -p t/t_EXAMPLE.pl t/t_BUG.pl + cp -p t/t_EXAMPLE.py t/t_BUG.py cp -p t/t_EXAMPLE.v t/t_BUG.v There are many hints on how to write a good test in the -:file:`test_regress/driver.pl` documentation which can be seen by running: +:file:`test_regress/driver.py` documentation which can be seen by running: .. code-block:: bash cd $VERILATOR_ROOT # Need the original distribution kit - test_regress/driver.pl --help + test_regress/driver.py --help -Edit :file:`t/t_BUG.pl` to suit your example; you can do anything you want +Edit :file:`t/t_BUG.py` to suit your example; you can do anything you want in the Verilog code there; just make sure it retains the single clk input and no outputs. Now, the following should fail: @@ -48,20 +48,38 @@ and no outputs. Now, the following should fail: cd $VERILATOR_ROOT # Need the original distribution kit cd test_regress - t/t_BUG.pl # Run on Verilator - t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator - t/t_BUG.pl --vcs # Run on VCS simulator - t/t_BUG.pl --nc|--iv|--ghdl # Likewise on other simulators + t/t_BUG.py # Run on Verilator + t/t_BUG.py --debug # Run on Verilator, passing --debug to Verilator + t/t_BUG.py --vcs # Run on VCS simulator + t/t_BUG.py --nc|--iv|--ghdl # Likewise on other simulators The test driver accepts a number of options, many of which mirror the main Verilator options. For example the previous test could have been run with debugging enabled. The full set of test options can be seen by running -:command:`driver.pl --help` as shown above. +:command:`driver.py --help` as shown above. Finally, report the bug at `Verilator Issues `_. The bug will become publicly visible; if this is unacceptable, mail the bug report to ``wsnyder@wsnyder.org``. +.. _Minimizing bug-inducing code: + +Minimizing bug-inducing code +============================ + +In some cases, the part of the code that causes the bug is clearly visible +and the design can be easily manually reduced. In other cases, the bug is +caused by a complex interaction of many parts of the design, and it is not +clear which parts are necessary to reproduce the bug. In these cases, an +Open Source tool called `sv-bugpoint +_` can be used to automatically +reduce a SystemVerilog design to the smallest possible reproducer. +It can be used to automatically reduce a design with hundreds of thousands of +lines to a minimal test case while preserving the bug-inducing behavior. + +Please refer to the `README +`_ file for more +information on how to use `sv-bugpoint`. .. Contributing .. ============ diff --git a/docs/guide/deprecations.rst b/docs/guide/deprecations.rst index 214ea02f4..881583518 100644 --- a/docs/guide/deprecations.rst +++ b/docs/guide/deprecations.rst @@ -12,7 +12,7 @@ C++14 compiler support Verilated models with --no-timing. Verilator will require C++20 or newer compilers for both compiling - Verilator and compiling all Verilated models no sooner than January 2025. + Verilator and compiling all Verilated models no sooner than May 2025. XML output Verilator currently supports XML parser output (enabled with `--xml-only`). diff --git a/docs/guide/example_sc.rst b/docs/guide/example_sc.rst index 441c8e542..f844f4a25 100644 --- a/docs/guide/example_sc.rst +++ b/docs/guide/example_sc.rst @@ -28,6 +28,7 @@ Now, let's create an example Verilog, and SystemC wrapper file: cat >sc_main.cpp <<'EOF' #include "Vour.h" + using namespace sc_core; int sc_main(int argc, char** argv) { Verilated::commandArgs(argc, argv); sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true}; diff --git a/docs/guide/exe_sim.rst b/docs/guide/exe_sim.rst index b0867ae9f..7a449e3fb 100644 --- a/docs/guide/exe_sim.rst +++ b/docs/guide/exe_sim.rst @@ -40,8 +40,8 @@ Summary: .. option:: +verilator+error+limit+ Set number of non-fatal errors (e.g. assertion failures) before exiting - simulation runtime. Also affects number of $stop calls needed before - exit. Defaults to 1. + simulation runtime. Also affects number of `$stop` calls needed before + exit. Does not affect `$fatal`. Defaults to 1. .. option:: +verilator+help diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index fe70225cd..0ffe5afb3 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -958,6 +958,22 @@ Summary: delayed assignments. This option should only be used when suggested by the developers. +.. option:: --output-groups + + Enables concatenating the output .cpp files into the given number of + effective output .cpp files. This is useful if the compiler startup + overhead from compiling many small files becomes unacceptable, + which can happen in designs making extensive use of SystemVerilog classes, + templates or generate blocks. + + Using :vlopt:`--output-groups` can adversely impact caching and stability + (as in reproducibility) of compiled code. Compilation of larger .cpp + files also has higher memory requirements. Too low values might result in + swap thrashing with large designs, high values give no benefits. The + value should range from 2 to 20 for small to medium designs. + + Default is zero, which disables this feature. + .. option:: --output-split Enables splitting the output .cpp files into multiple outputs. When a @@ -1909,8 +1925,12 @@ Configuration Files In addition to the command line, warnings and other features for the :command:`verilator` command may be controlled with configuration files, -typically named with the .vlt extension (what makes it a configuration file -is the :option:`\`verilator_config` directive). An example: +typically named with the `.vlt` extension (what makes it a configuration +file is the :option:`\`verilator_config` directive). These files, when +named `.vlt`, are read before source code files; if this behavior is +undesired, name the config file with a `.v` suffix. + +An example: .. code-block:: sv diff --git a/docs/guide/exe_verilator_coverage.rst b/docs/guide/exe_verilator_coverage.rst index 37dbc977a..ddfd8aa93 100644 --- a/docs/guide/exe_verilator_coverage.rst +++ b/docs/guide/exe_verilator_coverage.rst @@ -58,32 +58,36 @@ to read multiple inputs. If no data file is specified, by default, Specifies the directory name to which source files with annotated coverage data should be written. -Converting from the Verilator coverage data format to the info format is -lossy; the info will have all forms of coverage merged line coverage, and -if there are multiple coverage points on a single line they will merge. -The minimum coverage across all merged points will be used to report -coverage of the line. +Points are children of each line coverage- branches or toggle points. +When point counts are aggregated into a line, the minimum and maximum counts +are used to determine the status of the line (complete, partial, failing) +The count is equal to the maximum of the points. Coverage data is annotated at the beginning of the line and is formatted as a special character followed by the number of coverage hits. The special -characters " ,%,+,-" indicate summary of the coverage, and allow use of grep +characters " ,%,~,+,-" indicate summary of the coverage, and allow use of grep to filter the report. -* " " (whitespace) indicates that all points on the line are above the coverage limit. -* "%" indicates at least one point on the line was below the coverage limit. -* "+" coverage point was at or above the limit. Only used with :option:`--annotate-points`. -* "-" coverage point was below the limit. Only used with :option:`--annotate-points`. +* " " (whitespace) indicates that all points on the line are above the coverage min. +* "%" indicates that all points on the line are below the coverage min. +* "~" indicates that some points on the line are above the coverage min and some are below. +* "+" coverage point was at or above the min. Only used with :option:`--annotate-points`. +* "-" coverage point was below the min. Only used with :option:`--annotate-points`. .. code-block:: - 100000 input logic a; // Begins with whitespace, because - // number of hits (100000) is above the limit. - +100000 point: comment=a // Begins with +, because - // number of hits (100000) is above the limit. - %000000 input logic b; // Begins with %, because - // number of hits (0) is below the limit. - -000000 point: comment=b // Begins with -, because - // number of hits (0) is below the limit. + 100000 input logic a; // Begins with whitespace, because + // number of hits (100000) is above the min. + +100000 point: comment=a // Begins with +, because + // number of hits (100000) is above the min. + %000000 input logic b; // Begins with %, because + // number of hits (0) is below the min. + -000000 point: comment=b // Begins with -, because + // number of hits (0) is below the min. + ~000010 if (cyc!=0) begin // Begins with ~, because + // branches are below and above the min. + +000010 point: comment=if // The if branch is above the min. + -000000 point: comment=else // The else branch is below the min. .. option:: --annotate-all @@ -154,10 +158,7 @@ generated from random test runs) into one master coverage file. Specifies the aggregate coverage results, summed across all the files, should be written to the given filename in :command:`lcov` .info format. This may be used to feed into :command:`lcov` to aggregate or generate -reports. - -Converting from the Verilator coverage data format to the info format is -lossy; the info will have all forms of coverage merged line coverage, and -if there are multiple coverage points on a single line they will merge. -The minimum coverage across all merged points will be used to report -coverage of the line. +reports. This format lacks the comments for cover points that the +verilator_coverage format has. It can be used with :command:`genhtml` +to generate an HTML report. :command:`genhtml --branch-coverage` will +also display the branch coverage, analogous to :option:`--annotate-points` diff --git a/docs/guide/install.rst b/docs/guide/install.rst index ecc06bc48..05a58d244 100644 --- a/docs/guide/install.rst +++ b/docs/guide/install.rst @@ -19,13 +19,33 @@ started. (Note packages are unlikely to have the most recent version, so :ref:`Git Install` might be a better alternative.) To install as a package: -:: +.. code-block:: shell apt-get install verilator # On Ubuntu For other distributions, refer to `Repology Verilator Distro Packages `__. +.. _pre-commit Quick Install: + +pre-commit Quick Install +============================= + +You can use Verilator's `pre-commit `__ hook to +lint your code before committing it. It encapsulates the :ref:`Verilator +Build Docker Container`, so you need docker on your system to use it. The +verilator image will be downloaded automatically. + +To use the hook, add the following entry to your :code:`.pre-commit-config.yaml`: + +.. code-block:: yaml + + repos: + - repo: https://github.com/verilator/verilator + rev: v5.026 # or later + hooks: + - id: verilator + .. _Git Install: Git Quick Install @@ -36,7 +56,7 @@ options and details, see :ref:`Detailed Build Instructions` below. In brief, to install from git: -:: +.. code-block:: shell # Prerequisites: #sudo apt-get install git help2man perl python3 make autoconf g++ flex bison ccache @@ -89,7 +109,7 @@ Install Prerequisites To build or run Verilator, you need these standard packages: -:: +.. code-block:: shell sudo apt-get install git help2man perl python3 make sudo apt-get install g++ # Alternatively, clang @@ -101,7 +121,7 @@ To build or run Verilator, you need these standard packages: To build or run Verilator, the following are optional but should be installed for good performance: -:: +.. code-block:: shell sudo apt-get install ccache # If present at build, needed for run sudo apt-get install mold # If present at build, needed for run @@ -110,27 +130,26 @@ for good performance: The following is optional but is recommended for nicely rendered command line help when running Verilator: -:: +.. code-block:: shell sudo apt-get install perl-doc To build Verilator you will need to install these packages; these do not need to be present to run Verilator: -:: +.. code-block:: shell sudo apt-get install git autoconf flex bison Those developing Verilator itself may also want these (see internals.rst): -:: +.. code-block:: shell sudo apt-get install clang clang-format-14 cmake gdb gprof graphviz lcov sudo apt-get install python3-clang yapf3 bear jq sudo pip3 install sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe ruff sudo pip3 install git+https://github.com/antmicro/astsee.git cpan install Pod::Perldoc - cpan install Parallel::Forker Install SystemC @@ -171,14 +190,14 @@ Obtain Sources Get the sources from the git repository: (You need to do this only once, ever.) -:: +.. code-block:: shell git clone https://github.com/verilator/verilator # Only first time ## Note the URL above is not a page you can see with a browser; it's for git only Enter the checkout and determine what version/branch to use: -:: +.. code-block:: shell cd verilator git pull # Make sure we're up-to-date @@ -193,7 +212,7 @@ Auto Configure Create the configuration script: -:: +.. code-block:: shell autoconf # Create ./configure script @@ -219,7 +238,7 @@ directory (don't run ``make install``). This allows the easiest experimentation and upgrading, and allows many versions of Verilator to co-exist on a system. -:: +.. code-block:: shell export VERILATOR_ROOT=`pwd` # if your shell is bash setenv VERILATOR_ROOT `pwd` # if your shell is csh @@ -241,7 +260,7 @@ that may support multiple versions of every tool. Tell configure the eventual destination directory name. We recommend that the destination location include the Verilator version name: -:: +.. code-block:: shell unset VERILATOR_ROOT # if your shell is bash unsetenv VERILATOR_ROOT # if your shell is csh @@ -253,7 +272,7 @@ the ``bin`` directory to your ``PATH``. Or, if you use `modulecmd `__, you'll want a module file like the following: -:: +.. code-block:: shell set install_root /CAD_DISK/verilator/{version-number-used-above} unsetenv VERILATOR_ROOT @@ -268,7 +287,7 @@ following: The final option is to eventually install Verilator globally, using configure's default system paths: -:: +.. code-block:: shell unset VERILATOR_ROOT # if your shell is bash unsetenv VERILATOR_ROOT # if your shell is csh @@ -285,7 +304,7 @@ The command to configure the package was described in the previous step. Developers should configure to have more complete developer tests. Additional packages may be required for these tests. -:: +.. code-block:: shell export VERILATOR_AUTHOR_SITE=1 # Put in your .bashrc ./configure --enable-longtests ...above options... @@ -296,7 +315,7 @@ Compile Compile Verilator: -:: +.. code-block:: shell make -j `nproc` # Or if error on `nproc`, the number of CPUs in system @@ -306,7 +325,7 @@ Test Check the compilation by running self-tests: -:: +.. code-block:: shell make test @@ -318,7 +337,7 @@ If you used any install option other than the `1. Run-in-Place from VERILATOR_ROOT <#_1_run_in_place_from_verilator_root>`__ scheme, install the files: -:: +.. code-block:: shell make install diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst index bb2f6e002..f62bada5c 100644 --- a/docs/guide/simulating.rst +++ b/docs/guide/simulating.rst @@ -18,7 +18,9 @@ Simulation Summary Report ========================= When simulation finishes, it will print a report to stdout summarizing the -simulation. This requires the model being Verilated with :vlopt:`--main`. +simulation. This requires the model being Verilated with :vlopt:`--main`, +or the user's `main()` calling `VerilatedContext->statsPrintSummary()`. + The report may be disabled with :vlopt:`+verilator+quiet`. For example: diff --git a/docs/internals.rst b/docs/internals.rst index 89502b1d9..0bea6adc7 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -1472,9 +1472,6 @@ For all tests to pass, you must install the following packages: - SystemC to compile the SystemC outputs, see http://systemc.org -- Parallel::Forker from CPAN to run tests in parallel; you can install - this with e.g. "sudo cpan install Parallel::Forker". - - vcddiff to find differences in VCD outputs. See the readme at https://github.com/veripool/vcddiff @@ -1484,7 +1481,7 @@ For all tests to pass, you must install the following packages: Controlling the Test Driver --------------------------- -The test driver script `driver.pl` runs tests; see the `Test Driver` +The test driver script `driver.py` runs tests; see the `Test Driver` section. The individual test drivers are written in Perl; see `Test Language`. @@ -1497,7 +1494,7 @@ A specific regression test can be executed manually. To start the :: - test_regress/t/t_EXAMPLE.pl + test_regress/t/t_EXAMPLE.py Regression Testing for Developers @@ -1517,13 +1514,6 @@ Developers will also want to call ./configure with two extra flags: disabled by default, as SystemC installation problems would otherwise falsely indicate a Verilator problem. -When enabling the long tests, some additional Perl modules are needed, -which you can install using cpan. - -:: - - cpan install Parallel::Forker - There are some traps to avoid when running regression tests - When checking the MANIFEST, the test will fail on unexpected code in the @@ -1871,7 +1861,7 @@ represent the pointers (``op1p``, ``op2p``, etc) between the nodes. Debugging with GDB ------------------ -The `driver.pl` script accepts ``--debug --gdb`` to start +The `driver.py` script accepts ``--debug --gdb`` to start Verilator under gdb and break when an error is hit, or the program is about to exit. You can also use ``--debug --gdbbt`` to just backtrace and then exit gdb. To debug the Verilated executable, use ``--gdbsim``. @@ -1882,7 +1872,7 @@ can use ``--debug`` and look at the underlying invocation of :: - t/t_alw_dly.pl --debug + t/t_alw_dly.py --debug shows it invokes the command: @@ -1979,7 +1969,7 @@ Generally, what would you do to add a new feature? Follow the convention described above about the AstNode type hierarchy. Ordering of definitions is enforced by ``astgen``. -5. Now you can run ``test_regress/t/t_.pl --debug`` and it'll +5. Now you can run ``test_regress/t/t_.py --debug`` and it'll probably fail, but you'll see a ``test_regress/obj_dir/t_/*.tree`` file which you can examine to see if the parsing worked. See also the sections above on debugging. @@ -2028,7 +2018,7 @@ IEEE 1800-2023 33 Config Test Driver =========== -This section documents the test driver script, `driver.pl`. driver.pl +This section documents the test driver script, `driver.py`. driver.py invokes Verilator or another simulator on each test file. For test file contents description see `Test Language`. @@ -2040,7 +2030,7 @@ the regression tests with OBJCACHE enabled and in parallel on a machine with many cores. See the -j option and OBJCACHE environment variable. -driver.pl Non-Scenario Arguments +driver.py Non-Scenario Arguments -------------------------------- --benchmark [] @@ -2110,13 +2100,13 @@ driver.pl Non-Scenario Arguments memory leaks. --site - Run site specific tests also. + Run site-specific tests also. --stop Stop on the first error. --trace - Set the simulator specific flags to request waveform tracing. + Set the simulator-specific flags to request waveform tracing. --valgrind Same as ``verilator --valgrind``: Run Verilator under `Valgrind `_. @@ -2129,7 +2119,7 @@ driver.pl Non-Scenario Arguments For tests using the standard C++ wrapper, enable runtime debug mode. -driver.pl Scenario Arguments +driver.py Scenario Arguments ---------------------------- The following options control which simulator is used, and which tests are @@ -2171,7 +2161,7 @@ simultaneously. Run Xilinx XSim simulator tests. -driver.pl Environment +driver.py Environment --------------------- HARNESS_UPDATE_GOLDEN @@ -2231,30 +2221,30 @@ VERILATOR_XVLOG Test Language ============= -This section describes the format of the ``test_regress/t/*.pl`` test -language files, executed by `driver.pl`. +This section describes the format of the ``test_regress/t/*.py`` test +language files, executed by `driver.py`. Test Language Summary --------------------- For convenience, a summary of the most commonly used features is provided here, with a reference in a later section. All test files typically have a -call to the ``lint`` or ``compile`` subroutine to compile the test. For -run-time tests, this is followed by a call to the ``execute`` -subroutine. Both of these functions can optionally be provided with -arguments specifying additional options. +call to the ``test.lint`` or ``test.compile`` methods to compile the +test. For run-time tests, this is followed by a call to the +``test.execute`` method. Both of these functions can optionally be provided +with arguments specifying additional options. -If those complete, the script calls ``ok`` to increment the count of -successful tests and then returns 1 as its result. +If those complete, the script calls ``test.passes`` to increment the count +of successful tests. -The driver.pl script assumes by default that the source Verilog file name +The driver.py script assumes by default that the source Verilog file name matches the test script name. So a test whose driver is -``t/t_mytest.pl`` will expect a Verilog source file ``t/t_mytest.v``. +``t/t_mytest.py`` will expect a Verilog source file ``t/t_mytest.v``. This can be changed using the ``top_filename`` subroutine, for example :: - top_filename("t/t_myothertest.v"); + test.top_filename = "t/t_myothertest.v" By default, all tests will run with major simulators (Icarus Verilog, NC, VCS, ModelSim, etc.) as well as Verilator, to allow results to be @@ -2263,26 +2253,25 @@ can use the following: :: - scenarios(vlt => 1); + test.scenarios('vlt') -Of the many options that can be set through arguments to ``compiler`` and -``execute``, the following are particularly useful: +Of the many options that can be set through arguments to ``test.compiler`` +and ``test.execute``, the following are particularly useful: ``verilator_flags2`` A list of flags to be passed to verilator when compiling. ``fails`` - Set to 1 to indicate that the compilation or execution is intended to fail. + Set true to indicate that the compilation or execution is intended to fail. For example, the following would specify that compilation requires two defines and is expected to fail. :: - compile( + test.compile( verilator_flags2 => ["-DSMALL_CLOCK -DGATED_COMMENT"], - fails => 1, - ); + fails = True) Hints On Writing Tests ---------------------- @@ -2295,10 +2284,10 @@ same name as the test, but with .cpp as suffix :: - compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); + test.compile( + make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.t_dir + "/" + test.name + ".cpp"]) Tests should be self-checking, rather than producing lots of output. If a test succeeds it should print ``*-* All Finished *-*`` to standard output @@ -2338,9 +2327,8 @@ compile time, it is the only option. For example: :: compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); + fails=True, + expect_filename=test.golden_filename) Note ``expect_filename`` strips some debugging information from the logfile when comparing. @@ -2349,9 +2337,9 @@ when comparing. Test Language Compile/Lint/Run Arguments ---------------------------------------- -This section describes common arguments to ``compile()``, ``lint()``, and -``run()``. The full list of arguments can be found by looking at the -``driver.pl`` source code. +This section describes common arguments to ``test.compile``, ``test.lint``, +and ``test.run``. The full list of arguments can be found by looking at +the ``driver.py`` source code. all_run_flags A list of flags to be passed when running the simulator (Verilated model @@ -2362,11 +2350,6 @@ check_finished string ``*-* All Finished *-*`` being printed on standard output. This is the normal way for successful tests to finish. -expect - A quoted list of strings or regular expression to be matched in the - output. See `Hints On Writing Tests` for more detail on how this argument - should be used. - fails True to indicate this step is expected to fail. Tests that are expected to fail generally have _bad in their filename. diff --git a/docs/spelling.txt b/docs/spelling.txt index a8c52fd37..76b0bec90 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -20,6 +20,7 @@ Ashutosh Ast Atmel Aurelien +Badáň Bagri Balboni Baltazar @@ -74,6 +75,7 @@ Deepa Defparams Delm Denio +Deniz Deprecations Deroo Desai @@ -109,8 +111,10 @@ Eugen Fabrizio Faucher Faure +Feinberg Fekete Ferrandi +Filip Flachs Flavien Florian @@ -149,6 +153,7 @@ Grulfen Gu Gunter Guo +Güzel Hameed Hao Haojin @@ -243,6 +248,7 @@ Liwei Lockhart Longo Luca +Luiza Lussier Lübeck MMD @@ -273,6 +279,8 @@ MinW Mindspeed MingW Miodrag +Moberg +Mobert ModelSim Modport Moinak @@ -354,6 +362,7 @@ Sasselli Scharrer Seitz Shahid +Shahrestani Shankar Shanshan Sharad @@ -364,6 +373,7 @@ Shi Shinkarovsky Shinya Shirakawa +Shou Shuba Shunyao Slager @@ -375,6 +385,7 @@ Solaris Solomatnikov Solt Southwell +Spack Srini Srinivasan Stamness @@ -516,6 +527,7 @@ basename bbox benchmarking biguint +bindir biops bisonpre bitOpTree @@ -585,6 +597,7 @@ datadir datafiles david ddd +de deassign debugi defenv @@ -865,6 +878,7 @@ phelter picoChip pinIndex pinout +pkgdatadir plusargs pmos poping @@ -929,6 +943,7 @@ redeclaring regs reloop replaceShiftOp +reproducibility resetall respecified rodata @@ -1018,6 +1033,8 @@ traceEverOn tran treei tri +triand +trior tristate tristates trunc @@ -1093,6 +1110,7 @@ warmup waveforms whitespace widthed +wor wreal writeb writeme @@ -1112,4 +1130,3 @@ zdave Øyvind Алексеевич Исаак - diff --git a/examples/cmake_hello_c/CMakeLists.txt b/examples/cmake_hello_c/CMakeLists.txt index 0bd119277..338cacc85 100644 --- a/examples/cmake_hello_c/CMakeLists.txt +++ b/examples/cmake_hello_c/CMakeLists.txt @@ -24,8 +24,11 @@ cmake_policy(SET CMP0074 NEW) project(cmake_hello_c) find_package(verilator HINTS $ENV{VERILATOR_ROOT} ${VERILATOR_ROOT}) -if (NOT verilator_FOUND) - message(FATAL_ERROR "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable") +if(NOT verilator_FOUND) + message( + FATAL_ERROR + "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable" + ) endif() # Create a new executable target that will contain all your sources @@ -35,4 +38,5 @@ target_compile_features(example PUBLIC cxx_std_14) # Add the Verilated circuit to the target verilate(example INCLUDE_DIRS "../make_hello_c" - SOURCES ../make_hello_c/top.v) + SOURCES ../make_hello_c/top.v +) diff --git a/examples/cmake_hello_sc/CMakeLists.txt b/examples/cmake_hello_sc/CMakeLists.txt index 647e7cf07..58d434439 100644 --- a/examples/cmake_hello_sc/CMakeLists.txt +++ b/examples/cmake_hello_sc/CMakeLists.txt @@ -24,8 +24,11 @@ cmake_policy(SET CMP0074 NEW) project(cmake_hello_sc CXX) find_package(verilator HINTS $ENV{VERILATOR_ROOT} ${VERILATOR_ROOT}) -if (NOT verilator_FOUND) - message(FATAL_ERROR "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable") +if(NOT verilator_FOUND) + message( + FATAL_ERROR + "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable" + ) endif() # SystemC dependencies @@ -39,14 +42,12 @@ find_package(SystemCLanguage QUIET) add_executable(example ../make_hello_sc/sc_main.cpp) target_compile_features(example PUBLIC cxx_std_14) -set_property( - TARGET example - PROPERTY CXX_STANDARD ${SystemC_CXX_STANDARD} - ) +set_property(TARGET example PROPERTY CXX_STANDARD ${SystemC_CXX_STANDARD}) # Add the Verilated circuit to the target verilate(example SYSTEMC INCLUDE_DIRS "../make_hello_sc" - SOURCES ../make_hello_sc/top.v) + SOURCES ../make_hello_sc/top.v +) verilator_link_systemc(example) diff --git a/examples/cmake_protect_lib/CMakeLists.txt b/examples/cmake_protect_lib/CMakeLists.txt index eb581a3c8..ec07f0716 100644 --- a/examples/cmake_protect_lib/CMakeLists.txt +++ b/examples/cmake_protect_lib/CMakeLists.txt @@ -24,8 +24,11 @@ cmake_policy(SET CMP0074 NEW) project(cmake_protect_lib) find_package(verilator HINTS $ENV{VERILATOR_ROOT} ${VERILATOR_ROOT}) -if (NOT verilator_FOUND) - message(FATAL_ERROR "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable") +if(NOT verilator_FOUND) + message( + FATAL_ERROR + "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable" + ) endif() # Create the main executable target @@ -55,9 +58,11 @@ verilate(verilated_secret VERILATOR_ARGS --protect-lib verilated_secret --protect-key ${PROTECT_KEY} DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/verilated_secret - SOURCES ../make_protect_lib/secret_impl.v) + SOURCES ../make_protect_lib/secret_impl.v +) # Include location of verilated_secret.sv wrapper verilate(example VERILATOR_ARGS "-I${CMAKE_CURRENT_BINARY_DIR}/verilated_secret" - SOURCES ../make_protect_lib/top.v) + SOURCES ../make_protect_lib/top.v +) diff --git a/examples/cmake_tracing_c/CMakeLists.txt b/examples/cmake_tracing_c/CMakeLists.txt index 6d605b93b..312c8d2b9 100644 --- a/examples/cmake_tracing_c/CMakeLists.txt +++ b/examples/cmake_tracing_c/CMakeLists.txt @@ -24,8 +24,11 @@ cmake_policy(SET CMP0074 NEW) project(cmake_tracing_c) find_package(verilator HINTS $ENV{VERILATOR_ROOT} ${VERILATOR_ROOT}) -if (NOT verilator_FOUND) - message(FATAL_ERROR "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable") +if(NOT verilator_FOUND) + message( + FATAL_ERROR + "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable" + ) endif() # Create a new executable target that will contain all your sources @@ -36,4 +39,5 @@ target_compile_features(example PUBLIC cxx_std_14) verilate(example COVERAGE TRACE INCLUDE_DIRS "../make_tracing_c" VERILATOR_ARGS -f ../make_tracing_c/input.vc -x-assign fast - SOURCES ../make_tracing_c/top.v) + SOURCES ../make_tracing_c/top.v +) diff --git a/examples/cmake_tracing_sc/CMakeLists.txt b/examples/cmake_tracing_sc/CMakeLists.txt index 4ad12f861..1ce7870d2 100644 --- a/examples/cmake_tracing_sc/CMakeLists.txt +++ b/examples/cmake_tracing_sc/CMakeLists.txt @@ -25,8 +25,11 @@ cmake_policy(SET CMP0074 NEW) project(cmake_tracing_sc_example CXX) find_package(verilator HINTS $ENV{VERILATOR_ROOT} ${VERILATOR_ROOT}) -if (NOT verilator_FOUND) - message(FATAL_ERROR "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable") +if(NOT verilator_FOUND) + message( + FATAL_ERROR + "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable" + ) endif() # SystemC dependencies @@ -40,15 +43,13 @@ find_package(SystemCLanguage QUIET) add_executable(example ../make_tracing_sc/sc_main.cpp) target_compile_features(example PUBLIC cxx_std_14) -set_property( - TARGET example - PROPERTY CXX_STANDARD ${SystemC_CXX_STANDARD} - ) +set_property(TARGET example PROPERTY CXX_STANDARD ${SystemC_CXX_STANDARD}) # Add the Verilated circuit to the target verilate(example SYSTEMC COVERAGE TRACE INCLUDE_DIRS "../make_tracing_sc" VERILATOR_ARGS -f ../make_tracing_sc/input.vc -x-assign fast - SOURCES ../make_tracing_sc/top.v) + SOURCES ../make_tracing_sc/top.v +) verilator_link_systemc(example) diff --git a/examples/json_py/sub.v b/examples/json_py/sub.v index 67b577285..3396d47b5 100644 --- a/examples/json_py/sub.v +++ b/examples/json_py/sub.v @@ -13,6 +13,6 @@ module sub ); // Some simple logic - always_comb out = ~ in; + always_comb out = ~in; endmodule diff --git a/examples/json_py/vl_file_copy b/examples/json_py/vl_file_copy index 6425ffb33..96b138fa1 100755 --- a/examples/json_py/vl_file_copy +++ b/examples/json_py/vl_file_copy @@ -25,8 +25,7 @@ class VlFileCopy: self.debug = debug - with NamedTemporaryFile() as tree_temp, NamedTemporaryFile( - ) as meta_temp: + with NamedTemporaryFile() as tree_temp, NamedTemporaryFile() as meta_temp: vargs = [ '--json-only-output', tree_temp.name, @@ -61,8 +60,7 @@ class VlFileCopy: print("\t%s " % command) status = subprocess.call(command, shell=True) if status != 0: - raise RuntimeError("Command failed running Verilator with '" + - command + "', stopped") + raise RuntimeError("Command failed running Verilator with '" + command + "', stopped") ####################################################################### @@ -71,8 +69,7 @@ if __name__ == '__main__': parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawTextHelpFormatter, - description= - """Example of using Verilator JSON output to copy a list of files to an + description="""Example of using Verilator JSON output to copy a list of files to an output directory (-odir, defaults to 'copied'), e.g. to easily create a tarball of the design to pass to others. @@ -95,11 +92,7 @@ This file ONLY is placed under the Creative Commons Public Domain, for any use, without warranty, 2019 by Wilson Snyder. SPDX-License-Identifier: CC0-1.0 """) - parser.add_argument('-debug', - '--debug', - action='store_const', - const=9, - help='enable debug') + parser.add_argument('-debug', '--debug', action='store_const', const=9, help='enable debug') parser.add_argument('-odir', '--odir', action='store', @@ -108,9 +101,7 @@ SPDX-License-Identifier: CC0-1.0 help='target output directory') (args, rem) = parser.parse_known_args() - print( - "NOTE: vl_file_copy is only an example starting point for writing your own tool." - ) + print("NOTE: vl_file_copy is only an example starting point for writing your own tool.") # That is: # 1. We will accept basic patches # 2. We are not expecting to make this globally useful. (e.g. we don't cleanup obj_dir) diff --git a/examples/json_py/vl_hier_graph b/examples/json_py/vl_hier_graph index fd6bfc2e1..6070768b3 100755 --- a/examples/json_py/vl_hier_graph +++ b/examples/json_py/vl_hier_graph @@ -24,8 +24,7 @@ class VlHierGraph: self.next_vertex_number = 0 self.addr_to_number = {} - with NamedTemporaryFile() as tree_temp, NamedTemporaryFile( - ) as meta_temp: + with NamedTemporaryFile() as tree_temp, NamedTemporaryFile() as meta_temp: vargs = [ '--json-only-output', tree_temp.name, @@ -45,9 +44,7 @@ class VlHierGraph: fh.write("digraph {\n") fh.write(" dpi=300;\n") fh.write(" order=LR;\n") - fh.write( - " node [fontsize=8 shape=\"box\" margin=0.01 width=0 height=0]" - ) + fh.write(" node [fontsize=8 shape=\"box\" margin=0.01 width=0 height=0]") fh.write(" edge [fontsize=6]") # Find cells modules = self.flatten(self.tree, lambda n: n['type'] == "MODULE") @@ -101,8 +98,7 @@ class VlHierGraph: print("\t%s " % command) status = subprocess.call(command, shell=True) if status != 0: - raise RuntimeError("Command failed running Verilator with '" + - command + "', stopped") + raise RuntimeError("Command failed running Verilator with '" + command + "', stopped") ####################################################################### @@ -111,8 +107,7 @@ if __name__ == '__main__': parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawTextHelpFormatter, - description= - """Example of using Verilator JSON output to create a .dot file showing the + description="""Example of using Verilator JSON output to create a .dot file showing the design module hierarchy. Example usage: @@ -134,11 +129,7 @@ This file ONLY is placed under the Creative Commons Public Domain, for any use, without warranty, 2019 by Wilson Snyder. SPDX-License-Identifier: CC0-1.0 """) - parser.add_argument('-debug', - '--debug', - action='store_const', - const=9, - help='enable debug') + parser.add_argument('-debug', '--debug', action='store_const', const=9, help='enable debug') parser.add_argument('-o', '--o', action='store', @@ -147,18 +138,14 @@ SPDX-License-Identifier: CC0-1.0 help='output filename') (args, rem) = parser.parse_known_args() - print( - "NOTE: vl_hier_graph is only an example starting point for writing your own tool." - ) + print("NOTE: vl_hier_graph is only an example starting point for writing your own tool.") # That is: # 1. We will accept basic patches # 2. We are not expecting to make this globally useful. (e.g. we don't cleanup obj_dir) # 3. "make install" will not install this. # 4. This has not had production-worthy validation. - fc = VlHierGraph(output_filename=args.o, - debug=args.debug, - verilator_args=rem) + fc = VlHierGraph(output_filename=args.o, debug=args.debug, verilator_args=rem) ###################################################################### # Local Variables: diff --git a/examples/make_tracing_c/sub.v b/examples/make_tracing_c/sub.v index 47975db0c..463691411 100644 --- a/examples/make_tracing_c/sub.v +++ b/examples/make_tracing_c/sub.v @@ -13,7 +13,7 @@ module sub // Example counter/flop reg [31:0] count_c; - always_ff @ (posedge clk) begin + always_ff @(posedge clk) begin if (!reset_l) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops @@ -32,11 +32,11 @@ module sub end // An example assertion - always_ff @ (posedge clk) begin - AssertionExample: assert (!reset_l || count_c<100); + always_ff @(posedge clk) begin + AssertionExample : assert (!reset_l || count_c < 100); end // And example coverage analysis - cover property (@(posedge clk) count_c==3); + cover property (@(posedge clk) count_c == 3); endmodule diff --git a/examples/make_tracing_sc/sub.v b/examples/make_tracing_sc/sub.v index 75529a924..100a97570 100644 --- a/examples/make_tracing_sc/sub.v +++ b/examples/make_tracing_sc/sub.v @@ -14,7 +14,7 @@ module sub // Example counter/flop reg [31:0] count_f; - always_ff @ (posedge fastclk) begin + always_ff @(posedge fastclk) begin if (!reset_l) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops @@ -28,7 +28,7 @@ module sub // Another example flop reg [31:0] count_c; - always_ff @ (posedge clk) begin + always_ff @(posedge clk) begin if (!reset_l) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops @@ -38,8 +38,7 @@ module sub else begin count_c <= count_c + 1; if (count_c >= 3) begin - $display("[%0t] fastclk is %0d times faster than clk\n", - $time, count_f/count_c); + $display("[%0t] fastclk is %0d times faster than clk\n", $time, count_f / count_c); // This write is a magic value the Makefile uses to make sure the // test completes successfully. $write("*-* All Finished *-*\n"); @@ -49,11 +48,11 @@ module sub end // An example assertion - always_ff @ (posedge clk) begin - AssertionExample: assert(!reset_l || count_c<100); + always_ff @(posedge clk) begin + AssertionExample : assert (!reset_l || count_c < 100); end // And example coverage analysis - cover property (@(posedge clk) count_c==3); + cover property (@(posedge clk) count_c == 3); endmodule diff --git a/include/gtkwave/fstapi.c b/include/gtkwave/fstapi.c index 7bc7fd821..70f1bb171 100644 --- a/include/gtkwave/fstapi.c +++ b/include/gtkwave/fstapi.c @@ -550,8 +550,9 @@ return(rc); static uint32_t fstReaderVarint32(FILE *f) { -int chk_len = 5; /* TALOS-2023-1783 */ -unsigned char buf[chk_len]; +const int chk_len_max = 5; /* TALOS-2023-1783 */ +int chk_len = chk_len_max; +unsigned char buf[chk_len_max]; unsigned char *mem = buf; uint32_t rc = 0; int ch; @@ -582,8 +583,9 @@ return(rc); static uint32_t fstReaderVarint32WithSkip(FILE *f, uint32_t *skiplen) { -int chk_len = 5; /* TALOS-2023-1783 */ -unsigned char buf[chk_len]; +const int chk_len_max = 5; /* TALOS-2023-1783 */ +int chk_len = chk_len_max; +unsigned char buf[chk_len_max]; unsigned char *mem = buf; uint32_t rc = 0; int ch; @@ -615,8 +617,9 @@ return(rc); static uint64_t fstReaderVarint64(FILE *f) { -int chk_len = 16; /* TALOS-2023-1783 */ -unsigned char buf[chk_len]; +const int chk_len_max = 16; /* TALOS-2023-1783 */ +int chk_len = chk_len_max; +unsigned char buf[chk_len_max]; unsigned char *mem = buf; uint64_t rc = 0; int ch; diff --git a/include/verilated.cpp b/include/verilated.cpp index 448b2f12f..9bb99166c 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -128,6 +128,7 @@ void vl_finish(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE #ifndef VL_USER_STOP ///< Define this to override the vl_stop function void vl_stop(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE { + // $stop or $fatal reporting; would break current API to add param as to which const char* const msg = "Verilog $stop"; Verilated::threadContextp()->gotError(true); Verilated::threadContextp()->gotFinish(true); @@ -172,6 +173,7 @@ void vl_fatal(const char* filename, int linenum, const char* hier, const char* m #ifndef VL_USER_STOP_MAYBE ///< Define this to override the vl_stop_maybe function void vl_stop_maybe(const char* filename, int linenum, const char* hier, bool maybe) VL_MT_UNSAFE { + // $stop or $fatal Verilated::threadContextp()->errorCountInc(); if (maybe && Verilated::threadContextp()->errorCount() < Verilated::threadContextp()->errorLimit()) { @@ -1763,9 +1765,8 @@ IData VL_SYSTEM_IQ(QData lhs) VL_MT_SAFE { return VL_SYSTEM_IW(VL_WQ_WORDS_E, lhsw); } IData VL_SYSTEM_IW(int lhswords, const WDataInP lhsp) VL_MT_SAFE { - char filenamez[VL_VALUE_STRING_MAX_CHARS + 1]; - _vl_vint_to_string(lhswords * VL_EDATASIZE, filenamez, lhsp); - return VL_SYSTEM_IN(filenamez); + const std::string lhs = VL_CVT_PACK_STR_NW(lhswords, lhsp); + return VL_SYSTEM_IN(lhs); } IData VL_SYSTEM_IN(const std::string& lhs) VL_MT_SAFE { const int code = std::system(lhs.c_str()); // Yes, std::system() is threadsafe @@ -1915,20 +1916,16 @@ std::string VL_TOUPPER_NN(const std::string& ld) VL_PURE { std::string VL_CVT_PACK_STR_NW(int lwords, const WDataInP lwp) VL_PURE { // See also _vl_vint_to_string - char destout[VL_VALUE_STRING_MAX_CHARS + 1]; + std::string result; + result.reserve((lwords * VL_EDATASIZE) / 8 + 1); const int obits = lwords * VL_EDATASIZE; int lsb = obits - 1; - char* destp = destout; - size_t len = 0; for (; lsb >= 0; --lsb) { lsb = (lsb / 8) * 8; // Next digit const IData charval = VL_BITRSHIFT_W(lwp, lsb) & 0xff; - if (charval) { - *destp++ = static_cast(charval); - ++len; - } + if (charval) result += static_cast(charval); } - return std::string{destout, len}; + return result; } std::string VL_CVT_PACK_STR_ND(const VlQueue& q) VL_PURE { @@ -3002,7 +2999,7 @@ const VerilatedScopeNameMap* VerilatedContext::scopeNameMap() VL_MT_SAFE { //====================================================================== // VerilatedContext:: Methods - trace -void VerilatedContext::trace(VerilatedTraceBaseC* tfp, int levels, int options) VL_MT_SAFE { +void VerilatedContext::trace(VerilatedTraceBaseC* tfp, int levels, int options) { VL_DEBUG_IF(VL_DBG_MSGF("+ VerilatedContext::trace\n");); if (tfp->isOpen()) { VL_FATAL_MT("", 0, "", diff --git a/include/verilated.h b/include/verilated.h index 169ced582..65ff30c95 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -221,19 +221,6 @@ public: void unlock() VL_RELEASE() VL_MT_SAFE { m_mutex.unlock(); } /// Try to acquire mutex. Returns true on success, and false on failure. bool try_lock() VL_TRY_ACQUIRE(true) VL_MT_SAFE { return m_mutex.try_lock(); } - /// Acquire/lock mutex and check for stop request - /// It tries to lock the mutex and if it fails, it check if stop request was send. - /// It returns after locking mutex. - /// This function should be extracted to V3ThreadPool, but due to clang thread-safety - /// limitations it needs to be placed here. - void lockCheckStopRequest(std::function checkStopRequestFunction) - VL_ACQUIRE() VL_MT_SAFE { - while (true) { - checkStopRequestFunction(); - if (m_mutex.try_lock()) return; - VL_CPU_RELAX(); - } - } }; /// Lock guard for mutex (ala std::unique_lock), wrapped to allow -fthread_safety checks @@ -809,8 +796,6 @@ class Verilated final { public: // METHODS - User called - /// Enable debug of internal verilated code - static void debug(int level) VL_MT_SAFE; #ifdef VL_DEBUG /// Return debug level /// When multithreaded this may not immediately react to another thread @@ -820,6 +805,8 @@ public: /// Return constant 0 debug level, so C++'s optimizer rips up static constexpr int debug() VL_PURE { return 0; } #endif + /// Enable debug of internal verilated code + static void debug(int level) VL_MT_SAFE; /// Set the last VerilatedContext accessed /// Generally threadContextp(value) should be called instead @@ -878,44 +865,44 @@ public: static const char* commandArgsPlusMatch(const char* prefixp) VL_MT_SAFE { return Verilated::threadContextp()->commandArgsPlusMatch(prefixp); } - /// Call VerilatedContext::errorLimit using current thread's VerilatedContext - static void errorLimit(int val) VL_MT_SAFE { Verilated::threadContextp()->errorLimit(val); } /// Return VerilatedContext::errorLimit using current thread's VerilatedContext static int errorLimit() VL_MT_SAFE { return Verilated::threadContextp()->errorLimit(); } + /// Call VerilatedContext::errorLimit using current thread's VerilatedContext + static void errorLimit(int val) VL_MT_SAFE { Verilated::threadContextp()->errorLimit(val); } + /// Return VerilatedContext::fatalOnError using current thread's VerilatedContext + static bool fatalOnError() VL_MT_SAFE { return Verilated::threadContextp()->fatalOnError(); } /// Call VerilatedContext::fatalOnError using current thread's VerilatedContext static void fatalOnError(bool flag) VL_MT_SAFE { Verilated::threadContextp()->fatalOnError(flag); } - /// Return VerilatedContext::fatalOnError using current thread's VerilatedContext - static bool fatalOnError() VL_MT_SAFE { return Verilated::threadContextp()->fatalOnError(); } - /// Call VerilatedContext::fatalOnVpiError using current thread's VerilatedContext - static void fatalOnVpiError(bool flag) VL_MT_SAFE { - Verilated::threadContextp()->fatalOnVpiError(flag); - } /// Return VerilatedContext::fatalOnVpiError using current thread's VerilatedContext static bool fatalOnVpiError() VL_MT_SAFE { return Verilated::threadContextp()->fatalOnVpiError(); } - /// Call VerilatedContext::gotError using current thread's VerilatedContext - static void gotError(bool flag) VL_MT_SAFE { Verilated::threadContextp()->gotError(flag); } + /// Call VerilatedContext::fatalOnVpiError using current thread's VerilatedContext + static void fatalOnVpiError(bool flag) VL_MT_SAFE { + Verilated::threadContextp()->fatalOnVpiError(flag); + } /// Return VerilatedContext::gotError using current thread's VerilatedContext static bool gotError() VL_MT_SAFE { return Verilated::threadContextp()->gotError(); } - /// Call VerilatedContext::gotFinish using current thread's VerilatedContext - static void gotFinish(bool flag) VL_MT_SAFE { Verilated::threadContextp()->gotFinish(flag); } + /// Call VerilatedContext::gotError using current thread's VerilatedContext + static void gotError(bool flag) VL_MT_SAFE { Verilated::threadContextp()->gotError(flag); } /// Return VerilatedContext::gotFinish using current thread's VerilatedContext static bool gotFinish() VL_MT_SAFE { return Verilated::threadContextp()->gotFinish(); } - /// Call VerilatedContext::randReset using current thread's VerilatedContext - static void randReset(int val) VL_MT_SAFE { Verilated::threadContextp()->randReset(val); } + /// Call VerilatedContext::gotFinish using current thread's VerilatedContext + static void gotFinish(bool flag) VL_MT_SAFE { Verilated::threadContextp()->gotFinish(flag); } /// Return VerilatedContext::randReset using current thread's VerilatedContext static int randReset() VL_MT_SAFE { return Verilated::threadContextp()->randReset(); } - /// Call VerilatedContext::randSeed using current thread's VerilatedContext - static void randSeed(int val) VL_MT_SAFE { Verilated::threadContextp()->randSeed(val); } + /// Call VerilatedContext::randReset using current thread's VerilatedContext + static void randReset(int val) VL_MT_SAFE { Verilated::threadContextp()->randReset(val); } /// Return VerilatedContext::randSeed using current thread's VerilatedContext static int randSeed() VL_MT_SAFE { return Verilated::threadContextp()->randSeed(); } - /// Call VerilatedContext::time using current thread's VerilatedContext - static void time(uint64_t val) VL_MT_SAFE { Verilated::threadContextp()->time(val); } + /// Call VerilatedContext::randSeed using current thread's VerilatedContext + static void randSeed(int val) VL_MT_SAFE { Verilated::threadContextp()->randSeed(val); } /// Return VerilatedContext::time using current thread's VerilatedContext static uint64_t time() VL_MT_SAFE { return Verilated::threadContextp()->time(); } + /// Call VerilatedContext::time using current thread's VerilatedContext + static void time(uint64_t val) VL_MT_SAFE { Verilated::threadContextp()->time(val); } /// Call VerilatedContext::timeInc using current thread's VerilatedContext static void timeInc(uint64_t add) VL_MT_UNSAFE { Verilated::threadContextp()->timeInc(add); } // Deprecated diff --git a/include/verilated_cov.h b/include/verilated_cov.h index 13c3d2806..d27b648af 100644 --- a/include/verilated_cov.h +++ b/include/verilated_cov.h @@ -92,8 +92,8 @@ public: std::string defaultFilename() VL_MT_SAFE; /// Make all data per_instance, overriding point's per_instance void forcePerInstance(bool flag) VL_MT_SAFE; - void write() VL_MT_SAFE { write(defaultFilename()); } /// Write all coverage data to a file + void write() VL_MT_SAFE { write(defaultFilename()); } void write(const std::string& filename) VL_MT_SAFE; /// Clear coverage points (and call delete on all items) void clear() VL_MT_SAFE; @@ -165,8 +165,8 @@ public: /// Return default filename for the current thread static std::string defaultFilename() VL_MT_SAFE { return threadCovp()->defaultFilename(); } /// Write all coverage data to a file for the current thread - static void write(const std::string& filename) VL_MT_SAFE { threadCovp()->write(filename); } static void write() VL_MT_SAFE { write(defaultFilename()); } + static void write(const std::string& filename) VL_MT_SAFE { threadCovp()->write(filename); } /// Clear coverage points (and call delete on all items) for the current thread static void clear() VL_MT_SAFE { threadCovp()->clear(); } /// Clear items not matching the provided string for the current thread diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index 05422641f..348ffa001 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -127,6 +127,7 @@ void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, uint32_t elemen // TODO: should return std::optional, but I can't have C++17 static std::pair toFstScopeType(VerilatedTracePrefixType type) { switch (type) { + case VerilatedTracePrefixType::ROOTIO_MODULE: return {true, FST_ST_VCD_MODULE}; case VerilatedTracePrefixType::SCOPE_MODULE: return {true, FST_ST_VCD_MODULE}; case VerilatedTracePrefixType::SCOPE_INTERFACE: return {true, FST_ST_VCD_INTERFACE}; case VerilatedTracePrefixType::STRUCT_PACKED: @@ -137,7 +138,20 @@ static std::pair toFstScopeType(VerilatedTracePrefixType typ } void VerilatedFst::pushPrefix(const std::string& name, VerilatedTracePrefixType type) { - const std::string newPrefix = m_prefixStack.back().first + name; + assert(!m_prefixStack.empty()); // Constructor makes an empty entry + std::string pname = name; + // An empty name means this is the root of a model created with name()=="". The + // tools get upset if we try to pass this as empty, so we put the signals under a + // new scope, but the signals further down will be peers, not children (as usual + // for name()!="") + // Terminate earlier $root? + if (m_prefixStack.back().second == VerilatedTracePrefixType::ROOTIO_MODULE) popPrefix(); + if (pname.empty()) { // Start new temporary root + pname = "$rootio"; // VCD names are not backslash escaped + m_prefixStack.emplace_back("", VerilatedTracePrefixType::ROOTIO_WRAPPER); + type = VerilatedTracePrefixType::ROOTIO_MODULE; + } + const std::string newPrefix = m_prefixStack.back().first + pname; const auto pair = toFstScopeType(type); const bool properScope = pair.first; const fstScopeType scopeType = pair.second; @@ -149,10 +163,11 @@ void VerilatedFst::pushPrefix(const std::string& name, VerilatedTracePrefixType } void VerilatedFst::popPrefix() { + assert(!m_prefixStack.empty()); const bool properScope = toFstScopeType(m_prefixStack.back().second).first; if (properScope) fstWriterSetUpscope(m_fst); m_prefixStack.pop_back(); - assert(!m_prefixStack.empty()); + assert(!m_prefixStack.empty()); // Always one left, the constructor's initial one } void VerilatedFst::declare(uint32_t code, const char* name, int dtypenum, @@ -294,7 +309,7 @@ void VerilatedFst::configure(const VerilatedTraceConfig& config) { // so always inline them. VL_ATTR_ALWINLINE -void VerilatedFstBuffer::emitEvent(uint32_t code, const VlEventBase* newval) { +void VerilatedFstBuffer::emitEvent(uint32_t code) { VL_DEBUG_IFDEF(assert(m_symbolp[code]);); fstWriterEmitValueChange(m_fst, m_symbolp[code], "1"); } diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index a8559c464..891bf0fc2 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -47,7 +47,7 @@ private: friend VerilatedFstBuffer; // Give the buffer access to the private bits //========================================================================= - // FST specific internals + // FST-specific internals void* m_fst = nullptr; std::map m_code2symbol; @@ -177,7 +177,7 @@ class VerilatedFstBuffer VL_NOT_FINAL { // Implementations of duck-typed methods for VerilatedTraceBuffer. These are // called from only one place (the full* methods), so always inline them. - VL_ATTR_ALWINLINE void emitEvent(uint32_t code, const VlEventBase* newval); + VL_ATTR_ALWINLINE void emitEvent(uint32_t code); VL_ATTR_ALWINLINE void emitBit(uint32_t code, CData newval); VL_ATTR_ALWINLINE void emitCData(uint32_t code, CData newval, int bits); VL_ATTR_ALWINLINE void emitSData(uint32_t code, SData newval, int bits); diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h index 21e3117c5..eea56ac26 100644 --- a/include/verilated_funcs.h +++ b/include/verilated_funcs.h @@ -42,19 +42,20 @@ extern void vl_finish(const char* filename, int linenum, const char* hier) VL_MT /// Routine to call for $stop and non-fatal error /// User code may wish to replace this function, to do so, define VL_USER_STOP. /// This code does not have to be thread safe. -/// Verilator internal code must call VL_FINISH_MT instead, which eventually calls this. +/// Verilator internal code must call VL_STOP_MT instead, which eventually calls this. extern void vl_stop(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE; /// Routine to call for fatal messages /// User code may wish to replace this function, to do so, define VL_USER_FATAL. /// This code does not have to be thread safe. -/// Verilator internal code must call VL_FINISH_MT instead, which eventually calls this. +/// Verilator internal code must call VL_FATAL_MT instead, which eventually calls this. extern void vl_fatal(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_UNSAFE; /// Routine to call for warning messages /// User code may wish to replace this function, to do so, define VL_USER_WARN. /// This code does not have to be thread safe. +/// Verilator internal code must call VL_WARN_MT instead, which eventually calls this. extern void vl_warn(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_UNSAFE; @@ -2206,84 +2207,94 @@ static inline void VL_UNPACK_II(int lbits, int rbits, VlQueue& q, IData f const size_t size = (rbits + lbits - 1) / lbits; q.renew(size); const IData mask = VL_MASK_I(lbits); - for (size_t i = 0; i < size; ++i) q.at(i) = (from >> (i * lbits)) & mask; + for (size_t i = 0; i < size; ++i) q.atWrite(i) = (from >> (i * lbits)) & mask; } static inline void VL_UNPACK_II(int lbits, int rbits, VlQueue& q, IData from) { const size_t size = (rbits + lbits - 1) / lbits; q.renew(size); const IData mask = VL_MASK_I(lbits); - for (size_t i = 0; i < size; ++i) q.at(i) = (from >> (i * lbits)) & mask; + for (size_t i = 0; i < size; ++i) q.atWrite(i) = (from >> (i * lbits)) & mask; } static inline void VL_UNPACK_II(int lbits, int rbits, VlQueue& q, IData from) { const size_t size = (rbits + lbits - 1) / lbits; q.renew(size); const IData mask = VL_MASK_I(lbits); - for (size_t i = 0; i < size; ++i) q.at(i) = (from >> (i * lbits)) & mask; + for (size_t i = 0; i < size; ++i) q.atWrite(i) = (from >> (i * lbits)) & mask; } static inline void VL_UNPACK_IQ(int lbits, int rbits, VlQueue& q, QData from) { const size_t size = (rbits + lbits - 1) / lbits; q.renew(size); const IData mask = VL_MASK_I(lbits); - for (size_t i = 0; i < size; ++i) q.at(i) = (from >> (i * lbits)) & mask; + for (size_t i = 0; i < size; ++i) q.atWrite(i) = (from >> (i * lbits)) & mask; } static inline void VL_UNPACK_IQ(int lbits, int rbits, VlQueue& q, QData from) { const size_t size = (rbits + lbits - 1) / lbits; q.renew(size); const IData mask = VL_MASK_I(lbits); - for (size_t i = 0; i < size; ++i) q.at(i) = (from >> (i * lbits)) & mask; + for (size_t i = 0; i < size; ++i) q.atWrite(i) = (from >> (i * lbits)) & mask; } static inline void VL_UNPACK_IQ(int lbits, int rbits, VlQueue& q, QData from) { const size_t size = (rbits + lbits - 1) / lbits; q.renew(size); const IData mask = VL_MASK_I(lbits); - for (size_t i = 0; i < size; ++i) q.at(i) = (from >> (i * lbits)) & mask; + for (size_t i = 0; i < size; ++i) q.atWrite(i) = (from >> (i * lbits)) & mask; } static inline void VL_UNPACK_QQ(int lbits, int rbits, VlQueue& q, QData from) { const size_t size = (rbits + lbits - 1) / lbits; q.renew(size); const QData mask = VL_MASK_Q(lbits); - for (size_t i = 0; i < size; ++i) q.at(i) = (from >> (i * lbits)) & mask; + for (size_t i = 0; i < size; ++i) q.atWrite(i) = (from >> (i * lbits)) & mask; } static inline void VL_UNPACK_IW(int lbits, int rbits, VlQueue& q, WDataInP rwp) { const int size = (rbits + lbits - 1) / lbits; q.renew(size); const IData mask = VL_MASK_I(lbits); - for (size_t i = 0; i < size; ++i) q.at(i) = VL_SEL_IWII(rbits, rwp, i * lbits, lbits) & mask; + for (size_t i = 0; i < size; ++i) { + q.atWrite(i) = VL_SEL_IWII(rbits, rwp, i * lbits, lbits) & mask; + } } static inline void VL_UNPACK_IW(int lbits, int rbits, VlQueue& q, WDataInP rwp) { const int size = (rbits + lbits - 1) / lbits; q.renew(size); const IData mask = VL_MASK_I(lbits); - for (size_t i = 0; i < size; ++i) q.at(i) = VL_SEL_IWII(rbits, rwp, i * lbits, lbits) & mask; + for (size_t i = 0; i < size; ++i) { + q.atWrite(i) = VL_SEL_IWII(rbits, rwp, i * lbits, lbits) & mask; + } } static inline void VL_UNPACK_IW(int lbits, int rbits, VlQueue& q, WDataInP rwp) { const int size = (rbits + lbits - 1) / lbits; q.renew(size); const IData mask = VL_MASK_I(lbits); - for (size_t i = 0; i < size; ++i) q.at(i) = VL_SEL_IWII(rbits, rwp, i * lbits, lbits) & mask; + for (size_t i = 0; i < size; ++i) { + q.atWrite(i) = VL_SEL_IWII(rbits, rwp, i * lbits, lbits) & mask; + } } static inline void VL_UNPACK_QW(int lbits, int rbits, VlQueue& q, WDataInP rwp) { const int size = (rbits + lbits - 1) / lbits; q.renew(size); const QData mask = VL_MASK_Q(lbits); - for (size_t i = 0; i < size; ++i) q.at(i) = VL_SEL_QWII(rbits, rwp, i * lbits, lbits) & mask; + for (size_t i = 0; i < size; ++i) { + q.atWrite(i) = VL_SEL_QWII(rbits, rwp, i * lbits, lbits) & mask; + } } template static inline void VL_UNPACK_WW(int lbits, int rbits, VlQueue>& q, WDataInP rwp) { const int size = (rbits + lbits - 1) / lbits; q.renew(size); - for (size_t i = 0; i < size; ++i) VL_SEL_WWII(lbits, rbits, q.at(i), rwp, i * lbits, lbits); + for (size_t i = 0; i < size; ++i) { + VL_SEL_WWII(lbits, rbits, q.atWrite(i), rwp, i * lbits, lbits); + } } template diff --git a/include/verilated_intrinsics.h b/include/verilated_intrinsics.h index a8c153e49..ff5f56fbd 100644 --- a/include/verilated_intrinsics.h +++ b/include/verilated_intrinsics.h @@ -12,13 +12,13 @@ //************************************************************************* /// /// \file -/// \brief Verilator common target specific intrinsics header +/// \brief Verilator common target-specific intrinsics header /// /// This file is not part of the Verilated public-facing API. /// -/// It is only for internal use; code using machine specific intrinsics for +/// It is only for internal use; code using machine-specific intrinsics for /// optimization should include this header rather than directly including -/// he target specific headers. We provide macros to check for availability +/// the target-specific headers. We provide macros to check for availability /// of instruction sets, and a common mechanism to disable them. /// //************************************************************************* diff --git a/include/verilated_random.cpp b/include/verilated_random.cpp index 47d2973a5..324e6cdbe 100644 --- a/include/verilated_random.cpp +++ b/include/verilated_random.cpp @@ -230,7 +230,7 @@ static Process& getSolver() { const char* const* const cmd = &s_argv[0]; s_solver.open(cmd); - s_solver << "(set-logic QF_BV)\n"; + s_solver << "(set-logic QF_ABV)\n"; s_solver << "(check-sat)\n"; s_solver << "(reset)\n"; std::string s; @@ -250,32 +250,78 @@ static Process& getSolver() { return s_solver; } +std::string readUntilBalanced(std::istream& stream) { + std::string result; + std::string token; + int parenCount = 1; + while (stream >> token) { + for (const char c : token) { + if (c == '(') { + ++parenCount; + } else if (c == ')') { + --parenCount; + } + } + result += token + " "; + if (parenCount == 0) break; + } + return result; +} + +std::string parseNestedSelect(const std::string& nested_select_expr, + std::vector& indices) { + std::istringstream nestedStream(nested_select_expr); + std::string name, idx; + nestedStream >> name; + if (name == "(select") { + const std::string further_nested_expr = readUntilBalanced(nestedStream); + name = parseNestedSelect(further_nested_expr, indices); + } + std::getline(nestedStream, idx, ')'); + indices.push_back(idx); + return name; +} + +std::string flattenIndices(const std::vector& indices, const VlRandomVar* const var) { + int flattenedIndex = 0; + int multiplier = 1; + for (int i = indices.size() - 1; i >= 0; --i) { + int indexValue = 0; + std::string trimmedIndex = indices[i]; + + trimmedIndex.erase(0, trimmedIndex.find_first_not_of(" \t")); + trimmedIndex.erase(trimmedIndex.find_last_not_of(" \t") + 1); + + if (trimmedIndex.find("#x") == 0) { + indexValue = std::strtoul(trimmedIndex.substr(2).c_str(), nullptr, 16); + } else if (trimmedIndex.find("#b") == 0) { + indexValue = std::strtoul(trimmedIndex.substr(2).c_str(), nullptr, 2); + } else { + indexValue = std::strtoul(trimmedIndex.c_str(), nullptr, 10); + } + const int length = var->getLength(i); + if (length == -1) { + VL_WARN_MT(__FILE__, __LINE__, "randomize", + "Internal: Wrong Call: Only RandomArray can call getLength()"); + break; + } + flattenedIndex += indexValue * multiplier; + multiplier *= length; + } + std::string hexString = std::to_string(flattenedIndex); + while (hexString.size() < 8) { hexString.insert(0, "0"); } + return "#x" + hexString; +} //====================================================================== // VlRandomizer:: Methods -void VlRandomVar::emit(std::ostream& s) const { s << m_name; } -void VlRandomConst::emit(std::ostream& s) const { - s << "#b"; - for (int i = 0; i < m_width; i++) s << (VL_BITISSET_Q(m_val, m_width - i - 1) ? '1' : '0'); +void VlRandomVar::emitGetValue(std::ostream& s) const { s << ' ' << m_name; } +void VlRandomVar::emitExtract(std::ostream& s, int i) const { + s << " ((_ extract " << i << ' ' << i << ") " << m_name << ')'; } -void VlRandomBinOp::emit(std::ostream& s) const { - s << '(' << m_op << ' '; - m_lhs->emit(s); - s << ' '; - m_rhs->emit(s); - s << ')'; -} -void VlRandomExtract::emit(std::ostream& s) const { - s << "((_ extract " << m_idx << ' ' << m_idx << ") "; - m_expr->emit(s); - s << ')'; -} -bool VlRandomVar::set(std::string&& val) const { - VlWide qowp; - VL_SET_WQ(qowp, 0ULL); - WDataOutP owp = qowp; - int obits = width(); - if (obits > VL_QUADSIZE) owp = reinterpret_cast(datap()); +void VlRandomVar::emitType(std::ostream& s) const { s << "(_ BitVec " << width() << ')'; } +int VlRandomVar::totalWidth() const { return m_width; } +static bool parseSMTNum(int obits, WDataOutP owp, const std::string& val) { int i; for (i = 0; val[i] && val[i] != '#'; i++) {} if (val[i++] != '#') return false; @@ -289,17 +335,31 @@ bool VlRandomVar::set(std::string&& val) const { "Internal: Unable to parse solver's randomized number"); return false; } + return true; +} +bool VlRandomVar::set(const std::string& idx, const std::string& val) const { + VlWide qowp; + VL_SET_WQ(qowp, 0ULL); + WDataOutP owp = qowp; + const int obits = width(); + VlWide qiwp; + VL_SET_WQ(qiwp, 0ULL); + if (!idx.empty() && !parseSMTNum(64, qiwp, idx)) return false; + const int nidx = qiwp[0]; + if (obits > VL_QUADSIZE) owp = reinterpret_cast(datap(nidx)); + if (!parseSMTNum(obits, owp, val)) return false; + if (obits <= VL_BYTESIZE) { - CData* const p = static_cast(datap()); + CData* const p = static_cast(datap(nidx)); *p = VL_CLEAN_II(obits, obits, owp[0]); } else if (obits <= VL_SHORTSIZE) { - SData* const p = static_cast(datap()); + SData* const p = static_cast(datap(nidx)); *p = VL_CLEAN_II(obits, obits, owp[0]); } else if (obits <= VL_IDATASIZE) { - IData* const p = static_cast(datap()); + IData* const p = static_cast(datap(nidx)); *p = VL_CLEAN_II(obits, obits, owp[0]); } else if (obits <= VL_QUADSIZE) { - QData* const p = static_cast(datap()); + QData* const p = static_cast(datap(nidx)); *p = VL_CLEAN_QQ(obits, obits, VL_SET_QW(owp)); } else { _vl_clean_inplace_w(obits, owp); @@ -307,27 +367,31 @@ bool VlRandomVar::set(std::string&& val) const { return true; } -std::shared_ptr VlRandomizer::randomConstraint(VlRNG& rngr, int bits) { - unsigned long long hash = VL_RANDOM_RNG_I(rngr) & ((1 << bits) - 1); - std::shared_ptr concat = nullptr; - std::vector> varbits; - for (const auto& var : m_vars) { - for (int i = 0; i < var.second->width(); i++) - varbits.emplace_back(std::make_shared(var.second, i)); - } +void VlRandomizer::randomConstraint(std::ostream& os, VlRNG& rngr, int bits) { + const IData hash = VL_RANDOM_RNG_I(rngr) & ((1 << bits) - 1); + int varBits = 0; + for (const auto& var : m_vars) varBits += var.second->totalWidth(); + os << "(= #b"; + for (int i = bits - 1; i >= 0; i--) os << (VL_BITISSET_I(hash, i) ? '1' : '0'); + if (bits > 1) os << " (concat"; for (int i = 0; i < bits; i++) { - std::shared_ptr bit = nullptr; - for (unsigned j = 0; j * 2 < varbits.size(); j++) { - unsigned idx = j + VL_RANDOM_RNG_I(rngr) % (varbits.size() - j); - auto sel = varbits[idx]; - std::swap(varbits[idx], varbits[j]); - bit = bit == nullptr ? sel : std::make_shared("bvxor", bit, sel); + IData varBitsLeft = varBits; + IData varBitsWant = (varBits + 1) / 2; + if (varBits > 2) os << " (bvxor"; + for (const auto& var : m_vars) { + for (int j = 0; j < var.second->totalWidth(); j++, varBitsLeft--) { + const bool doEmit = (VL_RANDOM_RNG_I(rngr) % varBitsLeft) < varBitsWant; + if (doEmit) { + var.second->emitExtract(os, j); + if (--varBitsWant == 0) break; + } + } + if (varBitsWant == 0) break; } - concat = concat == nullptr ? bit - : std::make_shared("concat", concat, bit); + if (varBits > 2) os << ')'; } - return std::make_shared( - "=", concat, std::make_shared(hash, bits)); + if (bits > 1) os << ')'; + os << ')'; } bool VlRandomizer::next(VlRNG& rngr) { @@ -336,12 +400,17 @@ bool VlRandomizer::next(VlRNG& rngr) { if (!f) return false; f << "(set-option :produce-models true)\n"; - f << "(set-logic QF_BV)\n"; + f << "(set-logic QF_ABV)\n"; + f << "(define-fun __Vbv ((b Bool)) (_ BitVec 1) (ite b #b1 #b0))\n"; + f << "(define-fun __Vbool ((v (_ BitVec 1))) Bool (= #b1 v))\n"; for (const auto& var : m_vars) { - f << "(declare-fun " << var.second->name() << " () (_ BitVec " << var.second->width() - << "))\n"; + f << "(declare-fun " << var.second->name() << " () "; + var.second->emitType(f); + f << ")\n"; + } + for (const std::string& constraint : m_constraints) { + f << "(assert (= #b1 " << constraint << "))\n"; } - for (const std::string& constraint : m_constraints) { f << "(assert " << constraint << ")\n"; } f << "(check-sat)\n"; bool sat = parseSolution(f); @@ -349,10 +418,9 @@ bool VlRandomizer::next(VlRNG& rngr) { f << "(reset)\n"; return false; } - for (int i = 0; i < _VL_SOLVER_HASH_LEN_TOTAL && sat; i++) { f << "(assert "; - randomConstraint(rngr, _VL_SOLVER_HASH_LEN)->emit(f); + randomConstraint(f, rngr, _VL_SOLVER_HASH_LEN); f << ")\n"; f << "\n(check-sat)\n"; sat = parseSolution(f); @@ -376,7 +444,7 @@ bool VlRandomizer::parseSolution(std::iostream& f) { } f << "(get-value ("; - for (const auto& var : m_vars) f << var.second->name() << ' '; + for (const auto& var : m_vars) var.second->emitGetValue(f); f << "))\n"; // Quasi-parse S-expression of the form ((x #xVALUE) (y #bVALUE) (z #xVALUE)) @@ -396,21 +464,29 @@ bool VlRandomizer::parseSolution(std::iostream& f) { "Internal: Unable to parse solver's response: invalid S-expression"); return false; } - - std::string name, value; + std::string name, idx, value; + std::vector indices; f >> name; + indices.clear(); + if (name == "(select") { + const std::string selectExpr = readUntilBalanced(f); + name = parseNestedSelect(selectExpr, indices); + idx = indices[0]; + } std::getline(f, value, ')'); - - auto it = m_vars.find(name); + const auto it = m_vars.find(name); if (it == m_vars.end()) continue; const VlRandomVar& varr = *it->second; if (m_randmode && !varr.randModeIdxNone()) { if (!(m_randmode->at(varr.randModeIdx()))) continue; } - - varr.set(std::move(value)); + if (indices.size() > 1) { + const std::string flattenedIndex = flattenIndices(indices, &varr); + varr.set(flattenedIndex, value); + } else { + varr.set(idx, value); + } } - return true; } diff --git a/include/verilated_random.h b/include/verilated_random.h index b53e0eb82..2ae2dcb22 100644 --- a/include/verilated_random.h +++ b/include/verilated_random.h @@ -27,71 +27,163 @@ #include "verilated.h" +#include + //============================================================================= // VlRandomExpr and subclasses represent expressions for the constraint solver. -class VlRandomExpr VL_NOT_FINAL { -public: - virtual void emit(std::ostream& s) const = 0; -}; -class VlRandomVar final : public VlRandomExpr { +class VlRandomVar VL_NOT_FINAL { const char* const m_name; // Variable name void* const m_datap; // Reference to variable data const int m_width; // Variable width in bits + const int m_dimension; //Variable dimension, default is 0 const std::uint32_t m_randModeIdx; // rand_mode index public: - VlRandomVar(const char* name, int width, void* datap, std::uint32_t randModeIdx) + VlRandomVar(const char* name, int width, void* datap, int dimension, std::uint32_t randModeIdx) : m_name{name} , m_datap{datap} , m_width{width} + , m_dimension{dimension} , m_randModeIdx{randModeIdx} {} + virtual ~VlRandomVar() = default; const char* name() const { return m_name; } int width() const { return m_width; } - void* datap() const { return m_datap; } + int dimension() const { return m_dimension; } + virtual void* datap(int idx) const { return m_datap; } std::uint32_t randModeIdx() const { return m_randModeIdx; } bool randModeIdxNone() const { return randModeIdx() == std::numeric_limits::max(); } - bool set(std::string&&) const; - void emit(std::ostream& s) const override; + bool set(const std::string& idx, const std::string& val) const; + virtual void emitGetValue(std::ostream& s) const; + virtual void emitExtract(std::ostream& s, int i) const; + virtual void emitType(std::ostream& s) const; + virtual int totalWidth() const; + virtual int getLength(int dimension) const { return -1; } }; -class VlRandomConst final : public VlRandomExpr { - const QData m_val; // Constant value - const int m_width; // Constant width in bits - +template +class VlRandomQueueVar final : public VlRandomVar { public: - VlRandomConst(QData val, int width) - : m_val{val} - , m_width{width} { - assert(width <= sizeof(m_val) * 8); + VlRandomQueueVar(const char* name, int width, void* datap, int dimension, + std::uint32_t randModeIdx) + : VlRandomVar{name, width, datap, dimension, randModeIdx} {} + void* datap(int idx) const override { + return &static_cast(VlRandomVar::datap(idx))->atWrite(idx); + } + void emitSelect(std::ostream& s, int i) const { + s << " (select " << name() << " #x"; + for (int j = 28; j >= 0; j -= 4) s << "0123456789abcdef"[(i >> j) & 0xf]; + s << ')'; + } + void emitGetValue(std::ostream& s) const override { + const int length = static_cast(VlRandomVar::datap(0))->size(); + for (int i = 0; i < length; i++) emitSelect(s, i); + } + void emitType(std::ostream& s) const override { + s << "(Array (_ BitVec 32) (_ BitVec " << width() << "))"; + } + int totalWidth() const override { + const int length = static_cast(VlRandomVar::datap(0))->size(); + return width() * length; + } + void emitExtract(std::ostream& s, int i) const override { + const int j = i / width(); + i = i % width(); + s << " ((_ extract " << i << ' ' << i << ')'; + emitSelect(s, j); + s << ')'; } - void emit(std::ostream& s) const override; }; -class VlRandomExtract final : public VlRandomExpr { - const std::shared_ptr m_expr; // Sub-expression - const unsigned m_idx; // Extracted index - +template +class VlRandomArrayVar final : public VlRandomVar { public: - VlRandomExtract(std::shared_ptr expr, unsigned idx) - : m_expr{expr} - , m_idx{idx} {} - void emit(std::ostream& s) const override; + VlRandomArrayVar(const char* name, int width, void* datap, int dimension, + std::uint32_t randModeIdx) + : VlRandomVar{name, width, datap, dimension, randModeIdx} {} + + void* datap(int idx) const override { + if (idx < 0) return &static_cast(VlRandomVar::datap(0))->operator[](0); + std::vector indices(dimension()); + for (int dim = dimension() - 1; dim >= 0; --dim) { + const int length = getLength(dim); + indices[dim] = idx % length; + idx /= length; + } + return &static_cast(VlRandomVar::datap(0))->find_element(indices); + } + + void emitSelect(std::ostream& s, const std::vector& indices) const { + for (size_t idx = 0; idx < indices.size(); ++idx) s << "(select "; + s << name(); + for (size_t idx = 0; idx < indices.size(); ++idx) { + s << " #x"; + for (int j = 28; j >= 0; j -= 4) { + s << "0123456789abcdef"[(indices[idx] >> j) & 0xf]; + } + s << ")"; + } + } + + int getLength(int dimension) const override { + const auto var = static_cast(datap(-1)); + const int lenth = var->find_length(dimension); + return lenth; + } + + void emitGetValue(std::ostream& s) const override { + const int total_dimensions = dimension(); + std::vector lengths; + for (int dim = 0; dim < total_dimensions; dim++) { + const int len = getLength(dim); + lengths.push_back(len); + } + std::vector indices(total_dimensions, 0); + while (true) { + emitSelect(s, indices); + int currentDimension = total_dimensions - 1; + while (currentDimension >= 0 + && ++indices[currentDimension] >= lengths[currentDimension]) { + indices[currentDimension] = 0; + --currentDimension; + } + if (currentDimension < 0) break; + } + } + + void emitType(std::ostream& s) const override { + if (dimension() > 0) { + for (int i = 0; i < dimension(); ++i) s << "(Array (_ BitVec 32) "; + s << "(_ BitVec " << width() << ")"; + for (int i = 0; i < dimension(); ++i) s << ")"; + } + } + + int totalWidth() const override { + int totalLength = 1; + for (int dim = 0; dim < dimension(); ++dim) { + const int length = getLength(dim); + if (length == -1) return 0; + totalLength *= length; + } + return width() * totalLength; + } + + void emitExtract(std::ostream& s, int i) const override { + const int j = i / width(); + i = i % width(); + std::vector indices(dimension()); + int idx = j; + for (int dim = dimension() - 1; dim >= 0; --dim) { + int length = getLength(dim); + indices[dim] = idx % length; + idx /= length; + } + s << " ((_ extract " << i << ' ' << i << ')'; + emitSelect(s, indices); + s << ')'; + } }; - -class VlRandomBinOp final : public VlRandomExpr { - const char* const m_op; // Binary operation identifier - const std::shared_ptr m_lhs, m_rhs; // Sub-expressions - -public: - VlRandomBinOp(const char* op, std::shared_ptr lhs, - std::shared_ptr rhs) - : m_op{op} - , m_lhs{lhs} - , m_rhs{rhs} {} - void emit(std::ostream& s) const override; -}; - //============================================================================= // VlRandomizer is the object holding constraints and variable references. @@ -103,19 +195,38 @@ class VlRandomizer final { const VlQueue* m_randmode; // rand_mode state; // PRIVATE METHODS - std::shared_ptr randomConstraint(VlRNG& rngr, int bits); + void randomConstraint(std::ostream& os, VlRNG& rngr, int bits); bool parseSolution(std::iostream& file); public: + // CONSTRUCTORS + VlRandomizer() = default; + ~VlRandomizer() = default; + // METHODS // Finds the next solution satisfying the constraints bool next(VlRNG& rngr); template - void write_var(T& var, int width, const char* name, + void write_var(T& var, int width, const char* name, int dimension, std::uint32_t randmodeIdx = std::numeric_limits::max()) { - auto it = m_vars.find(name); - if (it != m_vars.end()) return; - m_vars[name] = std::make_shared(name, width, &var, randmodeIdx); + if (m_vars.find(name) != m_vars.end()) return; + // TODO: make_unique once VlRandomizer is per-instance not per-ref + m_vars[name] + = std::make_shared(name, width, &var, dimension, randmodeIdx); + } + template + void write_var(VlQueue& var, int width, const char* name, int dimension, + std::uint32_t randmodeIdx = std::numeric_limits::max()) { + if (m_vars.find(name) != m_vars.end()) return; + m_vars[name] = std::make_shared>>( + name, width, &var, dimension, randmodeIdx); + } + template + void write_var(VlUnpacked& var, int width, const char* name, int dimension, + std::uint32_t randmodeIdx = std::numeric_limits::max()) { + if (m_vars.find(name) != m_vars.end()) return; + m_vars[name] = std::make_shared>>( + name, width, &var, dimension, randmodeIdx); } void hard(std::string&& constraint); void clear(); diff --git a/include/verilated_trace.h b/include/verilated_trace.h index dd47ad81b..87d5025b4 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -49,10 +49,12 @@ class VerilatedTraceOffloadBuffer; //============================================================================= // Common enumerations -enum class VerilatedTracePrefixType : uint32_t { +enum class VerilatedTracePrefixType : uint8_t { // Note: Entries must match VTracePrefixType (by name, not necessarily by value) ARRAY_PACKED, ARRAY_UNPACKED, + ROOTIO_MODULE, // $rootio, used when name()=="", other modules become peers + ROOTIO_WRAPPER, // "Above" ROOTIO_MODULE SCOPE_MODULE, SCOPE_INTERFACE, STRUCT_PACKED, @@ -61,7 +63,7 @@ enum class VerilatedTracePrefixType : uint32_t { }; // Direction attribute for ports -enum class VerilatedTraceSigDirection : uint32_t { +enum class VerilatedTraceSigDirection : uint8_t { NONE, INPUT, OUTPUT, @@ -69,7 +71,7 @@ enum class VerilatedTraceSigDirection : uint32_t { }; // Kind of signal. Similar to nettype but with a few more alternatives -enum class VerilatedTraceSigKind : uint32_t { +enum class VerilatedTraceSigKind : uint8_t { PARAMETER, SUPPLY0, SUPPLY1, @@ -81,7 +83,7 @@ enum class VerilatedTraceSigKind : uint32_t { }; // Base data type of signal -enum class VerilatedTraceSigType : uint32_t { +enum class VerilatedTraceSigType : uint8_t { DOUBLE, INTEGER, BIT, @@ -198,8 +200,8 @@ public: //============================================================================= // VerilatedTrace -// T_Trace is the format specific subclass of VerilatedTrace. -// T_Buffer is the format specific base class of VerilatedTraceBuffer. +// T_Trace is the format-specific subclass of VerilatedTrace. +// T_Buffer is the format-specific base class of VerilatedTraceBuffer. template class VerilatedTrace VL_NOT_FINAL { public: @@ -348,7 +350,7 @@ private: protected: //========================================================================= - // Internals available to format specific implementations + // Internals available to format-specific implementations mutable VerilatedMutex m_mutex; // Ensure dump() etc only called from single thread @@ -381,7 +383,7 @@ protected: } //========================================================================= - // Virtual functions to be provided by the format specific implementation + // Virtual functions to be provided by the format-specific implementation // Called when the trace moves forward to a new time point virtual void emitTimeChange(uint64_t timeui) = 0; @@ -438,7 +440,7 @@ public: //============================================================================= // VerilatedTraceBuffer -// T_Buffer is the format specific base class of VerilatedTraceBuffer. +// T_Buffer is the format-specific base class of VerilatedTraceBuffer. // The format-specific hot-path methods use duck-typing via T_Buffer for performance. template class VerilatedTraceBuffer VL_NOT_FINAL : public T_Buffer { @@ -464,7 +466,7 @@ public: // Hot path internal interface to Verilator generated code // Implementation note: We rely on the following duck-typed implementations - // in the derived class T_Derived. These emit* functions record a format + // in the derived class T_Derived. These emit* functions record a format- // specific trace entry. Normally one would use pure virtual functions for // these here, but we cannot afford dynamic dispatch for calling these as // this is very hot code during tracing. @@ -487,7 +489,8 @@ public: void fullQData(uint32_t* oldp, QData newval, int bits); void fullWData(uint32_t* oldp, const WData* newvalp, int bits); void fullDouble(uint32_t* oldp, double newval); - void fullEvent(uint32_t* oldp, const VlEventBase* newval); + void fullEvent(uint32_t* oldp, const VlEventBase* newvalp); + void fullEventTriggered(uint32_t* oldp); // In non-offload mode, these are called directly by the trace callbacks, // and are called chg*. In offload mode, they are called by the worker @@ -524,9 +527,10 @@ public: } } } - VL_ATTR_ALWINLINE void chgEvent(uint32_t* oldp, const VlEventBase* newval) { - fullEvent(oldp, newval); + VL_ATTR_ALWINLINE void chgEvent(uint32_t* oldp, const VlEventBase* newvalp) { + if (newvalp->isTriggered()) fullEvent(oldp, newvalp); } + VL_ATTR_ALWINLINE void chgEventTriggered(uint32_t* oldp) { fullEventTriggered(oldp); } VL_ATTR_ALWINLINE void chgDouble(uint32_t* oldp, double newval) { double old; std::memcpy(&old, oldp, sizeof(old)); @@ -537,7 +541,7 @@ public: //============================================================================= // VerilatedTraceOffloadBuffer -// T_Buffer is the format specific base class of VerilatedTraceBuffer. +// T_Buffer is the format-specific base class of VerilatedTraceBuffer. // The format-specific hot-path methods use duck-typing via T_Buffer for performance. template class VerilatedTraceOffloadBuffer final : public VerilatedTraceBuffer { @@ -605,7 +609,10 @@ public: m_offloadBufferWritep += 4; VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp);); } - void chgEvent(uint32_t code, const VlEventBase* newval) { + void chgEvent(uint32_t code, const VlEventBase* newvalp) { + if (newvalp->isTriggered()) chgEventTriggered(code); + } + void chgEventTriggered(uint32_t code) { m_offloadBufferWritep[0] = VerilatedTraceOffloadCommand::CHG_EVENT; m_offloadBufferWritep[1] = code; m_offloadBufferWritep += 2; diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h index 94549dc19..ba5bd22e2 100644 --- a/include/verilated_trace_imp.h +++ b/include/verilated_trace_imp.h @@ -12,7 +12,7 @@ //============================================================================= // // Verilated tracing implementation code template common to all formats. -// This file is included by the format specific implementations and +// This file is included by the format-specific implementations and // should not be used otherwise. // //============================================================================= @@ -169,7 +169,7 @@ void VerilatedTrace::offloadWorkerThreadMain() { continue; case VerilatedTraceOffloadCommand::CHG_EVENT: VL_TRACE_OFFLOAD_DEBUG("Command CHG_EVENT " << top); - traceBufp->chgEvent(oldp, reinterpret_cast(readp)); + traceBufp->chgEventTriggered(oldp); continue; //=== @@ -299,7 +299,7 @@ VerilatedTrace::~VerilatedTrace() { } //========================================================================= -// Internals available to format specific implementations +// Internals available to format-specific implementations template <> void VerilatedTrace::traceInit() VL_MT_UNSAFE { @@ -401,7 +401,7 @@ bool VerilatedTrace::declCode(uint32_t code, const std::stri } //========================================================================= -// Internals available to format specific implementations +// Internals available to format-specific implementations template <> std::string VerilatedTrace::timeResStr() const { @@ -543,7 +543,7 @@ void VerilatedTrace::dump(uint64_t timeui) VL_MT_SAFE_EXCLUD Verilated::quiesce(); - // Call hook for format specific behaviour + // Call hook for format-specific behaviour if (VL_UNLIKELY(m_fullDump)) { if (!preFullDump()) return; } else { @@ -667,7 +667,7 @@ void VerilatedTrace::addModel(VerilatedModel* modelp) VL_FATAL_MT(__FILE__, __LINE__, "", "Cannot use parallel tracing with offloading"); } // LCOV_EXCL_STOP - // Configure format specific sub class + // Configure format-specific sub class configure(*(configp.get())); } @@ -818,8 +818,8 @@ VerilatedTraceBuffer::VerilatedTraceBuffer(Trace& owner) , m_sigs_enabledp{owner.m_sigs_enabledp} {} // These functions must write the new value back into the old value store, -// and subsequently call the format specific emit* implementations. Note -// that this file must be included in the format specific implementation, so +// and subsequently call the format-specific emit* implementations. Note +// that this file must be included in the format-specific implementation, so // the emit* functions can be inlined for performance. template <> @@ -831,10 +831,17 @@ void VerilatedTraceBuffer::fullBit(uint32_t* oldp, CData newval) { } template <> -void VerilatedTraceBuffer::fullEvent(uint32_t* oldp, const VlEventBase* newval) { +void VerilatedTraceBuffer::fullEvent(uint32_t* oldp, const VlEventBase* newvalp) { const uint32_t code = oldp - m_sigs_oldvalp; - *oldp = 1; // Do we really store an "event" ? - emitEvent(code, newval); + // No need to update *oldp + if (newvalp->isTriggered()) emitEvent(code); +} + +template <> +void VerilatedTraceBuffer::fullEventTriggered(uint32_t* oldp) { + const uint32_t code = oldp - m_sigs_oldvalp; + // No need to update *oldp + emitEvent(code); } template <> diff --git a/include/verilated_types.h b/include/verilated_types.h index ea831514a..773b20212 100644 --- a/include/verilated_types.h +++ b/include/verilated_types.h @@ -485,6 +485,8 @@ private: public: using const_iterator = typename Deque::const_iterator; + template + using WithFuncReturnType = decltype(std::declval()(0, std::declval())); private: // MEMBERS @@ -593,18 +595,28 @@ public: return v; } - // Setting. Verilog: assoc[index] = v - // Can't just overload operator[] or provide a "at" reference to set, - // because we need to be able to insert only when the value is set - T_Value& at(int32_t index) { + // Setting. Verilog: assoc[index] = v (should only be used by dynamic arrays) + T_Value& atWrite(int32_t index) { + // cppcheck-suppress variableScope static thread_local T_Value t_throwAway; // Needs to work for dynamic arrays, so does not use T_MaxSize if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) { t_throwAway = atDefault(); return t_throwAway; - } else { - return m_deque[index]; } + return m_deque[index]; + } + // Setting. Verilog: assoc[index] = v (should only be used by queues) + T_Value& atWriteAppend(int32_t index) { + // cppcheck-suppress variableScope + static thread_local T_Value t_throwAway; + if (VL_UNLIKELY(index < 0 || index > m_deque.size())) { + t_throwAway = atDefault(); + return t_throwAway; + } else if (VL_UNLIKELY(index == m_deque.size())) { + push_back(atDefault()); + } + return m_deque[index]; } // Accessing. Verilog: v = assoc[index] const T_Value& at(int32_t index) const { @@ -616,7 +628,7 @@ public: } } // Access with an index counted from end (e.g. q[$]) - T_Value& atBack(int32_t index) { return at(m_deque.size() - 1 - index); } + T_Value& atWriteAppendBack(int32_t index) { return atWriteAppend(m_deque.size() - 1 - index); } const T_Value& atBack(int32_t index) const { return at(m_deque.size() - 1 - index); } // function void q.insert(index, value); @@ -821,70 +833,63 @@ public: return out; } template - T_Value r_sum(Func with_func) const { - T_Value out(0); // Type must have assignment operator + WithFuncReturnType r_sum(Func with_func) const { + WithFuncReturnType out = WithFuncReturnType(0); IData index = 0; for (const auto& i : m_deque) out += with_func(index++, i); return out; } T_Value r_product() const { - if (m_deque.empty()) return T_Value(0); - auto it = m_deque.cbegin(); - T_Value out{*it}; - ++it; - for (; it != m_deque.cend(); ++it) out *= *it; + if (m_deque.empty()) return T_Value(0); // The big three do it this way + T_Value out = T_Value(1); + for (const auto& i : m_deque) out *= i; return out; } template - T_Value r_product(Func with_func) const { - if (m_deque.empty()) return T_Value(0); - auto it = m_deque.cbegin(); + WithFuncReturnType r_product(Func with_func) const { + if (m_deque.empty()) return WithFuncReturnType(0); // The big three do it this way + WithFuncReturnType out = WithFuncReturnType(1); IData index = 0; - T_Value out{with_func(index, *it)}; - ++it; - ++index; - for (; it != m_deque.cend(); ++it) out *= with_func(index++, *it); + for (const auto& i : m_deque) out *= with_func(index++, i); return out; } T_Value r_and() const { - if (m_deque.empty()) return T_Value(0); - auto it = m_deque.cbegin(); - T_Value out{*it}; - ++it; - for (; it != m_deque.cend(); ++it) out &= *it; + if (m_deque.empty()) return T_Value(0); // The big three do it this way + T_Value out = ~T_Value(0); + for (const auto& i : m_deque) out &= i; return out; } template - T_Value r_and(Func with_func) const { - if (m_deque.empty()) return T_Value(0); - auto it = m_deque.cbegin(); + WithFuncReturnType r_and(Func with_func) const { + if (m_deque.empty()) return WithFuncReturnType(0); // The big three do it this way IData index = 0; - T_Value out{with_func(index, *it)}; - ++it; - ++index; - for (; it != m_deque.cend(); ++it) out &= with_func(index, *it); + WithFuncReturnType out = ~WithFuncReturnType(0); + for (const auto& i : m_deque) out &= with_func(index++, i); return out; } T_Value r_or() const { - T_Value out(0); // Type must have assignment operator + T_Value out = T_Value(0); for (const auto& i : m_deque) out |= i; return out; } template - T_Value r_or(Func with_func) const { - T_Value out(0); // Type must have assignment operator + WithFuncReturnType r_or(Func with_func) const { + WithFuncReturnType out = WithFuncReturnType(0); IData index = 0; for (const auto& i : m_deque) out |= with_func(index++, i); return out; } T_Value r_xor() const { - T_Value out(0); // Type must have assignment operator +#ifdef VERILATOR_BIG3_NULLARY_ARITHMETICS_QUIRKS + if (m_deque.empty()) return T_Value(0); +#endif + T_Value out = T_Value(0); for (const auto& i : m_deque) out ^= i; return out; } template - T_Value r_xor(Func with_func) const { - T_Value out(0); // Type must have assignment operator + WithFuncReturnType r_xor(Func with_func) const { + WithFuncReturnType out = WithFuncReturnType(0); IData index = 0; for (const auto& i : m_deque) out ^= with_func(index++, i); return out; @@ -921,6 +926,9 @@ private: public: using const_iterator = typename Map::const_iterator; + template + using WithFuncReturnType + = decltype(std::declval()(std::declval(), std::declval())); private: // MEMBERS @@ -1167,64 +1175,56 @@ public: return out; } template - T_Value r_sum(Func with_func) const { - T_Value out(0); // Type must have assignment operator + WithFuncReturnType r_sum(Func with_func) const { + WithFuncReturnType out = WithFuncReturnType(0); for (const auto& i : m_map) out += with_func(i.first, i.second); return out; } T_Value r_product() const { - if (m_map.empty()) return T_Value(0); - auto it = m_map.cbegin(); - T_Value out{it->second}; - ++it; - for (; it != m_map.cend(); ++it) out *= it->second; + if (m_map.empty()) return T_Value(0); // The big three do it this way + T_Value out = T_Value(1); + for (const auto& i : m_map) out *= i.second; return out; } template - T_Value r_product(Func with_func) const { - if (m_map.empty()) return T_Value(0); - auto it = m_map.cbegin(); - T_Value out{with_func(it->first, it->second)}; - ++it; - for (; it != m_map.cend(); ++it) out *= with_func(it->first, it->second); + WithFuncReturnType r_product(Func with_func) const { + if (m_map.empty()) return WithFuncReturnType(0); // The big three do it this way + WithFuncReturnType out = WithFuncReturnType(1); + for (const auto& i : m_map) out *= with_func(i.first, i.second); return out; } T_Value r_and() const { - if (m_map.empty()) return T_Value(0); - auto it = m_map.cbegin(); - T_Value out{it->second}; - ++it; - for (; it != m_map.cend(); ++it) out &= it->second; + if (m_map.empty()) return T_Value(0); // The big three do it this way + T_Value out = ~T_Value(0); + for (const auto& i : m_map) out &= i.second; return out; } template - T_Value r_and(Func with_func) const { - if (m_map.empty()) return T_Value(0); - auto it = m_map.cbegin(); - T_Value out{with_func(it->first, it->second)}; - ++it; - for (; it != m_map.cend(); ++it) out &= with_func(it->first, it->second); + WithFuncReturnType r_and(Func with_func) const { + if (m_map.empty()) return WithFuncReturnType(0); // The big three do it this way + WithFuncReturnType out = ~WithFuncReturnType(0); + for (const auto& i : m_map) out &= with_func(i.first, i.second); return out; } T_Value r_or() const { - T_Value out(0); // Type must have assignment operator + T_Value out = T_Value(0); for (const auto& i : m_map) out |= i.second; return out; } template T_Value r_or(Func with_func) const { - T_Value out(0); // Type must have assignment operator + T_Value out = T_Value(0); for (const auto& i : m_map) out |= with_func(i.first, i.second); return out; } T_Value r_xor() const { - T_Value out(0); // Type must have assignment operator + T_Value out = T_Value(0); for (const auto& i : m_map) out ^= i.second; return out; } template - T_Value r_xor(Func with_func) const { - T_Value out(0); // Type must have assignment operator + WithFuncReturnType r_xor(Func with_func) const { + WithFuncReturnType out = WithFuncReturnType(0); for (const auto& i : m_map) out ^= with_func(i.first, i.second); return out; } @@ -1312,6 +1312,43 @@ public: WData* data() { return &m_storage[0]; } const WData* data() const { return &m_storage[0]; } + std::size_t size() const { return T_Depth; } + // To fit C++14 + template + int find_length(int dimension, std::false_type) const { + return size(); + } + + template + int find_length(int dimension, std::true_type) const { + if (dimension == CurrentDimension) { + return size(); + } else { + return m_storage[0].template find_length(dimension); + } + } + + template + int find_length(int dimension) const { + return find_length(dimension, std::is_class{}); + } + + template + auto& find_element(const std::vector& indices, std::false_type) { + return m_storage[indices[CurrentDimension]]; + } + + template + auto& find_element(const std::vector& indices, std::true_type) { + return m_storage[indices[CurrentDimension]].template find_element( + indices); + } + + template + auto& find_element(const std::vector& indices) { + return find_element(indices, std::is_class{}); + } + T_Value& operator[](size_t index) { return m_storage[index]; } const T_Value& operator[](size_t index) const { return m_storage[index]; } @@ -1794,9 +1831,9 @@ public: struct VlNull final { operator bool() const { return false; } - bool operator==(void* ptr) const { return !ptr; } + bool operator==(const void* ptr) const { return !ptr; } }; -inline bool operator==(void* ptr, VlNull) { return !ptr; } +inline bool operator==(const void* ptr, VlNull) { return !ptr; } //=================================================================== // Verilog class reference container diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index fb6ea3fa8..9d45ae541 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -305,8 +305,22 @@ void VerilatedVcd::printIndent(int level_change) { } void VerilatedVcd::pushPrefix(const std::string& name, VerilatedTracePrefixType type) { - std::string newPrefix = m_prefixStack.back().first + name; + assert(!m_prefixStack.empty()); // Constructor makes an empty entry + std::string pname = name; + // An empty name means this is the root of a model created with name()=="". The + // tools get upset if we try to pass this as empty, so we put the signals under a + // new scope, but the signals further down will be peers, not children (as usual + // for name()!="") + // Terminate earlier $root? + if (m_prefixStack.back().second == VerilatedTracePrefixType::ROOTIO_MODULE) popPrefix(); + if (pname.empty()) { // Start new temporary root + pname = "$rootio"; // VCD names are not backslash escaped + m_prefixStack.emplace_back("", VerilatedTracePrefixType::ROOTIO_WRAPPER); + type = VerilatedTracePrefixType::ROOTIO_MODULE; + } + std::string newPrefix = m_prefixStack.back().first + pname; switch (type) { + case VerilatedTracePrefixType::ROOTIO_MODULE: case VerilatedTracePrefixType::SCOPE_MODULE: case VerilatedTracePrefixType::SCOPE_INTERFACE: case VerilatedTracePrefixType::STRUCT_PACKED: @@ -326,7 +340,9 @@ void VerilatedVcd::pushPrefix(const std::string& name, VerilatedTracePrefixType } void VerilatedVcd::popPrefix() { + assert(!m_prefixStack.empty()); switch (m_prefixStack.back().second) { + case VerilatedTracePrefixType::ROOTIO_MODULE: case VerilatedTracePrefixType::SCOPE_MODULE: case VerilatedTracePrefixType::SCOPE_INTERFACE: case VerilatedTracePrefixType::STRUCT_PACKED: @@ -338,7 +354,7 @@ void VerilatedVcd::popPrefix() { default: break; } m_prefixStack.pop_back(); - assert(!m_prefixStack.empty()); + assert(!m_prefixStack.empty()); // Always one left, the constructor's initial one } void VerilatedVcd::declare(uint32_t code, const char* name, const char* wirep, bool array, @@ -573,16 +589,11 @@ void VerilatedVcdBuffer::finishLine(uint32_t code, char* writep) { // so always inline them. VL_ATTR_ALWINLINE -void VerilatedVcdBuffer::emitEvent(uint32_t code, const VlEventBase* newval) { - const bool triggered = newval->isTriggered(); - // TODO : It seems that untriggered events are not filtered - // should be tested before this last step - if (triggered) { - // Don't prefetch suffix as it's a bit too late; - char* wp = m_writep; - *wp++ = '1'; - finishLine(code, wp); - } +void VerilatedVcdBuffer::emitEvent(uint32_t code) { + // Don't prefetch suffix as it's a bit too late; + char* wp = m_writep; + *wp++ = '1'; + finishLine(code, wp); } VL_ATTR_ALWINLINE diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index 82f222345..fffb4fab3 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -43,7 +43,7 @@ private: friend VerilatedVcdBuffer; // Give the buffer access to the private bits //========================================================================= - // VCD specific internals + // VCD-specific internals VerilatedVcdFile* m_filep; // File we're writing to bool m_fileNewed; // m_filep needs destruction @@ -214,7 +214,7 @@ class VerilatedVcdBuffer VL_NOT_FINAL { // Implementation of VerilatedTraceBuffer interface // Implementations of duck-typed methods for VerilatedTraceBuffer. These are // called from only one place (the full* methods), so always inline them. - VL_ATTR_ALWINLINE void emitEvent(uint32_t code, const VlEventBase* newval); + VL_ATTR_ALWINLINE void emitEvent(uint32_t code); VL_ATTR_ALWINLINE void emitBit(uint32_t code, CData newval); VL_ATTR_ALWINLINE void emitCData(uint32_t code, CData newval, int bits); VL_ATTR_ALWINLINE void emitSData(uint32_t code, SData newval, int bits); diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 7d6becb74..ed2009ecf 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -896,6 +896,9 @@ public: if (VL_LIKELY(it != s().m_futureCbs.cend())) return it->first.first; return ~0ULL; // maxquad } + static bool hasCbs(const uint32_t reason) VL_MT_UNSAFE_ONE { + return !s().m_cbCurrentLists[reason].empty(); + } static bool callCbs(const uint32_t reason) VL_MT_UNSAFE_ONE { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: callCbs reason=%u\n", reason);); assertOneCheck(); @@ -1056,6 +1059,10 @@ bool VerilatedVpi::callCbs(uint32_t reason) VL_MT_UNSAFE_ONE { return VerilatedVpiImp::callCbs(reason); } +bool VerilatedVpi::hasCbs(uint32_t reason) VL_MT_UNSAFE_ONE { + return VerilatedVpiImp::hasCbs(reason); +} + // Historical, before we had multiple kinds of timed callbacks void VerilatedVpi::callTimedCbs() VL_MT_UNSAFE_ONE { VerilatedVpiImp::callCbs(cbAfterDelay); } @@ -2468,7 +2475,7 @@ void vl_get_value(const VerilatedVar* varp, void* varDatap, p_vpi_value valuep, vl_strprintf(t_outDynamicStr, "%u", static_cast(*(reinterpret_cast(varDatap)))); } else if (varp->vltype() == VLVT_UINT64) { - vl_strprintf(t_outDynamicStr, "%llu", + vl_strprintf(t_outDynamicStr, "%llu", // lintok-format-ll static_cast(*(reinterpret_cast(varDatap)))); } valuep->value.str = const_cast(t_outDynamicStr.c_str()); @@ -2690,7 +2697,8 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ } else if (valuep->format == vpiDecStrVal) { char remainder[16]; unsigned long long val; - const int success = std::sscanf(valuep->value.str, "%30llu%15s", &val, remainder); + const int success = std::sscanf(valuep->value.str, "%30llu%15s", // lintok-format-ll + &val, remainder); if (success < 1) { VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Parsing failed for '%s' as value %s for %s", __func__, valuep->value.str, diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h index a8e525a6f..51727cb01 100644 --- a/include/verilated_vpi.h +++ b/include/verilated_vpi.h @@ -49,6 +49,9 @@ public: /// Call callbacks of arbitrary types. /// User wrapper code should call this from their main loops. static bool callCbs(uint32_t reason) VL_MT_UNSAFE_ONE; + /// Returns true if there are callbacks of the given reason registered. + /// User wrapper code should call this from their main loops. + static bool hasCbs(uint32_t reason) VL_MT_UNSAFE_ONE; /// Returns time of the next registered VPI callback, or /// ~(0ULL) if none are registered static QData cbNextDeadline() VL_MT_UNSAFE_ONE; diff --git a/include/verilatedos.h b/include/verilatedos.h index 1d3b0c90e..6cb83732f 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -200,6 +200,11 @@ // Comment tag that Function is pure (and thus also VL_MT_SAFE) #define VL_PURE VL_CLANG_ATTR(annotate("PURE")) +// Annotated function can be called only in MT_DISABLED context, i.e. either in a code unit +// compiled with VL_MT_DISABLED_CODE_UNIT preprocessor definition, or in the main thread. +#define VL_MT_DISABLED \ + VL_CLANG_ATTR(annotate("MT_DISABLED")) \ + VL_EXCLUDES(VlOs::MtScopeMutex::s_haveThreadScope) // Comment tag that function is threadsafe #define VL_MT_SAFE VL_CLANG_ATTR(annotate("MT_SAFE")) // Comment tag that function is threadsafe, only if @@ -216,7 +221,7 @@ // protected to make sure single-caller #define VL_MT_UNSAFE_ONE VL_CLANG_ATTR(annotate("MT_UNSAFE_ONE")) // Comment tag that function is entry point of parallelization -#define VL_MT_START VL_CLANG_ATTR(annotate("MT_START")) +#define VL_MT_START VL_CLANG_ATTR(annotate("MT_START")) VL_REQUIRES(VlOs::MtScopeMutex::s_haveThreadScope) #ifndef VL_NO_LEGACY # define VL_ULL(c) (c##ULL) // Add appropriate suffix to 64-bit constant (deprecated) @@ -463,8 +468,6 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() #define VL_VALUE_STRING_MAX_WORDS 64 ///< Max size in words of String conversion operation #endif -#define VL_VALUE_STRING_MAX_CHARS (VL_VALUE_STRING_MAX_WORDS * VL_EDATASIZE / VL_BYTESIZE) - //========================================================================= // Base macros @@ -588,9 +591,9 @@ static inline double VL_ROUND(double n) { #endif //========================================================================= -// Macros controlling target specific optimizations +// Macros controlling target-specific optimizations -// Define VL_PORTABLE_ONLY to disable all target specific optimizations +// Define VL_PORTABLE_ONLY to disable all target-specific optimizations #ifndef VL_PORTABLE_ONLY # ifdef __x86_64__ # define VL_X86_64 1 @@ -653,6 +656,14 @@ public: return (m_start == 0.0) ? 0.0 : gettime() - m_start; } }; + +// Used by clang's -fthread-safety, ensures that only one instance of V3ThreadScope +// is created at a time +class VL_CAPABILITY("mutex") MtScopeMutex final { +public: + static MtScopeMutex s_haveThreadScope; +}; + } //namespace VlOs //========================================================================= diff --git a/nodist/clang_check_attributes b/nodist/clang_check_attributes index 61ac3555c..34714de5b 100755 --- a/nodist/clang_check_attributes +++ b/nodist/clang_check_attributes @@ -48,9 +48,11 @@ def fully_qualified_name(node): if node.kind == CursorKind.TRANSLATION_UNIT: return [] res = fully_qualified_name(node.semantic_parent) + displayname = node.displayname + displayname = [displayname] if displayname else [] if res: - return res + ([node.displayname] if node.displayname else []) - return [node.displayname] if node.displayname else [] + return res + displayname + return displayname # Returns True, if `class_node` contains node @@ -106,9 +108,8 @@ class VlAnnotations: def is_mt_safe_call(self): return (not self.is_mt_unsafe_call() - and (self.mt_safe or self.mt_safe_postinit or self.pure - or self.requires or self.excludes or self.acquire - or self.release)) + and (self.mt_safe or self.mt_safe_postinit or self.pure or self.requires + or self.excludes or self.acquire or self.release)) def is_pure_call(self): return self.pure @@ -140,31 +141,32 @@ class VlAnnotations: result = VlAnnotations() for node in nodes: if node.kind == CursorKind.ANNOTATE_ATTR: - if node.displayname == "MT_START": + displayname = node.displayname + if displayname == "MT_START": result.mt_start = True - elif node.displayname == "MT_SAFE": + elif displayname == "MT_SAFE": result.mt_safe = True - elif node.displayname == "MT_STABLE": + elif displayname == "MT_STABLE": result.stable_tree = True - elif node.displayname == "MT_SAFE_POSTINIT": + elif displayname == "MT_SAFE_POSTINIT": result.mt_safe_postinit = True - elif node.displayname == "MT_UNSAFE": + elif displayname == "MT_UNSAFE": result.mt_unsafe = True - elif node.displayname == "MT_UNSAFE_ONE": + elif displayname == "MT_UNSAFE_ONE": result.mt_unsafe_one = True - elif node.displayname == "MT_DISABLED": + elif displayname == "MT_DISABLED": result.mt_disabled = True - elif node.displayname == "PURE": + elif displayname == "PURE": result.pure = True - elif node.displayname in ["ACQUIRE", "ACQUIRE_SHARED"]: + elif displayname in ["ACQUIRE", "ACQUIRE_SHARED"]: result.acquire = True - elif node.displayname in ["RELEASE", "RELEASE_SHARED"]: + elif displayname in ["RELEASE", "RELEASE_SHARED"]: result.release = True - elif node.displayname == "REQUIRES": + elif displayname == "REQUIRES": result.requires = True - elif node.displayname in ["EXCLUDES", "MT_SAFE_EXCLUDES"]: + elif displayname in ["EXCLUDES", "MT_SAFE_EXCLUDES"]: result.excludes = True - elif node.displayname == "GUARDED_BY": + elif displayname == "GUARDED_BY": result.guarded = True # Attributes are always at the beginning elif not node.kind.is_attribute(): @@ -203,9 +205,7 @@ class FunctionInfo: annotations: VlAnnotations ftype: FunctionType - _hash: Optional[int] = dataclasses.field(default=None, - init=False, - repr=False) + _hash: Optional[int] = dataclasses.field(default=None, init=False, repr=False) @property def name(self): @@ -220,15 +220,13 @@ class FunctionInfo: return self._hash def __eq__(self, other): - return (self.usr == other.usr and self.file == other.file - and self.line == other.line) + return (self.usr == other.usr and self.file == other.file and self.line == other.line) def copy(self, /, **changes): return dataclasses.replace(self, **changes) @staticmethod - def from_decl_file_line_and_refd_node(file: str, line: int, - refd: clang.cindex.Cursor, + def from_decl_file_line_and_refd_node(file: str, line: int, refd: clang.cindex.Cursor, annotations: VlAnnotations): file = os.path.abspath(file) refd = refd.canonical @@ -277,14 +275,11 @@ class Diagnostic: source_ctx: FunctionInfo kind: DiagnosticKind - _hash: Optional[int] = dataclasses.field(default=None, - init=False, - repr=False) + _hash: Optional[int] = dataclasses.field(default=None, init=False, repr=False) def __hash__(self): if not self._hash: - self._hash = hash( - hash(self.target) ^ hash(self.source_ctx) ^ hash(self.kind)) + self._hash = hash(hash(self.target) ^ hash(self.source_ctx) ^ hash(self.kind)) return self._hash @@ -292,9 +287,9 @@ class CallAnnotationsValidator: def __init__(self, diagnostic_cb: Callable[[Diagnostic], None], is_ignored_top_level: Callable[[clang.cindex.Cursor], bool], - is_ignored_def: Callable[ - [clang.cindex.Cursor, clang.cindex.Cursor], bool], - is_ignored_call: Callable[[clang.cindex.Cursor], bool]): + is_ignored_def: Callable[[clang.cindex.Cursor, clang.cindex.Cursor], + bool], is_ignored_call: Callable[[clang.cindex.Cursor], + bool]): self._diagnostic_cb = diagnostic_cb self._is_ignored_top_level = is_ignored_top_level self._is_ignored_call = is_ignored_call @@ -312,6 +307,7 @@ class CallAnnotationsValidator: self._defines: dict[str, str] = {} self._call_location: Optional[FunctionInfo] = None self._caller: Optional[FunctionInfo] = None + self._base_func_declarations: dict[str, clang.cindex.Cursor] = {} self._constructor_context: list[clang.cindex.Cursor] = [] self._level: int = 0 @@ -329,8 +325,7 @@ class CallAnnotationsValidator: with open(source_file, "r", encoding="utf-8") as file: for line in file: line = line.strip() - match = re.fullmatch( - r"^#\s*(define\s+(\w+)(?:\s+(.*))?|include\s+.*)$", line) + match = re.fullmatch(r"^#\s*(define\s+(\w+)(?:\s+(.*))?|include\s+.*)$", line) if match: if match.group(1).startswith("define"): key = match.group(2) @@ -341,16 +336,14 @@ class CallAnnotationsValidator: return defs @staticmethod - def filter_out_unsupported_compiler_args( - args: list[str]) -> tuple[list[str], dict[str, str]]: + def filter_out_unsupported_compiler_args(args: list[str]) -> tuple[list[str], dict[str, str]]: filtered_args = [] defines = {} args_iter = iter(args) try: while arg := next(args_iter): # Skip positional arguments (input file name). - if not arg.startswith("-") and (arg.endswith(".cpp") - or arg.endswith(".c") + if not arg.startswith("-") and (arg.endswith(".cpp") or arg.endswith(".c") or arg.endswith(".h")): continue @@ -367,8 +360,7 @@ class CallAnnotationsValidator: # Preserved options with separate value argument. if arg in [ "-x" - "-Xclang", "-I", "-isystem", "-iquote", "-include", - "-include-pch" + "-Xclang", "-I", "-isystem", "-iquote", "-include", "-include-pch" ]: filtered_args += [arg, next(args_iter)] continue @@ -406,14 +398,12 @@ class CallAnnotationsValidator: return (filtered_args, defines) - def compile_and_analyze_file(self, source_file: str, - compiler_args: list[str], + def compile_and_analyze_file(self, source_file: str, compiler_args: list[str], build_dir: Optional[str]): filename = os.path.abspath(source_file) initial_cwd = "." - filtered_args, defines = self.filter_out_unsupported_compiler_args( - compiler_args) + filtered_args, defines = self.filter_out_unsupported_compiler_args(compiler_args) defines.update(self.parse_initial_defines(source_file)) if build_dir: @@ -451,8 +441,7 @@ class CallAnnotationsValidator: self._diagnostic_cb(Diagnostic(target, source, source_ctx, kind)) else: self._diagnostic_cb( - Diagnostic(FunctionInfo.from_node(target), source, source_ctx, - kind)) + Diagnostic(FunctionInfo.from_node(target), source, source_ctx, kind)) def iterate_children(self, children: Iterable[clang.cindex.Cursor], handler: Callable[[clang.cindex.Cursor], None]): @@ -465,8 +454,7 @@ class CallAnnotationsValidator: @staticmethod def get_referenced_node_info( node: clang.cindex.Cursor - ) -> tuple[bool, Optional[clang.cindex.Cursor], VlAnnotations, - Iterable[clang.cindex.Cursor]]: + ) -> tuple[bool, Optional[clang.cindex.Cursor], VlAnnotations, Iterable[clang.cindex.Cursor]]: if not node.spelling and not node.displayname: return (False, None, VlAnnotations(), []) @@ -480,8 +468,7 @@ class CallAnnotationsValidator: annotations = VlAnnotations.from_nodes_list(children) return (True, refd, annotations, children) - def check_mt_safe_call(self, node: clang.cindex.Cursor, - refd: clang.cindex.Cursor, + def check_mt_safe_call(self, node: clang.cindex.Cursor, refd: clang.cindex.Cursor, annotations: VlAnnotations): is_mt_safe = False @@ -513,8 +500,7 @@ class CallAnnotationsValidator: # we are calling local method. It is MT safe # only if this method is also only calling local methods or # MT-safe methods - self.iterate_children(refd.get_children(), - self.dispatch_node_inside_definition) + self.iterate_children(refd.get_children(), self.dispatch_node_inside_definition) is_mt_safe = True # class/struct member elif refn and refn.kind == CursorKind.MEMBER_REF_EXPR and refn.referenced: @@ -525,18 +511,15 @@ class CallAnnotationsValidator: if self.is_constructor_context() and refn.semantic_parent: # we are in constructor, so calling local members is MT_SAFE, # make sure object that we are calling is local to the constructor - constructor_class = self._constructor_context[ - -1].semantic_parent + constructor_class = self._constructor_context[-1].semantic_parent if refn.semantic_parent.spelling == constructor_class.spelling: if check_class_member_exists(constructor_class, refn): is_mt_safe = True else: # check if this class inherits from some base class - base_class = get_base_class(constructor_class, - refn.semantic_parent) + base_class = get_base_class(constructor_class, refn.semantic_parent) if base_class: - if check_class_member_exists( - base_class.get_declaration(), refn): + if check_class_member_exists(base_class.get_declaration(), refn): is_mt_safe = True # variable elif refn and refn.kind == CursorKind.DECL_REF_EXPR and refn.referenced: @@ -567,8 +550,7 @@ class CallAnnotationsValidator: # Call handling - def process_method_call(self, node: clang.cindex.Cursor, - refd: clang.cindex.Cursor, + def process_method_call(self, node: clang.cindex.Cursor, refd: clang.cindex.Cursor, annotations: VlAnnotations): assert self._call_location ctx = self._call_location.annotations @@ -576,58 +558,48 @@ class CallAnnotationsValidator: # MT-safe context if ctx.is_mt_safe_context(): if not self.check_mt_safe_call(node, refd, annotations): - self.emit_diagnostic( - FunctionInfo.from_node(refd, refd, annotations), - DiagnosticKind.NON_MT_SAFE_CALL_IN_MT_SAFE_CTX) + self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), + DiagnosticKind.NON_MT_SAFE_CALL_IN_MT_SAFE_CTX) # stable tree context if ctx.is_stabe_tree_context(): if annotations.is_mt_unsafe_call() or not ( - annotations.is_stabe_tree_call() - or annotations.is_pure_call() + annotations.is_stabe_tree_call() or annotations.is_pure_call() or self.check_mt_safe_call(node, refd, annotations)): - self.emit_diagnostic( - FunctionInfo.from_node(refd, refd, annotations), - DiagnosticKind.NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX) + self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), + DiagnosticKind.NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX) # pure context if ctx.is_pure_context(): if not annotations.is_pure_call(): - self.emit_diagnostic( - FunctionInfo.from_node(refd, refd, annotations), - DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) + self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), + DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) - def process_function_call(self, refd: clang.cindex.Cursor, - annotations: VlAnnotations): + def process_function_call(self, refd: clang.cindex.Cursor, annotations: VlAnnotations): assert self._call_location ctx = self._call_location.annotations # MT-safe context if ctx.is_mt_safe_context(): if not annotations.is_mt_safe_call(): - self.emit_diagnostic( - FunctionInfo.from_node(refd, refd, annotations), - DiagnosticKind.NON_MT_SAFE_CALL_IN_MT_SAFE_CTX) + self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), + DiagnosticKind.NON_MT_SAFE_CALL_IN_MT_SAFE_CTX) # stable tree context if ctx.is_stabe_tree_context(): - if annotations.is_mt_unsafe_call() or not ( - annotations.is_pure_call() - or annotations.is_mt_safe_call() - or annotations.is_stabe_tree_call()): - self.emit_diagnostic( - FunctionInfo.from_node(refd, refd, annotations), - DiagnosticKind.NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX) + if annotations.is_mt_unsafe_call() or not (annotations.is_pure_call() + or annotations.is_mt_safe_call() + or annotations.is_stabe_tree_call()): + self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), + DiagnosticKind.NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX) # pure context if ctx.is_pure_context(): if not annotations.is_pure_call(): - self.emit_diagnostic( - FunctionInfo.from_node(refd, refd, annotations), - DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) + self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), + DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) - def process_constructor_call(self, refd: clang.cindex.Cursor, - annotations: VlAnnotations): + def process_constructor_call(self, refd: clang.cindex.Cursor, annotations: VlAnnotations): assert self._call_location ctx = self._call_location.annotations @@ -635,31 +607,26 @@ class CallAnnotationsValidator: # only if they call local methods or MT-safe functions. if ctx.is_mt_safe_context() or self.is_constructor_context(): self._constructor_context.append(refd) - self.iterate_children(refd.get_children(), - self.dispatch_node_inside_definition) + self.iterate_children(refd.get_children(), self.dispatch_node_inside_definition) self._constructor_context.pop() # stable tree context if ctx.is_stabe_tree_context(): self._constructor_context.append(refd) - self.iterate_children(refd.get_children(), - self.dispatch_node_inside_definition) + self.iterate_children(refd.get_children(), self.dispatch_node_inside_definition) self._constructor_context.pop() # pure context if ctx.is_pure_context(): - if not annotations.is_pure_call( - ) and not refd.is_default_constructor(): - self.emit_diagnostic( - FunctionInfo.from_node(refd, refd, annotations), - DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) + if not annotations.is_pure_call() and not refd.is_default_constructor(): + self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), + DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) def dispatch_call_node(self, node: clang.cindex.Cursor): [supported, refd, annotations, _] = self.get_referenced_node_info(node) if not supported: - self.iterate_children(node.get_children(), - self.dispatch_node_inside_definition) + self.iterate_children(node.get_children(), self.dispatch_node_inside_definition) return True assert refd is not None @@ -676,19 +643,14 @@ class CallAnnotationsValidator: assert self._call_location is not None node_file = os.path.abspath(node.location.file.name) - self._call_location = self._call_location.copy(file=node_file, - line=node.location.line) + self._call_location = self._call_location.copy(file=node_file, line=node.location.line) # Standalone functions and static class methods if (refd.kind == CursorKind.FUNCTION_DECL - or refd.kind == CursorKind.CXX_METHOD - and refd.is_static_method()): + or refd.kind == CursorKind.CXX_METHOD and refd.is_static_method()): self.process_function_call(refd, annotations) # Function pointer - elif refd.kind in [ - CursorKind.VAR_DECL, CursorKind.FIELD_DECL, - CursorKind.PARM_DECL - ]: + elif refd.kind in [CursorKind.VAR_DECL, CursorKind.FIELD_DECL, CursorKind.PARM_DECL]: self.process_function_call(refd, annotations) # Non-static class methods elif refd.kind == CursorKind.CXX_METHOD: @@ -726,18 +688,25 @@ class CallAnnotationsValidator: if self.dispatch_call_node(node) is False: return None elif node.is_definition() and node.kind in [ - CursorKind.CXX_METHOD, CursorKind.FUNCTION_DECL, - CursorKind.CONSTRUCTOR, CursorKind.CONVERSION_FUNCTION + CursorKind.CXX_METHOD, CursorKind.FUNCTION_DECL, CursorKind.CONSTRUCTOR, + CursorKind.CONVERSION_FUNCTION ]: self.process_function_definition(node) return None - return self.iterate_children(node.get_children(), - self.dispatch_node_inside_definition) + return self.iterate_children(node.get_children(), self.dispatch_node_inside_definition) def process_function_definition(self, node: clang.cindex.Cursor): [supported, refd, annotations, _] = self.get_referenced_node_info(node) + # Fetch virtual annotations from base class. + # Set refd to virtual definition if present. + signature = node.displayname + if signature in self._base_func_declarations: + refd = self._base_func_declarations[signature] + virtual_annotations = VlAnnotations.from_nodes_list(refd.get_children()) + annotations = annotations | virtual_annotations + if refd and self._is_ignored_def(node, refd): return None @@ -752,30 +721,29 @@ class CallAnnotationsValidator: # Implicitly mark definitions in VL_MT_DISABLED_CODE_UNIT .cpp files as # VL_MT_DISABLED. Existence of the annotation on declarations in .h # files is verified below. - # Also sets VL_REQUIRES, as this annotation is added together with + # Also sets VL_EXCLUDES, as this annotation is added together with # explicit VL_MT_DISABLED. if self.is_mt_disabled_code_unit(): if node.location.file.name == self._main_source_file: annotations.mt_disabled = True - annotations.requires = True + annotations.excludes = True if refd.location.file.name == self._main_source_file: def_annotations.mt_disabled = True - def_annotations.requires = True + def_annotations.excludes = True - if not (def_annotations.is_empty() or def_annotations == annotations): + if def_annotations != annotations: # Use definition's annotations for the diagnostic # source (i.e. the definition) self._caller = FunctionInfo.from_node(node, refd, def_annotations) self._call_location = self._caller - self.emit_diagnostic( - FunctionInfo.from_node(refd, refd, annotations), - DiagnosticKind.ANNOTATIONS_DEF_DECL_MISMATCH) + self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), + DiagnosticKind.ANNOTATIONS_DEF_DECL_MISMATCH) - # Use concatenation of definition and declaration annotations - # for calls validation. - self._caller = FunctionInfo.from_node(node, refd, - def_annotations | annotations) + else: + # Use concatenation of definition and declaration annotations + # for calls validation. + self._caller = FunctionInfo.from_node(node, refd, def_annotations | annotations) prev_call_location = self._call_location self._call_location = self._caller @@ -793,8 +761,7 @@ class CallAnnotationsValidator: if declarations: del self._external_decls[usr] - self.iterate_children(node_children, - self.dispatch_node_inside_definition) + self.iterate_children(node_children, self.dispatch_node_inside_definition) self._call_location = prev_call_location self._caller = prev_call_location @@ -804,25 +771,37 @@ class CallAnnotationsValidator: # Nodes not located inside definition def dispatch_node(self, node: clang.cindex.Cursor): - if node.kind in [ - CursorKind.CXX_METHOD, CursorKind.FUNCTION_DECL, - CursorKind.CONSTRUCTOR, CursorKind.CONVERSION_FUNCTION + kind = node.kind + if kind is CursorKind.CXX_BASE_SPECIFIER: + # Get referenced virtual declarations from base class. + for base in node.get_children(): + if base.referenced: + for declaration in base.referenced.get_children(): + self._base_func_declarations[declaration.displayname] = declaration + elif kind in [ + CursorKind.CXX_METHOD, CursorKind.FUNCTION_DECL, CursorKind.CONSTRUCTOR, + CursorKind.CONVERSION_FUNCTION ]: if node.is_definition(): return self.process_function_definition(node) - # else: return self.process_function_declaration(node) - return self.iterate_children(node.get_children(), self.dispatch_node) + result = self.iterate_children(node.get_children(), self.dispatch_node) - def process_translation_unit( - self, translation_unit: clang.cindex.TranslationUnit): + # Clean declarations if class declaration processing is finished. + if kind in [ + CursorKind.CLASS_DECL, CursorKind.STRUCT_DECL, CursorKind.UNION_DECL, + CursorKind.ENUM_DECL, CursorKind.UNEXPOSED_DECL + ]: + self._base_func_declarations = {} + return result + + def process_translation_unit(self, translation_unit: clang.cindex.TranslationUnit): self._level += 1 kv_defines = sorted([f"{k}={v}" for k, v in self._defines.items()]) concat_defines = '\n'.join(kv_defines) # List of headers already processed in a TU with specified set of defines. - tu_processed_headers = self._processed_headers.setdefault( - concat_defines, set()) + tu_processed_headers = self._processed_headers.setdefault(concat_defines, set()) for child in translation_unit.cursor.get_children(): if self._is_ignored_top_level(child): continue @@ -833,10 +812,8 @@ class CallAnnotationsValidator: self.dispatch_node(child) self._level -= 1 - tu_processed_headers.update([ - os.path.abspath(str(hdr.source)) - for hdr in translation_unit.get_includes() - ]) + tu_processed_headers.update( + [os.path.abspath(str(hdr.source)) for hdr in translation_unit.get_includes()]) @dataclass @@ -857,8 +834,7 @@ def get_filter_funcs(verilator_root: str): filename = os.path.abspath(node.location.file.name) return not filename.startswith(verilator_root) - def is_ignored_def(node: clang.cindex.Cursor, - refd: clang.cindex.Cursor) -> bool: + def is_ignored_def(node: clang.cindex.Cursor, refd: clang.cindex.Cursor) -> bool: # __* if str(refd.spelling).startswith("__"): return True @@ -901,8 +877,7 @@ def precompile_header(compile_command: CompileCommand, tmp_dir: str) -> str: os.chdir(compile_command.directory) index = Index.create() - translation_unit = index.parse(compile_command.filename, - compile_command.args) + translation_unit = index.parse(compile_command.filename, compile_command.args) for diag in translation_unit.diagnostics: if diag.severity >= clang.cindex.Diagnostic.Error: errors.append(str(diag)) @@ -910,23 +885,20 @@ def precompile_header(compile_command: CompileCommand, tmp_dir: str) -> str: if len(errors) == 0: pch_file = os.path.join( tmp_dir, - f"{compile_command.refid:02}_{os.path.basename(compile_command.filename)}.pch" - ) + f"{compile_command.refid:02}_{os.path.basename(compile_command.filename)}.pch") translation_unit.save(pch_file) if pch_file: return pch_file - except (TranslationUnitSaveError, TranslationUnitLoadError, - OSError) as exception: + except (TranslationUnitSaveError, TranslationUnitLoadError, OSError) as exception: print(f"%Warning: {exception}", file=sys.stderr) finally: os.chdir(initial_cwd) - print( - f"%Warning: Precompilation failed, skipping: {compile_command.filename}", - file=sys.stderr) + print(f"%Warning: Precompilation failed, skipping: {compile_command.filename}", + file=sys.stderr) for error in errors: print(f" {error}", file=sys.stderr) return "" @@ -934,10 +906,8 @@ def precompile_header(compile_command: CompileCommand, tmp_dir: str) -> str: # Compile and analyze inputs in a single process. def run_analysis(ccl: Iterable[CompileCommand], pccl: Iterable[CompileCommand], - diagnostic_cb: Callable[[Diagnostic], - None], verilator_root: str): - (is_ignored_top_level, is_ignored_def, - is_ignored_call) = get_filter_funcs(verilator_root) + diagnostic_cb: Callable[[Diagnostic], None], verilator_root: str): + (is_ignored_top_level, is_ignored_def, is_ignored_call) = get_filter_funcs(verilator_root) prefix = "verilator_clang_check_attributes_" with tempfile.TemporaryDirectory(prefix=prefix) as tmp_dir: @@ -947,8 +917,8 @@ def run_analysis(ccl: Iterable[CompileCommand], pccl: Iterable[CompileCommand], if pch_file: extra_args += ["-include-pch", pch_file] - cav = CallAnnotationsValidator(diagnostic_cb, is_ignored_top_level, - is_ignored_def, is_ignored_call) + cav = CallAnnotationsValidator(diagnostic_cb, is_ignored_top_level, is_ignored_def, + is_ignored_call) for compile_command in ccl: cav.compile_and_analyze_file(compile_command.filename, extra_args + compile_command.args, @@ -963,12 +933,11 @@ class ParallelAnalysisProcess: @staticmethod def init_data(verilator_root: str, tmp_dir: str): - (is_ignored_top_level, is_ignored_def, - is_ignored_call) = get_filter_funcs(verilator_root) + (is_ignored_top_level, is_ignored_def, is_ignored_call) = get_filter_funcs(verilator_root) ParallelAnalysisProcess.cav = CallAnnotationsValidator( - ParallelAnalysisProcess._diagnostic_handler, is_ignored_top_level, - is_ignored_def, is_ignored_call) + ParallelAnalysisProcess._diagnostic_handler, is_ignored_top_level, is_ignored_def, + is_ignored_call) ParallelAnalysisProcess.tmp_dir = tmp_dir @staticmethod @@ -979,31 +948,27 @@ class ParallelAnalysisProcess: def analyze_cpp_file(compile_command: CompileCommand) -> set[Diagnostic]: ParallelAnalysisProcess.diags = set() assert ParallelAnalysisProcess.cav is not None - ParallelAnalysisProcess.cav.compile_and_analyze_file( - compile_command.filename, compile_command.args, - compile_command.directory) + ParallelAnalysisProcess.cav.compile_and_analyze_file(compile_command.filename, + compile_command.args, + compile_command.directory) return ParallelAnalysisProcess.diags @staticmethod def precompile_header(compile_command: CompileCommand) -> str: - return precompile_header(compile_command, - ParallelAnalysisProcess.tmp_dir) + return precompile_header(compile_command, ParallelAnalysisProcess.tmp_dir) # Compile and analyze inputs in multiple processes. -def run_parallel_analysis(ccl: Iterable[CompileCommand], - pccl: Iterable[CompileCommand], - diagnostic_cb: Callable[[Diagnostic], None], - jobs_count: int, verilator_root: str): +def run_parallel_analysis(ccl: Iterable[CompileCommand], pccl: Iterable[CompileCommand], + diagnostic_cb: Callable[[Diagnostic], + None], jobs_count: int, verilator_root: str): prefix = "verilator_clang_check_attributes_" with tempfile.TemporaryDirectory(prefix=prefix) as tmp_dir: - with multiprocessing.Pool( - processes=jobs_count, - initializer=ParallelAnalysisProcess.init_data, - initargs=[verilator_root, tmp_dir]) as pool: + with multiprocessing.Pool(processes=jobs_count, + initializer=ParallelAnalysisProcess.init_data, + initargs=[verilator_root, tmp_dir]) as pool: extra_args = [] - for pch_file in pool.imap_unordered( - ParallelAnalysisProcess.precompile_header, pccl): + for pch_file in pool.imap_unordered(ParallelAnalysisProcess.precompile_header, pccl): if pch_file: extra_args += ["-include-pch", pch_file] @@ -1011,8 +976,7 @@ def run_parallel_analysis(ccl: Iterable[CompileCommand], for compile_command in ccl: compile_command.args = compile_command.args + extra_args - for diags in pool.imap_unordered( - ParallelAnalysisProcess.analyze_cpp_file, ccl, 1): + for diags in pool.imap_unordered(ParallelAnalysisProcess.analyze_cpp_file, ccl, 1): for diag in diags: diagnostic_cb(diag) @@ -1057,8 +1021,7 @@ class TopDownSummaryPrinter(): row_groups: dict[str, list[list[str]]] = {} column_widths = [0, 0] for func in sorted(self._funcs.values(), - key=lambda func: - (func.info.file, func.info.line, func.info.usr)): + key=lambda func: (func.info.file, func.info.line, func.info.usr)): func_info = func.info relfile = os.path.relpath(func_info.file, root_dir) @@ -1082,31 +1045,23 @@ class TopDownSummaryPrinter(): if func.mismatch: mrelfile = os.path.relpath(func.mismatch.file, root_dir) row_group.append([ - f"{mrelfile}:{func.mismatch.line}:", - f"[{func.mismatch.annotations}]", + f"{mrelfile}:{func.mismatch.line}:", f"[{func.mismatch.annotations}]", func.mismatch.name + " [declaration]" ]) - row_group.append([ - f"{relfile}:{func_info.line}:", f"[{func_info.annotations}]", - func_info.name - ]) + row_group.append( + [f"{relfile}:{func_info.line}:", f"[{func_info.annotations}]", func_info.name]) - for callee in sorted(func.calees, - key=lambda func: - (func.file, func.line, func.usr)): + for callee in sorted(func.calees, key=lambda func: (func.file, func.line, func.usr)): crelfile = os.path.relpath(callee.file, root_dir) - row_group.append([ - f"{crelfile}:{callee.line}:", f"[{callee.annotations}]", - " " + callee.name - ]) + row_group.append( + [f"{crelfile}:{callee.line}:", f"[{callee.annotations}]", " " + callee.name]) row_groups[name] = row_group for row in row_group: for row_id, value in enumerate(row[0:-1]): - column_widths[row_id] = max(column_widths[row_id], - len(value)) + column_widths[row_id] = max(column_widths[row_id], len(value)) for label, rows in sorted(row_groups.items(), key=lambda kv: kv[0]): self.begin_group(label) @@ -1114,21 +1069,17 @@ class TopDownSummaryPrinter(): print(f"{row[0]:<{column_widths[0]}} " f"{row[1]:<{column_widths[1]}} " f"{row[2]}") - print( - f"Number of functions reported unsafe: {len(self._unsafe_in_safe)}" - ) + print(f"Number of functions reported unsafe: {len(self._unsafe_in_safe)}") def main(): - default_verilator_root = os.path.abspath( - os.path.join(os.path.dirname(__file__), "..")) + default_verilator_root = os.path.abspath(os.path.join(os.path.dirname(__file__), "..")) parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Check function annotations for correctness""", - epilog= - """Copyright 2022-2024 by Wilson Snyder. Verilator is free software; + epilog="""Copyright 2022-2024 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Apache License 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Apache-2.0""") @@ -1142,29 +1093,23 @@ def main(): type=int, default=0, help="Number of parallel jobs to use.") - parser.add_argument( - "--compile-commands-dir", - type=str, - default=None, - help="Path to directory containing compile_commands.json.") + parser.add_argument("--compile-commands-dir", + type=str, + default=None, + help="Path to directory containing compile_commands.json.") parser.add_argument("--cxxflags", type=str, default=None, help="Extra flags passed to clang++.") - parser.add_argument( - "--compilation-root", - type=str, - default=os.getcwd(), - help="Directory used as CWD when compiling source files.") - parser.add_argument( - "-c", - "--precompile", - action="append", - help="Header file to be precompiled and cached at the start.") - parser.add_argument("file", + parser.add_argument("--compilation-root", type=str, - nargs="+", - help="Source file to analyze.") + default=os.getcwd(), + help="Directory used as CWD when compiling source files.") + parser.add_argument("-c", + "--precompile", + action="append", + help="Header file to be precompiled and cached at the start.") + parser.add_argument("file", type=str, nargs="+", help="Source file to analyze.") cmdline = parser.parse_args() @@ -1179,8 +1124,7 @@ def main(): compdb: Optional[CompilationDatabase] = None if cmdline.compile_commands_dir: - compdb = CompilationDatabase.fromDirectory( - cmdline.compile_commands_dir) + compdb = CompilationDatabase.fromDirectory(cmdline.compile_commands_dir) if cmdline.cxxflags is not None: common_cxxflags = shlex.split(cmdline.cxxflags) @@ -1230,8 +1174,7 @@ def main(): summary_printer.handle_diagnostic, verilator_root) else: run_parallel_analysis(compile_commands_list, precompile_commands_list, - summary_printer.handle_diagnostic, cmdline.jobs, - verilator_root) + summary_printer.handle_diagnostic, cmdline.jobs, verilator_root) summary_printer.print_summary(verilator_root) diff --git a/nodist/code_coverage b/nodist/code_coverage index 87534b0b7..2b9a59fb9 100755 --- a/nodist/code_coverage +++ b/nodist/code_coverage @@ -58,15 +58,12 @@ def test(): if not Args.scenarios or re.match('dist', Args.scenarios): run("make examples VERILATOR_NO_OPT_BUILD=1") run("make test_regress VERILATOR_NO_OPT_BUILD=1" + - (" SCENARIOS='" + Args.scenarios + - "'" if Args.scenarios else "") + - (" DRIVER_HASHSET='--hashset=" + Args.hashset + - "'" if Args.hashset else "") + + (" SCENARIOS='" + Args.scenarios + "'" if Args.scenarios else "") + + (" DRIVER_HASHSET='--hashset=" + Args.hashset + "'" if Args.hashset else "") + ('' if Args.stop else ' || true')) else: for test in Args.tests: - if not os.path.exists(test) and os.path.exists( - "test_regress/t/" + test): + if not os.path.exists(test) and os.path.exists("test_regress/t/" + test): test = "test_regress/t/" + test run(test) ci_fold_end() @@ -78,8 +75,7 @@ def test(): os.makedirs(cc_dir, exist_ok=True) os.makedirs(cc_dir + "/info", exist_ok=True) - with subprocess.Popen("find . -print | grep .gcda", - shell=True, + with subprocess.Popen("find . -print | grep .gcda", shell=True, stdout=subprocess.PIPE) as sp: datout = sp.stdout.read() @@ -98,8 +94,7 @@ def test(): del dats[dat] break - with subprocess.Popen("find . -print | grep .gcno", - shell=True, + with subprocess.Popen("find . -print | grep .gcno", shell=True, stdout=subprocess.PIPE) as sp: datout = sp.stdout.read() @@ -116,8 +111,7 @@ def test(): if gbase in gcnos: os.symlink(gcnos[gbase], gcno) else: - print("MISSING .gcno for a .gcda: " + gcno, - file=sys.stderr) + print("MISSING .gcno for a .gcda: " + gcno, file=sys.stderr) ci_fold_end() if Args.stage_enabled[5]: @@ -142,8 +136,7 @@ def test(): if Args.stage_enabled[11]: ci_fold_start("dirs") print("Stage 11: Cleanup paths") - cleanup_abs_paths_info(cc_dir, cc_dir + "/app_total.info", - cc_dir + "/app_total.info") + cleanup_abs_paths_info(cc_dir, cc_dir + "/app_total.info", cc_dir + "/app_total.info") ci_fold_end() if Args.stage_enabled[12]: @@ -164,17 +157,15 @@ def test(): inc = "--include " + inc if exc != '': exc = "--exclude " + exc - run("cd " + cc_dir + " ; " + RealPath + - "/fastcov.py -C app_total.info " + inc + " " + exc + - " -x --lcov -o app_total_f.info") + run("cd " + cc_dir + " ; " + RealPath + "/fastcov.py -C app_total.info " + inc + " " + + exc + " -x --lcov -o app_total_f.info") ci_fold_end() if Args.stage_enabled[17]: ci_fold_start("report") print("Stage 17: Create HTML") run("cd " + cc_dir + " ; genhtml app_total_f.info --demangle-cpp" + - " --rc lcov_branch_coverage=1 --rc genhtml_hi_limit=100 --output-directory html" - ) + " --rc lcov_branch_coverage=1 --rc genhtml_hi_limit=100 --output-directory html") ci_fold_end() if Args.stage_enabled[18]: @@ -186,8 +177,7 @@ def test(): # So, remove gcno files before calling codecov upload_dir = "nodist/obj_dir/upload" os.makedirs(upload_dir, exist_ok=True) - cmd = ("ci/codecov -v upload-process -Z" + " -f " + cc_dir + - "/app_total.info )") + cmd = "ci/codecov -v upload-process -Z" + " -f " + cc_dir + "/app_total.info )" print("print: Not running:") print(" export CODECOV_TOKEN=") print(" find . -name '*.gcno' -exec rm {} \\;") @@ -198,9 +188,7 @@ def test(): print("*-* All Finished *-*") print("") print("* See report in " + cc_dir + "/html/index.html") - print( - "* Remember to make distclean && ./configure before working on non-coverage" - ) + print("* Remember to make distclean && ./configure before working on non-coverage") def clone_sources(cc_dir): @@ -209,9 +197,8 @@ def clone_sources(cc_dir): for globf in Source_Globs: for infile in glob.glob(globf): if re.match(r'^/', infile): - sys.exit( - "%Error: source globs should be relative not absolute filenames, " - + infile) + sys.exit("%Error: source globs should be relative not absolute filenames, " + + infile) outfile = cc_dir + "/" + infile outpath = re.sub(r'/[^/]*$', '', outfile, count=1) os.makedirs(outpath, exist_ok=True) @@ -252,10 +239,8 @@ def clone_sources(cc_dir): done = True ofh.write(line + "\n") - print("Number of source lines automatically LCOV_EXCL_LINE'ed: %d" % - excluded_lines) - print("Number of source lines automatically LCOV_EXCL_BR_LINE'ed: %d" % - excluded_br_lines) + print("Number of source lines automatically LCOV_EXCL_LINE'ed: %d" % excluded_lines) + print("Number of source lines automatically LCOV_EXCL_BR_LINE'ed: %d" % excluded_br_lines) def cleanup_abs_paths_info(cc_dir, infile, outfile): @@ -263,20 +248,11 @@ def cleanup_abs_paths_info(cc_dir, infile, outfile): with open(infile, "r", encoding="utf8") as fh: for line in fh: if re.search(r'^SF:', line) and not re.search(r'^SF:/usr/', line): - line = re.sub(os.environ['VERILATOR_ROOT'] + '/', - '', - line, - count=1) + line = re.sub(os.environ['VERILATOR_ROOT'] + '/', '', line, count=1) line = re.sub(cc_dir + '/', '', line, count=1) - line = re.sub(r'^SF:.*?/include/', - 'SF:include/', - line, - count=1) + line = re.sub(r'^SF:.*?/include/', 'SF:include/', line, count=1) line = re.sub(r'^SF:.*?/src/', 'SF:src/', line, count=1) - line = re.sub(r'^SF:.*?/test_regress/', - 'SF:test_regress/', - line, - count=1) + line = re.sub(r'^SF:.*?/test_regress/', 'SF:test_regress/', line, count=1) line = re.sub(r'obj_dbg/verilog.y$', 'verilog.y', line) # print("Remaining SF: "+line) lines.append(line) @@ -358,15 +334,13 @@ def ci_fold_end(): parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, - description= - """code_coverage builds Verilator with C++ coverage support and runs + description="""code_coverage builds Verilator with C++ coverage support and runs tests with coverage enabled. This will rebuild the current object files. Run as: cd $VERILATOR_ROOT nodist/code_coverage""", - epilog= - """Copyright 2019-2024 by Wilson Snyder. This program is free software; you + epilog="""Copyright 2019-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. @@ -376,23 +350,20 @@ SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_true', help='enable debug') parser.add_argument('--hashset', action='store', - help='pass test hashset onto driver.pl test harness') + help='pass test hashset onto driver.py test harness') parser.add_argument('--scenarios', action='store', - help='pass test scenarios onto driver.pl test harness') -parser.add_argument( - '--stages', - '--stage', - action='store', - help='runs a specific stage or range of stages (see the script)') + help='pass test scenarios onto driver.py test harness') +parser.add_argument('--stages', + '--stage', + action='store', + help='runs a specific stage or range of stages (see the script)') parser.add_argument( '--tests', '--test', action='append', default=[], - help= - 'Instead of normal regressions, run the specified test(s), may be used multiple times' -) + help='Instead of normal regressions, run the specified test(s), may be used multiple times') parser.add_argument('--no-stop', dest='stop', action='store_false', diff --git a/nodist/dot_importer b/nodist/dot_importer index c2a8215fe..33dba831b 100755 --- a/nodist/dot_importer +++ b/nodist/dot_importer @@ -20,8 +20,7 @@ def dotread(filename): vnum = 0 vertex_re = re.compile(r'^\t([a-zA-Z0-9_]+)\t(.*)$') - edge_re = re.compile( - r'^\t([a-zA-Z0-9_]+)\s+->\s+([a-zA-Z0-9_]+)\s*(.*)$') + edge_re = re.compile(r'^\t([a-zA-Z0-9_]+)\s+->\s+([a-zA-Z0-9_]+)\s*(.*)$') for line in fh: vertex_match = re.search(vertex_re, line) @@ -29,11 +28,7 @@ def dotread(filename): if vertex_match: if vertex_match.group(1) != 'nTITLE': header = False - Vertexes.append({ - 'num': vnum, - 'line': line, - 'name': vertex_match.group(1) - }) + Vertexes.append({'num': vnum, 'line': line, 'name': vertex_match.group(1)}) vnum += 1 elif edge_match: fromv = edge_match.group(1) @@ -65,14 +60,13 @@ def cwrite(filename): fh.write("void V3GraphTestImport::dotImport() {\n") fh.write(" auto* gp = &m_graph;\n") for ver in sorted(Vertexes, key=lambda ver: ver['num']): - fh.write( - " auto* %s = new V3GraphTestVertex{gp, \"%s\"}; if (%s) {}\n" - % (ver['name'], ver['name'], ver['name'])) + fh.write(" auto* %s = new V3GraphTestVertex{gp, \"%s\"}; if (%s) {}\n" % + (ver['name'], ver['name'], ver['name'])) fh.write("\n") for edge in Edges: - fh.write(" new V3GraphEdge{gp, %s, %s, %s, %s};\n" % - (edge['from'], edge['to'], edge['weight'], - "true" if edge['cutable'] else "false")) + fh.write( + " new V3GraphEdge{gp, %s, %s, %s, %s};\n" % + (edge['from'], edge['to'], edge['weight'], "true" if edge['cutable'] else "false")) fh.write("}\n") @@ -82,22 +76,17 @@ def cwrite(filename): parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, - description= - """dot_importer takes a graphvis .dot file and converts into .cpp file. + description="""dot_importer takes a graphvis .dot file and converts into .cpp file. This x.cpp file is then manually included in V3GraphTest.cpp to verify various xsub-algorithms.""", - epilog= - """Copyright 2005-2024 by Wilson Snyder. This program is free software; you + epilog="""Copyright 2005-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") -parser.add_argument('--debug', - action='store_const', - const=9, - help='enable debug') +parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('filename', help='input .dot filename to process') Args = parser.parse_args() diff --git a/nodist/fuzzer/actual_fail b/nodist/fuzzer/actual_fail index 8a8f2fdc8..9bca018f3 100755 --- a/nodist/fuzzer/actual_fail +++ b/nodist/fuzzer/actual_fail @@ -19,9 +19,12 @@ from argparse import ArgumentParser def interesting(s): - if 'assert' in s: return 1 - if 'Assert' in s: return 1 - if 'Aborted' in s: return 1 + if 'assert' in s: + return 1 + if 'Assert' in s: + return 1 + if 'Aborted' in s: + return 1 if 'terminate' in s: if 'unterminated' in s: return 0 @@ -41,8 +44,7 @@ def main(): for infile in glob(args.dir + '/*'): # Input filenames are known not to contain spaces or other unusual # characters, therefore this works. - status, output = getstatusoutput('../../bin/verilator_bin --cc ' + - infile) + status, output = getstatusoutput('../../bin/verilator_bin --cc ' + infile) if interesting(output): print(infile) print(status) diff --git a/nodist/fuzzer/generate_dictionary b/nodist/fuzzer/generate_dictionary index c03c899ed..d58bd4c73 100755 --- a/nodist/fuzzer/generate_dictionary +++ b/nodist/fuzzer/generate_dictionary @@ -51,9 +51,11 @@ def write_file(filename, contents): def parse_line(s): # str->maybe str - if len(s) == 0: return None + if len(s) == 0: + return None part = skip_while(lambda x: x != '"', s) - if len(part) == 0 or part[0] != '"': return None + if len(part) == 0 or part[0] != '"': + return None literal_part = take_while(lambda x: x != '"', part[1:]) return ''.join(filter(lambda x: x != '\\', literal_part)) diff --git a/nodist/install_test b/nodist/install_test index cfb9afebb..8534ebf4f 100755 --- a/nodist/install_test +++ b/nodist/install_test @@ -31,7 +31,10 @@ def test(): print("== stage 0") run("/bin/rm -rf " + blddir) run("/bin/mkdir -p " + blddir) - run("cd " + blddir + " && " + srcdir + "/configure --prefix " + prefix) + # Matches Ubuntu's e.g. /usr/share/pkgconfig/verilator.pc + run("cd " + blddir + " && " + srcdir + "/configure --prefix " + prefix + + " --exec-prefix " + prefix + " --datarootdir " + prefix + "/share" + " --includedir " + + prefix + "/share/verilator/include") run("cd " + blddir + " && make -j " + str(calc_jobs())) # Install it under the prefix @@ -41,8 +44,7 @@ def test(): run("/bin/mkdir -p " + prefix) run("cd " + blddir + " && make install") run("test -e " + prefix + "/share/man/man1/verilator.1") - run("test -e " + prefix + - "/share/verilator/examples/make_tracing_c/Makefile") + run("test -e " + prefix + "/share/verilator/examples/make_tracing_c/Makefile") run("test -e " + prefix + "/share/verilator/include/verilated.h") run("test -e " + prefix + "/bin/verilator") run("test -e " + prefix + "/bin/verilator_bin") @@ -58,10 +60,8 @@ def test(): run("/bin/mkdir -p " + odir) path = prefix + "/bin" + ":" + prefix + "/share/bin" write_verilog(odir) - run("cd " + odir + " && PATH=" + path + - ":$PATH verilator --cc top.v --exe sim_main.cpp") - run("cd " + odir + "/obj_dir && PATH=" + path + - ":$PATH make -f Vtop.mk") + run("cd " + odir + " && PATH=" + path + ":$PATH verilator --cc top.v --exe sim_main.cpp") + run("cd " + odir + "/obj_dir && PATH=" + path + ":$PATH make -f Vtop.mk") run("cd " + odir + " && PATH=" + path + ":$PATH obj_dir/Vtop") # run a test using exact path to binary @@ -72,8 +72,7 @@ def test(): run("/bin/mkdir -p " + odir) write_verilog(odir) bin1 = prefix + "/bin" - run("cd " + odir + " && " + bin1 + - "/verilator --cc top.v --exe sim_main.cpp") + run("cd " + odir + " && " + bin1 + "/verilator --cc top.v --exe sim_main.cpp") run("cd " + odir + "/obj_dir && make -f Vtop.mk") run("cd " + odir + "/obj_dir && ./Vtop") @@ -88,8 +87,7 @@ def write_verilog(odir): def cleanenv(): for var in os.environ: - if var in ('VERILATOR_ROOT', 'VERILATOR_INCLUDE', - 'VERILATOR_NO_OPT_BUILD'): + if var in ('VERILATOR_ROOT', 'VERILATOR_INCLUDE', 'VERILATOR_NO_OPT_BUILD'): print("unset %s # Was '%s'" % (var, os.environ[var])) del os.environ[var] @@ -113,21 +111,16 @@ def run(command): parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, - description= - """install_test performs several make-and-install iterations to verify the + description="""install_test performs several make-and-install iterations to verify the Verilator kit. It isn't part of the normal "make test" due to the number of builds required.""", - epilog= - """Copyright 2009-2024 by Wilson Snyder. This program is free software; you + epilog="""Copyright 2009-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") -parser.add_argument('--debug', - action='store_const', - const=9, - help='enable debug') +parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('--stage', type=int, default=0, diff --git a/nodist/lint_py_test_filter b/nodist/lint_py_test_filter new file mode 100755 index 000000000..813d11fc0 --- /dev/null +++ b/nodist/lint_py_test_filter @@ -0,0 +1,59 @@ +#!/usr/bin/env python3 +# pylint: disable= +###################################################################### + +import argparse +import re +import sys + +SUPPRESSES = [ + "**********", + "E0602: Undefined variable 'test' (undefined-variable)", + "E0602: Undefined variable 're' (undefined-variable)", + "E0602: Undefined variable 'os' (undefined-variable)", + "E0602: Undefined variable 'glob' (undefined-variable)", + "W0611: Unused import vltest_bootstrap (unused-import)", + ] + +###################################################################### + +def process(): + anymsg = False + for line in sys.stdin: + line = line.rstrip(); + show = True + for msg in SUPPRESSES: + if msg in line: + show = False + continue + if show: + print(line) + anymsg = True + + if anymsg: + sys.exit("%Error: See messages above") + +####################################################################### +####################################################################### + +parser = argparse.ArgumentParser( + allow_abbrev=False, + formatter_class=argparse.RawDescriptionHelpFormatter, + description="""lint_py_test_filter is used to filter +pylint output for expected errors in Verilator test_regress/*.py tests.""", + epilog="""Copyright 2024-2024 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") + +parser.add_argument('--debug', action='store_true', help='enable debug') + +Args = parser.parse_args() +process() + +###################################################################### +# Local Variables: +# compile-command: "cd .. ; make lint-py-pylint-tests" +# End: diff --git a/nodist/log_changes b/nodist/log_changes index 9a0df69d3..a6ec47276 100755 --- a/nodist/log_changes +++ b/nodist/log_changes @@ -101,8 +101,7 @@ parser = argparse.ArgumentParser( allow_abbrev=False, prog="log_changes", description="Create example entries for 'Changes' from parsing 'git log'", - epilog= - """Copyright 2019-2024 by Wilson Snyder. This program is free software; you + epilog="""Copyright 2019-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/src/.gdbinit.py b/src/.gdbinit.py index 767f88387..e7090604c 100644 --- a/src/.gdbinit.py +++ b/src/.gdbinit.py @@ -47,9 +47,12 @@ class AstseeCmd(gdb.Command): def _null_check(self, old, new): err = "" - if old == "\n": err += "old == \n" - if new == "\n": err += "new == " - if err: raise gdb.GdbError(err.strip("\n")) + if old == "\n": + err += "old == \n" + if new == "\n": + err += "new == " + if err: + raise gdb.GdbError(err.strip("\n")) def invoke(self, arg_str, from_tty): from astsee import verilator_cli as astsee # pylint: disable=import-error,import-outside-toplevel @@ -58,8 +61,8 @@ class AstseeCmd(gdb.Command): # We hack `astsee_verilator`'s arg parser to find arguments with nodes # After finding them, we replace them with proper files astsee_args = astsee.parser.parse_args(gdb.string_to_argv(arg_str)) - with _vltgdb_tmpfile() as oldfile, _vltgdb_tmpfile( - ) as newfile, _vltgdb_tmpfile() as metafile: + with _vltgdb_tmpfile() as oldfile, _vltgdb_tmpfile() as newfile, _vltgdb_tmpfile( + ) as metafile: if astsee_args.file: _vltgdb_fwrite(oldfile, _vltgdb_get_dump(astsee_args.file)) astsee_args.file = oldfile.name @@ -68,8 +71,7 @@ class AstseeCmd(gdb.Command): astsee_args.newfile = newfile.name if astsee_args.meta is None: # pass - gdb.execute( - f'call AstNode::dumpJsonMetaFileGdb("{metafile.name}")') + gdb.execute(f'call AstNode::dumpJsonMetaFileGdb("{metafile.name}")') astsee_args.meta = metafile.name try: astsee.main(astsee_args) diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 2cc6a0166..e0b1792a6 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -14,14 +14,23 @@ # # Utilities -macro (addBuildType sourceConfig newConfig) +macro(addBuildType sourceConfig newConfig) get_cmake_property(variableNames VARIABLES) - foreach (variableName ${variableNames}) - if (variableName MATCHES "^CMAKE_.*_${sourceConfig}(|_.*)$") - string(REPLACE _${sourceConfig} _${newConfig} newVariableName ${variableName}) + foreach(variableName ${variableNames}) + if(variableName MATCHES "^CMAKE_.*_${sourceConfig}(|_.*)$") + string( + REPLACE + _${sourceConfig} + _${newConfig} + newVariableName + ${variableName} + ) set(${newVariableName} ${${variableName}}) mark_as_advanced(${newVariableName}) - message(DEBUG " Propagating ${variableName} to ${newVariableName} = ${${newVariableName}}") + message( + DEBUG + " Propagating ${variableName} to ${newVariableName} = ${${newVariableName}}" + ) endif() endforeach() endmacro() @@ -163,7 +172,6 @@ set(HEADERS V3Table.h V3Task.h V3ThreadPool.h - V3ThreadSafety.h V3Timing.h V3Trace.h V3TraceDecl.h @@ -328,15 +336,11 @@ set(COMMON_SOURCES V3PreProc.cpp ) -SET(COVERAGE_SOURCES - VlcMain.cpp -) +set(COVERAGE_SOURCES VlcMain.cpp) # Note about tests: # VlcMain.cpp #includes the following files: # V3Error.cpp, V3String.cpp, V3Os.cpp and VlcTop.cpp -# V3Number_test.cpp #includes the following files: -# V3FileLine.cpp # # Generated sources and headers for the verilator binary @@ -355,34 +359,49 @@ configure_file(config_package.h.in config_package.h @ONLY) add_custom_command( OUTPUT V3Ast__gen_forward_class_decls.h V3Dfg__gen_forward_class_decls.h DEPENDS ./V3Ast.h ${ASTGEN} - COMMAND ${PYTHON3} ARGS - ${ASTGEN} -I "${srcdir}" --astdef V3AstNodeDType.h --astdef V3AstNodeExpr.h --astdef V3AstNodeOther.h --dfgdef V3DfgVertices.h --classes + COMMAND ${PYTHON3} + ARGS + ${ASTGEN} -I "${srcdir}" --astdef V3AstNodeDType.h --astdef + V3AstNodeExpr.h --astdef V3AstNodeOther.h --dfgdef V3DfgVertices.h + --classes +) +list( + APPEND + GENERATED_FILES + V3Ast__gen_forward_class_decls.h + V3Dfg__gen_forward_class_decls.h ) -list(APPEND GENERATED_FILES V3Ast__gen_forward_class_decls.h V3Dfg__gen_forward_class_decls.h) # Output used directly by the `verilator` target -set(verilog_y "${srcdir}/verilog.y" ) -set(BISON_V3ParseBison_OUTPUT_HEADER "${CMAKE_CURRENT_BINARY_DIR}/V3ParseBison.h") -set(BISON_V3ParseBison_OUTPUT_SOURCE "${CMAKE_CURRENT_BINARY_DIR}/V3ParseBison.c") +set(verilog_y "${srcdir}/verilog.y") +set(BISON_V3ParseBison_OUTPUT_HEADER + "${CMAKE_CURRENT_BINARY_DIR}/V3ParseBison.h" +) +set(BISON_V3ParseBison_OUTPUT_SOURCE + "${CMAKE_CURRENT_BINARY_DIR}/V3ParseBison.c" +) add_custom_command( OUTPUT V3ParseBison.c V3ParseBison.h MAIN_DEPENDENCY ./verilog.y DEPENDS ${BISONPRE} - COMMAND ${PYTHON3} ARGS - ${BISONPRE} --yacc "${BISON_EXECUTABLE}" -d -v - -o "${BISON_V3ParseBison_OUTPUT_SOURCE}" "${verilog_y}" + COMMAND ${PYTHON3} + ARGS + ${BISONPRE} --yacc "${BISON_EXECUTABLE}" -d -v -o + "${BISON_V3ParseBison_OUTPUT_SOURCE}" "${verilog_y}" ) list(APPEND GENERATED_FILES V3ParseBison.c V3ParseBison.h) # Output used directly by the `verilator` target set(verilog_l "${srcdir}/verilog.l") -set(FLEX_V3Lexer_pregen_OUTPUTS "${CMAKE_CURRENT_BINARY_DIR}/V3Lexer_pregen.yy.cpp") +set(FLEX_V3Lexer_pregen_OUTPUTS + "${CMAKE_CURRENT_BINARY_DIR}/V3Lexer_pregen.yy.cpp" +) add_custom_command( OUTPUT V3Lexer_pregen.yy.cpp MAIN_DEPENDENCY ./verilog.l DEPENDS ${BISON_V3ParseBison_OUTPUT_HEADER} ${HEADERS} - COMMAND ${FLEX_EXECUTABLE} ARGS - ${LFLAGS} -o "${FLEX_V3Lexer_pregen_OUTPUTS}" "${verilog_l}" + COMMAND ${FLEX_EXECUTABLE} + ARGS ${LFLAGS} -o "${FLEX_V3Lexer_pregen_OUTPUTS}" "${verilog_l}" ) # Output used by another command @@ -391,19 +410,26 @@ add_custom_command( OUTPUT V3Lexer.yy.cpp MAIN_DEPENDENCY ${FLEX_V3Lexer_pregen_OUTPUTS} DEPENDS ${FLEXFIX} - COMMAND ${PYTHON3} ARGS - ${FLEXFIX} V3Lexer < "$" > "$" + COMMAND ${PYTHON3} + ARGS + ${FLEXFIX} V3Lexer < "$" > + "$" +) +add_custom_target( + V3Lexer_yy_cpp${CMAKE_BUILD_TYPE} + DEPENDS ${FLEX_V3Lexer_OUTPUTS} ) -add_custom_target(V3Lexer_yy_cpp${CMAKE_BUILD_TYPE} DEPENDS ${FLEX_V3Lexer_OUTPUTS}) # Output included by another source file -set(FLEX_V3PreLex_pregen_OUTPUTS ${CMAKE_CURRENT_BINARY_DIR}/V3PreLex_pregen.yy.cpp) +set(FLEX_V3PreLex_pregen_OUTPUTS + ${CMAKE_CURRENT_BINARY_DIR}/V3PreLex_pregen.yy.cpp +) add_custom_command( OUTPUT V3PreLex_pregen.yy.cpp MAIN_DEPENDENCY ./V3PreLex.l DEPENDS ${HEADERS} - COMMAND ${FLEX_EXECUTABLE} ARGS - ${LFLAGS} -o "${FLEX_V3PreLex_pregen_OUTPUTS}" "${srcdir}/V3PreLex.l" + COMMAND ${FLEX_EXECUTABLE} + ARGS ${LFLAGS} -o "${FLEX_V3PreLex_pregen_OUTPUTS}" "${srcdir}/V3PreLex.l" ) # Output used by another command @@ -412,37 +438,45 @@ add_custom_command( OUTPUT V3PreLex.yy.cpp MAIN_DEPENDENCY ${FLEX_V3PreLex_pregen_OUTPUTS} DEPENDS ${FLEXFIX} - COMMAND ${PYTHON3} ARGS - ${FLEXFIX} V3PreLex < "$" > "$" + COMMAND ${PYTHON3} + ARGS + ${FLEXFIX} V3PreLex < "$" > + "$" +) +add_custom_target( + V3PreLex_yy_cpp${CMAKE_BUILD_TYPE} + DEPENDS ${FLEX_V3PreLex_OUTPUTS} ) -add_custom_target(V3PreLex_yy_cpp${CMAKE_BUILD_TYPE} DEPENDS ${FLEX_V3PreLex_OUTPUTS}) # Output included by another source file set(gitHead ${srcdir}/../.git/logs/HEAD) -if (NOT EXISTS ${githead}) +if(NOT EXISTS ${githead}) set(gitHead "") endif() add_custom_command( OUTPUT config_rev.h MAIN_DEPENDENCY ${gitHead} DEPENDS ${CONFIG_REV} - COMMAND ${PYTHON3} ARGS - ${CONFIG_REV} "${srcdir}" > "$" + COMMAND ${PYTHON3} + ARGS + ${CONFIG_REV} "${srcdir}" > + "$" ) list(APPEND GENERATED_FILES config_rev.h) # Output used directly by the `verilator` target -set(ASTGENERATED_NAMES - V3Const -) +set(ASTGENERATED_NAMES V3Const) foreach(astgen_name ${ASTGENERATED_NAMES}) add_custom_command( OUTPUT ${astgen_name}__gen.cpp MAIN_DEPENDENCY ${astgen_name}.cpp DEPENDS ${ASTGEN} V3Ast.h - COMMAND ${PYTHON3} ARGS - ${ASTGEN} -I "${srcdir}" --astdef V3AstNodeDType.h --astdef V3AstNodeExpr.h --astdef V3AstNodeOther.h --dfgdef V3DfgVertices.h ${astgen_name}.cpp + COMMAND ${PYTHON3} + ARGS + ${ASTGEN} -I "${srcdir}" --astdef V3AstNodeDType.h --astdef + V3AstNodeExpr.h --astdef V3AstNodeOther.h --dfgdef V3DfgVertices.h + ${astgen_name}.cpp ) list(APPEND GENERATED_FILES ${astgen_name}__gen.cpp) endforeach() @@ -450,7 +484,7 @@ endforeach() # # Set up the Coverage build type -addBuildType(DEBUG COVERAGE) +addbuildtype(DEBUG COVERAGE) # This regenerates include/verilated_cov_key.h in the source tree. # It is a custom_target, not custom_command, because vlcovgen.d is @@ -459,8 +493,7 @@ add_custom_target( vlcovgen.d${CMAKE_BUILD_TYPE} DEPENDS ../include/verilated_cov_key.h ${VLCOVGEN} COMMENT "Updating include/verilated_cov_key.h" - COMMAND ${PYTHON3} - ${VLCOVGEN} --srcdir ${srcdir} + COMMAND ${PYTHON3} ${VLCOVGEN} --srcdir ${srcdir} ) # @@ -468,24 +501,29 @@ add_custom_target( set(verilator verilator${CMAKE_BUILD_TYPE}) -add_executable(${verilator} +add_executable( + ${verilator} $<$>:${COMMON_SOURCES}> $<$>:${GENERATED_FILES}> - $<$:${COVERAGE_SOURCES} config_rev.h> + $<$:${COVERAGE_SOURCES} + config_rev.h> ) -set_target_properties(${verilator} PROPERTIES - OUTPUT_NAME_RELEASE verilator_bin - OUTPUT_NAME_DEBUG verilator_bin_dbg - OUTPUT_NAME_COVERAGE verilator_coverage_bin_dbg - #UNITY_BUILD $,FALSE,${CMAKE_UNITY_BUILD}> - MSVC_RUNTIME_LIBRARY MultiThreaded$,,DebugDLL> - #JOB_POOL_LINK one_job # Linking takes lots of resources - INTERPROCEDURAL_OPTIMIZATION_RELEASE $ - INCLUDE_DIRECTORIES ${FLEX_INCLUDE_DIR} +set_target_properties( + ${verilator} + PROPERTIES + OUTPUT_NAME_RELEASE verilator_bin + OUTPUT_NAME_DEBUG verilator_bin_dbg + OUTPUT_NAME_COVERAGE verilator_coverage_bin_dbg + #UNITY_BUILD $,FALSE,${CMAKE_UNITY_BUILD}> + MSVC_RUNTIME_LIBRARY MultiThreaded$,,DebugDLL> + #JOB_POOL_LINK one_job # Linking takes lots of resources + INTERPROCEDURAL_OPTIMIZATION_RELEASE $ + INCLUDE_DIRECTORIES ${FLEX_INCLUDE_DIR} ) -add_dependencies(${verilator} +add_dependencies( + ${verilator} V3Lexer_yy_cpp${CMAKE_BUILD_TYPE} V3PreLex_yy_cpp${CMAKE_BUILD_TYPE} ) @@ -495,41 +533,49 @@ target_link_libraries(${verilator} PRIVATE Threads::Threads) # verilated_cov_key.h is only regenerated in a single-configuration environment. # This limitation can be lifted when `add_dependencies` will support generator # expressions. See https://gitlab.kitware.com/cmake/cmake/issues/19467 -if (CMAKE_BUILD_TYPE STREQUAL Coverage) +if(CMAKE_BUILD_TYPE STREQUAL Coverage) add_dependencies(${verilator} vlcovgen.d${CMAKE_BUILD_TYPE}) endif() -if (NOT MSVC) +if(NOT MSVC) target_compile_features(${verilator} PRIVATE cxx_std_11) endif() -target_compile_definitions(${verilator} PRIVATE - YYDEBUG # Required to get nice error messages - $<$:VL_DEBUG> - $<$:_GLIBCXX_DEBUG> -) - -target_include_directories(${verilator} +target_compile_definitions( + ${verilator} PRIVATE - ../include - ${WIN_FLEX_BISON} - ${CMAKE_CURRENT_BINARY_DIR} - ${CMAKE_CURRENT_BINARY_DIR}/../include - ${CMAKE_CURRENT_SOURCE_DIR} + YYDEBUG # Required to get nice error messages + $<$:VL_DEBUG> + $<$:_GLIBCXX_DEBUG> ) -if (WIN32) +target_include_directories( + ${verilator} + PRIVATE + ../include + ${WIN_FLEX_BISON} + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_BINARY_DIR}/../include + ${CMAKE_CURRENT_SOURCE_DIR} +) + +if(WIN32) if(MINGW) target_compile_options(${verilator} PRIVATE -Wa,-mbig-obj) - target_link_options(${verilator} PRIVATE -Wl,--stack,10000000 -mconsole -lcomctl32 -DWIN_32_LEAN_AND_MEAN) + target_link_options( + ${verilator} + PRIVATE + -Wl,--stack,10000000 + -mconsole + -lcomctl32 + -DWIN_32_LEAN_AND_MEAN + ) else() target_compile_options(${verilator} PRIVATE /bigobj) target_link_options(${verilator} PRIVATE /STACK:10000000) endif() - target_compile_definitions(${verilator} PRIVATE - YY_NO_UNISTD_H - ) + target_compile_definitions(${verilator} PRIVATE YY_NO_UNISTD_H) target_include_directories(${verilator} PRIVATE ../platform/win32) target_link_libraries(${verilator} PRIVATE bcrypt psapi) endif() diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in index a524c16a4..d29baa840 100644 --- a/src/Makefile_obj.in +++ b/src/Makefile_obj.in @@ -49,7 +49,7 @@ prefix = @prefix@ # Directory in which to install data across multiple architectures datarootdir = @datarootdir@ -# Directory in which to install package specific files +# Directory in which to install package-specific files # Generally ${prefix}/share/verilator pkgdatadir = @pkgdatadir@ @@ -210,6 +210,7 @@ RAW_OBJS_PCH_ASTMT = \ V3Options.o \ V3Stats.o \ V3StatsReport.o \ + V3VariableOrder.o \ RAW_OBJS_PCH_ASTNOMT = \ V3Active.o \ @@ -309,7 +310,6 @@ RAW_OBJS_PCH_ASTNOMT = \ V3Undriven.o \ V3Unknown.o \ V3Unroll.o \ - V3VariableOrder.o \ V3Width.o \ V3WidthCommit.o \ V3WidthSel.o \ @@ -355,9 +355,6 @@ $(TGT): $(PREDEP_H) $(OBJS) @echo " Linking $@..." ${LINK} ${LDFLAGS} -o $@ $(OBJS) $(CCMALLOC) ${LIBS} -V3Number_test: V3Number_test.o - ${LINK} ${LDFLAGS} -o $@ $^ ${LIBS} - #### Modules %__gen.cpp: %.cpp $(ASTGEN) $(AST_DEFS) $(DFG_DEFS) @@ -366,7 +363,7 @@ V3Number_test: V3Number_test.o .SECONDARY: %.gch: % - $(OBJCACHE) ${CXX} ${CXXFLAGS} ${CPPFLAGSWALL} ${CFG_CXXFLAGS_PCH} $< -o $@ + $(OBJCACHE) ${CXX} ${CXXFLAGS} ${CPPFLAGSWALL} ${CFG_CXXFLAGS_PCH} -c $< -o $@ %.o: %.cpp $(OBJCACHE) ${CXX} ${CXXFLAGS} ${CPPFLAGSWALL} -c $< -o $@ %.o: %.c diff --git a/src/V3Active.h b/src/V3Active.h index b1ec9db2d..431a46e64 100644 --- a/src/V3Active.h +++ b/src/V3Active.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3ActiveTop.h b/src/V3ActiveTop.h index 6abd1e078..979041114 100644 --- a/src/V3ActiveTop.h +++ b/src/V3ActiveTop.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index 315902813..b90e1e106 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -189,7 +189,7 @@ class AssertVisitor final : public VNVisitor { AstNodeStmt* const bodysp = dispp; replaceDisplay(dispp, "%%Error"); // Convert to standard DISPLAY format if (exprsp) dispp->fmtp()->exprsp()->addNext(exprsp); - if (v3Global.opt.stopFail()) bodysp->addNext(new AstStop{nodep->fileline(), true}); + if (v3Global.opt.stopFail()) bodysp->addNext(new AstStop{nodep->fileline(), false}); return bodysp; } diff --git a/src/V3Assert.h b/src/V3Assert.h index d3362e5c6..08f6bbb5e 100644 --- a/src/V3Assert.h +++ b/src/V3Assert.h @@ -21,7 +21,6 @@ #include "verilatedos.h" #include "V3Ast.h" -#include "V3ThreadSafety.h" //============================================================================ diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp index acd482f0e..d22004656 100644 --- a/src/V3AssertPre.cpp +++ b/src/V3AssertPre.cpp @@ -216,8 +216,16 @@ private: skewedReadRefp->cloneTree(false)}); if (skewp->isZero()) { // Drive the var in Re-NBA (IEEE 1800-2023 14.16) - m_clockingp->addNextHere(new AstAlwaysReactive{ - flp, new AstSenTree{flp, m_clockingp->sensesp()->cloneTree(false)}, ifp}); + AstSenTree* senTreep + = new AstSenTree{flp, m_clockingp->sensesp()->cloneTree(false)}; + senTreep->addSensesp( + new AstSenItem{flp, VEdgeType::ET_CHANGED, skewedReadRefp->cloneTree(false)}); + AstCMethodHard* const trigp = new AstCMethodHard{ + nodep->fileline(), + new AstVarRef{flp, m_clockingp->ensureEventp(), VAccess::READ}, "isTriggered"}; + trigp->dtypeSetBit(); + ifp->condp(new AstLogAnd{flp, ifp->condp()->unlinkFrBack(), trigp}); + m_clockingp->addNextHere(new AstAlwaysReactive{flp, senTreep, ifp}); } else if (skewp->fileline()->timingOn()) { // Create a fork so that this AlwaysObserved can be retriggered before the // assignment happens. Also then it can be combo, avoiding the need for creating diff --git a/src/V3AssertPre.h b/src/V3AssertPre.h index 2c87823c9..2a68a20d1 100644 --- a/src/V3AssertPre.h +++ b/src/V3AssertPre.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Ast.h b/src/V3Ast.h index d84a87888..5bd63e855 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -215,7 +215,7 @@ public: return names[m_e]; } const char* arrow() const { - static const char* const names[] = {"[RV] <-", "[LV] =>", "[LV] <=>", "--"}; + static const char* const names[] = {"[RV] <-", "[LV] =>", "[LRV] <=>", "--"}; return names[m_e]; } VAccess() @@ -899,6 +899,8 @@ public: SUPPLY1, WIRE, WREAL, + TRIAND, + TRIOR, TRIWIRE, TRI0, TRI1, @@ -919,20 +921,24 @@ public: constexpr operator en() const { return m_e; } const char* ascii() const { static const char* const names[] - = {"?", "GPARAM", "LPARAM", "GENVAR", "VAR", "SUPPLY0", "SUPPLY1", - "WIRE", "WREAL", "TRIWIRE", "TRI0", "TRI1", "PORT", "BLOCKTEMP", - "MODULETEMP", "STMTTEMP", "XTEMP", "IFACEREF", "MEMBER"}; + = {"?", "GPARAM", "LPARAM", "GENVAR", "VAR", "SUPPLY0", "SUPPLY1", + "WIRE", "WREAL", "TRIAND", "TRIOR", "TRIWIRE", "TRI0", "TRI1", + "PORT", "BLOCKTEMP", "MODULETEMP", "STMTTEMP", "XTEMP", "IFACEREF", "MEMBER"}; return names[m_e]; } bool isParam() const { return m_e == GPARAM || m_e == LPARAM; } bool isSignal() const { return (m_e == WIRE || m_e == WREAL || m_e == TRIWIRE || m_e == TRI0 || m_e == TRI1 - || m_e == PORT || m_e == SUPPLY0 || m_e == SUPPLY1 || m_e == VAR); + || m_e == PORT || m_e == SUPPLY0 || m_e == SUPPLY1 || m_e == VAR || m_e == TRIOR + || m_e == TRIAND); } bool isNet() const { return (m_e == WIRE || m_e == TRIWIRE || m_e == TRI0 || m_e == TRI1 || m_e == SUPPLY0 - || m_e == SUPPLY1); + || m_e == SUPPLY1 || m_e == TRIOR || m_e == TRIAND); } + bool isWor() const { return (m_e == TRIOR); } + bool isWand() const { return (m_e == TRIAND); } + bool isWiredNet() const { return (m_e == TRIOR || m_e == TRIAND); } bool isContAssignable() const { // In Verilog, always ok in SystemVerilog return (m_e == SUPPLY0 || m_e == SUPPLY1 || m_e == WIRE || m_e == WREAL || m_e == TRIWIRE || m_e == TRI0 || m_e == TRI1 || m_e == PORT || m_e == BLOCKTEMP @@ -963,6 +969,8 @@ public: /* SUPPLY1: */ "SUPPLY1", /* WIRE: */ "WIRE", /* WREAL: */ "WIRE", + /* TRIAND: */ "TRIAND", + /* TRIOR: */ "TRIOR", /* TRIWIRE: */ "TRI", /* TRI0: */ "TRI0", /* TRI1: */ "TRI1", @@ -2182,7 +2190,7 @@ public: virtual void tag(const string& text) {} virtual string tag() const { return ""; } virtual string verilogKwd() const { return ""; } - string nameProtect() const; // Name with --protect-id applied + string nameProtect() const VL_MT_STABLE; // Name with --protect-id applied string origNameProtect() const; // origName with --protect-id applied string shortName() const; // Name with __PVT__ removed for concatenating scopes static string dedotName(const string& namein); // Name with dots removed @@ -2362,8 +2370,9 @@ public: AstNodeDType* findBitDType(int width, int widthMin, VSigning numeric) const; AstNodeDType* findLogicDType(int width, int widthMin, VSigning numeric) const; AstNodeDType* findLogicRangeDType(const VNumRange& range, int widthMin, - VSigning numeric) const; - AstNodeDType* findBitRangeDType(const VNumRange& range, int widthMin, VSigning numeric) const; + VSigning numeric) const VL_MT_STABLE; + AstNodeDType* findBitRangeDType(const VNumRange& range, int widthMin, + VSigning numeric) const VL_MT_STABLE; AstNodeDType* findBasicDType(VBasicDTypeKwd kwd) const; static AstBasicDType* findInsertSameDType(AstBasicDType* nodep); @@ -2440,7 +2449,7 @@ public: static void dumpTreeFileGdb(const AstNode* nodep, const char* filenamep = nullptr); void dumpTreeDot(std::ostream& os = std::cout) const; void dumpTreeDotFile(const string& filename, bool doDump = true); - virtual void dumpJson(std::ostream& os) const { dumpJsonGen(os); }; // node specific fields + virtual void dumpJson(std::ostream& os) const { dumpJsonGen(os); }; // node-specific fields // Generated by 'astgen'. Dumps node-specific pointers and calls 'dumpJson()' of parent class // Note that we don't make it virtual as it would result in infinite recursion void dumpJsonGen(std::ostream& os) const {}; diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h index 7e7f4be4b..3dc9d7d2c 100644 --- a/src/V3AstNodeDType.h +++ b/src/V3AstNodeDType.h @@ -54,7 +54,7 @@ public: void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; virtual void dumpSmall(std::ostream& str) const VL_MT_STABLE; - bool hasDType() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } /// Require VlUnpacked, instead of [] for POD elements. /// A non-POD object is always compound, but some POD elements /// are compound when methods calls operate on object, or when @@ -74,7 +74,7 @@ public: virtual int widthAlignBytes() const = 0; // (Slow) recurses - Width in bytes rounding up 1,2,4,8,12,... virtual int widthTotalBytes() const = 0; - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } // Iff has a non-null refDTypep(), as generic node function virtual AstNodeDType* virtRefDTypep() const { return nullptr; } // Iff has refDTypep(), set as generic node function @@ -86,7 +86,7 @@ public: // Assignable equivalence. Call skipRefp() on this and samep before calling virtual bool similarDType(const AstNodeDType* samep) const = 0; // Iff has a non-null subDTypep(), as generic node function - virtual AstNodeDType* subDTypep() const VL_MT_SAFE { return nullptr; } + virtual AstNodeDType* subDTypep() const VL_MT_STABLE { return nullptr; } virtual bool isFourstate() const; // Ideally an IEEE $typename virtual string prettyDTypeName(bool) const { return prettyTypeName(); } @@ -105,14 +105,14 @@ public: m_numeric = nodep->m_numeric; } // - int width() const VL_MT_SAFE { return m_width; } + int width() const VL_MT_STABLE { return m_width; } void numeric(VSigning flag) { m_numeric = flag; } - bool isSigned() const VL_MT_SAFE { return m_numeric.isSigned(); } + bool isSigned() const VL_MT_STABLE { return m_numeric.isSigned(); } bool isNosign() const VL_MT_SAFE { return m_numeric.isNosign(); } - VSigning numeric() const { return m_numeric; } - int widthWords() const VL_MT_SAFE { return VL_WORDS_I(width()); } - int widthMin() const VL_MT_SAFE { // If sized, the size, - // if unsized the min digits to represent it + VSigning numeric() const VL_MT_STABLE { return m_numeric; } + int widthWords() const VL_MT_STABLE { return VL_WORDS_I(width()); } + int widthMin() const VL_MT_STABLE { // If sized, the size, + // if unsized the min digits to represent it return m_widthMin ? m_widthMin : m_width; } int widthPow2() const; @@ -209,6 +209,12 @@ protected: m_packed = (numericUnpack != VSigning::NOSIGN); numeric(VSigning::fromBool(numericUnpack.isSigned())); } + AstNodeUOrStructDType(const AstNodeUOrStructDType& other) + : AstNodeDType(other) + , m_name(other.m_name) + , m_uniqueNum(uniqueNumInc()) + , m_packed(other.m_packed) + , m_isFourstate(other.m_isFourstate) {} public: ASTGEN_MEMBERS_AstNodeUOrStructDType; @@ -218,7 +224,7 @@ public: string prettyDTypeName(bool) const override; bool isCompound() const override { return !packed(); } // For basicp() we reuse the size to indicate a "fake" basic type of same size - AstBasicDType* basicp() const override { + AstBasicDType* basicp() const override VL_MT_STABLE { if (!m_packed) return nullptr; return (isFourstate() ? VN_AS(findLogicRangeDType(VNumRange{width() - 1, 0}, width(), numeric()), @@ -244,9 +250,11 @@ public: static bool packedUnsup() { return true; } void isFourstate(bool flag) { m_isFourstate = flag; } bool isFourstate() const override VL_MT_SAFE { return m_isFourstate; } - static int lo() { return 0; } - int hi() const { return dtypep()->width() - 1; } // Packed classes look like arrays - VNumRange declRange() const { return VNumRange{hi(), lo()}; } + static int lo() VL_MT_STABLE { return 0; } + int hi() const VL_MT_STABLE { + return dtypep()->width() - 1; + } // Packed classes look like arrays + VNumRange declRange() const VL_MT_STABLE { return VNumRange{hi(), lo()}; } AstNodeModule* classOrPackagep() const { return m_classOrPackagep; } void classOrPackagep(AstNodeModule* classpackagep) { m_classOrPackagep = classpackagep; } }; @@ -269,8 +277,8 @@ public: } ASTGEN_MEMBERS_AstEnumItem; string name() const override VL_MT_STABLE { return m_name; } - bool maybePointedTo() const override { return true; } - bool hasDType() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } void name(const string& flag) override { m_name = flag; } }; @@ -416,8 +424,8 @@ public: return m.m_keyword; } bool isBitLogic() const { return keyword().isBitLogic(); } - bool isDouble() const VL_MT_SAFE { return keyword().isDouble(); } - bool isEvent() const VL_MT_SAFE { return keyword() == VBasicDTypeKwd::EVENT; } + bool isDouble() const VL_MT_STABLE { return keyword().isDouble(); } + bool isEvent() const VL_MT_STABLE { return keyword() == VBasicDTypeKwd::EVENT; } bool isTriggerVec() const VL_MT_SAFE { return keyword() == VBasicDTypeKwd::TRIGGERVEC; } bool isForkSync() const VL_MT_SAFE { return keyword() == VBasicDTypeKwd::FORK_SYNC; } bool isProcessRef() const VL_MT_SAFE { return keyword() == VBasicDTypeKwd::PROCESS_REFERENCE; } @@ -434,7 +442,7 @@ public: return keyword() == VBasicDTypeKwd::RANDOM_GENERATOR; } bool isOpaque() const VL_MT_SAFE { return keyword().isOpaque(); } - bool isString() const VL_MT_SAFE { return keyword().isString(); } + bool isString() const VL_MT_STABLE { return keyword().isString(); } bool isZeroInit() const { return keyword().isZeroInit(); } bool isRanged() const { return rangep() || m.m_nrange.ranged(); } bool isDpiBitVec() const { // DPI uses svBitVecVal @@ -479,7 +487,7 @@ public: // METHODS // Will be removed in V3Width, which relies on this // being a child not a dtype pointed node - bool maybePointedTo() const override { return false; } + bool maybePointedTo() const override VL_MT_SAFE { return false; } AstBasicDType* basicp() const override VL_MT_STABLE { return nullptr; } AstNodeDType* skipRefp() const override VL_MT_STABLE { return (AstNodeDType*)this; } AstNodeDType* skipRefToConstp() const override { return (AstNodeDType*)this; } @@ -563,7 +571,7 @@ public: int widthTotalBytes() const override { return 0; } AstNodeDType* virtRefDTypep() const override { return nullptr; } void virtRefDTypep(AstNodeDType* nodep) override {} - AstNodeDType* subDTypep() const override VL_MT_SAFE { return nullptr; } + AstNodeDType* subDTypep() const override VL_MT_STABLE { return nullptr; } AstNodeModule* classOrPackagep() const { return m_classOrPackagep; } void classOrPackagep(AstNodeModule* nodep) { m_classOrPackagep = nodep; } AstClass* classp() const VL_MT_STABLE { return m_classp; } @@ -624,10 +632,10 @@ public: dtypep(this); } ASTGEN_MEMBERS_AstConstraintRefDType; - bool hasDType() const override { return true; } - bool maybePointedTo() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } bool undead() const override { return true; } - AstNodeDType* subDTypep() const override VL_MT_SAFE { return nullptr; } + AstNodeDType* subDTypep() const override VL_MT_STABLE { return nullptr; } AstNodeDType* virtRefDTypep() const override { return nullptr; } void virtRefDTypep(AstNodeDType* nodep) override {} bool similarDType(const AstNodeDType* samep) const override { return this == samep; } @@ -662,6 +670,11 @@ public: childDTypep(dtp); // Only for parser dtypep(nullptr); // V3Width will resolve } + AstDefImplicitDType(const AstDefImplicitDType& other) + : AstNodeDType(other) + , m_name(other.m_name) + , m_containerp(other.m_containerp) + , m_uniqueNum(uniqueNumInc()) {} ASTGEN_MEMBERS_AstDefImplicitDType; int uniqueNum() const { return m_uniqueNum; } bool same(const AstNode* samep) const override { @@ -749,10 +762,10 @@ public: } ASTGEN_MEMBERS_AstEmptyQueueDType; void dumpSmall(std::ostream& str) const override; - bool hasDType() const override { return true; } - bool maybePointedTo() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } bool undead() const override { return true; } - AstNodeDType* subDTypep() const override VL_MT_SAFE { return nullptr; } + AstNodeDType* subDTypep() const override VL_MT_STABLE { return nullptr; } AstNodeDType* virtRefDTypep() const override { return nullptr; } void virtRefDTypep(AstNodeDType* nodep) override {} bool similarDType(const AstNodeDType* samep) const override { return this == samep; } @@ -791,6 +804,10 @@ public: dtypep(nullptr); // V3Width will resolve widthFromSub(subDTypep()); } + AstEnumDType(const AstEnumDType& other) + : AstNodeDType(other) + , m_name(other.m_name) + , m_uniqueNum(uniqueNumInc()) {} ASTGEN_MEMBERS_AstEnumDType; const char* broken() const override; @@ -931,8 +948,8 @@ public: ASTGEN_MEMBERS_AstMemberDType; void dumpSmall(std::ostream& str) const override; string name() const override VL_MT_STABLE { return m_name; } // * = Var name - bool hasDType() const override { return true; } - bool maybePointedTo() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } AstNodeDType* getChildDTypep() const override { return childDTypep(); } AstNodeUOrStructDType* getChildStructp() const; AstNodeDType* subDTypep() const override VL_MT_STABLE { @@ -979,11 +996,11 @@ public: } ASTGEN_MEMBERS_AstNBACommitQueueDType; - AstNodeDType* subDTypep() const override { return m_subDTypep; } + AstNodeDType* subDTypep() const override VL_MT_STABLE { return m_subDTypep; } bool partial() const { return m_partial; } bool similarDType(const AstNodeDType* samep) const override { return this == samep; } - AstBasicDType* basicp() const override { return nullptr; } - AstNodeDType* skipRefp() const override { return (AstNodeDType*)this; } + AstBasicDType* basicp() const override VL_MT_STABLE { return nullptr; } + AstNodeDType* skipRefp() const override VL_MT_STABLE { return (AstNodeDType*)this; } AstNodeDType* skipRefToConstp() const override { return (AstNodeDType*)this; } AstNodeDType* skipRefToEnump() const override { return (AstNodeDType*)this; } int widthAlignBytes() const override { return 1; } @@ -1025,8 +1042,8 @@ public: int widthTotalBytes() const override { return dtypep()->widthTotalBytes(); } // METHODS string name() const override VL_MT_STABLE { return m_name; } - bool maybePointedTo() const override { return true; } - bool hasDType() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } void name(const string& flag) override { m_name = flag; } VVarType varType() const { return m_varType; } // * = Type of variable bool isParam() const { return true; } @@ -1044,7 +1061,7 @@ public: explicit AstParseTypeDType(FileLine* fl) : ASTGEN_SUPER_ParseTypeDType(fl) {} ASTGEN_MEMBERS_AstParseTypeDType; - AstNodeDType* dtypep() const { return nullptr; } + AstNodeDType* dtypep() const VL_MT_STABLE { return nullptr; } // METHODS bool similarDType(const AstNodeDType* samep) const override { return this == samep; } AstBasicDType* basicp() const override VL_MT_STABLE { return nullptr; } @@ -1119,7 +1136,7 @@ public: bool isCompound() const override { return true; } }; class AstRefDType final : public AstNodeDType { - // @astgen op1 := typeofp : Optional[AstNode] + // @astgen op1 := typeofp : Optional[AstNode] // @astgen op2 := classOrPackageOpp : Optional[AstNodeExpr] // @astgen op3 := paramsp : List[AstPin] // @@ -1263,10 +1280,10 @@ public: } ASTGEN_MEMBERS_AstStreamDType; void dumpSmall(std::ostream& str) const override; - bool hasDType() const override { return true; } - bool maybePointedTo() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } bool undead() const override { return true; } - AstNodeDType* subDTypep() const override VL_MT_SAFE { return nullptr; } + AstNodeDType* subDTypep() const override VL_MT_STABLE { return nullptr; } AstNodeDType* virtRefDTypep() const override { return nullptr; } void virtRefDTypep(AstNodeDType* nodep) override {} bool similarDType(const AstNodeDType* samep) const override { return this == samep; } @@ -1331,10 +1348,10 @@ public: } ASTGEN_MEMBERS_AstVoidDType; void dumpSmall(std::ostream& str) const override; - bool hasDType() const override { return true; } - bool maybePointedTo() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } bool undead() const override { return true; } - AstNodeDType* subDTypep() const override VL_MT_SAFE { return nullptr; } + AstNodeDType* subDTypep() const override VL_MT_STABLE { return nullptr; } AstNodeDType* virtRefDTypep() const override { return nullptr; } void virtRefDTypep(AstNodeDType* nodep) override {} bool similarDType(const AstNodeDType* samep) const override { return this == samep; } diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index 8ceec8cb7..a883caa2f 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -52,7 +52,7 @@ public: void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; // TODO: The only AstNodeExpr without dtype is AstArg. Otherwise this could be final. - bool hasDType() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } virtual string emitVerilog() = 0; /// Format string for verilog writing; see V3EmitV // For documentation on emitC format see EmitCFunc::emitOpName virtual string emitC() = 0; @@ -420,7 +420,7 @@ public: const V3Number& ths) override; string emitVerilog() override { return "%k(%l %f? %r %k: %t)"; } string emitC() override { return "VL_COND_%nq%lq%rq%tq(%nw, %P, %li, %ri, %ti)"; } - string emitSMT() const override { return "(ite %l %r %t)"; } + string emitSMT() const override { return "(ite (__Vbool %l) %r %t)"; } bool cleanOut() const override { return false; } // clean if e1 & e2 clean bool cleanLhs() const override { return true; } bool cleanRhs() const override { return false; } @@ -525,7 +525,7 @@ public: int instrCount() const override { return widthInstrs(); } VAccess access() const { return m_access; } void access(const VAccess& flag) { m_access = flag; } // Avoid using this; Set in constructor - AstVar* varp() const { return m_varp; } // [After Link] Pointer to variable + AstVar* varp() const VL_MT_STABLE { return m_varp; } // [After Link] Pointer to variable void varp(AstVar* varp) { m_varp = varp; dtypeFrom((AstNode*)varp); @@ -578,7 +578,7 @@ public: this->exprp(exprp); } ASTGEN_MEMBERS_AstArg; - bool hasDType() const override { return false; } + bool hasDType() const override VL_MT_SAFE { return false; } string name() const override VL_MT_STABLE { return m_name; } // * = Pin name, ""=go by number void name(const string& name) override { m_name = name; } bool emptyConnectNoNext() const { return !exprp() && name() == "" && !nextp(); } @@ -589,7 +589,7 @@ public: }; class AstAttrOf final : public AstNodeExpr { // Return a value of a attribute, for example a LSB or array LSB of a signal - // @astgen op1 := fromp : Optional[AstNode] // Expr or DType + // @astgen op1 := fromp : Optional[AstNode] // @astgen op2 := dimp : Optional[AstNodeExpr] VAttrType m_attrType; // What sort of extraction public: @@ -1660,6 +1660,17 @@ public: bool same(const AstNode* /*samep*/) const override { return true; } int instrCount() const override { return widthInstrs(); } }; +class AstParseHolder final : public AstNodeExpr { + // A reference to something soon to replace, used in a select at parse time + // that needs conversion to pull the upper lvalue later +public: + AstParseHolder(FileLine* fl) + : ASTGEN_SUPER_ParseHolder(fl) {} + ASTGEN_MEMBERS_AstParseHolder; + string emitVerilog() override { V3ERROR_NA_RETURN(""); } + string emitC() override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const override { V3ERROR_NA_RETURN(true); } +}; class AstParseRef final : public AstNodeExpr { // A reference to a variable, function or task // We don't know which at parse time due to bison constraints @@ -2014,12 +2025,12 @@ public: } ASTGEN_MEMBERS_AstSelLoopVars; bool same(const AstNode* /*samep*/) const override { return true; } - bool maybePointedTo() const override { return false; } + bool maybePointedTo() const override VL_MT_SAFE { return false; } string emitVerilog() override { V3ERROR_NA_RETURN(""); } string emitC() override { V3ERROR_NA_RETURN(""); } bool cleanOut() const override { V3ERROR_NA_RETURN(true); } - bool hasDType() const override { return false; } + bool hasDType() const override VL_MT_SAFE { return false; } }; class AstSetAssoc final : public AstNodeExpr { // Set an assoc array element and return object, '{} @@ -2583,7 +2594,7 @@ public: } string emitVerilog() override { return "%k(%l %f==? %r)"; } string emitC() override { return "VL_EQ_%lq(%lW, %P, %li, %ri)"; } - string emitSMT() const override { return "(= %l %r)"; } + string emitSMT() const override { return "(__Vbv (= %l %r))"; } string emitSimpleOperator() override { return "=="; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -2706,7 +2717,7 @@ public: } string emitVerilog() override { return "%k(%l %f> %r)"; } string emitC() override { return "VL_GT_%lq(%lW, %P, %li, %ri)"; } - string emitSMT() const override { return "(bvugt %l %r)"; } + string emitSMT() const override { return "(__Vbv (bvugt %l %r))"; } string emitSimpleOperator() override { return ">"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -2777,7 +2788,7 @@ public: } string emitVerilog() override { return "%k(%l %f> %r)"; } string emitC() override { return "VL_GTS_%nq%lq%rq(%lw, %P, %li, %ri)"; } - string emitSMT() const override { return "(bvsgt %l %r)"; } + string emitSMT() const override { return "(__Vbv (bvsgt %l %r))"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -2801,7 +2812,7 @@ public: } string emitVerilog() override { return "%k(%l %f>= %r)"; } string emitC() override { return "VL_GTE_%lq(%lW, %P, %li, %ri)"; } - string emitSMT() const override { return "(bvuge %l %r)"; } + string emitSMT() const override { return "(__Vbv (bvuge %l %r))"; } string emitSimpleOperator() override { return ">="; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -2872,7 +2883,7 @@ public: } string emitVerilog() override { return "%k(%l %f>= %r)"; } string emitC() override { return "VL_GTES_%nq%lq%rq(%lw, %P, %li, %ri)"; } - string emitSMT() const override { return "(bvsge %l %r)"; } + string emitSMT() const override { return "(__Vbv (bvsge %l %r))"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -2896,7 +2907,7 @@ public: } string emitVerilog() override { return "%k(%l %f&& %r)"; } string emitC() override { return "VL_LOGAND_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } - string emitSMT() const override { return "(and %l %r)"; } + string emitSMT() const override { return "(bvand %l %r)"; } string emitSimpleOperator() override { return "&&"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -2920,7 +2931,7 @@ public: } string emitVerilog() override { return "%k(%l %f-> %r)"; } string emitC() override { return "VL_LOGIF_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } - string emitSMT() const override { return "(=> %l %r)"; } + string emitSMT() const override { return "(__Vbv (=> (__Vbool %l) (__Vbool %r)))"; } string emitSimpleOperator() override { return "->"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -2944,7 +2955,7 @@ public: } string emitVerilog() override { return "%k(%l %f|| %r)"; } string emitC() override { return "VL_LOGOR_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } - string emitSMT() const override { return "(or %l %r)"; } + string emitSMT() const override { return "(bvor %l %r)"; } string emitSimpleOperator() override { return "||"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -2968,7 +2979,7 @@ public: } string emitVerilog() override { return "%k(%l %f< %r)"; } string emitC() override { return "VL_LT_%lq(%lW, %P, %li, %ri)"; } - string emitSMT() const override { return "(bvult %l %r)"; } + string emitSMT() const override { return "(__Vbv (bvult %l %r))"; } string emitSimpleOperator() override { return "<"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -3039,7 +3050,7 @@ public: } string emitVerilog() override { return "%k(%l %f< %r)"; } string emitC() override { return "VL_LTS_%nq%lq%rq(%lw, %P, %li, %ri)"; } - string emitSMT() const override { return "(bvslt %l %r)"; } + string emitSMT() const override { return "(__Vbv (bvslt %l %r))"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -3063,7 +3074,7 @@ public: } string emitVerilog() override { return "%k(%l %f<= %r)"; } string emitC() override { return "VL_LTE_%lq(%lW, %P, %li, %ri)"; } - string emitSMT() const override { return "(bvule %l %r)"; } + string emitSMT() const override { return "(__Vbv (bvule %l %r))"; } string emitSimpleOperator() override { return "<="; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -3134,7 +3145,7 @@ public: } string emitVerilog() override { return "%k(%l %f<= %r)"; } string emitC() override { return "VL_LTES_%nq%lq%rq(%lw, %P, %li, %ri)"; } - string emitSMT() const override { return "(bvsle %l %r)"; } + string emitSMT() const override { return "(__Vbv (bvsle %l %r))"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -3637,7 +3648,7 @@ public: } string emitVerilog() override { return "%k(%l %f== %r)"; } string emitC() override { return "VL_EQ_%lq(%lW, %P, %li, %ri)"; } - string emitSMT() const override { return "(= %l %r)"; } + string emitSMT() const override { return "(__Vbv (= %l %r))"; } string emitSimpleOperator() override { return "=="; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -3779,7 +3790,7 @@ public: string emitVerilog() override { return "%k(%l %f!= %r)"; } string emitC() override { return "VL_NEQ_%lq(%lW, %P, %li, %ri)"; } string emitSimpleOperator() override { return "!="; } - string emitSMT() const override { return "(not (= %l %r))"; } + string emitSMT() const override { return "(__Vbv (not (= %l %r)))"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } bool cleanRhs() const override { return true; } @@ -4136,6 +4147,7 @@ public: } string emitVerilog() override { return "%k(%l%f[%r])"; } string emitC() override { return "%li%k[%ri]"; } + string emitSMT() const override { return "(select %l %r)"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return false; } bool cleanRhs() const override { return true; } @@ -4176,8 +4188,9 @@ public: bool cleanRhs() const override { return true; } bool sizeMattersLhs() const override { return false; } bool sizeMattersRhs() const override { return false; } - bool isGateOptimizable() const override { return true; } // esp for V3Const::ifSameAssign + bool isGateOptimizable() const override { return false; } // AssocSel creates on miss bool isPredictOptimizable() const override { return false; } + bool isPure() override { return false; } // AssocSel creates on miss bool same(const AstNode* /*samep*/) const override { return true; } int instrCount() const override { return widthInstrs(); } }; @@ -4411,6 +4424,8 @@ class AstSelBit final : public AstNodePreSel { // Single bit range extraction, perhaps with non-constant selection or array selection // Gets replaced during link with AstArraySel or AstSel // @astgen alias op2 := bitp +private: + VAccess m_access; // Left hand side assignment public: AstSelBit(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp) : ASTGEN_SUPER_SelBit(fl, fromp, bitp, nullptr) { @@ -4418,6 +4433,8 @@ public: "not coded to create after dtypes resolved"); } ASTGEN_MEMBERS_AstSelBit; + VAccess access() const { return m_access; } + void access(const VAccess& flag) { m_access = flag; } }; class AstSelExtract final : public AstNodePreSel { // Range extraction, gets replaced with AstSel @@ -4692,8 +4709,8 @@ public: int widthConst() const { return VN_AS(widthp(), Const)->toSInt(); } int lsbConst() const { return VN_AS(lsbp(), Const)->toSInt(); } int msbConst() const { return lsbConst() + widthConst() - 1; } - VNumRange& declRange() { return m_declRange; } - const VNumRange& declRange() const { return m_declRange; } + VNumRange& declRange() VL_MT_STABLE { return m_declRange; } + const VNumRange& declRange() const VL_MT_STABLE { return m_declRange; } void declRange(const VNumRange& flag) { m_declRange = flag; } int declElWidth() const { return m_declElWidth; } void declElWidth(int flag) { m_declElWidth = flag; } @@ -4727,8 +4744,8 @@ public: bool same(const AstNode*) const override { return true; } int instrCount() const override { return 10; } // Removed before matters // For widthConst()/loConst etc, see declRange().elements() and other VNumRange methods - VNumRange& declRange() { return m_declRange; } - const VNumRange& declRange() const { return m_declRange; } + VNumRange& declRange() VL_MT_STABLE { return m_declRange; } + const VNumRange& declRange() const VL_MT_STABLE { return m_declRange; } void declRange(const VNumRange& flag) { m_declRange = flag; } }; class AstSubstrN final : public AstNodeTriop { @@ -5150,7 +5167,7 @@ public: void numberOperate(V3Number& out, const V3Number& lhs) override { out.opLogNot(lhs); } string emitVerilog() override { return "%f(! %l)"; } string emitC() override { return "VL_LOGNOT_%nq%lq(%nw,%lw, %P, %li)"; } - string emitSMT() const override { return "(not %l)"; } + string emitSMT() const override { return "(__Vbv (not (__Vbool %l)))"; } string emitSimpleOperator() override { return "!"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index 926c19719..8387f70c9 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -125,7 +125,7 @@ public: void dump(std::ostream& str = std::cout) const override; void dumpJson(std::ostream& str = std::cout) const override; string name() const override VL_MT_STABLE { return m_name; } // * = Var name - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } bool isGateOptimizable() const override { return !((m_dpiExport || m_dpiImport) && !m_dpiPure); } @@ -193,6 +193,7 @@ public: isHideLocal(fromp->isHideLocal()); isHideProtected(fromp->isHideProtected()); isVirtual(fromp->isVirtual()); + isStatic(fromp->isStatic()); lifetime(fromp->lifetime()); underGenerate(fromp->underGenerate()); } @@ -263,7 +264,7 @@ public: ASTGEN_MEMBERS_AstNodeModule; void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } string name() const override VL_MT_STABLE { return m_name; } virtual bool timescaleMatters() const = 0; // ACCESSORS @@ -371,7 +372,7 @@ public: ASTGEN_MEMBERS_AstNodeAssign; // Clone single node, just get same type back. virtual AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) = 0; - bool hasDType() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } virtual bool cleanRhs() const { return true; } int instrCount() const override { return widthInstrs(); } bool same(const AstNode*) const override { return true; } @@ -421,7 +422,7 @@ public: void name(const string& name) override { m_name = name; } void dump(std::ostream& str = std::cout) const override; void dumpJson(std::ostream& str = std::cout) const override; - VAssertType type() const { return m_type; } + VAssertType type() const VL_MT_SAFE { return m_type; } VAssertDirectiveType directive() const { return m_directive; } bool immediate() const { return this->type().containsAny(VAssertType::SIMPLE_IMMEDIATE @@ -673,7 +674,7 @@ public: } ASTGEN_MEMBERS_AstCFunc; string name() const override VL_MT_STABLE { return m_name; } - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } void dump(std::ostream& str = std::cout) const override; void dumpJson(std::ostream& str = std::cout) const override; bool same(const AstNode* samep) const override { @@ -830,7 +831,7 @@ public: void cloneRelink() override {} // TODO V3Param shouldn't require avoiding cloneRelinkGen void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } // ACCESSORS string name() const override VL_MT_STABLE { return m_name; } // * = Cell name void name(const string& name) override { m_name = name; } @@ -872,7 +873,7 @@ public: void dumpJson(std::ostream& str) const override; // ACCESSORS string name() const override VL_MT_STABLE { return m_name; } // * = Cell name - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } string origModName() const { return m_origModName; } // * = modp()->origName() before inlining void name(const string& name) override { m_name = name; } void timeunit(const VTimescale& flag) { m_timeunit = flag; } @@ -900,7 +901,7 @@ public: void dumpJson(std::ostream& str) const override; // ACCESSORS string name() const override VL_MT_STABLE { return m_cellp->name(); } - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } AstScope* scopep() const VL_MT_STABLE { return m_scopep; } // Pointer to scope it's under string origModName() const { return m_cellp->origModName(); @@ -926,7 +927,7 @@ public: ASTGEN_MEMBERS_AstClassExtends; void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; - bool hasDType() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } string verilogKwd() const override { return isImplements() ? "implements" : "extends"; } // Class being extended (after link and instantiation if needed) AstClass* classOrNullp() const; @@ -961,6 +962,7 @@ public: std::string name() const override VL_MT_STABLE { return m_name; } bool isDefault() const { return m_isDefault; } bool isGlobal() const { return m_isGlobal; } + AstVar* ensureEventp(bool childDType = false); }; class AstClockingItem final : public AstNode { // Parents: CLOCKING @@ -987,7 +989,7 @@ public: VDirection direction() const { return m_direction; } AstClockingItem* outputp() const { return m_outputp; } void outputp(AstClockingItem* outputp) { m_outputp = outputp; } - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } }; class AstConstPool final : public AstNode { // Container for const static data @@ -1003,7 +1005,7 @@ class AstConstPool final : public AstNode { public: explicit AstConstPool(FileLine* fl); ASTGEN_MEMBERS_AstConstPool; - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } void cloneRelink() override { V3ERROR_NA; } AstModule* modp() const { return m_modp; } @@ -1035,7 +1037,7 @@ public: string name() const override VL_MT_STABLE { return m_name; } // * = Scope name bool isGateOptimizable() const override { return false; } bool isPredictOptimizable() const override { return false; } - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } bool same(const AstNode* /*samep*/) const override { return true; } void isStatic(bool flag) { m_isStatic = flag; } bool isStatic() const { return m_isStatic; } @@ -1173,8 +1175,8 @@ public: this->valuep(valuep); } ASTGEN_MEMBERS_AstInitItem; - bool maybePointedTo() const override { return true; } - bool hasDType() const override { return false; } // See valuep()'s dtype instead + bool maybePointedTo() const override VL_MT_SAFE { return true; } + bool hasDType() const override VL_MT_SAFE { return false; } // See valuep()'s dtype instead }; class AstIntfRef final : public AstNode { // An interface reference @@ -1223,7 +1225,7 @@ public: this->addVarsp(varsp); } string name() const override VL_MT_STABLE { return m_name; } - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } ASTGEN_MEMBERS_AstModport; }; class AstModportFTaskRef final : public AstNode { @@ -1268,7 +1270,7 @@ public: string name() const override VL_MT_STABLE { return m_name; } void direction(const VDirection& flag) { m_direction = flag; } VDirection direction() const { return m_direction; } - AstVar* varp() const { return m_varp; } // [After Link] Pointer to variable + AstVar* varp() const VL_MT_STABLE { return m_varp; } // [After Link] Pointer to variable void varp(AstVar* varp) { m_varp = varp; } }; class AstNetlist final : public AstNode { @@ -1338,19 +1340,32 @@ class AstPackageExport final : public AstNode { // A package export declaration // // @astgen ptr := m_packagep : Optional[AstPackage] // Package hierarchy - string m_name; + string m_name; // What imported e.g. "*" + string m_pkgName; // Module the cell instances public: AstPackageExport(FileLine* fl, AstPackage* packagep, const string& name) : ASTGEN_SUPER_PackageExport(fl) , m_name{name} - , m_packagep{packagep} {} + , m_packagep{packagep} { + pkgNameFrom(); + } + AstPackageExport(FileLine* fl, const string& pkgName, const string& name) + : ASTGEN_SUPER_PackageExport(fl) + , m_name{name} + , m_pkgName{pkgName} + , m_packagep{nullptr} {} ASTGEN_MEMBERS_AstPackageExport; void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; string name() const override VL_MT_STABLE { return m_name; } + string pkgName() const VL_MT_STABLE { return m_pkgName; } + string prettyPkgNameQ() const { return "'" + prettyName(pkgName()) + "'"; } AstPackage* packagep() const { return m_packagep; } void packagep(AstPackage* nodep) { m_packagep = nodep; } + +private: + void pkgNameFrom(); }; class AstPackageExportStarStar final : public AstNode { // A package export *::* declaration @@ -1364,23 +1379,36 @@ class AstPackageImport final : public AstNode { // A package import declaration // // @astgen ptr := m_packagep : Optional[AstPackage] // Package hierarchy - string m_name; + string m_name; // What imported e.g. "*" + string m_pkgName; // Module the cell instances public: AstPackageImport(FileLine* fl, AstPackage* packagep, const string& name) : ASTGEN_SUPER_PackageImport(fl) , m_name{name} - , m_packagep{packagep} {} + , m_packagep{packagep} { + pkgNameFrom(); + } + AstPackageImport(FileLine* fl, const string& pkgName, const string& name) + : ASTGEN_SUPER_PackageImport(fl) + , m_name{name} + , m_pkgName{pkgName} + , m_packagep{nullptr} {} ASTGEN_MEMBERS_AstPackageImport; void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; string name() const override VL_MT_STABLE { return m_name; } + string pkgName() const VL_MT_STABLE { return m_pkgName; } + string prettyPkgNameQ() const { return "'" + prettyName(pkgName()) + "'"; } AstPackage* packagep() const { return m_packagep; } void packagep(AstPackage* nodep) { m_packagep = nodep; } + +private: + void pkgNameFrom(); }; class AstPin final : public AstNode { // A port or parameter assignment on an instantiation - // @astgen op1 := exprp : Optional[AstNode] // NodeExpr or NodeDType (nullptr if unconnected) + // @astgen op1 := exprp : Optional[AstNode] // nullptr=unconnected // // @astgen ptr := m_modVarp : Optional[AstVar] // Input/output connects to on submodule // @astgen ptr := m_modPTypep : Optional[AstParamTypeDType] // Param type connects to on sub @@ -1462,7 +1490,7 @@ public: this->propp(propp); } ASTGEN_MEMBERS_AstPropSpec; - bool hasDType() const override { + bool hasDType() const override VL_MT_SAFE { return true; } // Used under Cover, which expects a bool child }; @@ -1511,7 +1539,7 @@ public: BROKEN_RTN(!m_modp); return nullptr; } - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } string name() const override VL_MT_STABLE { return m_name; } // * = Scope name void name(const string& name) override { m_name = name; } void dump(std::ostream& str) const override; @@ -1593,7 +1621,7 @@ public: ASTGEN_MEMBERS_AstSenTree; void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } bool isMulti() const { return m_multi; } void multi(bool flag) { m_multi = true; } // METHODS @@ -1643,7 +1671,7 @@ class AstTopScope final : public AstNode { public: ASTGEN_MEMBERS_AstTopScope; - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } }; class AstTypeTable final : public AstNode { // Container for hash of standard data types @@ -1662,7 +1690,7 @@ class AstTypeTable final : public AstNode { public: explicit AstTypeTable(FileLine* fl); ASTGEN_MEMBERS_AstTypeTable; - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } void cloneRelink() override { V3ERROR_NA; } AstBasicDType* findBasicDType(FileLine* fl, VBasicDTypeKwd kwd); AstBasicDType* findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, int width, int widthMin, @@ -1687,12 +1715,16 @@ class AstTypedef final : public AstNode { string m_name; string m_tag; // Holds the string of the verilator tag -- used in XML output. bool m_attrPublic = false; + bool m_isHideLocal : 1; // Verilog local + bool m_isHideProtected : 1; // Verilog protected public: AstTypedef(FileLine* fl, const string& name, AstNode* attrsp, VFlagChildDType, AstNodeDType* dtp) : ASTGEN_SUPER_Typedef(fl) - , m_name{name} { + , m_name{name} + , m_isHideLocal{false} + , m_isHideProtected{false} { childDTypep(dtp); // Only for parser addAttrsp(attrsp); dtypep(nullptr); // V3Width will resolve @@ -1706,11 +1738,15 @@ public: } // METHODS string name() const override VL_MT_STABLE { return m_name; } - bool maybePointedTo() const override { return true; } - bool hasDType() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } void name(const string& flag) override { m_name = flag; } bool attrPublic() const { return m_attrPublic; } void attrPublic(bool flag) { m_attrPublic = flag; } + bool isHideLocal() const { return m_isHideLocal; } + void isHideLocal(bool flag) { m_isHideLocal = flag; } + bool isHideProtected() const { return m_isHideProtected; } + void isHideProtected(bool flag) { m_isHideProtected = flag; } void tag(const string& text) override { m_tag = text; } string tag() const override { return m_tag; } }; @@ -1725,7 +1761,7 @@ public: ASTGEN_MEMBERS_AstTypedefFwd; // METHODS string name() const override VL_MT_STABLE { return m_name; } - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } }; class AstUdpTable final : public AstNode { // @astgen op1 := linesp : List[AstUdpTableLine] @@ -1745,7 +1781,7 @@ public: , m_text{text} {} ASTGEN_MEMBERS_AstUdpTableLine; string name() const override VL_MT_STABLE { return m_text; } - string text() const { return m_text; } + string text() const VL_MT_SAFE { return m_text; } }; class AstVar final : public AstNode { // A variable (in/out/wire/reg/param) inside a module @@ -1754,7 +1790,8 @@ class AstVar final : public AstNode { // @astgen op2 := delayp : Optional[AstDelay] // Net delay // Initial value that never changes (static const), or constructor argument for // MTASKSTATE variables - // @astgen op3 := valuep : Optional[AstNode] // May be a DType for type parameter defaults + // @astgen op3 := valuep : Optional[AstNode] + // Value is a DType for type parameter defaults // @astgen op4 := attrsp : List[AstNode] // Attributes during early parse // @astgen ptr := m_sensIfacep : Optional[AstIface] // Interface type to which reads from this // var are sensitive @@ -1811,6 +1848,7 @@ class AstVar final : public AstNode { bool m_isForcedByCode : 1; // May be forced/released from AstAssignForce/AstRelease bool m_isWrittenByDpi : 1; // This variable can be written by a DPI Export bool m_isWrittenBySuspendable : 1; // This variable can be written by a suspendable process + bool m_ignorePostWrite : 1; // Ignore writes in 'Post' blocks during ordering void init() { m_ansi = false; @@ -1855,6 +1893,7 @@ class AstVar final : public AstNode { m_isForcedByCode = false; m_isWrittenByDpi = false; m_isWrittenBySuspendable = false; + m_ignorePostWrite = false; m_attrClocker = VVarAttrClocker::CLOCKER_UNKNOWN; } @@ -1906,9 +1945,9 @@ public: void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; bool same(const AstNode* samep) const override; - string name() const override VL_MT_STABLE VL_MT_SAFE { return m_name; } // * = Var name - bool hasDType() const override { return true; } - bool maybePointedTo() const override { return true; } + string name() const override VL_MT_STABLE { return m_name; } // * = Var name + bool hasDType() const override VL_MT_SAFE { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } string origName() const override { return m_origName; } // * = Original name void origName(const string& name) { m_origName = name; } VVarType varType() const VL_MT_SAFE { return m_varType; } // * = Type of variable @@ -2010,6 +2049,8 @@ public: void setWrittenByDpi() { m_isWrittenByDpi = true; } bool isWrittenBySuspendable() const { return m_isWrittenBySuspendable; } void setWrittenBySuspendable() { m_isWrittenBySuspendable = true; } + bool ignorePostWrite() const { return m_ignorePostWrite; } + void setIgnorePostWrite() { m_ignorePostWrite = true; } // METHODS void name(const string& name) override { m_name = name; } @@ -2026,13 +2067,16 @@ public: bool isRef() const VL_MT_SAFE { return m_direction.isRef(); } bool isWritable() const VL_MT_SAFE { return m_direction.isWritable(); } bool isTristate() const { return m_tristate; } - bool isPrimaryIO() const { return m_primaryIO; } + bool isPrimaryIO() const VL_MT_SAFE { return m_primaryIO; } bool isPrimaryInish() const { return isPrimaryIO() && isNonOutput(); } bool isIfaceRef() const { return (varType() == VVarType::IFACEREF); } bool isIfaceParent() const { return m_isIfaceParent; } bool isInternal() const { return m_isInternal; } bool isSignal() const { return varType().isSignal(); } bool isNet() const { return varType().isNet(); } + bool isWor() const { return varType().isWor(); } + bool isWand() const { return varType().isWand(); } + bool isWiredNet() const { return varType().isWiredNet(); } bool isTemp() const { return varType().isTemp(); } bool isToggleCoverable() const { return ((isIO() || isSignal()) @@ -2050,15 +2094,15 @@ public: AstBasicDType* bdtypep = basicp(); return bdtypep && bdtypep->isBitLogic(); } - bool isUsedClock() const { return m_usedClock; } + bool isUsedClock() const VL_MT_SAFE { return m_usedClock; } bool isUsedParam() const { return m_usedParam; } bool isUsedLoopIdx() const { return m_usedLoopIdx; } bool isSc() const VL_MT_SAFE { return m_sc; } bool isScQuad() const; - bool isScBv() const; + bool isScBv() const VL_MT_STABLE; bool isScUint() const; bool isScUintBool() const; - bool isScBigUint() const; + bool isScBigUint() const VL_MT_STABLE; bool isScSensitive() const { return m_scSensitive; } bool isSigPublic() const; bool isSigModPublic() const { return m_sigModPublic; } @@ -2150,12 +2194,12 @@ public: } cloneRelinkGen(); } - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } string name() const override VL_MT_STABLE { return scopep()->name() + "->" + varp()->name(); } void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; bool same(const AstNode* samep) const override; - bool hasDType() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } AstVar* varp() const VL_MT_STABLE { return m_varp; } // [After Link] Pointer to variable AstScope* scopep() const VL_MT_STABLE { return m_scopep; } // Pointer to scope it's under void scopep(AstScope* nodep) { m_scopep = nodep; } @@ -2216,7 +2260,7 @@ public: this->fvarp(fvarp); } ASTGEN_MEMBERS_AstFunc; - bool hasDType() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } AstNodeFTask* cloneType(const string& name) override { return new AstFunc{fileline(), name, nullptr, nullptr}; } @@ -2229,7 +2273,7 @@ public: AstLet(FileLine* fl, const string& name) : ASTGEN_SUPER_Let(fl, name, nullptr) {} ASTGEN_MEMBERS_AstLet; - bool hasDType() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } const char* broken() const override { BROKEN_RTN(!VN_IS(stmtsp(), StmtExpr)); return nullptr; @@ -2242,7 +2286,7 @@ public: AstProperty(FileLine* fl, const string& name, AstNode* stmtp) : ASTGEN_SUPER_Property(fl, name, stmtp) {} ASTGEN_MEMBERS_AstProperty; - bool hasDType() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } AstNodeFTask* cloneType(const string& name) override { return new AstProperty{fileline(), name, nullptr}; } @@ -2262,6 +2306,7 @@ public: class AstCFile final : public AstNodeFile { // C++ output file // Parents: NETLIST + uint64_t m_complexityScore = 0; bool m_slow : 1; ///< Compile w/o optimization bool m_source : 1; ///< Source file (vs header file) bool m_support : 1; ///< Support file (non systemc) @@ -2274,6 +2319,8 @@ public: ASTGEN_MEMBERS_AstCFile; void dump(std::ostream& str = std::cout) const override; void dumpJson(std::ostream& str = std::cout) const override; + uint64_t complexityScore() const { return m_complexityScore; } + void complexityScore(uint64_t newScore) { m_complexityScore = newScore; } bool slow() const { return m_slow; } void slow(bool flag) { m_slow = flag; } bool source() const { return m_source; } @@ -2310,13 +2357,13 @@ public: : ASTGEN_SUPER_Class(fl, name) {} ASTGEN_MEMBERS_AstClass; string verilogKwd() const override { return "class"; } - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; bool timescaleMatters() const override { return false; } - AstClassPackage* classOrPackagep() const VL_MT_SAFE { return m_classOrPackagep; } + AstClassPackage* classOrPackagep() const VL_MT_STABLE { return m_classOrPackagep; } void classOrPackagep(AstClassPackage* classpackagep) { m_classOrPackagep = classpackagep; } - AstNode* membersp() const { return stmtsp(); } + AstNode* membersp() const VL_MT_STABLE { return stmtsp(); } void addMembersp(AstNode* nodep) { addStmtsp(nodep); } bool isExtended() const { return m_extended; } void isExtended(bool flag) { m_extended = flag; } @@ -2349,8 +2396,8 @@ public: && std::is_base_of::value, "Callable 'f' must have a signature compatible with 'void(AstClass*, T_Node*)', " "with 'T_Node' being a subtype of 'AstNode'"); - if (AstClassExtends* const extendsp = this->extendsp()) { - extendsp->classp()->foreachMember(f); + if (AstClassExtends* const cextendsp = this->extendsp()) { + cextendsp->classp()->foreachMember(f); } for (AstNode* stmtp = stmtsp(); stmtp; stmtp = stmtp->nextp()) { if (AstNode::privateTypeTest(stmtp)) f(this, static_cast(stmtp)); @@ -2364,8 +2411,8 @@ public: && std::is_base_of::value, "Predicate 'p' must have a signature compatible with 'bool(const AstClass*, " "const T_Node*)', with 'T_Node' being a subtype of 'AstNode'"); - if (AstClassExtends* const extendsp = this->extendsp()) { - if (extendsp->classp()->existsMember(p)) return true; + if (AstClassExtends* const cextendsp = this->extendsp()) { + if (cextendsp->classp()->existsMember(p)) return true; } for (AstNode* stmtp = stmtsp(); stmtp; stmtp = stmtp->nextp()) { if (AstNode::privateTypeTest(stmtp)) { @@ -2529,7 +2576,7 @@ public: class AstBracketRange final : public AstNodeRange { // Parser only concept "[lhsp]", an AstUnknownRange, QueueRange or Range, // unknown until lhsp type is determined - // @astgen op1 := elementsp : AstNode // Expr or DType + // @astgen op1 := elementsp : AstNode public: AstBracketRange(FileLine* fl, AstNode* elementsp) : ASTGEN_SUPER_BracketRange(fl) { @@ -2541,7 +2588,7 @@ public: bool same(const AstNode* /*samep*/) const override { return true; } // Will be removed in V3Width, which relies on this // being a child not a dtype pointed node - bool maybePointedTo() const override { return false; } + bool maybePointedTo() const override VL_MT_SAFE { return false; } }; class AstRange final : public AstNodeRange { // Range specification, for use under variables and cells @@ -2780,7 +2827,7 @@ public: void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; int instrCount() const override { return 1 + 2 * INSTR_COUNT_LD; } - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } int binNum() const { return m_binNum; } void binNum(int flag) { m_binNum = flag; } int offset() const { return m_offset; } @@ -3065,7 +3112,7 @@ public: ASTGEN_MEMBERS_AstJumpBlock; const char* broken() const override; int instrCount() const override { return 0; } - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } bool same(const AstNode* /*samep*/) const override { return true; } int labelNum() const { return m_labelNum; } void labelNum(int flag) { m_labelNum = flag; } @@ -3111,7 +3158,7 @@ public: : ASTGEN_SUPER_JumpLabel(fl) , m_blockp{blockp} {} ASTGEN_MEMBERS_AstJumpLabel; - bool maybePointedTo() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } const char* broken() const override { BROKEN_RTN(!blockp()->brokeExistsAbove()); BROKEN_RTN(blockp()->labelp() != this); @@ -3269,10 +3316,14 @@ public: bool isPure() override { return exprp()->isPure(); } }; class AstStop final : public AstNodeStmt { + const bool m_isFatal; // $fatal not $stop public: - AstStop(FileLine* fl, bool maybe) - : ASTGEN_SUPER_Stop(fl) {} + AstStop(FileLine* fl, bool isFatal) + : ASTGEN_SUPER_Stop(fl) + , m_isFatal(isFatal) {} ASTGEN_MEMBERS_AstStop; + void dump(std::ostream& str) const override; + void dumpJson(std::ostream& str) const override; bool isGateOptimizable() const override { return false; } bool isPredictOptimizable() const override { return false; } bool isPure() override { return false; } // SPECIAL: $display has 'visual' ordering @@ -3280,6 +3331,8 @@ public: bool isUnlikely() const override { return true; } int instrCount() const override { return 0; } // Rarely executes bool same(const AstNode* samep) const override { return fileline() == samep->fileline(); } + string emitVerilog() const { return m_isFatal ? "$fatal" : "$stop"; } + bool isFatal() const { return m_isFatal; } }; class AstSysFuncAsTask final : public AstNodeStmt { // TODO: This is superseded by AstStmtExpr, remove @@ -3370,8 +3423,8 @@ public: int instrCount() const override { return 100; } // Large... ASTGEN_MEMBERS_AstTraceDecl; string name() const override VL_MT_STABLE { return m_showname; } - bool maybePointedTo() const override { return true; } - bool hasDType() const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } bool same(const AstNode* samep) const override { return false; } string showname() const { return m_showname; } // * = Var name // Details on what we're tracing @@ -3412,7 +3465,7 @@ public: void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; int instrCount() const override { return 10 + 2 * INSTR_COUNT_LD; } - bool hasDType() const override { return true; } + bool hasDType() const override VL_MT_SAFE { return true; } bool same(const AstNode* samep) const override { return declp() == VN_DBG_AS(samep, TraceInc)->declp(); } @@ -3610,6 +3663,7 @@ public: }); } bool brokeLhsMustBeLvalue() const override { return true; } + AstDelay* getLhsNetDelay() const; AstAlways* convertToAlways(); }; diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index a4d3fca90..326a3d77d 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -76,7 +76,12 @@ bool AstNodeFTaskRef::isPure() { // cached. return false; } else { - if (!m_purity.isCached()) m_purity.set(this->getPurityRecurse()); + if (!m_purity.isCached()) { + m_purity.set(true); // To prevent infinite recursion, set to true before getting + // the actual purity. If there are impure statements in the + // task/function, they'll taint this call anyway. + m_purity.set(this->getPurityRecurse()); + } return m_purity.get(); } } @@ -322,6 +327,24 @@ AstNodeExpr* AstInsideRange::newAndFromInside(AstNodeExpr* exprp, AstNodeExpr* l return new AstLogAnd{fileline(), ap, bp}; } +AstVar* AstClocking::ensureEventp(bool childDType) { + if (!eventp()) { + AstVar* const evp + = childDType ? new AstVar{fileline(), VVarType::MODULETEMP, m_name, VFlagChildDType{}, + new AstBasicDType{fileline(), VBasicDTypeKwd::EVENT}} + : new AstVar{fileline(), VVarType::MODULETEMP, m_name, + findBasicDType(VBasicDTypeKwd::EVENT)}; + evp->lifetime(VLifetime::STATIC); + eventp(evp); + // Trigger the clocking event in Observed (IEEE 1800-2023 14.13) + addNextHere(new AstAlwaysObserved{ + fileline(), new AstSenTree{fileline(), sensesp()->cloneTree(false)}, + new AstFireEvent{fileline(), new AstVarRef{fileline(), evp, VAccess::WRITE}, false}}); + v3Global.setHasEvents(); + } + return eventp(); +} + void AstConsDynArray::dump(std::ostream& str) const { this->AstNodeExpr::dump(str); if (lhsIsValue()) str << " [LVAL]"; @@ -2008,9 +2031,10 @@ void AstRefDType::dump(std::ostream& str) const { if (!s_recursing) { // Prevent infinite dump if circular typedefs s_recursing = true; str << " -> "; - if (const auto subp = typedefp()) { + if (const auto subp = subDTypep()) { + if (typedefp()) str << "typedef=" << static_cast(typedefp()) << " -> "; subp->dump(str); - } else if (const auto subp = subDTypep()) { + } else if (const auto subp = typedefp()) { subp->dump(str); } s_recursing = false; @@ -2173,14 +2197,28 @@ void AstNodeModule::dumpJson(std::ostream& str) const { } void AstPackageExport::dump(std::ostream& str) const { this->AstNode::dump(str); - str << " -> " << packagep(); + if (packagep()) { + str << " -> " << packagep(); + } else { + str << " ->UNLINKED:" << pkgName(); + } } void AstPackageExport::dumpJson(std::ostream& str) const { dumpJsonGen(str); } +void AstPackageExport::pkgNameFrom() { + if (packagep()) m_pkgName = packagep()->name(); +} void AstPackageImport::dump(std::ostream& str) const { this->AstNode::dump(str); - str << " -> " << packagep(); + if (packagep()) { + str << " -> " << packagep(); + } else { + str << " ->UNLINKED:" << pkgName(); + } } void AstPackageImport::dumpJson(std::ostream& str) const { dumpJsonGen(str); } +void AstPackageImport::pkgNameFrom() { + if (packagep()) m_pkgName = packagep()->name(); +} void AstPatMember::dump(std::ostream& str) const { this->AstNodeExpr::dump(str); if (isDefault()) str << " [DEFAULT]"; @@ -2676,6 +2714,14 @@ void AstFork::dumpJson(std::ostream& str) const { dumpJsonStr(str, "joinType", joinType().ascii()); dumpJsonGen(str); } +void AstStop::dump(std::ostream& str) const { + this->AstNodeStmt::dump(str); + if (isFatal()) str << " [FATAL]"; +} +void AstStop::dumpJson(std::ostream& str) const { + dumpJsonBoolFunc(str, isFatal); + dumpJsonGen(str); +} void AstTraceDecl::dump(std::ostream& str) const { this->AstNodeStmt::dump(str); if (code()) str << " [code=" << code() << "]"; @@ -2788,6 +2834,7 @@ void AstCMethodHard::setPurity() { {"assign", false}, {"at", true}, {"atBack", true}, + {"atWrite", true}, {"awaitingCurrentTime", true}, {"clear", false}, {"clearFired", false}, @@ -2851,9 +2898,28 @@ void AstCMethodHard::setPurity() { {"word", true}, {"write_var", false}}; + if (name() == "atWriteAppend" || name() == "atWriteAppendBack") { + m_pure = false; + // Treat atWriteAppend as pure if the argument is a loop iterator + if (AstNodeExpr* const argp = pinsp()) { + if (AstVarRef* const varrefp = VN_CAST(argp, VarRef)) { + if (varrefp->varp()->isUsedLoopIdx()) m_pure = true; + } + } + return; + } auto isPureIt = isPureMethod.find(name()); UASSERT_OBJ(isPureIt != isPureMethod.end(), this, "Unknown purity of method " + name()); m_pure = isPureIt->second; + if (!m_pure) return; + if (!fromp()->isPure()) m_pure = false; + if (!m_pure) return; + for (AstNodeExpr* argp = pinsp(); argp; argp = VN_AS(argp->nextp(), NodeExpr)) { + if (!argp->isPure()) { + m_pure = false; + return; + } + } } void AstCUse::dump(std::ostream& str) const { @@ -2865,6 +2931,15 @@ void AstCUse::dumpJson(std::ostream& str) const { dumpJsonGen(str); } +static AstDelay* getLhsNetDelayRecurse(const AstNodeExpr* const nodep) { + if (const AstNodeVarRef* const refp = VN_CAST(nodep, NodeVarRef)) { + if (refp->varp()->delayp()) return refp->varp()->delayp(); + } else if (const AstNodeSel* const selp = VN_CAST(nodep, NodeSel)) { + return getLhsNetDelayRecurse(selp->fromp()); + } + return nullptr; +} +AstDelay* AstAssignW::getLhsNetDelay() const { return getLhsNetDelayRecurse(lhsp()); } AstAlways* AstAssignW::convertToAlways() { const bool hasTimingControl = isTimingControl(); AstNodeExpr* const lhs1p = lhsp()->unlinkFrBack(); diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp index 5a9ced53c..d6e881f40 100644 --- a/src/V3Begin.cpp +++ b/src/V3Begin.cpp @@ -427,7 +427,9 @@ AstNode* V3Begin::convertToWhile(AstForeach* nodep) { AstNode* bodyPointp = new AstBegin{nodep->fileline(), "[EditWrapper]", nullptr}; AstNode* newp = nullptr; AstNode* lastp = nodep; - + // subfromp used to traverse each dimension of multi-d variable-sized unpacked array (queue, + // dyn-arr and associative-arr) + AstNodeExpr* subfromp = fromp->cloneTreePure(false); // Major dimension first for (AstNode *argsp = loopsp->elementsp(), *next_argsp; argsp; argsp = next_argsp) { next_argsp = argsp->nextp(); @@ -458,7 +460,10 @@ AstNode* V3Begin::convertToWhile(AstForeach* nodep) { } else if (VN_IS(fromDtp, DynArrayDType) || VN_IS(fromDtp, QueueDType)) { AstConst* const leftp = new AstConst{fl, 0}; AstNodeExpr* const rightp - = new AstCMethodHard{fl, fromp->cloneTreePure(false), "size"}; + = new AstCMethodHard{fl, subfromp->cloneTreePure(false), "size"}; + AstVarRef* varRefp = new AstVarRef{fl, varp, VAccess::READ}; + subfromp = new AstCMethodHard{fl, subfromp, "at", varRefp}; + subfromp->dtypep(fromDtp); rightp->dtypeSetSigned32(); rightp->protect(false); loopp = createForeachLoop(nodep, bodyPointp, varp, leftp, rightp, VNType::atLt); @@ -473,13 +478,16 @@ AstNode* V3Begin::convertToWhile(AstForeach* nodep) { first_varp->usedLoopIdx(true); first_varp->lifetime(VLifetime::AUTOMATIC); AstNodeExpr* const firstp - = new AstCMethodHard{fl, fromp->cloneTreePure(false), "first", + = new AstCMethodHard{fl, subfromp->cloneTreePure(false), "first", new AstVarRef{fl, varp, VAccess::READWRITE}}; firstp->dtypeSetSigned32(); AstNodeExpr* const nextp - = new AstCMethodHard{fl, fromp->cloneTreePure(false), "next", + = new AstCMethodHard{fl, subfromp->cloneTreePure(false), "next", new AstVarRef{fl, varp, VAccess::READWRITE}}; nextp->dtypeSetSigned32(); + AstVarRef* varRefp = new AstVarRef{fl, varp, VAccess::READ}; + subfromp = new AstCMethodHard{fl, subfromp, "at", varRefp}; + subfromp->dtypep(fromDtp); AstNode* const first_clearp = new AstAssign{fl, new AstVarRef{fl, first_varp, VAccess::WRITE}, new AstConst{fl, AstConst::BitFalse{}}}; diff --git a/src/V3Begin.h b/src/V3Begin.h index ac65da30f..5be8886e0 100644 --- a/src/V3Begin.h +++ b/src/V3Begin.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; class AstNode; class AstForeach; diff --git a/src/V3Branch.h b/src/V3Branch.h index 7357ef907..5d7f291c8 100644 --- a/src/V3Branch.h +++ b/src/V3Branch.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3CCtors.h b/src/V3CCtors.h index b719ee466..aa8b84f38 100644 --- a/src/V3CCtors.h +++ b/src/V3CCtors.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - //============================================================================ class V3CCtors final { diff --git a/src/V3CUse.h b/src/V3CUse.h index 5c864adba..8102c823e 100644 --- a/src/V3CUse.h +++ b/src/V3CUse.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - //============================================================================ class V3CUse final { diff --git a/src/V3Case.h b/src/V3Case.h index 7233866ed..bc2fdac11 100644 --- a/src/V3Case.h +++ b/src/V3Case.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; class AstNodeCase; diff --git a/src/V3Cast.h b/src/V3Cast.h index d519b5c74..15cee107e 100644 --- a/src/V3Cast.h +++ b/src/V3Cast.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Class.h b/src/V3Class.h index 072566cab..d23c4bd21 100644 --- a/src/V3Class.h +++ b/src/V3Class.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Clean.h b/src/V3Clean.h index 5112001fd..f7d40f4fc 100644 --- a/src/V3Clean.h +++ b/src/V3Clean.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp index 0c67de410..4739d6982 100644 --- a/src/V3Clock.cpp +++ b/src/V3Clock.cpp @@ -31,7 +31,7 @@ #include "V3Clock.h" -#include "V3Sched.h" +#include "V3Const.h" VL_DEFINE_DEBUG_FUNCTIONS; @@ -176,6 +176,11 @@ public: // CONSTRUCTORS explicit ClockVisitor(AstNetlist* netlistp) { m_evalp = netlistp->evalp(); + // Simplify all SenTrees + for (AstSenTree* senTreep = netlistp->topScopep()->senTreesp(); senTreep; + senTreep = VN_AS(senTreep->nextp(), SenTree)) { + V3Const::constifyExpensiveEdit(senTreep); + } iterate(netlistp); } ~ClockVisitor() override = default; diff --git a/src/V3Clock.h b/src/V3Clock.h index ab7906645..f7fc9d31d 100644 --- a/src/V3Clock.h +++ b/src/V3Clock.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Combine.h b/src/V3Combine.h index 8778f7eaa..3f84519c8 100644 --- a/src/V3Combine.h +++ b/src/V3Combine.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Common.cpp b/src/V3Common.cpp index 04e44b88e..abf3eb5e0 100644 --- a/src/V3Common.cpp +++ b/src/V3Common.cpp @@ -31,6 +31,24 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### // Common component builders +string V3Common::makeToStringCall(AstNodeDType* nodep, const std::string& lhs) { + std::string stmt; + if (VN_IS(nodep->skipRefp(), BasicDType) && nodep->isWide()) { + stmt += "VL_TO_STRING_W("; + stmt += cvtToStr(nodep->widthWords()); + stmt += ", "; + } else if (VN_IS(nodep->skipRefp(), BasicDType) && nodep->isWide()) { + stmt += "VL_TO_STRING_W("; + stmt += cvtToStr(nodep->widthWords()); + stmt += ", "; + } else { + stmt += "VL_TO_STRING("; + } + stmt += lhs; + stmt += ")"; + return stmt; +} + static void makeVlToString(AstClass* nodep) { AstCFunc* const funcp = new AstCFunc{nodep->fileline(), "VL_TO_STRING", nullptr, "std::string"}; @@ -78,14 +96,8 @@ static void makeVlToString(AstNodeUOrStructDType* nodep) { stmt += ", "; } stmt += VIdProtect::protect(itemp->prettyName()) + ":\" + "; - if (VN_IS(itemp->dtypep()->skipRefp(), BasicDType) && itemp->isWide()) { - stmt += "VL_TO_STRING_W("; - stmt += cvtToStr(itemp->widthWords()); - stmt += ", "; - } else { - stmt += "VL_TO_STRING("; - } - stmt += "obj." + itemp->nameProtect() + ");\n"; + stmt += V3Common::makeToStringCall(itemp->dtypep(), "obj."s + itemp->nameProtect()); + stmt += ";\n"; funcp->addStmtsp(new AstCStmt{nodep->fileline(), stmt}); } funcp->addStmtsp(new AstCStmt{nodep->fileline(), "out += \"}\";\n"}); @@ -121,15 +133,8 @@ static void makeToStringMiddle(AstClass* nodep) { comma = ", "; stmt += itemp->origNameProtect(); stmt += ":\" + "; - if (VN_IS(itemp->dtypep()->skipRefp(), BasicDType) && itemp->isWide()) { - stmt += "VL_TO_STRING_W("; - stmt += cvtToStr(itemp->widthWords()); - stmt += ", "; - } else { - stmt += "VL_TO_STRING("; - } - stmt += itemp->nameProtect(); - stmt += ");\n"; + stmt += V3Common::makeToStringCall(itemp->dtypep(), itemp->nameProtect()); + stmt += ";\n"; nodep->user1(true); // So what we extend dumps this funcp->addStmtsp(new AstCStmt{nodep->fileline(), stmt}); } diff --git a/src/V3Common.h b/src/V3Common.h index bc3e0e9dc..249b985e0 100644 --- a/src/V3Common.h +++ b/src/V3Common.h @@ -20,13 +20,14 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" +class AstNodeDType; //============================================================================ class V3Common final { public: static void commonAll() VL_MT_DISABLED; + static string makeToStringCall(AstNodeDType* nodep, const std::string& lhs); }; #endif // Guard diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 54c1d3704..dbe81ed4a 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -20,7 +20,7 @@ // If operands are constant, replace this node with constant. //************************************************************************* -#define VL_MT_DISABLED_CODE_UNIT 1 +#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT #include "config_build.h" #include "verilatedos.h" @@ -548,6 +548,7 @@ class ConstBitOpTreeVisitor final : public VNVisitorConst { VL_RESTORER(m_leafp); Restorer restorer{*this}; LeafInfo leafInfo{m_lsb}; + // cppcheck-suppress danglingLifetime m_leafp = &leafInfo; AstNodeExpr* opp = right ? nodep->rhsp() : nodep->lhsp(); const bool origFailed = m_failed; @@ -1161,11 +1162,10 @@ class ConstVisitor final : public VNVisitor { } else if (const AstShiftL* const shiftp = VN_CAST(nodep->rhsp(), ShiftL)) { if (const AstConst* const scp = VN_CAST(shiftp->rhsp(), Const)) { // Check if mask is full over the non-zero bits - V3Number maskLo{nodep, nodep->width()}; - V3Number maskHi{nodep, nodep->width()}; - maskLo.setMask(nodep->width() - scp->num().toUInt()); - maskHi.opShiftL(maskLo, scp->num()); - return checkMask(maskHi); + V3Number mask{nodep, nodep->width()}; + const uint32_t shiftAmount = scp->num().toUInt(); + mask.setMask(nodep->width() - shiftAmount, shiftAmount); + return checkMask(mask); } } return false; diff --git a/src/V3Const.h b/src/V3Const.h index 20e1bb95d..5395a7cb4 100644 --- a/src/V3Const.h +++ b/src/V3Const.h @@ -21,7 +21,6 @@ #include "verilatedos.h" #include "V3Ast.h" -#include "V3ThreadSafety.h" //============================================================================ diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp index 486fccc56..7f36c409f 100644 --- a/src/V3Coverage.cpp +++ b/src/V3Coverage.cpp @@ -65,22 +65,24 @@ class CoverageVisitor final : public VNVisitor { && v3Global.opt.coverageLine(); } }; - int m_nextHandle = 0; // NODE STATE // Entire netlist: // AstIf::user1() -> bool. True indicates ifelse processed const VNUser1InUse m_inuser1; - // STATE + // STATE - across all visitors + int m_nextHandle = 0; + + // STATE - for current visit position (use VL_RESTORER) CheckState m_state; // State save-restored on each new coverage scope/block AstNodeModule* m_modp = nullptr; // Current module to add statement to bool m_inToggleOff = false; // In function/task etc - // Uniquification of inserted variable names - std::unordered_map m_varnames; string m_beginHier; // AstBegin hier name for user coverage points - std::unordered_map - m_handleLines; // All line numbers for a given m_stateHandle + + // STATE - cleared each module + std::unordered_map m_varnames; // Uniquify inserted variable names + std::unordered_map m_handleLines; // Line numbers for given m_stateHandle // METHODS @@ -207,18 +209,16 @@ class CoverageVisitor final : public VNVisitor { const AstNodeModule* const origModp = m_modp; VL_RESTORER(m_modp); VL_RESTORER(m_state); - { - createHandle(nodep); - m_modp = nodep; - m_state.m_inModOff - = nodep->isTop(); // Ignore coverage on top module; it's a shell we created - if (!origModp) { - // No blocks cross (non-nested) modules, so save some memory - m_varnames.clear(); - m_handleLines.clear(); - } - iterateChildren(nodep); + createHandle(nodep); + m_modp = nodep; + m_state.m_inModOff + = nodep->isTop(); // Ignore coverage on top module; it's a shell we created + if (!origModp) { + // No blocks cross (non-nested) modules, so save some memory + m_varnames.clear(); + m_handleLines.clear(); } + iterateChildren(nodep); } void visit(AstNodeProcedure* nodep) override { iterateProcedure(nodep); } @@ -229,24 +229,22 @@ class CoverageVisitor final : public VNVisitor { void iterateProcedure(AstNode* nodep) { VL_RESTORER(m_state); VL_RESTORER(m_inToggleOff); - { - m_inToggleOff = true; - createHandle(nodep); - iterateChildren(nodep); - if (m_state.lineCoverageOn(nodep)) { - lineTrack(nodep); - AstNode* const newp - = newCoverInc(nodep->fileline(), "", "v_line", "block", - linesCov(m_state, nodep), 0, traceNameForLine(nodep, "block")); - if (AstNodeProcedure* const itemp = VN_CAST(nodep, NodeProcedure)) { - itemp->addStmtsp(newp); - } else if (AstNodeFTask* const itemp = VN_CAST(nodep, NodeFTask)) { - itemp->addStmtsp(newp); - } else if (AstWhile* const itemp = VN_CAST(nodep, While)) { - itemp->addStmtsp(newp); - } else { - nodep->v3fatalSrc("Bad node type"); - } + m_inToggleOff = true; + createHandle(nodep); + iterateChildren(nodep); + if (m_state.lineCoverageOn(nodep)) { + lineTrack(nodep); + AstNode* const newp + = newCoverInc(nodep->fileline(), "", "v_line", "block", linesCov(m_state, nodep), + 0, traceNameForLine(nodep, "block")); + if (AstNodeProcedure* const itemp = VN_CAST(nodep, NodeProcedure)) { + itemp->addStmtsp(newp); + } else if (AstNodeFTask* const itemp = VN_CAST(nodep, NodeFTask)) { + itemp->addStmtsp(newp); + } else if (AstWhile* const itemp = VN_CAST(nodep, While)) { + itemp->addStmtsp(newp); + } else { + nodep->v3fatalSrc("Bad node type"); } } } @@ -488,33 +486,29 @@ class CoverageVisitor final : public VNVisitor { UINFO(4, " CASEI: " << nodep << endl); if (m_state.lineCoverageOn(nodep)) { VL_RESTORER(m_state); - { - createHandle(nodep); - iterateAndNextNull(nodep->stmtsp()); - if (m_state.lineCoverageOn(nodep)) { // if the case body didn't disable it - lineTrack(nodep); - UINFO(4, " COVER: " << nodep << endl); - nodep->addStmtsp(newCoverInc(nodep->fileline(), "", "v_line", "case", - linesCov(m_state, nodep), 0, - traceNameForLine(nodep, "case"))); - } + createHandle(nodep); + iterateAndNextNull(nodep->stmtsp()); + if (m_state.lineCoverageOn(nodep)) { // if the case body didn't disable it + lineTrack(nodep); + UINFO(4, " COVER: " << nodep << endl); + nodep->addStmtsp(newCoverInc(nodep->fileline(), "", "v_line", "case", + linesCov(m_state, nodep), 0, + traceNameForLine(nodep, "case"))); } } } void visit(AstCover* nodep) override { UINFO(4, " COVER: " << nodep << endl); VL_RESTORER(m_state); - { - m_state.m_on = true; // Always do cover blocks, even if there's a $stop - createHandle(nodep); - iterateChildren(nodep); - if (!nodep->coverincsp() && v3Global.opt.coverageUser()) { - // Note the name may be overridden by V3Assert processing - lineTrack(nodep); - nodep->addCoverincsp(newCoverInc(nodep->fileline(), m_beginHier, "v_user", "cover", - linesCov(m_state, nodep), 0, - m_beginHier + "_vlCoverageUserTrace")); - } + m_state.m_on = true; // Always do cover blocks, even if there's a $stop + createHandle(nodep); + iterateChildren(nodep); + if (!nodep->coverincsp() && v3Global.opt.coverageUser()) { + // Note the name may be overridden by V3Assert processing + lineTrack(nodep); + nodep->addCoverincsp(newCoverInc(nodep->fileline(), m_beginHier, "v_user", "cover", + linesCov(m_state, nodep), 0, + m_beginHier + "_vlCoverageUserTrace")); } } void visit(AstStop* nodep) override { @@ -540,14 +534,12 @@ class CoverageVisitor final : public VNVisitor { // covers the code in that line.) VL_RESTORER(m_beginHier); VL_RESTORER(m_inToggleOff); - { - m_inToggleOff = true; - if (nodep->name() != "") { - m_beginHier = m_beginHier + (m_beginHier != "" ? "." : "") + nodep->name(); - } - iterateChildren(nodep); - lineTrack(nodep); + m_inToggleOff = true; + if (nodep->name() != "") { + m_beginHier = m_beginHier + (m_beginHier != "" ? "." : "") + nodep->name(); } + iterateChildren(nodep); + lineTrack(nodep); } // VISITORS - BOTH diff --git a/src/V3Coverage.h b/src/V3Coverage.h index 36a5558ba..a084ba3e5 100644 --- a/src/V3Coverage.h +++ b/src/V3Coverage.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3CoverageJoin.cpp b/src/V3CoverageJoin.cpp index a270d2f92..cf0e607a7 100644 --- a/src/V3CoverageJoin.cpp +++ b/src/V3CoverageJoin.cpp @@ -35,9 +35,10 @@ class CoverageJoinVisitor final : public VNVisitor { // NODE STATE // VNUser4InUse In V3Hasher via V3DupFinder - // STATE + // STATE - per active std::vector m_toggleps; // List of of all AstCoverToggle's + // STATE - Statistic tracking VDouble0 m_statToggleJoins; // Statistic tracking // METHODS diff --git a/src/V3CoverageJoin.h b/src/V3CoverageJoin.h index 07d83fa0b..57da38d8b 100644 --- a/src/V3CoverageJoin.h +++ b/src/V3CoverageJoin.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Dead.h b/src/V3Dead.h index 885a42c2a..17bc01243 100644 --- a/src/V3Dead.h +++ b/src/V3Dead.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index 59749239b..5edee1370 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -18,48 +18,86 @@ // Convert AstAssignDly into temporaries an specially scheduled blocks. // For the Pre/Post scheduling semantics, see V3OrderGraph. // -// A non-array LHS, outside suspendable processes and forks, e.g.:: -// a <= RHS; -// is converted as follows: +// There are several "Schemes" we can choose from for implementing a +// non-blocking assignment (NBA), repserented by an AstAssignDly. +// +// It is assumed and required in this pass that each NBA updates at +// most one variable. Earlier passes should have ensured this. +// +// Each variable is associated with a single NBA scheme, that is, all +// NBAs targeting the same variable will use the scheme assigned to +// that variable. This necessitates a global analysis of all NBAs +// before any decision can be made on how to handle them. +// +// The algorithm proceeds in 3 steps. +// 1. Gather all AstAssignDly non-blocking assignments (NBAs) in the +// whole design. Note usage context of variables updated by these NBAs. +// This is implemented in the 'visit' methods +// 2. For each variable that is the target of an NBA, decide which of +// the possible conversion schemes to use, based on info gathered in +// step 1. +// This is implemented in the 'chooseScheme' method +// 3. For each NBA gathered in step 1, convert it based on the scheme +// selected in step 2. +// This is implemented in the 'prepare*'/'convert*' methods. The +// 'prepare*' methods do the parts common for all NBAs updating +// the given variable. The 'convert*' methods then convert each +// AstAssignDly separately +// +// These are the possible NBA Schemes: +// "Shadow variable" scheme. Used for non-unpackedarray target +// variables in synthesizeable code. E.g.: +// LHS <= RHS; +// is converted to: // - Add new "Pre-scheduled" logic: -// __Vdly__a = a; -// - In the original logic, replace VarRefs on LHS with __Vdly__ variables: -// __Vdly__a = RHS; +// __Vdly__LHS = LHS; +// - In the original logic, replace the target variable 'LHS' with '__Vdly__LHS' variables: +// __Vdly__LHS = RHS; // - Add new "Post-scheduled" logic: -// a = __Vdly__a; +// LHS = __Vdly__LHS; // -// An array LHS, that is not inside a loop: -// a[idxa][idxb] <= RHS -// is converted: -// - Add new "Pre_scheduled" logic: -// __VdlySet__a = 0; +// "Shared flag" scheme. Used for unpacked array target variables +// in synthesizeable code. E.g.: +// LHS[idxa][idxb] <= RHS +// is converted to: +// - Add new "Pre-scheduled" logic: +// __VdlySet__LHS = 0; // - In the original logic, replace the AstAssignDelay with: -// __VdlySet__a = 1; -// __VdlyDim0__a = idxa; -// __VdlyDim1__a = idxb; -// __VdlyVal__a = RHS; +// __VdlySet__LHS = 1; +// __VdlyDim0__LHS = idxa; +// __VdlyDim1__LHS = idxb; +// __VdlyVal__LHS = RHS; // - Add new "Post-scheduled" logic: -// if (__VdlySet__a) a[__VdlyDim0__a][__VdlyDim1__a] = __VdlyVal__a; +// if (__VdlySet__LHS) a[__VdlyDim0__LHS][__VdlyDim1__LHS] = __VdlyVal__LHS; +// Multiple consecutive NBAs of compatible form can share the same __VdlySet* flag // -// Any AstAssignDly in a suspendable process or fork also uses the -// '__VdlySet' flag based scheme, like arrays, with some modifications. -// -// An array LHS, which is updated inside a loop (that is, we don't know -// statically how many updates there might be): -// a[idxa][idxb] <= RHS +// "Unique flag" scheme. Used for all variables updated by NBAs +// in suspendable processees or forks. E.g.: +// #1 LHS <= RHS; // is converted to: // - In the original logic, replace the AstAssignDelay with: -// __VdlyDim0__a = idxa; -// __VdlyDim1__a = idxb; -// __VdlyVal__a = RHS; -// __VdlyCommitQueue.enqueue(RHS, idxa, idxb); +// __VdlySet__LHS = 1; +// __VdlyVal__LHS = RHS; // - Add new "Post-scheduled" logic: -// __VdlyCommitQueue.commit(array-on-LHS); +// if (__VdlySet__LHS) { +// __VdlySet__LHS = 0; +// LHS = __VdlyVal__LHS; +// } // -// Note that it is necessary to use the same commit queue for all NBAs -// targeting the same array, if any NBAs require a commit queue. Hence -// we can only decide whether to use a commit queue or not after having -// examined all NBAs. +// The "Value Queue Whole/Partial" schemes are used for cases where the +// target of an assignment cannot be statically determined, for example, +// with an array LHS in a loop: +// LHS[idxa][idxb] <= RHS +// is converted to: +// - In the original logic, replace the AstAssignDelay with: +// __VdlyDim0__LHS = idxa; +// __VdlyDim1__LHS = idxb; +// __VdlyVal__LHS = RHS; +// __VdlyCommitQueue__LHS.enqueue(__VdlyVal__LHS, __VdlyDim0__LHS, __VdlyDim1__LHS); +// - Add new "Post-scheduled" logic: +// __VdlyCommitQueue.commit(LHS); +// +// TODO: generic LHS scheme as discussed in #5092 // //************************************************************************* @@ -76,102 +114,581 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### -// Delayed state, as a visitor of each AstNode +// Convert AstAssignDlys (NBAs) class DelayedVisitor final : public VNVisitor { // TYPES - // Components of an AstAssignDly LHS expression, e.g.: - // Sel(ArraySel(ArraySel(_: VarRef, _: Index), _: Index), _: Lsb, _: Width)) - struct LhsComponents final { - AstVarRef* refp = nullptr; // The referenced variable - std::vector arrIdxps; // The array indices applied to 'refp' - AstNodeExpr* selLsbp = nullptr; // The bit select LSB expression, after the array selects - AstConst* selWidthp = nullptr; // The width of the bit select + // The various NBA conversion schemes, including error cases + enum class Scheme : uint8_t { + Undecided = 0, + UnsupportedCompoundArrayInLoop, + ShadowVar, + FlagShared, + FlagUnique, + ValueQueueWhole, + ValueQueuePartial + }; + + // All info associated with a variable that is the target of an NBA + class VarScopeInfo final { + public: + // First write reference encountered to the VarScope as the target on an NBA + const AstVarRef* m_firstNbaRefp = nullptr; + // Active block 'm_firstNbaRefp' is under + const AstActive* m_fistActivep = nullptr; + bool m_partial = false; // Used on LHS of NBA under a Sel + bool m_inLoop = false; // Used on LHS of NBA in a loop + bool m_inSuspOrFork = false; // Used on LHS of NBA in suspendable process or fork + Scheme m_scheme = Scheme::Undecided; // Conversion scheme to use for this variable + uint32_t m_nTmp = 0; // Temporary number for unique names + + private: + // Combined sensitivities of all NBAs targeting this variable + AstSenTree* m_senTreep = nullptr; + + // Union of stuff needed for the various schemes - use accessors below! + union { + struct { // Stuff needed for Scheme::ShadowVar + AstVarScope* vscp; // The shadow variable + } m_shadowVariableKit; + struct { // Stuff needed for Scheme::FlagShared + AstActive* activep; // The active block for the Pre/Post logic + AstAlwaysPost* postp; // The post block for commiting results + AstIf* commitIfp; // The previous if statement for committing, for reuse + } m_flagSharedKit; + struct { // Stuff needed for Scheme::FlagUnique + AstAlwaysPost* postp; // The post block for commiting results + } m_flagUniqueKit; + struct { // Stuff needed for Scheme::ValueQueueWhole/Scheme::ValueQueuePartial + AstVarScope* vscp; // The commit queue variable + } m_valueQueueKit; + } m_kitUnion; + + public: + // Accessors for the above union fields + auto& shadowVariableKit() { + UASSERT(m_scheme == Scheme::ShadowVar, "Inconsistent Scheme"); + return m_kitUnion.m_shadowVariableKit; + } + auto& flagSharedKit() { + UASSERT(m_scheme == Scheme::FlagShared, "Inconsistent Scheme"); + return m_kitUnion.m_flagSharedKit; + } + auto& flagUniqueKit() { + UASSERT(m_scheme == Scheme::FlagUnique, "Inconsistent Scheme"); + return m_kitUnion.m_flagUniqueKit; + } + auto& valueQueueKit() { + UASSERT(m_scheme == Scheme::ValueQueuePartial || m_scheme == Scheme::ValueQueueWhole, + "Inconsistent Scheme"); + return m_kitUnion.m_valueQueueKit; + } + + // Accessor + AstSenTree* senTreep() const { return m_senTreep; } + + // Add sensitivities + void addSensitivity(AstSenItem* nodep) { + if (!m_senTreep) m_senTreep = new AstSenTree{nodep->fileline(), nullptr}; + // Add a copy of each term + m_senTreep->addSensesp(nodep->cloneTree(true)); + // Remove duplicates + V3Const::constifyExpensiveEdit(m_senTreep); + } + void addSensitivity(AstSenTree* nodep) { addSensitivity(nodep->sensesp()); } }; // Data required to lower AstAssignDelay later - struct Deferred final { - LhsComponents lhsComponents; // The components of the LHS - AstNodeExpr* rhsp = nullptr; // The captured value being assigned by the AstAssignDly - AstActive* activep = nullptr; // The active block the AstAssignDly is under - AstNode* insertionPointp = nullptr; // The insertion point after the AstAssignDly - std::string suffix; // Suffix to add to additional variables created - bool consecutive = false; // Record corresponds to an AstAssignDly immediately adjacent + struct NBA final { + AstAssignDly* nodep = nullptr; // The NBA this record refers to + AstVarScope* vscp = nullptr; // The target variable the NBA is updating }; // NODE STATE - // AstVarScope::user1p() -> aux - // AstVar::user1() -> bool. Set true if already made warning - // AstVarRef::user1() -> bool. Set true if is a non-blocking reference - // AstAlwaysPost::user1() -> AstIf*. Last IF (__VdlySet__) created under this AlwaysPost - // - // Cleared each scope/active: - // AstVarScope::user2() -> AstVarScope*. Commit queue for this variable - // AstVarRef::user2() -> bool. Set true if already processed - // AstAssignDly::user2() -> AstVarScope*. __VdlySet__ created for this assign - // AstAlwaysPost::user2() -> AstVarScope*. __VdlySet__ last referenced in IF - // AstNodeProcedure::user2() -> AstAcive*. Active block used by this suspendable process - const VNUser1InUse m_inuser1; - const VNUser2InUse m_inuser2; - - struct AuxAstVarScope final { - // Points to temp (shadow) variable created. - AstVarScope* delayVscp = nullptr; - // Points to AstActive block of the shadow variable 'delayVscp/post block 'postp' - AstActive* activep = nullptr; - // Post block for this variable - AstAlwaysPost* postp = nullptr; - // First reference encountered to the VarScope - const AstNodeVarRef* firstRefp = nullptr; - // If the implementation cannot be deferred, this is the location why - FileLine* nonDeferredFlp = nullptr; - // Variable requires a commit queue due to dynamic NBA - bool needsCommitQueue = false; - // Array element is partially updated by at least some NBA - bool hasPartialUpdate = false; - }; - AstUser1Allocator m_vscpAux; + // AstVar::user1() -> bool. Set true if already issued MULTIDRIVEN warning + // AstVarRef::user1() -> bool. Set true if target of NBA + // AstNodeModule::user1p() -> std::unorded_map temp map via m_varMap + // AstVarScope::user1p() -> VarScopeInfo via m_vscpInfo + // AstVarScope::user2p() -> AstVarRef*: First write reference to the Variable + const VNUser1InUse m_user1InUse{}; + const VNUser2InUse m_user2InUse{}; + AstUser1Allocator> m_varMap; + AstUser1Allocator m_vscpInfo; // STATE - across all visitors - std::unordered_map m_scopeVecMap; // Next var number for each scope std::set m_timingDomains; // Timing resume domains - // Table of new var names created under module - std::map, AstVar*> m_modVarMap; - AstNode* m_insertionPointp = nullptr; // Where to insert new statements // STATE - for current visit position (use VL_RESTORER) AstActive* m_activep = nullptr; // Current activate const AstCFunc* m_cfuncp = nullptr; // Current public C Function - AstAssignDly* m_nextDlyp = nullptr; // The nextp of the previous AstAssignDly AstNodeProcedure* m_procp = nullptr; // Current process - bool m_inDlyLhs = false; // True in lhs of AstAssignDelay bool m_inLoop = false; // True in for loops bool m_inSuspendableOrFork = false; // True in suspendable processes and forks bool m_ignoreBlkAndNBlk = false; // Suppress delayed assignment BLKANDNBLK + AstVarRef* m_currNbaLhsRefp = nullptr; // Current NBA LHS variable reference - // STATE - for deferred conversion - std::deque m_deferred; // Deferred AstAssignDly instances to lower at the end - AstVarScope* m_setVscp = nullptr; // The last used set flag, for reuse + // STATE - during NBA conversion (after visit) + std::vector m_nbas; // AstAssignDly instances to lower at the end + std::vector m_vscps; // Target variables on LHSs of NBAs + AstAssignDly* m_nextDlyp = nullptr; // The nextp of the previous AstAssignDly + AstVarScope* m_prevVscp = nullptr; // The target of the previous AstAssignDly // STATE - Statistic tracking - VDouble0 m_statSharedSet; // "VdlySet" variables eliminated by reuse - VDouble0 m_commitQueuesWhole; // Variables needing a commit queue without partial updates - VDouble0 m_commitQueuesPartial; // Variables needing a commit queue with partial updates + VDouble0 m_nSchemeShadowVar; // Number of variables using Scheme::ShadowVar + VDouble0 m_nSchemeFlagShared; // Number of variables using Scheme::FlagShared + VDouble0 m_nSchemeFlagUnique; // Number of variables using Scheme::FlagUnique + VDouble0 m_nSchemeValueQueuesWhole; // Number of variables using Scheme::ValueQueueWhole + VDouble0 m_nSchemeValueQueuesPartial; // Number of variables using Scheme::ValueQueuePartial + VDouble0 m_nSharedSetFlags; // "Set" flags actually shared by Scheme::FlagShared variables // METHODS - const AstNode* containingAssignment(const AstNode* nodep) { - while (nodep && !VN_IS(nodep, NodeAssign)) nodep = nodep->backp(); - return nodep; + // Choose the NBA scheme used for the given variable. + static Scheme chooseScheme(const AstVarScope* vscp, const VarScopeInfo& vscpInfo) { + UASSERT_OBJ(vscpInfo.m_scheme == Scheme::Undecided, vscp, "NBA scheme already decided"); + + const AstNodeDType* const dtypep = vscp->dtypep()->skipRefp(); + // Unpacked arrays + if (const AstUnpackArrayDType* const uaDTypep = VN_CAST(dtypep, UnpackArrayDType)) { + // If used in a loop, we must have a dynamic commit queue. (Also works in suspendables) + if (vscpInfo.m_inLoop) { + // Arrays with compound element types are currently not supported in loops + AstBasicDType* const basicp = uaDTypep->basicp(); + if (!basicp + || !(basicp->isIntegralOrPacked() // + || basicp->isDouble() // + || basicp->isString())) { + return Scheme::UnsupportedCompoundArrayInLoop; + } + if (vscpInfo.m_partial) return Scheme::ValueQueuePartial; + return Scheme::ValueQueueWhole; + } + // In a suspendable of fork, we must use the unique flag scheme, TODO: why? + if (vscpInfo.m_inSuspOrFork) return Scheme::FlagUnique; + // Otherwise use the shared flag scheme + return Scheme::FlagShared; + } + + // In a suspendable of fork, we must use the unique flag scheme, TODO: why? + if (vscpInfo.m_inSuspOrFork) return Scheme::FlagUnique; + // Otherwise use the simple shadow variable scheme + return Scheme::ShadowVar; + } + + // Create new AstVarScope in the given 'scopep', with the given 'name' and 'dtypep' + AstVarScope* createTemp(FileLine* flp, AstScope* scopep, const std::string& name, + AstNodeDType* dtypep) { + AstNodeModule* const modp = scopep->modp(); + // Get/create the corresponding AstVar + AstVar*& varp = m_varMap(modp)[name]; + if (!varp) { + varp = new AstVar{flp, VVarType::BLOCKTEMP, name, dtypep}; + modp->addStmtsp(varp); + } + // Create the AstVarScope + AstVarScope* const varscp = new AstVarScope{flp, scopep, varp}; + scopep->addVarsp(varscp); + return varscp; + } + + // Same as above but create a 2-state scalar of the given 'width' + AstVarScope* createTemp(FileLine* flp, AstScope* scopep, const std::string& name, int width) { + AstNodeDType* const dtypep = scopep->findBitDType(width, width, VSigning::UNSIGNED); + return createTemp(flp, scopep, name, dtypep); + } + + // Given an expression 'exprp', return a new expression that always evaluates to the + // value of the given expression at this point in the program. That is: + // - If given a non-constant expression, create a new temporary AstVarScope under the given + // 'scopep', with the given 'name', assign the expression to it, and return a read reference + // to the new AstVarScope. + // - If given a constant, just return that constant. + // New statements are inserted before 'insertp' + AstNodeExpr* captureVal(AstScope* const scopep, AstNodeStmt* const insertp, + AstNodeExpr* const exprp, const std::string& name) { + UASSERT_OBJ(!exprp->backp(), exprp, "Should have been unlinked"); + FileLine* const flp = exprp->fileline(); + if (VN_IS(exprp, Const)) return exprp; + // TODO: there are some const variables that could be simply referenced here + AstVarScope* const tmpVscp = createTemp(flp, scopep, name, exprp->dtypep()); + insertp->addHereThisAsNext( + new AstAssign{flp, new AstVarRef{flp, tmpVscp, VAccess::WRITE}, exprp}); + return new AstVarRef{flp, tmpVscp, VAccess::READ}; + }; + + // Similar to 'captureVal', but captures an LValue expression. That is, the returned + // expression will reference the same location as the input expression, at this point in the + // program. + AstNodeExpr* captureLhs(AstScope* const scopep, AstNodeStmt* const insertp, + AstNodeExpr* const lhsp, const std::string& baseName) { + UASSERT_OBJ(!lhsp->backp(), lhsp, "Should have been unlinked"); + // Running node pointer + AstNode* nodep = lhsp; + // Capture AstSel indices - there should be only one + if (AstSel* const selp = VN_CAST(nodep, Sel)) { + const std::string tmpName{"__VdlyLsb" + baseName}; + selp->lsbp(captureVal(scopep, insertp, selp->lsbp()->unlinkFrBack(), tmpName)); + // Continue with target + nodep = selp->fromp(); + } + UASSERT_OBJ(!VN_IS(nodep, Sel), lhsp, "Multiple 'AstSel' applied to LHS reference"); + // Capture AstArraySel indices - might be many + size_t nArraySels = 0; + while (AstArraySel* const arrSelp = VN_CAST(nodep, ArraySel)) { + const std::string tmpName{"__VdlyDim" + std::to_string(nArraySels++) + baseName}; + arrSelp->bitp(captureVal(scopep, insertp, arrSelp->bitp()->unlinkFrBack(), tmpName)); + nodep = arrSelp->fromp(); + } + // What remains must be an AstVarRef + UASSERT_OBJ(VN_IS(nodep, VarRef), lhsp, "Malformed LHS in NBA"); + // Now have been converted to use the captured values + return lhsp; + } + + // Create a temporary variable in the given 'scopep', with the given 'name', and with 'dtypep' + // type, with the bits selected by 'sLsbp'/'sWidthp' set to 'valuep', other bits set to zero. + // Insert new statements before 'insertp'. + // Returns a read reference to the temporary variable. + AstVarRef* createWidened(FileLine* flp, AstScope* scopep, AstNodeDType* dtypep, + AstNodeExpr* sLsbp, AstNodeExpr* sWidthp, const std::string& name, + AstNodeExpr* valuep, AstNode* insertp) { + // Create temporary variable. + AstVarScope* const tp = createTemp(flp, scopep, name, dtypep); + // Zero it + AstConst* const zerop = new AstConst{flp, AstConst::DTyped{}, dtypep}; + zerop->num().setAllBits0(); + insertp->addHereThisAsNext( + new AstAssign{flp, new AstVarRef{flp, tp, VAccess::WRITE}, zerop}); + // Set the selected bits to 'valuep' + AstSel* const selp = new AstSel{flp, new AstVarRef{flp, tp, VAccess::WRITE}, + sLsbp->cloneTreePure(true), sWidthp->cloneTreePure(true)}; + insertp->addHereThisAsNext(new AstAssign{flp, selp, valuep}); + // This is the expression to get the value of the temporary + return new AstVarRef{flp, tp, VAccess::READ}; + } + + // Scheme::ShadowVar + void prepareSchemeShadowVar(AstVarScope* vscp, VarScopeInfo& vscpInfo) { + UASSERT_OBJ(vscpInfo.m_scheme == Scheme::ShadowVar, vscp, "Inconsistent NBA scheme"); + FileLine* const flp = vscp->fileline(); + AstScope* const scopep = vscp->scopep(); + // Create the shadow variable + const std::string name = "__Vdly__" + vscp->varp()->shortName(); + AstVarScope* const shadowVscp = createTemp(flp, scopep, name, vscp->dtypep()); + vscpInfo.shadowVariableKit().vscp = shadowVscp; + // Create the AstActive for the Pre/Post logic + AstActive* const activep = new AstActive{flp, "nba-shadow-variable", vscpInfo.senTreep()}; + activep->sensesStorep(vscpInfo.senTreep()); + scopep->addBlocksp(activep); + // Add 'Pre' scheduled 'shadowVariable = originalVariable' assignment + activep->addStmtsp(new AstAssignPre{flp, new AstVarRef{flp, shadowVscp, VAccess::WRITE}, + new AstVarRef{flp, vscp, VAccess::READ}}); + // Add 'Post' scheduled 'originalVariable = shadowVariable' assignment + activep->addStmtsp(new AstAssignPost{flp, new AstVarRef{flp, vscp, VAccess::WRITE}, + new AstVarRef{flp, shadowVscp, VAccess::READ}}); + } + void convertSchemeShadowVar(AstAssignDly* nodep, AstVarScope* vscp, VarScopeInfo& vscpInfo) { + UASSERT_OBJ(vscpInfo.m_scheme == Scheme::ShadowVar, vscp, "Inconsistent NBA scheme"); + AstVarScope* const shadowVscp = vscpInfo.shadowVariableKit().vscp; + + // Replace the write ref on the LHS with the shadow variable + nodep->lhsp()->foreach([&](AstVarRef* const refp) { + if (!refp->access().isWriteOnly()) return; + UASSERT_OBJ(refp->varScopep() == vscp, nodep, "NBA not setting expected variable"); + refp->varScopep(shadowVscp); + refp->varp(shadowVscp->varp()); + }); + } + + // Scheme::FlagShared + void prepareSchemeFlagShared(AstVarScope* vscp, VarScopeInfo& vscpInfo) { + UASSERT_OBJ(vscpInfo.m_scheme == Scheme::FlagShared, vscp, "Inconsistent NBA scheme"); + FileLine* const flp = vscp->fileline(); + AstScope* const scopep = vscp->scopep(); + // Create the AstActive for the Pre/Post logic + AstActive* const activep = new AstActive{flp, "nba-flag-shared", vscpInfo.senTreep()}; + activep->sensesStorep(vscpInfo.senTreep()); + scopep->addBlocksp(activep); + vscpInfo.flagSharedKit().activep = activep; + // Add 'Post' scheduled process to be populated later + AstAlwaysPost* const postp = new AstAlwaysPost{flp}; + activep->addStmtsp(postp); + vscpInfo.flagSharedKit().postp = postp; + } + void convertSchemeFlagShared(AstAssignDly* nodep, AstVarScope* vscp, VarScopeInfo& vscpInfo) { + UASSERT_OBJ(vscpInfo.m_scheme == Scheme::FlagShared, vscp, "Inconsistent NBA scheme"); + FileLine* const flp = vscp->fileline(); + AstScope* const scopep = vscp->scopep(); + + // Base name suffix for signals constructed below + const std::string baseName{"__" + vscp->varp()->shortName() + "__v" + + std::to_string(vscpInfo.m_nTmp++)}; + + // Unlink and capture the RHS value + AstNodeExpr* const capturedRhsp + = captureVal(scopep, nodep, nodep->rhsp()->unlinkFrBack(), "__VdlyVal" + baseName); + + // Unlink and capture the LHS reference + AstNodeExpr* const capturedLhsp + = captureLhs(scopep, nodep, nodep->lhsp()->unlinkFrBack(), baseName); + + // Is this NBA adjacent after the previously processed NBA? + const bool consecutive = nodep == m_nextDlyp; + m_nextDlyp = VN_CAST(nodep->nextp(), AssignDly); + + // We can reuse the flag of the previous assignment if: + const bool reuseTheFlag = + // Consecutive NBAs + consecutive + // ... that use the same scheme + && m_vscpInfo(m_prevVscp).m_scheme == Scheme::FlagShared + // ... and share the same overall update domain + && m_vscpInfo(m_prevVscp).senTreep()->sameTree(vscpInfo.senTreep()); + + if (!reuseTheFlag) { + // Create new flag + AstVarScope* const flagVscp = createTemp(flp, scopep, "__VdlySet" + baseName, 1); + // Set the flag at the original NBA + nodep->addHereThisAsNext( // + new AstAssign{flp, new AstVarRef{flp, flagVscp, VAccess::WRITE}, + new AstConst{flp, AstConst::BitTrue{}}}); + // Add the 'Pre' scheduled reset for the flag + vscpInfo.flagSharedKit().activep->addStmtsp( + new AstAssignPre{flp, new AstVarRef{flp, flagVscp, VAccess::WRITE}, + new AstConst{flp, AstConst::BitFalse{}}}); + // Add the 'Post' scheduled commit + AstIf* const ifp = new AstIf{flp, new AstVarRef{flp, flagVscp, VAccess::READ}}; + vscpInfo.flagSharedKit().postp->addStmtsp(ifp); + vscpInfo.flagSharedKit().commitIfp = ifp; + } else { + // Reuse the commit block of the previous assignment + vscpInfo.flagSharedKit().commitIfp = m_vscpInfo(m_prevVscp).flagSharedKit().commitIfp; + ++m_nSharedSetFlags; + } + // Commit the captured value to the captured destination + vscpInfo.flagSharedKit().commitIfp->addThensp( + new AstAssign{flp, capturedLhsp, capturedRhsp}); + + // Remember the variable for the next NBA + m_prevVscp = vscp; + + // Delete original NBA + pushDeletep(nodep->unlinkFrBack()); + } + + // Scheme::FlagUnique + void prepareSchemeFlagUnique(AstVarScope* vscp, VarScopeInfo& vscpInfo) { + UASSERT_OBJ(vscpInfo.m_scheme == Scheme::FlagUnique, vscp, "Inconsistent NBA scheme"); + FileLine* const flp = vscp->fileline(); + AstScope* const scopep = vscp->scopep(); + // Create the AstActive for the Pre/Post logic + AstActive* const activep = new AstActive{flp, "nba-flag-unique", vscpInfo.senTreep()}; + activep->sensesStorep(vscpInfo.senTreep()); + scopep->addBlocksp(activep); + // Add 'Post' scheduled process to be populated later + AstAlwaysPost* const postp = new AstAlwaysPost{flp}; + activep->addStmtsp(postp); + vscpInfo.flagUniqueKit().postp = postp; + } + void convertSchemeFlagUnique(AstAssignDly* nodep, AstVarScope* vscp, VarScopeInfo& vscpInfo) { + UASSERT_OBJ(vscpInfo.m_scheme == Scheme::FlagUnique, vscp, "Inconsistent NBA scheme"); + FileLine* const flp = vscp->fileline(); + AstScope* const scopep = vscp->scopep(); + + // Base name suffix for signals constructed below + const std::string baseName{"__" + vscp->varp()->shortName() + "__v" + + std::to_string(vscpInfo.m_nTmp++)}; + + // Unlink and capture the RHS value + AstNodeExpr* const capturedRhsp + = captureVal(scopep, nodep, nodep->rhsp()->unlinkFrBack(), "__VdlyVal" + baseName); + + // Unlink and capture the LHS reference + AstNodeExpr* const capturedLhsp + = captureLhs(scopep, nodep, nodep->lhsp()->unlinkFrBack(), baseName); + + // Create new flag + AstVarScope* const flagVscp = createTemp(flp, scopep, "__VdlySet" + baseName, 1); + flagVscp->varp()->setIgnorePostWrite(); + // Set the flag at the original NBA + nodep->addHereThisAsNext( // + new AstAssign{flp, new AstVarRef{flp, flagVscp, VAccess::WRITE}, + new AstConst{flp, AstConst::BitTrue{}}}); + // Add the 'Post' scheduled commit + AstIf* const ifp = new AstIf{flp, new AstVarRef{flp, flagVscp, VAccess::READ}}; + vscpInfo.flagUniqueKit().postp->addStmtsp(ifp); + // Immediately clear the flag + ifp->addThensp(new AstAssign{flp, new AstVarRef{flp, flagVscp, VAccess::WRITE}, + new AstConst{flp, AstConst::BitFalse{}}}); + // Commit the value + ifp->addThensp(new AstAssign{flp, capturedLhsp, capturedRhsp}); + + // Delete original NBA + pushDeletep(nodep->unlinkFrBack()); + } + + // Scheme::ValueQueuePartial/Scheme::ValueQueueWhole + template + void prepareSchemeValueQueue(AstVarScope* vscp, VarScopeInfo& vscpInfo) { + UASSERT_OBJ(Partial ? vscpInfo.m_scheme == Scheme::ValueQueuePartial + : vscpInfo.m_scheme == Scheme::ValueQueueWhole, + vscp, "Inconsistencheme"); + FileLine* const flp = vscp->fileline(); + AstScope* const scopep = vscp->scopep(); + + // Create the commit queue variable + auto* const cqDTypep + = new AstNBACommitQueueDType{flp, vscp->dtypep()->skipRefp(), Partial}; + v3Global.rootp()->typeTablep()->addTypesp(cqDTypep); + const std::string name = "__VdlyCommitQueue" + vscp->varp()->shortName(); + AstVarScope* const queueVscp = createTemp(flp, scopep, name, cqDTypep); + queueVscp->varp()->noReset(true); + queueVscp->varp()->setIgnorePostWrite(); + vscpInfo.valueQueueKit().vscp = queueVscp; + // Create the AstActive for the Post logic + AstActive* const activep + = new AstActive{flp, "nba-value-queue-whole", vscpInfo.senTreep()}; + activep->sensesStorep(vscpInfo.senTreep()); + scopep->addBlocksp(activep); + // Add 'Post' scheduled process for the commit + AstAlwaysPost* const postp = new AstAlwaysPost{flp}; + activep->addStmtsp(postp); + // Add the commit + AstCMethodHard* const callp + = new AstCMethodHard{flp, new AstVarRef{flp, queueVscp, VAccess::READWRITE}, "commit"}; + callp->dtypeSetVoid(); + callp->addPinsp(new AstVarRef{flp, vscp, VAccess::WRITE}); + postp->addStmtsp(callp->makeStmt()); + } + + void convertSchemeValueQueue(AstAssignDly* nodep, AstVarScope* vscp, VarScopeInfo& vscpInfo, + bool partial) { + UASSERT_OBJ(partial ? vscpInfo.m_scheme == Scheme::ValueQueuePartial + : vscpInfo.m_scheme == Scheme::ValueQueueWhole, + vscp, "Inconsistent NBA scheme"); + FileLine* const flp = vscp->fileline(); + AstScope* const scopep = vscp->scopep(); + + // Base name suffix for signals constructed below + const std::string baseName{"__" + vscp->varp()->shortName() + "__v" + + std::to_string(vscpInfo.m_nTmp++)}; + + // Unlink and capture the RHS value + AstNodeExpr* const capturedRhsp + = captureVal(scopep, nodep, nodep->rhsp()->unlinkFrBack(), "__VdlyVal" + baseName); + + // Unlink and capture the LHS reference + AstNodeExpr* const capturedLhsp + = captureLhs(scopep, nodep, nodep->lhsp()->unlinkFrBack(), baseName); + + // RHS value (can be widened/masked iff Partial) + AstNodeExpr* valuep = capturedRhsp; + // RHS mask (iff Partial) + AstNodeExpr* maskp = nullptr; + + // Running node for LHS deconstruction + AstNodeExpr* lhsNodep = capturedLhsp; + + // If partial updates are required, construct the mask and the widened value + if (partial) { + // Type of array element + AstNodeDType* const eDTypep = [&]() -> AstNodeDType* { + AstNodeDType* dtypep = vscp->dtypep()->skipRefp(); + while (AstUnpackArrayDType* const ap = VN_CAST(dtypep, UnpackArrayDType)) { + dtypep = ap->subDTypep()->skipRefp(); + } + return dtypep; + }(); + + if (AstSel* const lSelp = VN_CAST(lhsNodep, Sel)) { + // This is a partial assignment. + // Need to create a mask and widen the value to element size. + lhsNodep = lSelp->fromp(); + AstNodeExpr* const sLsbp = lSelp->lsbp(); + AstConst* const sWidthp = VN_AS(lSelp->widthp(), Const); + + // Create mask value + maskp = [&]() -> AstNodeExpr* { + // Constant mask we can compute here + if (AstConst* const cLsbp = VN_CAST(sLsbp, Const)) { + AstConst* const cp = new AstConst{flp, AstConst::DTyped{}, eDTypep}; + cp->num().setMask(sWidthp->toSInt(), cLsbp->toSInt()); + return cp; + } + + // A non-constant mask we must compute at run-time. + AstConst* const onesp + = new AstConst{flp, AstConst::WidthedValue{}, sWidthp->toSInt(), 0}; + onesp->num().setAllBits1(); + return createWidened(flp, scopep, eDTypep, sLsbp, sWidthp, + "__VdlyMask" + baseName, onesp, nodep); + }(); + + // Adjust value to element size + valuep = [&]() -> AstNodeExpr* { + // Constant value with constant select we can compute here + if (AstConst* const cValuep = VN_CAST(valuep, Const)) { + if (AstConst* const cLsbp = VN_CAST(sLsbp, Const)) { + AstConst* const cp = new AstConst{flp, AstConst::DTyped{}, eDTypep}; + cp->num().setAllBits0(); + cp->num().opSelInto(cValuep->num(), cLsbp->toSInt(), + sWidthp->toSInt()); + return cp; + } + } + + // A non-constant value we must adjust. + return createWidened(flp, scopep, eDTypep, sLsbp, sWidthp, // + "__VdlyElem" + baseName, valuep, nodep); + }(); + } else { + // If this assignment is not partial, set mask to ones and we are done + AstConst* const ones = new AstConst{flp, AstConst::DTyped{}, eDTypep}; + ones->num().setAllBits1(); + maskp = ones; + } + } + + // Extract array indices + std::vector idxps; + { + UASSERT_OBJ(VN_IS(lhsNodep, ArraySel), lhsNodep, "Unexpected LHS form"); + while (AstArraySel* const aSelp = VN_CAST(lhsNodep, ArraySel)) { + idxps.emplace_back(aSelp->bitp()->unlinkFrBack()); + lhsNodep = aSelp->fromp(); + } + UASSERT_OBJ(VN_IS(lhsNodep, VarRef), lhsNodep, "Unexpected LHS form"); + std::reverse(idxps.begin(), idxps.end()); + } + + // Done with the LHS at this point + VL_DO_DANGLING(pushDeletep(capturedLhsp), capturedLhsp); + + // Enqueue the update at the site of the original NBA + AstCMethodHard* const callp = new AstCMethodHard{ + flp, new AstVarRef{flp, vscpInfo.valueQueueKit().vscp, VAccess::READWRITE}, "enqueue"}; + callp->dtypeSetVoid(); + callp->addPinsp(valuep); + if (partial) callp->addPinsp(maskp); + for (AstNodeExpr* const indexp : idxps) callp->addPinsp(indexp); + nodep->addHereThisAsNext(callp->makeStmt()); + + // Delete original NBA + pushDeletep(nodep->unlinkFrBack()); } // Record and warn if a variable is assigned by both blocking and nonblocking assignments - void markVarUsage(AstNodeVarRef* nodep, bool nonBlocking) { + void checkVarUsage(AstVarRef* nodep, bool nonBlocking) { // Ignore references in certain contexts if (m_ignoreBlkAndNBlk) return; // Ignore if warning is disabled on this reference (used by V3Force). if (nodep->fileline()->warnIsOff(V3ErrorCode::BLKANDNBLK)) return; + // Ignore if it's an array + // TODO: we do this because it used to be the previous behaviour. + // Is it still required, or should we warn for arrays as well? + // Scheduling is no different for them... + if (VN_IS(nodep->varScopep()->dtypep()->skipRefp(), UnpackArrayDType)) return; // Mark ref as blocking/non-blocking nodep->user1(nonBlocking); @@ -179,9 +696,9 @@ class DelayedVisitor final : public VNVisitor { AstVarScope* const vscp = nodep->varScopep(); // Pick up/set the first reference to this variable - const AstNodeVarRef* const firstRefp = m_vscpAux(vscp).firstRefp; + const AstVarRef* const firstRefp = VN_AS(vscp->user2p(), VarRef); if (!firstRefp) { - m_vscpAux(vscp).firstRefp = nodep; + vscp->user2p(nodep); return; } @@ -189,6 +706,11 @@ class DelayedVisitor final : public VNVisitor { if (firstRefp->user1() == static_cast(nonBlocking)) return; // Otherwise warn that both blocking and non-blocking assignments are used + const auto containingAssignment = [](const AstNode* nodep) -> const AstNode* { + while (!VN_IS(nodep, NodeAssign)) nodep = nodep->backp(); + return nodep; + }; + const AstNode* nonblockingp = nonBlocking ? nodep : firstRefp; if (const AstNode* np = containingAssignment(nonblockingp)) nonblockingp = np; const AstNode* blockingp = nonBlocking ? firstRefp : nodep; @@ -203,466 +725,89 @@ class DelayedVisitor final : public VNVisitor { << nonblockingp->warnContextSecondary()); } - // Create new AstVarScope in the scope of the given 'vscp', with the given 'name' and 'dtypep' - AstVarScope* createNewVarScope(AstVarScope* vscp, const string& name, AstNodeDType* dtypep) { - FileLine* const flp = vscp->fileline(); - AstScope* const scopep = vscp->scopep(); - AstNodeModule* const modp = scopep->modp(); - // Get/create the corresponding AstVar - AstVar*& varp = m_modVarMap[{modp, name}]; - if (!varp) { - varp = new AstVar{flp, VVarType::BLOCKTEMP, name, dtypep}; - modp->addStmtsp(varp); - } - // Create the AstVarScope - AstVarScope* const varscp = new AstVarScope{flp, scopep, varp}; - scopep->addVarsp(varscp); - return varscp; - } - - // Same as above but create a 2-state scalar of the given 'width' - AstVarScope* createNewVarScope(AstVarScope* vscp, const string& name, int width) { - AstNodeDType* const dtypep = vscp->findBitDType(width, width, VSigning::UNSIGNED); - return createNewVarScope(vscp, name, dtypep); - } - - // Create a new AstActive, using the sensitivity list of the given 'activep' - static AstActive* createActiveLike(FileLine* flp, AstActive* activep) { - AstActive* const newActivep = new AstActive{flp, "sequentdly", activep->sensesp()}; - activep->addNextHere(newActivep); - return newActivep; - } - - // Check and ensure the given 'activep' contains the sensitivity of the 'currentActivep'. - // Warn if they don't match (multiple domains assign the same signal via an NBA). - static void checkActiveSense(AstVarRef* refp, AstActive* acivep, AstActive* currentActivep) { - if (acivep->sensesp() == currentActivep->sensesp()) return; - - AstVar* const varp = refp->varScopep()->varp(); - // Warn once, if not turned off - if (!varp->user1SetOnce() && !varp->fileline()->warnIsOff(V3ErrorCode::MULTIDRIVEN)) { - varp->v3warn(MULTIDRIVEN, - "Signal has multiple driving blocks with different clocking: " - << varp->prettyNameQ() << '\n' - << refp->warnOther() << "... Location of first driving block\n" - << refp->warnContextPrimary() << '\n' - << acivep->warnOther() << "... Location of other driving block\n" - << acivep->warnContextSecondary()); - } - - // Make a new sensitivity list, which is the combination of both blocks - AstSenItem* const sena = currentActivep->sensesp()->sensesp()->cloneTree(true); - AstSenItem* const senb = acivep->sensesp()->sensesp()->cloneTree(true); - AstSenTree* const treep = new AstSenTree{currentActivep->fileline(), sena}; - V3Const::constifyExpensiveEdit(treep); // Remove duplicates - treep->addSensesp(senb); - if (AstSenTree* const storep = acivep->sensesStorep()) { - VL_DO_DANGLING(storep->unlinkFrBack()->deleteTree(), storep); - } - acivep->sensesStorep(treep); - acivep->sensesp(treep); - } - - // Gather components of the given 'lhsp'. The component sub-expressions - // are unlinked and unnecessary AstNodes deleted. - static LhsComponents deconstructLhs(AstNodeExpr* const lhsp) { - UASSERT_OBJ(!lhsp->backp(), lhsp, "Should have been unlinked"); - // The result being populated - LhsComponents components; - // Running node pointer - AstNode* nodep = lhsp; - // Gather AstSel applied - there should only be one - if (AstSel* const selp = VN_CAST(nodep, Sel)) { - nodep = selp->fromp()->unlinkFrBack(); - components.selLsbp = selp->lsbp()->unlinkFrBack(); - components.selWidthp = VN_AS(selp->widthp()->unlinkFrBack(), Const); - VL_DO_DANGLING(selp->deleteTree(), selp); - } - UASSERT_OBJ(!VN_IS(nodep, Sel), lhsp, "Multiple 'AstSel' applied to LHS reference"); - // Gather AstArraySels applied - while (AstArraySel* const arrSelp = VN_CAST(nodep, ArraySel)) { - nodep = arrSelp->fromp()->unlinkFrBack(); - components.arrIdxps.push_back(arrSelp->bitp()->unlinkFrBack()); - VL_DO_DANGLING(arrSelp->deleteTree(), arrSelp); - } - std::reverse(components.arrIdxps.begin(), components.arrIdxps.end()); - // What remains must be an AstVarRef - components.refp = VN_AS(nodep, VarRef); - // Done - return components; - } - - // Reconstruct an LHS expression from the given 'components'. The component members - // are linked under the returned expression without cloning, so they must be unlinked. - static AstNodeExpr* reconstructLhs(const LhsComponents& components, FileLine* flp) { - // Running node pointer - AstNodeExpr* nodep = components.refp; - // Apply AstArraySels - for (AstNodeExpr* const idxp : components.arrIdxps) { - nodep = new AstArraySel{flp, nodep, idxp}; - } - // Apply AstSel, if any - if (components.selLsbp) { - nodep = new AstSel{flp, nodep, components.selLsbp, components.selWidthp}; - } - // Done - return nodep; - } - - // Insert 'stmtp; after 'm_insertionPoint', then set 'm_insertionPoint' to the given statement - // so the next insertion goes after the inserted statement. - void insert(AstNode* stmtp) { - m_insertionPointp->addNextHere(stmtp); - m_insertionPointp = stmtp; - } - - // Process the given AstAssignDly. Returns 'true' if the conversion is complete and 'nodep' can - // be deleted. Returns 'false' if the 'nodep' must be retained for later processing. - bool processAssignDly(AstAssignDly* nodep) { - // Optimize consecutiev assignments - const bool consecutive = m_nextDlyp == nodep; - m_nextDlyp = VN_CAST(nodep->nextp(), AssignDly); - - // Insertion point - UASSERT_OBJ(!m_insertionPointp, nodep, "Insertion point should be null"); - VL_RESTORER(m_insertionPointp); - m_insertionPointp = nodep; - - // Deconstruct the LHS - LhsComponents lhsComponents = deconstructLhs(nodep->lhsp()->unlinkFrBack()); - - // The referenced variable - AstVarScope* const vscp = lhsComponents.refp->varScopep(); - - // Location of the AstAssignDly - FileLine* const flp = nodep->fileline(); - - // Name suffix for signals constructed below - const std::string baseName - = "__" + vscp->varp()->shortName() + "__v" + std::to_string(m_scopeVecMap[vscp]++); - - // Given an 'expression', return a new expression that always evaluates to the value of the - // given expression at this point in the program. That is: - // - If given a non-constant expression, create a new temporary AstVarScope with the given - // 'name' prefix, assign the expression to it, and return a read reference to the new - // AstVarScope. - // - If given a constant, just return that constant. - const auto capture = [&](AstNodeExpr* exprp, const std::string& name) -> AstNodeExpr* { - UASSERT_OBJ(!exprp->backp(), exprp, "Should have been unlinked"); - if (VN_IS(exprp, Const)) return exprp; - const std::string realName = "__" + name + baseName; - AstVarScope* const tmpVscp = createNewVarScope(vscp, realName, exprp->dtypep()); - insert(new AstAssign{flp, new AstVarRef{flp, tmpVscp, VAccess::WRITE}, exprp}); - return new AstVarRef{flp, tmpVscp, VAccess::READ}; - }; - - // Unlink and Capture the RHS value - AstNodeExpr* const rhsp = capture(nodep->rhsp()->unlinkFrBack(), "VdlyVal"); - - // Capture the AstSel LSB - The width is always an AstConst, so nothing to do with that - if (lhsComponents.selLsbp) { - lhsComponents.selLsbp = capture(lhsComponents.selLsbp, "VdlyLsb"); - } - - // Capture the AstArraySel indices - for (size_t i = 0; i < lhsComponents.arrIdxps.size(); ++i) { - AstNodeExpr*& arrIdxpr = lhsComponents.arrIdxps[i]; - arrIdxpr = capture(arrIdxpr, "VdlyDim" + std::to_string(i)); - } - - if (m_inSuspendableOrFork) { - if (m_inLoop && !lhsComponents.arrIdxps.empty()) { - nodep->v3warn(BLKLOOPINIT, - "Unsupported: Non-blocking assignment to array inside loop " - "in suspendable process or fork"); - return true; - } - - // Currently we convert all NBAs in suspendable blocks immediately. - if (!m_vscpAux(vscp).nonDeferredFlp) { - m_vscpAux(vscp).nonDeferredFlp = nodep->fileline(); - } - - // Get/Create 'Post' ordered block to commit the delayed value - AstAlwaysPost* postp = new AstAlwaysPost{flp}; - if (!m_procp->user2p()) { - m_procp->user2p(createActiveLike(lhsComponents.refp->fileline(), m_activep)); - } - VN_AS(m_procp->user2p(), Active)->addStmtsp(postp); - - // Create the flag denoting an update is pending - no reuse here - AstVarScope* const setVscp = createNewVarScope(vscp, "__VdlySet" + baseName, 1); - // Set the flag here - insert(new AstAssign{flp, new AstVarRef{flp, setVscp, VAccess::WRITE}, - new AstConst{flp, AstConst::BitTrue{}}}); - // Create 'if (__VdlySet) { ... commit .. }' - AstIf* const ifp = new AstIf{flp, new AstVarRef{flp, setVscp, VAccess::READ}}; - postp->addStmtsp(ifp); - // Clear __VdlySet in the post block - ifp->addThensp(new AstAssign{flp, new AstVarRef{flp, setVscp, VAccess::WRITE}, - new AstConst{flp, 0}}); - // Finally assign the delayed value to the reconstructed LHS - AstNodeExpr* const newLhsp = reconstructLhs(lhsComponents, flp); - ifp->addThensp(new AstAssign{flp, newLhsp, rhsp}); - // The original AstAssignDly ('nodep') can be deleted - return true; - } else { - if (m_inLoop) { - UASSERT_OBJ(!lhsComponents.arrIdxps.empty(), nodep, "Should be an array"); - const AstBasicDType* const basicp = vscp->dtypep()->basicp(); - if (!basicp - || !(basicp->isIntegralOrPacked() || basicp->isDouble() - || basicp->isString())) { - nodep->v3warn(BLKLOOPINIT, - "Unsupported: Non-blocking assignment to array with " - "compound element type inside loop"); - return true; - } - m_vscpAux(vscp).needsCommitQueue = true; - if (lhsComponents.selLsbp) m_vscpAux(vscp).hasPartialUpdate = true; - } - // Record this AstAssignDly for deferred processing - m_deferred.emplace_back(); - Deferred& record = m_deferred.back(); - // Populate it - record.lhsComponents = std::move(lhsComponents); - record.rhsp = rhsp; - record.activep = m_activep; - record.insertionPointp = m_insertionPointp; - record.suffix = std::move(baseName); - record.consecutive = consecutive; - // Note consecutive assignment for optimization - // If we inserted new statements, the original AstAssignDly ('nodep') - // can be deleted. Otherwise, it must be kept as a placeholder. - return m_insertionPointp != nodep; - } - } - - // Create a temporary variable in the scope of 'vscp',with the given 'name', and with 'dtypep' - // type, with the bits selected by 'sLsbp'/'sWidthp' set to 'insertp', other bits set to zero. - // Returns a read reference to the temporary variable. - AstVarRef* createWidened(FileLine* flp, AstVarScope* vscp, AstNodeDType* dtypep, - AstNodeExpr* sLsbp, AstNodeExpr* sWidthp, const std::string& name, - AstNodeExpr* insertp) { - // Create temporary variable. - AstVarScope* const tp = createNewVarScope(vscp, name, dtypep); - // Zero it - AstConst* const zerop = new AstConst{flp, AstConst::DTyped{}, dtypep}; - zerop->num().setAllBits0(); - insert(new AstAssign{flp, new AstVarRef{flp, tp, VAccess::WRITE}, zerop}); - // Set the selected bits to 'insertp' - AstSel* const selp = new AstSel{flp, new AstVarRef{flp, tp, VAccess::WRITE}, - sLsbp->cloneTreePure(true), sWidthp->cloneTreePure(true)}; - insert(new AstAssign{flp, selp, insertp}); - // This is the expression to get the value of the temporary - return new AstVarRef{flp, tp, VAccess::READ}; - }; - - // Convert the given deferred assignment for the given AstVarScope - void convertDeferred(Deferred& record) { - // Unpack all the parts - LhsComponents lhsComponents = std::move(record.lhsComponents); - AstActive*& oActivep = record.activep; // Original AstActive the AstAssignDly was under - - // Insertion point - UASSERT_OBJ(!m_insertionPointp, record.insertionPointp, "Insertion point should be null"); - VL_RESTORER(m_insertionPointp); - m_insertionPointp = record.insertionPointp; - - // If the original AstAssignDly was kept as a placeholder, we will need to delete it - AstAssignDly* const dlyp = VN_CAST(m_insertionPointp, AssignDly); - - FileLine* const flp = m_insertionPointp->fileline(); - AstVarScope* const vscp = lhsComponents.refp->varScopep(); - - // Get/Create 'Post' ordered block to commit the delayed value - AstAlwaysPost* const postp = [&]() { - if (AstAlwaysPost* const p = m_vscpAux(vscp).postp) return p; - // Make the new AstActive with identical sensitivity tree - AstActive* const activep = createActiveLike(lhsComponents.refp->fileline(), oActivep); - m_vscpAux(vscp).activep = activep; - // Add the 'Post' scheduled block - AstAlwaysPost* const p = new AstAlwaysPost{flp}; - activep->addStmtsp(p); - m_vscpAux(vscp).postp = p; - return p; - }(); - // Pick up the active block containing 'postp' - AstActive* const activep = m_vscpAux(vscp).activep; - // Ensure it contains the current sensitivities - checkActiveSense(lhsComponents.refp, activep, oActivep); - - if (m_vscpAux(vscp).needsCommitQueue) { - if (FileLine* const badFlp = m_vscpAux(vscp).nonDeferredFlp) { - m_insertionPointp->v3warn( - BLKLOOPINIT, - "Unsupported: Non-blocking assignment to array in both " - "loop and suspendable process/fork\n" - << badFlp->warnOther() - << "... Location of non-blocking assignment in suspendable process/fork\n" - << badFlp->warnContextSecondary() << m_insertionPointp->warnOther() - << "... Location of non-blocking assignment inside loop\n"); - return; - } - - // Need special handling for variables that require partial updates - const bool partial = m_vscpAux(vscp).hasPartialUpdate; - - // If partial updates are required, construct the mask and the widened value - AstNodeExpr* valuep = record.rhsp; - AstNodeExpr* maskp = nullptr; - if (partial) { - // Type of array element - AstNodeDType* const eDTypep = [&]() -> AstNodeDType* { - AstNodeDType* dtypep = vscp->dtypep()->skipRefp(); - while (AstUnpackArrayDType* const ap = VN_CAST(dtypep, UnpackArrayDType)) { - dtypep = ap->subDTypep()->skipRefp(); - } - return dtypep; - }(); - - if (AstNodeExpr* const sLsbp = lhsComponents.selLsbp) { - // This is a partial assignment. Need to create a mask and widen the value to - // element size. - AstConst* const sWidthp = lhsComponents.selWidthp; - - // Create mask value - maskp = [&]() -> AstNodeExpr* { - // Constant mask we can compute here - if (AstConst* const cLsbp = VN_CAST(sLsbp, Const)) { - AstConst* const cp = new AstConst{flp, AstConst::DTyped{}, eDTypep}; - cp->num().setAllBits0(); - const int lsb = cLsbp->toSInt(); - const int msb = lsb + sWidthp->toSInt() - 1; - for (int bit = lsb; bit <= msb; ++bit) cp->num().setBit(bit, '1'); - return cp; - } - - // A non-constant mask we must compute at run-time. - AstConst* const onesp - = new AstConst{flp, AstConst::WidthedValue{}, sWidthp->toSInt(), 0}; - onesp->num().setAllBits1(); - return createWidened(flp, vscp, eDTypep, sLsbp, sWidthp, // - "__VdlyMask" + record.suffix, onesp); - }(); - - // Adjust value to element size - valuep = [&]() -> AstNodeExpr* { - // Constant value with constant select we can compute here - if (AstConst* const cValuep = VN_CAST(valuep, Const)) { - if (AstConst* const cLsbp = VN_CAST(sLsbp, Const)) { // - AstConst* const cp - = new AstConst{flp, AstConst::DTyped{}, eDTypep}; - cp->num().setAllBits0(); - cp->num().opSelInto(cValuep->num(), cLsbp->toSInt(), - sWidthp->toSInt()); - return cp; - } - } - - // A non-constant value we must adjust. - return createWidened(flp, vscp, eDTypep, sLsbp, sWidthp, // - "__VdlyElem" + record.suffix, valuep); - }(); - - // Finished with the sel operands here - VL_DO_DANGLING(lhsComponents.selLsbp->deleteTree(), lhsComponents.selLsbp); - VL_DO_DANGLING(lhsComponents.selWidthp->deleteTree(), lhsComponents.selWidthp); - } else { - // If this assignment is not partial, set mask to ones and we are done - AstConst* const ones = new AstConst{flp, AstConst::DTyped{}, eDTypep}; - ones->num().setAllBits1(); - maskp = ones; - } - } - - // Create/get the commit queue - if (!vscp->user2p()) { - FileLine* const vflp = vscp->fileline(); - - // Statistics - if (partial) { - ++m_commitQueuesPartial; - } else { - ++m_commitQueuesWhole; - } - - // Create the commit queue variable - auto* const cqDTypep - = new AstNBACommitQueueDType{vflp, vscp->dtypep()->skipRefp(), partial}; - v3Global.rootp()->typeTablep()->addTypesp(cqDTypep); - const std::string name = "__VdlyCommitQueue" + record.suffix; - AstVarScope* const newCqp = createNewVarScope(vscp, name, cqDTypep); - newCqp->varp()->noReset(true); - vscp->user2p(newCqp); - - // Commit it in the 'Post' block - AstCMethodHard* const callp = new AstCMethodHard{ - vflp, new AstVarRef{vflp, newCqp, VAccess::READWRITE}, "commit"}; - callp->dtypeSetVoid(); - callp->addPinsp(lhsComponents.refp->cloneTreePure(false)); - postp->addStmtsp(callp->makeStmt()); - } - AstVarScope* const cqp = VN_AS(vscp->user2p(), VarScope); - - // Enqueue the update at the original location - AstCMethodHard* const callp - = new AstCMethodHard{flp, new AstVarRef{flp, cqp, VAccess::READWRITE}, "enqueue"}; - callp->dtypeSetVoid(); - callp->addPinsp(valuep); - if (maskp) callp->addPinsp(maskp); - for (AstNodeExpr* const indexp : lhsComponents.arrIdxps) callp->addPinsp(indexp); - insert(callp->makeStmt()); - } else { - // Create the flag denoting an update is pending - if (record.consecutive) { - // Simplistic optimization. If the previous assignment was immediately before this - // assignment, we can reuse the existing flag. This is good for code like: - // arrayA[0] <= something; - // arrayB[1] <= something; - ++m_statSharedSet; - } else { - // Create new flag - m_setVscp = createNewVarScope(vscp, "__VdlySet" + record.suffix, 1); - // Set it here - insert(new AstAssign{flp, new AstVarRef{flp, m_setVscp, VAccess::WRITE}, - new AstConst{flp, AstConst::BitTrue{}}}); - // Add the 'Pre' ordered reset for the flag - activep->addStmtsp(new AstAssignPre{ - flp, new AstVarRef{flp, m_setVscp, VAccess::WRITE}, new AstConst{flp, 0}}); - }; - - // Create/Get 'if (__VdlySet) { ... commit .. }' - AstIf* ifp = nullptr; - if (postp->user2p() == m_setVscp) { - // Optimize as above. If sharing VdlySet *ON SAME VARIABLE*, we can share the 'if' - ifp = VN_AS(postp->user1p(), If); - } else { - ifp = new AstIf{flp, new AstVarRef{flp, m_setVscp, VAccess::READ}}; - postp->addStmtsp(ifp); - postp->user1p(ifp); // Remember the associated 'AstIf' - postp->user2p(m_setVscp); // Remember the VdlySet variable used as the condition. - } - - // Finally assign the delayed value to the reconstructed LHS - AstNodeExpr* const newLhsp = reconstructLhs(lhsComponents, flp); - ifp->addThensp(new AstAssign{flp, newLhsp, record.rhsp}); - } - - // If the original AstAssignDelay was kept as a placeholder, we can nuke it now. - if (dlyp) pushDeletep(dlyp->unlinkFrBack()); - } - // VISITORS void visit(AstNetlist* nodep) override { iterateChildren(nodep); - // Convert all AstAssignDelay instances that were not converted during the traversal - for (Deferred& record : m_deferred) convertDeferred(record); - } - void visit(AstScope* nodep) override { - AstNode::user2ClearTree(); - iterateChildren(nodep); + // Decide which scheme to use for each variable and do the 'prepare' step + for (AstVarScope* const vscp : m_vscps) { + VarScopeInfo& vscpInfo = m_vscpInfo(vscp); + vscpInfo.m_scheme = chooseScheme(vscp, vscpInfo); + // Run 'prepare' step + switch (vscpInfo.m_scheme) { + case Scheme::Undecided: // LCOV_EXCL_START + UASSERT_OBJ(false, vscp, "Failed to choose NBA scheme"); + break; + case Scheme::UnsupportedCompoundArrayInLoop: { + // Will report error at the site of the NBA + break; + } + case Scheme::ShadowVar: { + ++m_nSchemeShadowVar; + prepareSchemeShadowVar(vscp, vscpInfo); + break; + } + case Scheme::FlagShared: { + ++m_nSchemeFlagShared; + prepareSchemeFlagShared(vscp, vscpInfo); + break; + } + case Scheme::FlagUnique: { + ++m_nSchemeFlagUnique; + prepareSchemeFlagUnique(vscp, vscpInfo); + break; + } + case Scheme::ValueQueueWhole: { + ++m_nSchemeValueQueuesWhole; + prepareSchemeValueQueue(vscp, vscpInfo); + break; + } + case Scheme::ValueQueuePartial: { + ++m_nSchemeValueQueuesPartial; + prepareSchemeValueQueue(vscp, vscpInfo); + break; + } + } + } + // Convert all NBAs + for (const NBA& nba : m_nbas) { + AstAssignDly* const nbap = nba.nodep; + AstVarScope* const vscp = nba.vscp; + VarScopeInfo& vscpInfo = m_vscpInfo(vscp); + // Run 'convert' step + switch (vscpInfo.m_scheme) { + case Scheme::Undecided: { // LCOV_EXCL_START + UASSERT_OBJ(false, vscp, "Unreachable"); + break; + } // LCOV_EXCL_STOP + case Scheme::UnsupportedCompoundArrayInLoop: { + // TODO: make this an E_UNSUPPORTED... + nbap->v3warn(BLKLOOPINIT, "Unsupported: Non-blocking assignment to array with " + "compound element type inside loop"); + break; + } + case Scheme::ShadowVar: { + convertSchemeShadowVar(nbap, vscp, vscpInfo); + break; + } + case Scheme::FlagShared: { + convertSchemeFlagShared(nbap, vscp, vscpInfo); + break; + } + case Scheme::FlagUnique: { + convertSchemeFlagUnique(nbap, vscp, vscpInfo); + break; + } + case Scheme::ValueQueueWhole: { + convertSchemeValueQueue(nbap, vscp, vscpInfo, /* partial: */ false); + break; + } + case Scheme::ValueQueuePartial: + convertSchemeValueQueue(nbap, vscp, vscpInfo, /* partial: */ true); + break; + } + } } + void visit(AstScope* nodep) override { iterateChildren(nodep); } void visit(AstCFunc* nodep) override { VL_RESTORER(m_cfuncp); m_cfuncp = nodep; @@ -675,11 +820,10 @@ class DelayedVisitor final : public VNVisitor { m_activep = nodep; AstSenTree* const senTreep = nodep->sensesp(); m_ignoreBlkAndNBlk = senTreep->hasStatic() || senTreep->hasInitial(); - // Two sets to same variable in different actives must use different vars. - AstNode::user2ClearTree(); iterateChildren(nodep); } void visit(AstNodeProcedure* nodep) override { + const size_t firstNBAAddedIndex = m_nbas.size(); { VL_RESTORER(m_inSuspendableOrFork); VL_RESTORER(m_procp); @@ -688,26 +832,24 @@ class DelayedVisitor final : public VNVisitor { iterateChildren(nodep); } if (m_timingDomains.empty()) return; - if (AstActive* const actp = VN_AS(nodep->user2p(), Active)) { - // Merge all timing domains (and possibly the original active's domain) - // to create a sentree for the pre/post logic - // TODO: allow multiple sentrees per active, so we don't have - // to merge them and create a new trigger - AstSenTree* senTreep = nullptr; - if (actp->sensesp()->hasClocked()) senTreep = actp->sensesp()->cloneTree(false); - for (AstSenTree* const domainp : m_timingDomains) { - if (!senTreep) { - senTreep = domainp->cloneTree(false); - } else { - senTreep->addSensesp(domainp->sensesp()->cloneTree(true)); - senTreep->multi(true); // Comment that it was made from multiple domains - } - } - V3Const::constifyExpensiveEdit(senTreep); // Remove duplicates - actp->sensesp(senTreep); - actp->sensesStorep(senTreep); + + // There were some timing domains involved in the process. Add all of them as sensitivities + // of all NBA targets in this process. Note this is a bit of a sledgehammer, we should only + // need those that directly preceed the NBA in control flow, but that is hard to compute, + // so we will hammer away. + + // First gather all senItems + AstSenItem* senItemp = nullptr; + for (AstSenTree* const domainp : m_timingDomains) { + senItemp = AstNode::addNext(senItemp, domainp->sensesp()->cloneTree(true)); } m_timingDomains.clear(); + // Add them to all nba targets we gathered in this process + for (size_t i = firstNBAAddedIndex; i < m_nbas.size(); ++i) { + m_vscpInfo(m_nbas[i].vscp).addSensitivity(senItemp); + } + // Done with these + VL_DO_DANGLING(senItemp->deleteTree(), senItemp); } void visit(AstFork* nodep) override { VL_RESTORER(m_inSuspendableOrFork); @@ -720,11 +862,21 @@ class DelayedVisitor final : public VNVisitor { void visit(AstFireEvent* nodep) override { UASSERT_OBJ(v3Global.hasEvents(), nodep, "Inconsistent"); FileLine* const flp = nodep->fileline(); + + AstNodeExpr* const eventp = nodep->operandp()->unlinkFrBack(); + + // Enqueue for clearing 'triggered' state on next eval + AstTextBlock* const blockp = new AstTextBlock{flp}; + blockp->addText(flp, "vlSymsp->fireEvent(", true); + blockp->addNodesp(eventp); + blockp->addText(flp, ");\n", true); + + AstNode* newp = new AstCStmt{flp, blockp}; if (nodep->isDelayed()) { - AstVarRef* const vrefp = VN_AS(nodep->operandp(), VarRef); - vrefp->unlinkFrBack(); + AstVarRef* const vrefp = VN_AS(eventp, VarRef); const std::string newvarname = "__Vdly__" + vrefp->varp()->shortName(); - AstVarScope* const dlyvscp = createNewVarScope(vrefp->varScopep(), newvarname, 1); + AstVarScope* const dlyvscp + = createTemp(flp, vrefp->varScopep()->scopep(), newvarname, 1); const auto dlyRef = [=](VAccess access) { // return new AstVarRef{flp, dlyvscp, access}; @@ -736,32 +888,20 @@ class DelayedVisitor final : public VNVisitor { { AstIf* const ifp = new AstIf{flp, dlyRef(VAccess::READ)}; postp->addStmtsp(ifp); - AstCMethodHard* const callp = new AstCMethodHard{flp, vrefp, "fire"}; - callp->dtypeSetVoid(); - ifp->addThensp(callp->makeStmt()); + ifp->addThensp(newp); } - AstActive* const activep = createActiveLike(flp, m_activep); + AstActive* const activep = new AstActive{flp, "nba-event", m_activep->sensesp()}; + m_activep->addNextHere(activep); activep->addStmtsp(prep); activep->addStmtsp(postp); - AstAssign* const assignp = new AstAssign{flp, dlyRef(VAccess::WRITE), - new AstConst{flp, AstConst::BitTrue{}}}; - nodep->replaceWith(assignp); - } else { - AstCMethodHard* const callp - = new AstCMethodHard{flp, nodep->operandp()->unlinkFrBack(), "fire"}; - callp->dtypeSetVoid(); - nodep->replaceWith(callp->makeStmt()); + newp = new AstAssign{flp, dlyRef(VAccess::WRITE), + new AstConst{flp, AstConst::BitTrue{}}}; } + nodep->replaceWith(newp); VL_DO_DANGLING(nodep->deleteTree(), nodep); } - - // Pre/Post logic are created here and their content need no further changes, so ignore. - void visit(AstAssignPre*) override {} - void visit(AstAssignPost*) override {} - void visit(AstAlwaysPost*) override {} - void visit(AstAssignDly* nodep) override { if (m_cfuncp) { if (!v3Global.rootp()->nbaEventp()) { @@ -772,85 +912,85 @@ class DelayedVisitor final : public VNVisitor { return; } UASSERT_OBJ(m_procp, nodep, "Delayed assignment not under process"); - const bool isArray = VN_IS(nodep->lhsp(), ArraySel) - || (VN_IS(nodep->lhsp(), Sel) - && VN_IS(VN_AS(nodep->lhsp(), Sel)->fromp(), ArraySel)); - if (isArray) { - if (const AstBasicDType* const basicp = nodep->lhsp()->dtypep()->basicp()) { - // TODO: this message is not covered by tests - if (basicp->isEvent()) nodep->v3warn(E_UNSUPPORTED, "Unsupported: event arrays"); - } - if (processAssignDly(nodep)) VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); - } else if (m_inSuspendableOrFork) { - const bool converted = processAssignDly(nodep); - // Current implementation always converts these - UASSERT_OBJ(converted, nodep, "NBA in suspendable processes should have be converted"); - VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); - } else { - { - VL_RESTORER(m_inDlyLhs); - m_inDlyLhs = true; - iterate(nodep->lhsp()); - } - iterate(nodep->rhsp()); - } - } + UASSERT_OBJ(m_activep, nodep, "<= not under sensitivity block"); + UASSERT_OBJ(m_inSuspendableOrFork || m_activep->hasClocked(), nodep, + "<= assignment in non-clocked block, should have been converted in V3Active"); + // Grab the reference to the target of the NBA + VL_RESTORER(m_currNbaLhsRefp); + UASSERT_OBJ(!m_currNbaLhsRefp, nodep, "NBAs should not nest"); + nodep->lhsp()->foreach([&](AstVarRef* nodep) { + // Ignore reads (e.g.: '_[*here*] <= _') + if (nodep->access().isReadOnly()) return; + // A RW ref on the LHS (e.g.: '_[preInc(*here*)] <= _') is asking for trouble at this + // point. These should be lowered in an earlier pass into sequenced temporaries. + UASSERT_OBJ(!nodep->access().isRW(), nodep, "RW ref on LHS of NBA"); + // Multiple target variables + // (e.g.: '{*here*, *and here*} <= _',or '*here*[*and here* = _] <= _'). + // These should be lowered in an earlier pass into sequenced statements. + UASSERT_OBJ(!m_currNbaLhsRefp, nodep, "Multiple Write refs on LHS of NBA"); + // Hold on to it + m_currNbaLhsRefp = nodep; + }); + // The target variable of the NBA (there can only be one per NBA at this point) + AstVarScope* const vscp = m_currNbaLhsRefp->varScopep(); + // Record it on first encounter + VarScopeInfo& vscpInfo = m_vscpInfo(vscp); + if (!vscpInfo.m_firstNbaRefp) { + vscpInfo.m_firstNbaRefp = m_currNbaLhsRefp; + vscpInfo.m_fistActivep = m_activep; + m_vscps.emplace_back(vscp); + } + // Note usage context + vscpInfo.m_partial |= VN_IS(nodep->lhsp(), Sel); + vscpInfo.m_inLoop |= m_inLoop; + vscpInfo.m_inSuspOrFork |= m_inSuspendableOrFork; + // Sensitivity might be non-clocked, in a suspendable process, which are handled elsewhere + if (m_activep->sensesp()->hasClocked()) { + if (vscpInfo.m_fistActivep != m_activep) { + AstVar* const varp = vscp->varp(); + if (!varp->user1SetOnce() + && !varp->fileline()->warnIsOff(V3ErrorCode::MULTIDRIVEN)) { + varp->v3warn(MULTIDRIVEN, + "Signal has multiple driving blocks with different clocking: " + << varp->prettyNameQ() << '\n' + << vscpInfo.m_firstNbaRefp->warnOther() + << "... Location of first driving block\n" + << vscpInfo.m_firstNbaRefp->warnContextSecondary() + << m_currNbaLhsRefp->warnOther() + << "... Location of other driving block\n" + << m_currNbaLhsRefp->warnContextPrimary() << '\n'); + } + } + // Add this sensitivity to the variable + vscpInfo.addSensitivity(m_activep->sensesp()); + } + + // Record the NBA for later processing + m_nbas.emplace_back(); + NBA& nba = m_nbas.back(); + nba.nodep = nodep; + nba.vscp = vscp; + + // Check var usage + checkVarUsage(m_currNbaLhsRefp, true); + + iterateChildren(nodep); + } void visit(AstVarRef* nodep) override { - // Ignore refs inserted by 'replaceWith' just below - if (nodep->user2()) return; + // Already checked the NBA LHS ref, ignore here + if (nodep == m_currNbaLhsRefp) return; // Only care about write refs if (!nodep->access().isWriteOrRW()) return; // Check var usage - markVarUsage(nodep, m_inDlyLhs); - - // Below we rewrite the LHS of AstAssignDelay only - if (!m_inDlyLhs) return; - - UASSERT_OBJ(!nodep->access().isRW(), nodep, "<= on read+write method"); - UASSERT_OBJ(m_activep, nodep, "<= not under sensitivity block"); - UASSERT_OBJ(m_activep->hasClocked(), nodep, - "<= assignment in non-clocked block, should have been converted in V3Active"); - - // Replace with reference to the shadow variable - FileLine* const flp = nodep->fileline(); - AstVarScope* const vscp = nodep->varScopep(); - AstVarScope*& dlyVscp = m_vscpAux(vscp).delayVscp; - - // Create the shadow variable and related active block if not yet exists - if (!dlyVscp) { - // Create the shadow variable - const std::string name = "__Vdly__" + vscp->varp()->shortName(); - dlyVscp = createNewVarScope(vscp, name, vscp->dtypep()); - // Make the new AstActive with identical sensitivity tree - AstActive* const activep = createActiveLike(flp, m_activep); - m_vscpAux(vscp).activep = activep; - - // Add 'Pre' scheduled 'shadowVariable = originalVariable' assignment - activep->addStmtsp(new AstAssignPre{flp, new AstVarRef{flp, dlyVscp, VAccess::WRITE}, - new AstVarRef{flp, vscp, VAccess::READ}}); - // Add 'Post' scheduled 'originalVariable = shadowVariable' assignment - activep->addStmtsp(new AstAssignPost{flp, new AstVarRef{flp, vscp, VAccess::WRITE}, - new AstVarRef{flp, dlyVscp, VAccess::READ}}); - } - - // Ensure the active block of the shadow variable contains the current sensitivities - checkActiveSense(nodep, m_vscpAux(vscp).activep, m_activep); - - // Replace reference with reference to the shadow variable - AstVarRef* const newRefp = new AstVarRef{flp, dlyVscp, VAccess::WRITE}; - newRefp->user2(true); // skip visit after repalce - nodep->replaceWith(newRefp); - VL_DO_DANGLING(pushDeletep(nodep), nodep); + checkVarUsage(nodep, false); } - void visit(AstNodeReadWriteMem* nodep) override { VL_RESTORER(m_ignoreBlkAndNBlk); // $readmem/$writemem often used in mem models so we suppress BLKANDNBLK warnings m_ignoreBlkAndNBlk = true; iterateChildren(nodep); } - void visit(AstNodeFor* nodep) override { // LCOV_EXCL_LINE nodep->v3fatalSrc("For statements should have been converted to while statements"); } @@ -859,12 +999,11 @@ class DelayedVisitor final : public VNVisitor { m_inLoop = true; iterateChildren(nodep); } - void visit(AstExprStmt* nodep) override { - VL_RESTORER(m_inDlyLhs); - // Restoring is needed, because AstExprStmt may contain assignments - m_inDlyLhs = false; - iterateChildren(nodep); - } + + // Pre/Post logic are created here and their content need no further changes, so ignore. + void visit(AstAssignPre*) override {} + void visit(AstAssignPost*) override {} + void visit(AstAlwaysPost*) override {} //-------------------- void visit(AstNode* nodep) override { iterateChildren(nodep); } @@ -873,11 +1012,13 @@ public: // CONSTRUCTORS explicit DelayedVisitor(AstNetlist* nodep) { iterate(nodep); } ~DelayedVisitor() override { - V3Stats::addStat("Optimizations, Delayed shared-sets", m_statSharedSet); - V3Stats::addStat("Dynamic NBA, variables needing commit queue with partial updates", - m_commitQueuesPartial); - V3Stats::addStat("Dynamic NBA, variables needing commit queue without partial updates", - m_commitQueuesWhole); + V3Stats::addStat("NBA, variables using ShadowVar scheme", m_nSchemeShadowVar); + V3Stats::addStat("NBA, variables using FlagShared scheme", m_nSchemeFlagShared); + V3Stats::addStat("NBA, variables using FlagUnique scheme", m_nSchemeFlagUnique); + V3Stats::addStat("NBA, variables using ValueQueueWhole scheme", m_nSchemeValueQueuesWhole); + V3Stats::addStat("NBA, variables using ValueQueuePartial scheme", + m_nSchemeValueQueuesPartial); + V3Stats::addStat("Optimizations, NBA flags shared", m_nSharedSetFlags); } }; diff --git a/src/V3Delayed.h b/src/V3Delayed.h index a70f8fa82..d01e25f5c 100644 --- a/src/V3Delayed.h +++ b/src/V3Delayed.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Depth.h b/src/V3Depth.h index 8ac8b2077..d563d2ad9 100644 --- a/src/V3Depth.h +++ b/src/V3Depth.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3DepthBlock.h b/src/V3DepthBlock.h index ab34bbb7c..cc1bcbfa0 100644 --- a/src/V3DepthBlock.h +++ b/src/V3DepthBlock.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Descope.h b/src/V3Descope.h index 017476129..f94f59d5a 100644 --- a/src/V3Descope.h +++ b/src/V3Descope.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Dfg.h b/src/V3Dfg.h index 18df1bddf..5fab278ee 100644 --- a/src/V3Dfg.h +++ b/src/V3Dfg.h @@ -38,7 +38,6 @@ #include "V3Global.h" #include "V3Hash.h" #include "V3List.h" -#include "V3ThreadSafety.h" #include "V3Dfg__gen_forward_class_decls.h" // From ./astgen @@ -207,11 +206,11 @@ public: UDEBUGONLY(UASSERT_OBJ(isSupportedDType(nodep->dtypep()), nodep, "Unsupported dtype");); // For simplicity, all packed types are represented with a fixed type if (AstUnpackArrayDType* const typep = VN_CAST(nodep->dtypep(), UnpackArrayDType)) { - AstNodeDType* const dtypep = new AstUnpackArrayDType{ + AstNodeDType* const adtypep = new AstUnpackArrayDType{ typep->fileline(), dtypeForWidth(typep->subDTypep()->width()), typep->rangep()->cloneTree(false)}; - v3Global.rootp()->typeTablep()->addTypesp(dtypep); - return dtypep; + v3Global.rootp()->typeTablep()->addTypesp(adtypep); + return adtypep; } return dtypeForWidth(nodep->width()); } diff --git a/src/V3DfgOptimizer.h b/src/V3DfgOptimizer.h index 0cb573c0b..067b5e801 100644 --- a/src/V3DfgOptimizer.h +++ b/src/V3DfgOptimizer.h @@ -21,7 +21,6 @@ #include "verilatedos.h" #include "V3Ast.h" -#include "V3ThreadSafety.h" //============================================================================ diff --git a/src/V3DfgPasses.h b/src/V3DfgPasses.h index 6fe0d7d54..2b1e08aa6 100644 --- a/src/V3DfgPasses.h +++ b/src/V3DfgPasses.h @@ -18,10 +18,10 @@ #define VERILATOR_V3DFGPASSES_H_ #include "config_build.h" +#include "verilatedos.h" #include "V3DfgPatternStats.h" #include "V3DfgPeephole.h" -#include "V3ThreadSafety.h" class AstModule; class DfgGraph; @@ -49,7 +49,7 @@ class V3DfgRegularizeContext final { public: VDouble0 m_temporariesIntroduced; // Number of temporaries introduced - std::string tmpNamePrefix(DfgGraph&); // Return prefix to use for given graph + std::string tmpNamePrefix(const DfgGraph&); // Return prefix to use for given graph explicit V3DfgRegularizeContext(const std::string& label) : m_label{label} {} diff --git a/src/V3DfgPeephole.cpp b/src/V3DfgPeephole.cpp index 649545c5e..531d5c35b 100644 --- a/src/V3DfgPeephole.cpp +++ b/src/V3DfgPeephole.cpp @@ -750,7 +750,7 @@ class V3DfgPeephole final : public DfgVisitor { // Full width select, replace with the source. if (fromp->width() == width) { - UASSERT_OBJ(lsb == 0, fromp, "OOPS"); + UASSERT_OBJ(lsb == 0, fromp, "Out of range select should have been fixed up earlier"); APPLYING(REMOVE_FULL_WIDTH_SEL) { replace(vtxp, fromp); return; diff --git a/src/V3DfgPeephole.h b/src/V3DfgPeephole.h index 92a228292..ff3debe57 100644 --- a/src/V3DfgPeephole.h +++ b/src/V3DfgPeephole.h @@ -18,8 +18,7 @@ #define VERILATOR_V3DFGPEEPHOLE_H_ #include "config_build.h" - -#include "V3ThreadSafety.h" +#include "verilatedos.h" #include diff --git a/src/V3DfgRegularize.cpp b/src/V3DfgRegularize.cpp index b2c836334..e521a5ebe 100644 --- a/src/V3DfgRegularize.cpp +++ b/src/V3DfgRegularize.cpp @@ -26,7 +26,7 @@ VL_DEFINE_DEBUG_FUNCTIONS; -std::string V3DfgRegularizeContext::tmpNamePrefix(DfgGraph& dfg) { +std::string V3DfgRegularizeContext::tmpNamePrefix(const DfgGraph& dfg) { // cppcheck-suppress unreadVariable // cppcheck bug V3Hash hash{dfg.modulep()->name()}; hash += m_label; diff --git a/src/V3DupFinder.h b/src/V3DupFinder.h index f22030602..81e59ee43 100644 --- a/src/V3DupFinder.h +++ b/src/V3DupFinder.h @@ -26,7 +26,6 @@ #include "V3Ast.h" #include "V3Error.h" #include "V3Hasher.h" -#include "V3ThreadSafety.h" #include #include diff --git a/src/V3EmitC.h b/src/V3EmitC.h index 6c9d90086..98231dba4 100644 --- a/src/V3EmitC.h +++ b/src/V3EmitC.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - //============================================================================ class V3EmitC final { diff --git a/src/V3EmitCBase.h b/src/V3EmitCBase.h index 0f6dca34b..28bdf76a8 100644 --- a/src/V3EmitCBase.h +++ b/src/V3EmitCBase.h @@ -22,7 +22,6 @@ #include "V3Ast.h" #include "V3File.h" -#include "V3ThreadSafety.h" #include #include @@ -68,7 +67,7 @@ public: } // Return C++ class name for a module/class object static string prefixNameProtect(const AstNode* nodep) VL_MT_STABLE; - static bool isAnonOk(const AstVar* varp) { + static bool isAnonOk(const AstVar* varp) VL_MT_STABLE { AstNodeDType* const dtp = varp->dtypep()->skipRefp(); return v3Global.opt.compLimitMembers() != 0 // Enabled && !varp->isStatic() // Not a static variable @@ -86,9 +85,38 @@ class EmitCBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst, public EmitCBa public: // STATE V3OutCFile* m_ofp = nullptr; + AstCFile* m_outFileNodep = nullptr; + int m_splitSize = 0; // # of cfunc nodes placed into output file bool m_trackText = false; // Always track AstText nodes // METHODS + + // Returns pointer to current output file object. V3OutCFile* ofp() const VL_MT_SAFE { return m_ofp; } + // Returns pointer to the AST node that represents the output file (`ofp()`) + AstCFile* outFileNodep() const VL_MT_SAFE { return m_outFileNodep; } + + // Sets ofp() and outFileNodep() to the given pointers, without closing a file these pointers + // currently point to. + void setOutputFile(V3OutCFile* ofp, AstCFile* nodep) { + m_ofp = ofp; + m_outFileNodep = nodep; + } + + // Sets ofp() and outFileNodep() to null, without closing a file these pointers currently point + // to. NOTE: Dummy nullptr argument is taken to make function calls more explicit. + void setOutputFile(std::nullptr_t nullp) { + UASSERT(nullp == nullptr, "Expected nullptr as the argument"); + m_ofp = nullp; + m_outFileNodep = nullp; + } + + // Closes current output file. Sets ofp() and outFileNodep() to nullptr. + void closeOutputFile() { + VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + m_outFileNodep->complexityScore(m_splitSize); + m_outFileNodep = nullptr; + } + void puts(const string& str) { ofp()->puts(str); } void putns(const AstNode* nodep, const string& str) { ofp()->putns(nodep, str); } void putsHeader() { ofp()->putsHeader(); } diff --git a/src/V3EmitCConstInit.h b/src/V3EmitCConstInit.h index 3950efb7a..b91ab9718 100644 --- a/src/V3EmitCConstInit.h +++ b/src/V3EmitCConstInit.h @@ -82,7 +82,9 @@ protected: for (uint64_t n = 0; n < size; ++n) { m_unpackedWord = n; if (n) puts((n % tabMod) ? ", " : ",\n"); - iterateConst(nodep->getIndexDefaultedValuep(n)); + AstNode* const itemp = nodep->getIndexDefaultedValuep(n); + UASSERT_OBJ(itemp, nodep, "Missing array init element"); + iterateConst(itemp); } puts("\n"); puts("}"); diff --git a/src/V3EmitCConstPool.cpp b/src/V3EmitCConstPool.cpp index 513d94e2e..c373e3160 100644 --- a/src/V3EmitCConstPool.cpp +++ b/src/V3EmitCConstPool.cpp @@ -30,6 +30,9 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Const pool emitter class EmitCConstPool final : public EmitCConstInit { + // TYPES + using OutCFilePair = std::pair; + // MEMBERS uint32_t m_outFileCount = 0; int m_outFileSize = 0; @@ -38,17 +41,17 @@ class EmitCConstPool final : public EmitCConstInit { // METHODS - V3OutCFile* newOutCFile() const { + OutCFilePair newOutCFile() const { const string fileName = v3Global.opt.makeDir() + "/" + topClassName() + "__ConstPool_" + cvtToStr(m_outFileCount) + ".cpp"; - newCFile(fileName, /* slow: */ true, /* source: */ true); + AstCFile* const cfilep = newCFile(fileName, /* slow: */ true, /* source: */ true); V3OutCFile* const ofp = new V3OutCFile{fileName}; ofp->putsHeader(); ofp->puts("// DESCRIPTION: Verilator output: Constant pool\n"); ofp->puts("//\n"); ofp->puts("\n"); ofp->puts("#include \"verilated.h\"\n"); - return ofp; + return {ofp, cfilep}; } void maybeSplitCFile() { @@ -56,11 +59,12 @@ class EmitCConstPool final : public EmitCConstInit { // Splitting file, so using parallel build. v3Global.useParallelBuild(true); // Close current file - VL_DO_DANGLING(delete m_ofp, m_ofp); + closeOutputFile(); // Open next file m_outFileSize = 0; ++m_outFileCount; - m_ofp = newOutCFile(); + const OutCFilePair outFileAndNodePair = newOutCFile(); + setOutputFile(outFileAndNodePair.first, outFileAndNodePair.second); } void emitVars(const AstConstPool* poolp) { @@ -75,7 +79,8 @@ class EmitCConstPool final : public EmitCConstInit { return ap->name() < bp->name(); }); - m_ofp = newOutCFile(); + const OutCFilePair outFileAndNodePair = newOutCFile(); + setOutputFile(outFileAndNodePair.first, outFileAndNodePair.second); for (const AstVar* varp : varps) { maybeSplitCFile(); @@ -95,7 +100,7 @@ class EmitCConstPool final : public EmitCConstInit { } } - VL_DO_DANGLING(delete m_ofp, m_ofp); + closeOutputFile(); } // VISITORS diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index 0e7ab1fdf..389b5d012 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -23,7 +23,6 @@ #include "V3EmitCConstInit.h" #include "V3Global.h" #include "V3MemberMap.h" -#include "V3ThreadSafety.h" #include #include @@ -119,7 +118,6 @@ class EmitCFunc VL_NOT_FINAL : public EmitCConstInit { VMemberMap m_memberMap; AstVarRef* m_wideTempRefp = nullptr; // Variable that _WW macros should be setting int m_labelNum = 0; // Next label number - int m_splitSize = 0; // # of cfunc nodes placed into output file bool m_inUC = false; // Inside an AstUCStmt or AstUCExpr bool m_emitConstInit = false; // Emitting constant initializer @@ -1005,6 +1003,7 @@ public: puts(", "); puts(cvtToStr(nodep->fileline()->lineno())); puts(", \"\""); + if (nodep->isFatal()) puts(", false"); puts(");\n"); } void visit(AstFinish* nodep) override { @@ -1215,9 +1214,8 @@ public: puts(")"); } void visit(AstNewCopy* nodep) override { - putns(nodep, "VL_NEW(" + prefixNameProtect(nodep->dtypep()) + ", " - + optionalProcArg(nodep->dtypep())); - puts("*"); // i.e. make into a reference + putns(nodep, "VL_NEW(" + prefixNameProtect(nodep->dtypep())); + puts(", *"); // i.e. make into a reference iterateAndNextConstNull(nodep->rhsp()); puts(")"); } @@ -1455,9 +1453,9 @@ public: EmitCFunc() : m_lazyDecls(*this) {} - EmitCFunc(AstNode* nodep, V3OutCFile* ofp, bool trackText = false) + EmitCFunc(AstNode* nodep, V3OutCFile* ofp, AstCFile* cfilep, bool trackText = false) : EmitCFunc{} { - m_ofp = ofp; + setOutputFile(ofp, cfilep); m_trackText = trackText; iterateConst(nodep); } diff --git a/src/V3EmitCHeaders.cpp b/src/V3EmitCHeaders.cpp index 36126ada1..839dc00ca 100644 --- a/src/V3EmitCHeaders.cpp +++ b/src/V3EmitCHeaders.cpp @@ -18,6 +18,7 @@ #include "V3EmitC.h" #include "V3EmitCConstInit.h" +#include "V3File.h" #include "V3UniqueNames.h" #include @@ -498,8 +499,11 @@ class EmitCHeader final : public EmitCConstInit { // Open output file const string filename = v3Global.opt.makeDir() + "/" + prefixNameProtect(modp) + ".h"; - newCFile(filename, /* slow: */ false, /* source: */ false); - m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename}; + AstCFile* const cfilep = newCFile(filename, /* slow: */ false, /* source: */ false); + V3OutCFile* const ofilep + = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename}; + + setOutputFile(ofilep, cfilep); ofp()->putsHeader(); puts("// DESCRIPTION: Verilator output: Design internal header\n"); @@ -539,7 +543,7 @@ class EmitCHeader final : public EmitCConstInit { ofp()->putsEndGuard(); // Close output file - VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + closeOutputFile(); } ~EmitCHeader() override = default; diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp index 2023785e7..5df77cf92 100644 --- a/src/V3EmitCImp.cpp +++ b/src/V3EmitCImp.cpp @@ -143,7 +143,7 @@ class EmitCGatherDependencies final : VNVisitorConst { } public: - static const std::set gather(AstCFunc* cfuncp) { + static const std::set gather(AstCFunc* cfuncp) VL_MT_STABLE { const EmitCGatherDependencies visitor{cfuncp}; return std::move(visitor.m_dependencies); } @@ -163,7 +163,7 @@ class EmitCImp final : EmitCFunc { // METHODS void openNextOutputFile(const std::set& headers, const string& subFileName) { - UASSERT(!m_ofp, "Output file already open"); + UASSERT(!ofp(), "Output file already open"); splitSizeReset(); // Reset file size tracking m_lazyDecls.reset(); // Need to emit new lazy declarations @@ -172,8 +172,10 @@ class EmitCImp final : EmitCFunc { // Unfortunately we have some lint checks here, so we can't just skip processing. // We should move them to a different stage. const string filename = VL_DEV_NULL; - m_cfilesr.push_back(createCFile(filename, /* slow: */ m_slow, /* source: */ true)); - m_ofp = new V3OutCFile{filename}; + AstCFile* const filep = createCFile(filename, /* slow: */ m_slow, /* source: */ true); + m_cfilesr.push_back(filep); + V3OutCFile* const ofilep = new V3OutCFile{filename}; + setOutputFile(ofilep, filep); } else { string filename = v3Global.opt.makeDir() + "/" + prefixNameProtect(m_fileModp); if (!subFileName.empty()) { @@ -182,8 +184,11 @@ class EmitCImp final : EmitCFunc { } if (m_slow) filename += "__Slow"; filename += ".cpp"; - m_cfilesr.push_back(createCFile(filename, /* slow: */ m_slow, /* source: */ true)); - m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename}; + AstCFile* const filep = createCFile(filename, /* slow: */ m_slow, /* source: */ true); + m_cfilesr.push_back(filep); + V3OutCFile* const ofilep + = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename}; + setOutputFile(ofilep, filep); } putsHeader(); @@ -321,6 +326,8 @@ class EmitCImp final : EmitCFunc { } // static doesn't need save-restore as is constant puts("static uint32_t fake_zero_count = 0;\n"); + puts("std::string fullhier = std::string{VerilatedModule::name()} + hierp;\n"); + puts("if (!fullhier.empty() && fullhier[0] == '.') fullhier = fullhier.substr(1);\n"); // Used for second++ instantiation of identical bin puts("if (!enable) count32p = &fake_zero_count;\n"); puts("*count32p = 0;\n"); @@ -329,9 +336,7 @@ class EmitCImp final : EmitCFunc { puts(" \"filename\",filenamep,"); puts(" \"lineno\",lineno,"); puts(" \"column\",column,\n"); - // Need to move hier into scopes and back out if do this - // puts( "\"hier\",std::string{vlSymsp->name()} + hierp,"); - puts("\"hier\",std::string{VerilatedModule::name()} + hierp,"); + puts("\"hier\",fullhier,"); puts(" \"page\",pagep,"); puts(" \"comment\",commentp,"); puts(" (linescovp[0] ? \"linescov\" : \"\"), linescovp);\n"); @@ -477,7 +482,7 @@ class EmitCImp final : EmitCFunc { doCommonImp(classp); } - VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + closeOutputFile(); } } void emitCFuncImp(const AstNodeModule* modp) { @@ -522,7 +527,7 @@ class EmitCImp final : EmitCFunc { iterateConst(funcp); } // Close output file - VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + closeOutputFile(); } } @@ -532,7 +537,7 @@ class EmitCImp final : EmitCFunc { // Splitting file, so using parallel build. v3Global.useParallelBuild(true); // Close old file - VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + closeOutputFile(); // Open a new file openNextOutputFile(*m_requiredHeadersp, m_subFileName); } @@ -562,7 +567,8 @@ class EmitCImp final : EmitCFunc { ~EmitCImp() override = default; public: - static void main(const AstNodeModule* modp, bool slow, std::deque& cfilesr) { + static void main(const AstNodeModule* modp, bool slow, + std::deque& cfilesr) VL_MT_STABLE { EmitCImp{modp, slow, cfilesr}; } }; @@ -586,7 +592,7 @@ class EmitCTrace final : EmitCFunc { // METHODS void openNextOutputFile() { - UASSERT(!m_ofp, "Output file already open"); + UASSERT(!ofp(), "Output file already open"); splitSizeReset(); // Reset file size tracking m_lazyDecls.reset(); // Need to emit new lazy declarations @@ -601,11 +607,10 @@ class EmitCTrace final : EmitCFunc { cfilep->support(true); m_cfilesr.push_back(cfilep); - if (optSystemC()) { - m_ofp = new V3OutScFile{filename}; - } else { - m_ofp = new V3OutCFile{filename}; - } + V3OutCFile* const ofilep + = optSystemC() ? new V3OutScFile{filename} : new V3OutCFile{filename}; + setOutputFile(ofilep, cfilep); + putsHeader(); puts("// DESCR" "IPTION: Verilator output: Tracing implementation internals\n"); @@ -903,7 +908,7 @@ class EmitCTrace final : EmitCFunc { // Splitting file, so using parallel build. v3Global.useParallelBuild(true); // Close old file - VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + closeOutputFile(); // Open a new file openNextOutputFile(); } @@ -955,7 +960,7 @@ class EmitCTrace final : EmitCFunc { if (AstCFunc* const funcp = VN_CAST(nodep, CFunc)) iterateConst(funcp); } // Close output file - VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + closeOutputFile(); if (m_slow) { callTypeSubs(); closeTypesFile(); @@ -977,7 +982,7 @@ void V3EmitC::emitcImp() { // Make parent module pointers available. const EmitCParentModule emitCParentModule; std::list> cfiles; - std::list> futures; + V3ThreadScope threadScope; // Process each module in turn for (const AstNode* nodep = v3Global.rootp()->modulesp(); nodep; nodep = nodep->nextp()) { @@ -985,29 +990,29 @@ void V3EmitC::emitcImp() { const AstNodeModule* const modp = VN_AS(nodep, NodeModule); cfiles.emplace_back(); auto& slowCfilesr = cfiles.back(); - futures.push_back(V3ThreadPool::s().enqueue( - [modp, &slowCfilesr]() { EmitCImp::main(modp, /* slow: */ true, slowCfilesr); })); + threadScope.enqueue( + [modp, &slowCfilesr] { EmitCImp::main(modp, /* slow: */ true, slowCfilesr); }); cfiles.emplace_back(); auto& fastCfilesr = cfiles.back(); - futures.push_back(V3ThreadPool::s().enqueue( - [modp, &fastCfilesr]() { EmitCImp::main(modp, /* slow: */ false, fastCfilesr); })); + threadScope.enqueue( + [modp, &fastCfilesr] { EmitCImp::main(modp, /* slow: */ false, fastCfilesr); }); } // Emit trace routines (currently they can only exist in the top module) if (v3Global.opt.trace() && !v3Global.opt.lintOnly()) { cfiles.emplace_back(); auto& slowCfilesr = cfiles.back(); - futures.push_back(V3ThreadPool::s().enqueue([&slowCfilesr]() { + threadScope.enqueue([&slowCfilesr] { EmitCTrace::main(v3Global.rootp()->topModulep(), /* slow: */ true, slowCfilesr); - })); + }); cfiles.emplace_back(); auto& fastCfilesr = cfiles.back(); - futures.push_back(V3ThreadPool::s().enqueue([&fastCfilesr]() { + threadScope.enqueue([&fastCfilesr] { EmitCTrace::main(v3Global.rootp()->topModulep(), /* slow: */ false, fastCfilesr); - })); + }); } // Wait for futures - V3ThreadPool::waitForFutures(futures); + threadScope.wait(); for (const auto& collr : cfiles) { for (const auto cfilep : collr) v3Global.rootp()->addFilesp(cfilep); } @@ -1022,7 +1027,7 @@ void V3EmitC::emitcFiles() { V3OutCFile of{cfilep->name()}; of.puts("// DESCR" "IPTION: Verilator generated C++\n"); - const EmitCFunc visitor{cfilep->tblockp(), &of, true}; + const EmitCFunc visitor{cfilep->tblockp(), &of, cfilep, true}; } } } diff --git a/src/V3EmitCMain.cpp b/src/V3EmitCMain.cpp index ac31e7f32..10bbd8769 100644 --- a/src/V3EmitCMain.cpp +++ b/src/V3EmitCMain.cpp @@ -42,9 +42,9 @@ private: // MAIN METHOD void emitInt() { const string filename = v3Global.opt.makeDir() + "/" + topClassName() + "__main.cpp"; - newCFile(filename, false /*slow*/, true /*source*/); + AstCFile* const cfilep = newCFile(filename, false /*slow*/, true /*source*/); V3OutCFile cf{filename}; - m_ofp = &cf; + setOutputFile(&cf, cfilep); // Not defining main_time/vl_time_stamp, so v3Global.opt.addCFlags("-DVL_TIME_CONTEXT"); // On MSVC++ anyways @@ -52,10 +52,7 @@ private: // Optional main top name argument, with empty string replacement string topArg; string topName = v3Global.opt.mainTopName(); - if (!topName.empty()) { - if (topName == "-") topName = ""; - topArg = ", \"" + topName + "\""; - } + if (topName == "-") topName = ""; // Heavily commented output, as users are likely to look at or copy this code ofp()->putsHeader(); @@ -77,7 +74,7 @@ private: puts("// Construct the Verilated model, from Vtop.h generated from Verilating\n"); puts("const std::unique_ptr<" + topClassName() + "> topp{new " + topClassName() - + "{contextp.get()" + topArg + "}};\n"); + + "{contextp.get(), \"" + topName + "\"}};\n"); puts("\n"); puts("// Simulate until $finish\n"); @@ -85,8 +82,10 @@ private: puts(/**/ "// Evaluate model\n"); puts(/**/ "topp->eval();\n"); puts(/**/ "// Advance time\n"); - if (v3Global.rootp()->delaySchedulerp()) { + if (v3Global.rootp()->delaySchedulerp() || v3Global.opt.timing()) { puts("if (!topp->eventsPending()) break;\n"); + } + if (v3Global.rootp()->delaySchedulerp()) { puts("contextp->time(topp->nextTimeSlot());\n"); } else { puts("contextp->timeInc(1);\n"); @@ -117,7 +116,7 @@ private: puts("return 0;\n"); puts("}\n"); - m_ofp = nullptr; + setOutputFile(nullptr); } }; diff --git a/src/V3EmitCMain.h b/src/V3EmitCMain.h index f0a8e2191..683df4573 100644 --- a/src/V3EmitCMain.h +++ b/src/V3EmitCMain.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - //============================================================================ class V3EmitCMain final { diff --git a/src/V3EmitCMake.h b/src/V3EmitCMake.h index a6ad712f5..cc0605b83 100644 --- a/src/V3EmitCMake.h +++ b/src/V3EmitCMake.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - //============================================================================ class V3EmitCMake final { diff --git a/src/V3EmitCModel.cpp b/src/V3EmitCModel.cpp index dee84efb3..54f625d13 100644 --- a/src/V3EmitCModel.cpp +++ b/src/V3EmitCModel.cpp @@ -53,11 +53,12 @@ class EmitCModel final : public EmitCFunc { } void emitHeader(AstNodeModule* modp) { - UASSERT(!m_ofp, "Output file should not be open"); + UASSERT(!ofp(), "Output file should not be open"); const string filename = v3Global.opt.makeDir() + "/" + topClassName() + ".h"; - newCFile(filename, /* slow: */ false, /* source: */ false); - m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename}; + setOutputFile(v3Global.opt.systemC() ? new V3OutScFile{filename} + : new V3OutCFile{filename}, + newCFile(filename, /* slow: */ false, /* source: */ false)); ofp()->putsHeader(); puts("// DESCRIPTION: Verilator output: Primary model header\n"); @@ -269,7 +270,7 @@ class EmitCModel final : public EmitCFunc { ofp()->putsEndGuard(); - VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + closeOutputFile(); } void emitConstructorImplementation(AstNodeModule* modp) { @@ -551,11 +552,11 @@ class EmitCModel final : public EmitCFunc { "0.\");\n"); puts("}\n"); puts("vlSymsp->__Vm_baseCode = code;\n"); - puts("if (strlen(vlSymsp->name())) tracep->pushPrefix(std::string{vlSymsp->name()}, " + puts("tracep->pushPrefix(std::string{vlSymsp->name()}, " "VerilatedTracePrefixType::SCOPE_MODULE);\n"); puts(topModNameProtected + "__" + protect("trace_decl_types") + "(tracep);\n"); puts(topModNameProtected + "__" + protect("trace_init_top") + "(vlSelf, tracep);\n"); - puts("if (strlen(vlSymsp->name())) tracep->popPrefix();\n"); + puts("tracep->popPrefix();\n"); puts("}\n"); // Forward declaration @@ -612,11 +613,12 @@ class EmitCModel final : public EmitCFunc { } void emitImplementation(AstNodeModule* modp) { - UASSERT(!m_ofp, "Output file should not be open"); + UASSERT(!ofp(), "Output file should not be open"); const string filename = v3Global.opt.makeDir() + "/" + topClassName() + ".cpp"; - newCFile(filename, /* slow: */ false, /* source: */ true); - m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename}; + setOutputFile(v3Global.opt.systemC() ? new V3OutScFile{filename} + : new V3OutCFile{filename}, + newCFile(filename, /* slow: */ false, /* source: */ true)); ofp()->putsHeader(); puts("// DESCRIPTION: Verilator output: " @@ -635,11 +637,11 @@ class EmitCModel final : public EmitCFunc { if (v3Global.opt.trace()) emitTraceMethods(modp); if (v3Global.opt.savable()) emitSerializationFunctions(); - VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + closeOutputFile(); } void emitDpiExportDispatchers(AstNodeModule* modp) { - UASSERT(!m_ofp, "Output file should not be open"); + UASSERT(!ofp(), "Output file should not be open"); // Emit DPI Export dispatchers for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) { @@ -650,19 +652,19 @@ class EmitCModel final : public EmitCFunc { // Splitting file, so using parallel build. v3Global.useParallelBuild(true); // Close old file - VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + closeOutputFile(); } - if (!m_ofp) { + if (!ofp()) { string filename = v3Global.opt.makeDir() + "/" + topClassName() + "__Dpi_Export"; filename = m_uniqueNames.get(filename); filename += ".cpp"; - newCFile(filename, /* slow: */ false, /* source: */ true); - m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename} - : new V3OutCFile{filename}; + setOutputFile(v3Global.opt.systemC() ? new V3OutScFile{filename} + : new V3OutCFile{filename}, + newCFile(filename, /* slow: */ false, /* source: */ true)); splitSizeReset(); // Reset file size tracking m_lazyDecls.reset(); - m_ofp->putsHeader(); + ofp()->putsHeader(); puts( "// DESCRIPTION: Verilator output: Implementation of DPI export functions.\n"); puts("//\n"); @@ -675,7 +677,7 @@ class EmitCModel final : public EmitCFunc { iterateConst(funcp); } - if (m_ofp) VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + if (ofp()) closeOutputFile(); } void main(AstNodeModule* modp) { diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 704e0ca92..14323fed6 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -403,13 +403,9 @@ public: void EmitCSyms::emitSymHdr() { UINFO(6, __FUNCTION__ << ": " << endl); const string filename = v3Global.opt.makeDir() + "/" + symClassName() + ".h"; - newCFile(filename, true /*slow*/, false /*source*/); - - if (v3Global.opt.systemC()) { - m_ofp = new V3OutScFile{filename}; - } else { - m_ofp = new V3OutCFile{filename}; - } + AstCFile* const cfilep = newCFile(filename, true /*slow*/, false /*source*/); + V3OutCFile* const ofilep = optSystemC() ? new V3OutScFile{filename} : new V3OutCFile{filename}; + setOutputFile(ofilep, cfilep); ofp()->putsHeader(); puts("// DESCRIPTION: Verilator output: Symbol table internal header\n"); @@ -550,22 +546,19 @@ void EmitCSyms::emitSymHdr() { if (v3Global.hasEvents()) { if (v3Global.assignsEvents()) { - puts("void enqueueTriggeredEventForClearing(VlAssignableEvent& event) {\n"); + puts("void fireEvent(VlAssignableEvent& event) {\n"); } else { - puts("void enqueueTriggeredEventForClearing(VlEvent& event) {\n"); + puts("void fireEvent(VlEvent& event) {\n"); } - puts("#ifdef VL_DEBUG\n"); - puts("if (VL_UNLIKELY(!event.isTriggered())) {\n"); - puts("VL_FATAL_MT(__FILE__, __LINE__, __FILE__, \"event passed to " - "'enqueueTriggeredEventForClearing' was not triggered\");\n"); - puts("}\n"); - puts("#endif\n"); + puts("if (VL_LIKELY(!event.isTriggered())) {\n"); if (v3Global.assignsEvents()) { puts("__Vm_triggeredEvents.push_back(event);\n"); } else { puts("__Vm_triggeredEvents.push_back(&event);\n"); } puts("}\n"); + puts("event.fire();\n"); + puts("}\n"); puts("void clearTriggeredEvents() {\n"); if (v3Global.assignsEvents()) { puts("for (auto& event : __Vm_triggeredEvents) event.clearTriggered();\n"); @@ -589,18 +582,18 @@ void EmitCSyms::emitSymHdr() { puts("};\n"); ofp()->putsEndGuard(); - VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + closeOutputFile(); } void EmitCSyms::closeSplit() { - if (!m_ofp || m_ofp == m_ofpBase) return; + if (!ofp() || ofp() == m_ofpBase) return; puts("}\n"); - VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + closeOutputFile(); } void EmitCSyms::checkSplit(bool usesVfinal) { - if (m_ofp + if (ofp() && (!v3Global.opt.outputSplitCFuncs() || m_numStmts < v3Global.opt.outputSplitCFuncs())) { return; } @@ -616,11 +609,8 @@ void EmitCSyms::checkSplit(bool usesVfinal) { m_usesVfinal[m_funcNum] = usesVfinal; closeSplit(); - if (v3Global.opt.systemC()) { - m_ofp = new V3OutScFile{filename}; - } else { - m_ofp = new V3OutCFile{filename}; - } + V3OutCFile* const ofilep = optSystemC() ? new V3OutScFile{filename} : new V3OutCFile{filename}; + setOutputFile(ofilep, cfilep); m_ofpBase->puts(symClassName() + "_" + cvtToStr(m_funcNum) + "("); if (usesVfinal) m_ofpBase->puts("__Vfinal"); @@ -700,13 +690,10 @@ void EmitCSyms::emitSymImp() { AstCFile* const cfilep = newCFile(filename, true /*slow*/, true /*source*/); cfilep->support(true); - if (v3Global.opt.systemC()) { - m_ofp = new V3OutScFile{filename}; - } else { - m_ofp = new V3OutCFile{filename}; - } + V3OutCFile* const ofilep = optSystemC() ? new V3OutScFile{filename} : new V3OutCFile{filename}; + setOutputFile(ofilep, cfilep); - m_ofpBase = m_ofp; + m_ofpBase = ofp(); emitSymImpPreamble(); if (v3Global.opt.savable()) { @@ -1036,7 +1023,7 @@ void EmitCSyms::emitSymImp() { m_ofpBase->puts("}\n"); closeSplit(); - m_ofp = nullptr; + setOutputFile(nullptr); VL_DO_CLEAR(delete m_ofpBase, m_ofpBase = nullptr); } @@ -1048,9 +1035,9 @@ void EmitCSyms::emitDpiHdr() { AstCFile* const cfilep = newCFile(filename, false /*slow*/, false /*source*/); cfilep->support(true); V3OutCFile hf{filename}; - m_ofp = &hf; + setOutputFile(&hf, cfilep); - m_ofp->putsHeader(); + ofp()->putsHeader(); puts("// DESCR" "IPTION: Verilator output: Prototypes for DPI import and export functions.\n"); puts("//\n"); @@ -1092,7 +1079,7 @@ void EmitCSyms::emitDpiHdr() { puts("#endif\n"); ofp()->putsEndGuard(); - m_ofp = nullptr; + setOutputFile(nullptr); } //###################################################################### @@ -1103,9 +1090,9 @@ void EmitCSyms::emitDpiImp() { AstCFile* const cfilep = newCFile(filename, false /*slow*/, true /*source*/); cfilep->support(true); V3OutCFile hf(filename); - m_ofp = &hf; + setOutputFile(&hf, cfilep); - m_ofp->putsHeader(); + ofp()->putsHeader(); puts("// DESCR" "IPTION: Verilator output: Implementation of DPI export functions.\n"); puts("//\n"); @@ -1149,7 +1136,7 @@ void EmitCSyms::emitDpiImp() { puts("\n"); } } - m_ofp = nullptr; + setOutputFile(nullptr); } //###################################################################### diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index 02c7e7b6a..48c6ad247 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -24,18 +24,502 @@ VL_DEFINE_DEBUG_FUNCTIONS; +// Groups adjacent files in a list, evenly distributing sum of scores +class EmitGroup final { +public: + struct FileOrConcatenatedFilesList final { + const std::string m_filename; // Filename or output group filename if grouping + std::vector m_concatenatedFilenames; // Grouped filenames if grouping + + bool isConcatenatingFile() const { return !m_concatenatedFilenames.empty(); } + }; + + struct FilenameWithScore final { + const std::string m_filename; // Input filename + const uint64_t m_score; // Input file complexity + }; + +private: + // Data of a single work unit used in `singleConcatenatedFilesList()`. + struct WorkList final { + uint64_t m_totalScore = 0; // Sum of scores of included files + std::vector m_files; // Included filenames + int m_bucketsNum + = 0; // Number of buckets assigned for this list. Used only in concatenable lists. + bool m_isConcatenable = true; // Indicated whether files on this list can be concatenated. + const int m_dbgId; // Work list ID for debugging. + + WorkList() = delete; + WorkList(int id) + : m_dbgId{id} {} + }; + + // MAIN PARAMETERS + + // Minimum number of input files required to perform concatenation. + // Concatenation of a small number of files does not give any performance advantages. + // The value has been chosen arbitrarily, most likely could be larger. + static constexpr size_t MIN_FILES_COUNT = 16; + + // Concatenation of only a few files most likely does not increase performance. + // The value has been chosen arbitrarily. + static constexpr size_t MIN_FILES_PER_BUCKET = 4; + + // MEMBERS + + const std::vector + m_inputFiles; // List of filenames from initial AstCFile list + std::vector + m_outputFiles; // Output list of files and group files + const uint64_t m_totalScore; // Sum of file scores + const std::string m_groupFilePrefix; // Prefix for output group filenames + std::vector m_workLists; // Lists of small enough files + std::unique_ptr m_logp; // Dump file + std::vector m_concatenableListsByDescSize; // Lists sorted by size, descending + + EmitGroup(std::vector inputFiles, uint64_t totalScore, + std::string groupFilePrefix) + : m_inputFiles{std::move(inputFiles)} + , m_totalScore{totalScore} + , m_groupFilePrefix{groupFilePrefix} {} + + // Debug logging: prints scores histogram + void dumpLogScoreHistogram(std::ostream& os) { + constexpr int MAX_BAR_LENGTH = 80; + constexpr int MAX_INTERVALS_NUM = 60; + + // All scores arranged in ascending order. + std::vector sortedScores; + sortedScores.reserve(m_inputFiles.size()); + std::transform(m_inputFiles.begin(), m_inputFiles.end(), std::back_inserter(sortedScores), + [](const FilenameWithScore& inputFile) { return inputFile.m_score; }); + std::sort(sortedScores.begin(), sortedScores.end()); + + const int64_t topScore = sortedScores.back(); + os << "Top score: " << topScore << endl; + const int maxScoreWidth = std::to_string(topScore).length(); + + const int64_t intervalsNum = std::min(topScore + 1, MAX_INTERVALS_NUM); + + struct Interval final { + uint64_t m_lowerBound = 0; + int m_size = 0; + }; + + std::vector intervals; + intervals.resize(intervalsNum); + + intervals[0].m_lowerBound = 0; + for (int i = 1; i < intervalsNum; i++) { + intervals[i].m_lowerBound = (topScore + 1) * i / intervalsNum + 1; + } + + for (const uint64_t score : sortedScores) { + const unsigned int ivIdx = score * intervalsNum / (topScore + 1); + ++intervals[ivIdx].m_size; + } + + int topIntervalSize = 0; + for (const Interval& iv : intervals) + topIntervalSize = std::max(topIntervalSize, iv.m_size); + + os << "Input files' scores histogram:" << endl; + + for (const Interval& iv : intervals) { + const int scaledSize = iv.m_size * (MAX_BAR_LENGTH + 1) / topIntervalSize; + std::string line = " |" + std::string(scaledSize, '#'); + + os << std::setw(maxScoreWidth) << iv.m_lowerBound << line << " " << iv.m_size << '\n'; + } + os << std::setw(maxScoreWidth) << (topScore + 1) << '\n'; + os << endl; + } + + // PRIVATE METHODS + + // Debug logging: dumps Work Lists and their lists of files + void dumpWorkLists(std::ostream& os) { + os << "Initial Work Lists with their concatenation eligibility status:" << endl; + for (const WorkList& list : m_workLists) { + os << "+ [" << (list.m_isConcatenable ? 'x' : ' ') << "] Work List #" << list.m_dbgId + << " (num of files: " << list.m_files.size() + << "; total score: " << list.m_totalScore << ")\n"; + if (debug() >= 6 || list.m_files.size() < 4) { + // Log all files + for (const FilenameWithScore& file : list.m_files) + os << "| + " << file.m_filename << " (score: " << file.m_score << ")\n"; + } else { + // Log only first and last file + const FilenameWithScore& first = list.m_files.front(); + const FilenameWithScore& last = list.m_files.back(); + os << "| + " << first.m_filename << " (score: " << first.m_score << ")\n"; + os << "| | (... " << (list.m_files.size() - 2) << " files ...)\n"; + os << "| + " << last.m_filename << " (score: " << last.m_score << ")\n"; + } + } + os << endl; + } + + // Debug logging: dumps list of output files. List of grouped files is additionally printed + // for each concatenating file. + void dumpOutputList(std::ostream& os) const { + os << "List of output files after execution of concatenation:" << endl; + + for (const FileOrConcatenatedFilesList& entry : m_outputFiles) { + if (entry.isConcatenatingFile()) { + os << "+ " << entry.m_filename << " (concatenating file)\n"; + for (const string& f : entry.m_concatenatedFilenames) { + os << "| + " << f << '\n'; + } + } else { + os << "+ " << entry.m_filename << '\n'; + } + } + } + + // Called when the concatenation is aborted, creates an identity mapping + bool fallbackNoGrouping(size_t inputFilesCount) { + const int totalBucketsNum = v3Global.opt.outputGroups(); + // Return early if there's nothing to do. + bool groupingRedundant = false; + if (inputFilesCount < MIN_FILES_COUNT) { + UINFO(4, "File concatenation skipped: Too few files (" + << m_inputFiles.size() << " < " << MIN_FILES_COUNT << ")" << endl); + groupingRedundant = true; + } + if (inputFilesCount < (MIN_FILES_PER_BUCKET * totalBucketsNum)) { + UINFO(4, "File concatenation skipped: Too few files per bucket (" + << m_inputFiles.size() << " < " << MIN_FILES_PER_BUCKET << " - " + << totalBucketsNum << ")" << endl); + groupingRedundant = true; + } + if (!groupingRedundant) return false; + + m_outputFiles.reserve(m_inputFiles.size()); + for (const FilenameWithScore& filename : m_inputFiles) { + m_outputFiles.push_back({std::move(filename.m_filename), {}}); + } + return true; + } + + void createWorkLists() { + // Create initial Work Lists. + + const int totalBucketsNum = v3Global.opt.outputGroups(); + // Input files with a score exceeding this value are excluded from concatenation. + const uint64_t concatenableFileMaxScore = m_totalScore / totalBucketsNum / 2; + + V3Stats::addStat("Concatenation max score", concatenableFileMaxScore); + int nextWorkListId = 0; + + if (m_logp) *m_logp << "Input files with their concatenation eligibility status:" << endl; + for (const FilenameWithScore& inputFile : m_inputFiles) { + const bool fileIsConcatenable = (inputFile.m_score <= concatenableFileMaxScore); + if (m_logp) + *m_logp << " + [" << (fileIsConcatenable ? 'x' : ' ') << "] " + << inputFile.m_filename << " (score: " << inputFile.m_score << ")" + << endl; + V3Stats::addStatSum(fileIsConcatenable ? "Concatenation total grouped score" + : "Concatenation total non-grouped score", + inputFile.m_score); + // Add new list if the last list's concatenability does not match the inputFile's + // concatenability + if (m_workLists.empty() || m_workLists.back().m_isConcatenable != fileIsConcatenable) { + m_workLists.push_back(WorkList{nextWorkListId++}); + m_workLists.back().m_isConcatenable = fileIsConcatenable; + } + // Add inputFile to the last list + WorkList& list = m_workLists.back(); + list.m_files.push_back({inputFile.m_filename, inputFile.m_score}); + list.m_totalScore += inputFile.m_score; + } + if (m_logp) *m_logp << endl; + } + + void assignBuckets(uint64_t concatenableFilesTotalScore) { + // Assign buckets to lists + + const size_t totalBucketsNum = v3Global.opt.outputGroups(); + + // More concatenable lists than buckets. Exclude lists with lowest number of files. + // Does not happen very often due to files being already filtered out by comparison of + // their score to ConcatenableFilesMaxScore. + if (m_concatenableListsByDescSize.size() > totalBucketsNum) { + // Debugging: Log which work lists will be kept + if (m_logp) { + *m_logp << "More Work Lists than buckets; " + "Work Lists with statuses indicating whether the list will be kept:" + << endl; + // Only lists that will be kept. List that will be removed are logged below. + std::for_each(m_concatenableListsByDescSize.begin(), + m_concatenableListsByDescSize.begin() + totalBucketsNum, + [&](WorkList* listp) { + *m_logp << "+ [x] Work List #" << listp->m_dbgId + << " (num of files: " << listp->m_files.size() + << "; total score: " << listp->m_totalScore << ")\n"; + }); + } + // NOTE: Not just debug logging - notice `isConcatenable` assignment in the loop. + std::for_each(m_concatenableListsByDescSize.begin() + totalBucketsNum, + m_concatenableListsByDescSize.end(), [&](WorkList* listp) { + listp->m_isConcatenable = false; + + if (m_logp) + *m_logp << "+ [ ] Work List #" << listp->m_dbgId + << " (num of files: " << listp->m_files.size() + << "; total score: " << listp->m_totalScore << ")\n"; + }); + if (m_logp) *m_logp << endl; + + m_concatenableListsByDescSize.resize(totalBucketsNum); + // Recalculate stats + concatenableFilesTotalScore = 0; + for (WorkList* listp : m_concatenableListsByDescSize) { + concatenableFilesTotalScore += listp->m_totalScore; + } + } + + const uint64_t idealBucketScore = concatenableFilesTotalScore / totalBucketsNum; + + V3Stats::addStat("Concatenation ideal bucket score", idealBucketScore); + + if (m_logp) *m_logp << "Buckets assigned to Work Lists:" << endl; + int availableBuckets = v3Global.opt.outputGroups(); + for (WorkList* listp : m_concatenableListsByDescSize) { + if (availableBuckets > 0) { + listp->m_bucketsNum = std::min( + availableBuckets, std::max(1, listp->m_totalScore / idealBucketScore)); + availableBuckets -= listp->m_bucketsNum; + if (m_logp) + *m_logp << "+ [" << std::setw(2) << listp->m_bucketsNum << "] Work List #" + << listp->m_dbgId << '\n'; + } else { + // Out of buckets. Instead of recalculating everything just exclude the list. + listp->m_isConcatenable = false; + if (m_logp) + *m_logp << "+ [ 0] Work List #" << std::left << std::setw(4) << listp->m_dbgId + << std::right << " (excluding from concatenation)\n"; + } + } + if (m_logp) *m_logp << endl; + } + + void buildOutputList() { + // Assign files to buckets and build final list of files + + // At this point the workLists contains concatenatable file lists separated by one or more + // non-concatenable file lists. Each concatenatable list has N buckets (where N > 0) + // assigned to it, which have to be filled with files from this list. Ideally, sum of file + // scores in every bucket should be the same. + int concatenatedFileId = 0; + for (WorkList& list : m_workLists) { + if (!list.m_isConcatenable) { + for (FilenameWithScore& file : list.m_files) { + m_outputFiles.push_back({std::move(file.m_filename), {}}); + } + continue; + } + + // Ideal bucket score limited to buckets and score of the current Work List. + const uint64_t listIdealBucketScore = list.m_totalScore / list.m_bucketsNum; + + auto fileIt = list.m_files.begin(); + for (int i = 0; i < list.m_bucketsNum; ++i) { + FileOrConcatenatedFilesList bucket{v3Global.opt.prefix() + "_" + m_groupFilePrefix + + std::to_string(concatenatedFileId++), + {}}; + + uint64_t bucketScore = 0; + + for (; fileIt != list.m_files.end(); ++fileIt) { + const uint64_t diffNow + = std::abs((int64_t)(listIdealBucketScore - bucketScore)); + const uint64_t diffIfAdded = std::abs( + (int64_t)(listIdealBucketScore - bucketScore - fileIt->m_score)); + if (bucketScore == 0 || fileIt->m_score == 0 || diffNow > diffIfAdded) { + // Bucket score will be better with the file in it. + bucketScore += fileIt->m_score; + bucket.m_concatenatedFilenames.push_back(std::move(fileIt->m_filename)); + } else { + // Best possible bucket score reached, process next bucket. + break; + } + } + + if (bucket.m_concatenatedFilenames.size() == 1) { + // Unwrap the bucket if it contains only one file. + m_outputFiles.push_back( + {std::move(bucket.m_concatenatedFilenames.front()), {}}); + } else if (bucket.m_concatenatedFilenames.size() > 1) { + m_outputFiles.push_back(std::move(bucket)); + } + // Most likely no bucket will be empty in normal situations. If it happen the + // bucket will just be dropped. + } + for (; fileIt != list.m_files.end(); ++fileIt) { + // The Work List is out of buckets, but some files were left. + // Add them to the last bucket. + m_outputFiles.back().m_concatenatedFilenames.push_back(fileIt->m_filename); + } + } + } + + void assertFilesSame() const { + auto ifIt = m_inputFiles.begin(); + auto ofIt = m_outputFiles.begin(); + while (ifIt != m_inputFiles.end() && ofIt != m_outputFiles.end()) { + if (ofIt->isConcatenatingFile()) { + for (const string& ocf : ofIt->m_concatenatedFilenames) { + UASSERT(ifIt != m_inputFiles.end(), + "More output files than input files. First extra file: " << ocf); + UASSERT(ifIt->m_filename == ocf, + "Name mismatch: " << ifIt->m_filename << " != " << ocf); + ++ifIt; + } + ++ofIt; + } else { + UASSERT(ifIt->m_filename == ofIt->m_filename, + "Name mismatch: " << ifIt->m_filename << " != " << ofIt->m_filename); + ++ifIt; + ++ofIt; + } + } + UASSERT(ifIt == m_inputFiles.end(), + "More input files than input files. First extra file: " << ifIt->m_filename); + UASSERT(ofIt == m_outputFiles.end(), + "More output files than input files. First extra file: " << ofIt->m_filename); + } + + void process() { + UINFO(4, __FUNCTION__ << ":" << endl); + UINFO(5, "Number of input files: " << m_inputFiles.size() << endl); + UINFO(5, "Total score: " << m_totalScore << endl); + UINFO(5, "Group file prefix: " << m_groupFilePrefix << endl); + + const int totalBucketsNum = v3Global.opt.outputGroups(); + UINFO(5, "Number of buckets: " << totalBucketsNum << endl); + UASSERT(totalBucketsNum > 0, "More than 0 buckets required"); + + if (fallbackNoGrouping(m_inputFiles.size())) return; + + if (dumpLevel() >= 6) { + const string filename = v3Global.debugFilename("outputgroup") + ".txt"; + m_logp = std::unique_ptr{V3File::new_ofstream(filename)}; + if (m_logp->fail()) v3fatal("Can't write " << filename); + } + + if (m_logp) dumpLogScoreHistogram(*m_logp); + + createWorkLists(); + + // Collect stats and mark lists with only one file as non-concatenable + + size_t concatenableFilesCount = 0; + int64_t concatenableFilesTotalScore = 0; + + for (WorkList& list : m_workLists) { + if (!list.m_isConcatenable) continue; + + // "Concatenation" of a single file is pointless + if (list.m_files.size() == 1) { + list.m_isConcatenable = false; + UINFO(5, "Excluding from concatenation: Work List contains only one file: " + "Work List #" + << list.m_dbgId << endl); + continue; + } + + concatenableFilesCount += list.m_files.size(); + concatenableFilesTotalScore += list.m_totalScore; + // This vector is sorted below + m_concatenableListsByDescSize.push_back(&list); + } + + if (m_logp) dumpWorkLists(*m_logp); + + // Check concatenation conditions again using more precise data + if (fallbackNoGrouping(concatenableFilesCount)) return; + + std::sort(m_concatenableListsByDescSize.begin(), m_concatenableListsByDescSize.end(), + [](const WorkList* ap, const WorkList* bp) { + // Sort in descending order by number of files + if (ap->m_files.size() != bp->m_files.size()) + return (ap->m_files.size() > bp->m_files.size()); + // As a fallback sort in ascending order by totalSize. This makes lists + // with higher score more likely to be excluded. + return bp->m_totalScore > ap->m_totalScore; + }); + + assignBuckets(concatenableFilesTotalScore); + + buildOutputList(); + + if (m_logp) dumpOutputList(*m_logp); + assertFilesSame(); + } + +public: + static std::vector + singleConcatenatedFilesList(std::vector inputFiles, uint64_t totalScore, + std::string groupFilePrefix) { + EmitGroup group{std::move(inputFiles), totalScore, groupFilePrefix}; + group.process(); + return group.m_outputFiles; + } +}; + // ###################################################################### // Emit statements and expressions class EmitMk final { + using FileOrConcatenatedFilesList = EmitGroup::FileOrConcatenatedFilesList; + using FilenameWithScore = EmitGroup::FilenameWithScore; + public: // METHODS + static void emitConcatenatingFile(const FileOrConcatenatedFilesList& entry) { + UASSERT(entry.isConcatenatingFile(), "Passed entry does not represent concatenating file"); + + V3OutCFile concatenatingFile{v3Global.opt.makeDir() + "/" + entry.m_filename + ".cpp"}; + concatenatingFile.putsHeader(); + for (const string& file : entry.m_concatenatedFilenames) { + concatenatingFile.puts("#include \"" + file + ".cpp\"\n"); + } + } + void putMakeClassEntry(V3OutMkFile& of, const string& name) { of.puts("\t" + V3Os::filenameNonDirExt(name) + " \\\n"); } void emitClassMake() { + std::vector vmClassesSlowList; + std::vector vmClassesFastList; + if (v3Global.opt.outputGroups() > 0) { + std::vector slowFiles; + std::vector fastFiles; + uint64_t slowTotalScore = 0; + uint64_t fastTotalScore = 0; + + for (AstNodeFile* nodep = v3Global.rootp()->filesp(); nodep; + nodep = VN_AS(nodep->nextp(), NodeFile)) { + const AstCFile* const cfilep = VN_CAST(nodep, CFile); + if (cfilep && cfilep->source() && cfilep->support() == false) { + std::vector& files = cfilep->slow() ? slowFiles : fastFiles; + uint64_t& totalScore = cfilep->slow() ? slowTotalScore : fastTotalScore; + + totalScore += cfilep->complexityScore(); + files.push_back( + {V3Os::filenameNonDirExt(cfilep->name()), cfilep->complexityScore()}); + } + } + + vmClassesSlowList = EmitGroup::singleConcatenatedFilesList( + std::move(slowFiles), slowTotalScore, "vm_classes_Slow_"); + vmClassesFastList = EmitGroup::singleConcatenatedFilesList( + std::move(fastFiles), fastTotalScore, "vm_classes_"); + } + // Generate the makefile V3OutMkFile of{v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + "_classes.mk"}; of.putsHeader(); @@ -113,6 +597,13 @@ public: putMakeClassEntry(of, "verilated_profiler.cpp"); } } else if (support == 2 && slow) { + } else if (support == 0 && v3Global.opt.outputGroups() > 0) { + const std::vector& list + = slow ? vmClassesSlowList : vmClassesFastList; + for (const FileOrConcatenatedFilesList& entry : list) { + if (entry.isConcatenatingFile()) { emitConcatenatingFile(entry); } + putMakeClassEntry(of, entry.m_filename); + } } else { for (AstNodeFile* nodep = v3Global.rootp()->filesp(); nodep; nodep = VN_AS(nodep->nextp(), NodeFile)) { @@ -213,9 +704,12 @@ public: const V3StringSet& cppFiles = v3Global.opt.cppFiles(); for (const auto& cppfile : cppFiles) { of.puts("\t" + V3Os::filenameNonDirExt(cppfile) + " \\\n"); - const string dir = V3Os::filenameDir(cppfile); + const string dir + = V3Os::filenameRelativePath(V3Os::filenameDir(cppfile), v3Global.opt.makeDir()); dirs.insert(dir); } + dirs.insert(V3Os::filenameRelativePath(".", v3Global.opt.makeDir())); + of.puts("\n"); of.puts("# User .cpp directories (from .cpp's on Verilator command line)\n"); diff --git a/src/V3EmitMk.h b/src/V3EmitMk.h index 61118a92a..a9b612a01 100644 --- a/src/V3EmitMk.h +++ b/src/V3EmitMk.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class V3HierBlockPlan; //============================================================================ diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index 6c1fd1d16..c3c9c7d8b 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -375,7 +375,10 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public EmitCBaseVisitorConst { iterateAndNextConstNull(nodep->lhsp()); puts(";\n"); } - void visit(AstStop* nodep) override { putfs(nodep, "$stop;\n"); } + void visit(AstStop* nodep) override { + emitVerilogFormat(nodep, nodep->emitVerilog()); + puts(";\n"); + } void visit(AstFinish* nodep) override { putfs(nodep, "$finish;\n"); } void visit(AstStmtExpr* nodep) override { iterateConst(nodep->exprp()); diff --git a/src/V3EmitV.h b/src/V3EmitV.h index c1839080f..2d15c39d2 100644 --- a/src/V3EmitV.h +++ b/src/V3EmitV.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNode; class AstSenTree; diff --git a/src/V3EmitXml.h b/src/V3EmitXml.h index 5d005b83a..04ae09ebc 100644 --- a/src/V3EmitXml.h +++ b/src/V3EmitXml.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - //============================================================================ class V3EmitXml final { diff --git a/src/V3Error.cpp b/src/V3Error.cpp index ac6cc65b5..60164e66c 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -23,6 +23,7 @@ # include "V3Stats.h" VL_DEFINE_DEBUG_FUNCTIONS; #endif +#include // clang-format on //====================================================================== @@ -88,7 +89,18 @@ void V3ErrorGuarded::vlAbortOrExit() VL_REQUIRES(m_mutex) { if (V3Error::debugDefault()) { std::cerr << msgPrefix() << "Aborting since under --debug" << endl; V3Error::vlAbort(); - } else { + } +#ifndef V3ERROR_NO_GLOBAL_ + else if (v3Global.opt.verilateJobs() > 1 + && v3Global.mainThreadId() != std::this_thread::get_id()) { + VL_GCOV_DUMP(); // No static destructors are called, thus must be called manually. + + // Exit without triggering any global destructors. + // Used to prevent detached V3ThreadPool jobs accessing destroyed static objects. + ::_exit(1); + } +#endif + else { std::exit(1); } } @@ -111,7 +123,7 @@ void V3ErrorGuarded::v3errorEnd(std::ostringstream& sstr, const string& extra) // Skip suppressed messages if (m_errorSuppressed // On debug, show only non default-off warning to prevent pages of warnings - && (!debug() || m_errorCode.defaultsOff())) + && (!debug() || debug() < 3 || m_errorCode.defaultsOff())) return; string msg = msgPrefix() + sstr.str(); // If suppressed print only first line to reduce verbosity @@ -209,7 +221,6 @@ void V3ErrorGuarded::v3errorEnd(std::ostringstream& sstr, const string& extra) #ifndef V3ERROR_NO_GLOBAL_ if (dumpTreeLevel() || dumpTreeJsonLevel() || debug()) { V3Broken::allowMidvisitorCheck(true); - const V3ThreadPool::ScopedExclusiveAccess exclusiveAccess; if (dumpTreeLevel()) { v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("final.tree", 990)); } @@ -222,8 +233,6 @@ void V3ErrorGuarded::v3errorEnd(std::ostringstream& sstr, const string& extra) V3Stats::statsFinalAll(v3Global.rootp()); V3Stats::statsReport(); } - // Abort in exclusive access to make sure other threads - // don't change error code vlAbortOrExit(); } #endif @@ -276,27 +285,14 @@ void V3Error::vlAbort() { VL_GCOV_DUMP(); std::abort(); } -void V3Error::v3errorAcquireLock(bool mtDisabledCodeUnit) VL_ACQUIRE(s().m_mutex) { -#if !defined(V3ERROR_NO_GLOBAL_) - if (!mtDisabledCodeUnit) { - V3Error::s().m_mutex.lockCheckStopRequest( - []() -> void { V3ThreadPool::s().waitIfStopRequested(); }); - } else { - V3Error::s().m_mutex.lock(); - } -#else +std::ostringstream& V3Error::v3errorPrep(V3ErrorCode code) VL_ACQUIRE(s().m_mutex) { V3Error::s().m_mutex.lock(); -#endif -} -std::ostringstream& V3Error::v3errorPrep(V3ErrorCode code, bool mtDisabledCodeUnit) - VL_ACQUIRE(s().m_mutex) { - v3errorAcquireLock(mtDisabledCodeUnit); s().v3errorPrep(code); return v3errorStr(); } -std::ostringstream& V3Error::v3errorPrepFileLine(V3ErrorCode code, const char* file, int line, - bool mtDisabledCodeUnit) VL_ACQUIRE(s().m_mutex) { - v3errorPrep(code, mtDisabledCodeUnit) << file << ":" << std::dec << line << ": "; +std::ostringstream& V3Error::v3errorPrepFileLine(V3ErrorCode code, const char* file, int line) + VL_ACQUIRE(s().m_mutex) { + v3errorPrep(code) << file << ":" << std::dec << line << ": "; return v3errorStr(); } std::ostringstream& V3Error::v3errorStr() VL_REQUIRES(s().m_mutex) { return s().v3errorStr(); } diff --git a/src/V3Error.h b/src/V3Error.h index aa81fd5ba..e2b669be3 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -24,9 +24,6 @@ // Limited V3 headers here - this is a base class for Vlc etc #include "V3String.h" -#ifndef VL_MT_DISABLED_CODE_UNIT -#include "V3ThreadPool.h" -#endif #include #include @@ -531,11 +528,8 @@ public: // Internals for v3error()/v3fatal() macros only // Error end takes the string stream to output, be careful to seek() as needed - static void v3errorAcquireLock(bool checkStopRequest) VL_ACQUIRE(s().m_mutex); - static std::ostringstream& v3errorPrep(V3ErrorCode code, bool mtDisabledCodeUnit) - VL_ACQUIRE(s().m_mutex); - static std::ostringstream& v3errorPrepFileLine(V3ErrorCode code, const char* file, int line, - bool mtDisabledCodeUnit) + static std::ostringstream& v3errorPrep(V3ErrorCode code) VL_ACQUIRE(s().m_mutex); + static std::ostringstream& v3errorPrepFileLine(V3ErrorCode code, const char* file, int line) VL_ACQUIRE(s().m_mutex); static std::ostringstream& v3errorStr() VL_REQUIRES(s().m_mutex); // static, but often overridden in classes. @@ -563,12 +557,9 @@ void v3errorEndFatal(std::ostringstream& sstr) // the comma operator (,) to guarantee the execution order here. #define v3errorBuildMessage(prep, msg) \ (prep, static_cast(V3Error::v3errorStr() << msg)) -#define v3warnCode(code, msg) \ - v3errorEnd( \ - v3errorBuildMessage(V3Error::v3errorPrep(code, VL_MT_DISABLED_CODE_UNIT_DEFINED), msg)) +#define v3warnCode(code, msg) v3errorEnd(v3errorBuildMessage(V3Error::v3errorPrep(code), msg)) #define v3warnCodeFatal(code, msg) \ - v3errorEndFatal( \ - v3errorBuildMessage(V3Error::v3errorPrep(code, VL_MT_DISABLED_CODE_UNIT_DEFINED), msg)) + v3errorEndFatal(v3errorBuildMessage(V3Error::v3errorPrep(code), msg)) #define v3warn(code, msg) v3warnCode(V3ErrorCode::code, msg) #define v3info(msg) v3warnCode(V3ErrorCode::EC_INFO, msg) #define v3error(msg) v3warnCode(V3ErrorCode::EC_ERROR, msg) @@ -578,13 +569,10 @@ void v3errorEndFatal(std::ostringstream& sstr) // Use this instead of fatal() to mention the source code line. #define v3fatalSrc(msg) \ v3errorEndFatal(v3errorBuildMessage( \ - V3Error::v3errorPrepFileLine(V3ErrorCode::EC_FATALSRC, __FILE__, __LINE__, \ - VL_MT_DISABLED_CODE_UNIT_DEFINED), \ - msg)) + V3Error::v3errorPrepFileLine(V3ErrorCode::EC_FATALSRC, __FILE__, __LINE__), msg)) // Use this when normal v3fatal is called in static method that overrides fileline. #define v3fatalStatic(msg) \ - ::v3errorEndFatal(v3errorBuildMessage( \ - V3Error::v3errorPrep(V3ErrorCode::EC_FATAL, VL_MT_DISABLED_CODE_UNIT_DEFINED), msg)) + ::v3errorEndFatal(v3errorBuildMessage(V3Error::v3errorPrep(V3ErrorCode::EC_FATAL), msg)) #define UINFO(level, stmsg) \ do { \ @@ -669,7 +657,7 @@ void v3errorEndFatal(std::ostringstream& sstr) // Takes an optional "name" (as __VA_ARGS__) #define VL_DEFINE_DUMP(func, tag) \ - VL_ATTR_UNUSED static int dump##func() { \ + VL_ATTR_UNUSED static int dump##func() VL_MT_SAFE { \ static int level = -1; \ if (VL_UNLIKELY(level < 0)) { \ const unsigned dumpTag = v3Global.opt.dumpLevel(tag); \ diff --git a/src/V3ExecGraph.cpp b/src/V3ExecGraph.cpp index f42a4e87d..63649f9c8 100644 --- a/src/V3ExecGraph.cpp +++ b/src/V3ExecGraph.cpp @@ -48,7 +48,7 @@ void ExecMTask::dump(std::ostream& str) const { if (priority() || cost()) str << " [pr=" << priority() << " c=" << cvtToStr(cost()) << "]"; } -uint32_t ExecMTask::s_nextId = 0; +std::atomic ExecMTask::s_nextId{0}; namespace V3ExecGraph { diff --git a/src/V3ExecGraph.h b/src/V3ExecGraph.h index 4cbaa475d..9b672a780 100644 --- a/src/V3ExecGraph.h +++ b/src/V3ExecGraph.h @@ -21,7 +21,8 @@ #include "verilatedos.h" #include "V3Graph.h" -#include "V3ThreadSafety.h" + +#include class AstNetlist; class AstMTaskBody; @@ -34,7 +35,7 @@ class ExecMTask final : public V3GraphVertex { private: AstMTaskBody* const m_bodyp; // Task body const uint32_t m_id; // Unique ID of this ExecMTask. - static uint32_t s_nextId; // Next ID to use + static std::atomic s_nextId; // Next ID to use const std::string m_hashName; // Hashed name based on body for profile-driven optimization // Predicted critical path from the start of this mtask to the ends of the graph that are // reachable from this mtask. In abstract time units. @@ -58,7 +59,7 @@ public: string hashName() const { return m_hashName; } void dump(std::ostream& str) const; - static uint32_t numUsedIds() { return s_nextId; } + static uint32_t numUsedIds() VL_MT_SAFE { return s_nextId; } }; inline std::ostream& operator<<(std::ostream& os, const ExecMTask& rhs) { diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp index 1ea5bf865..efe51bed3 100644 --- a/src/V3Expand.cpp +++ b/src/V3Expand.cpp @@ -551,7 +551,7 @@ class ExpandVisitor final : public VNVisitor { const int lsb = lhsp->lsbConst(); const int msb = lhsp->msbConst(); V3Number maskset{nodep, destp->widthMin()}; - for (int bit = lsb; bit < (msb + 1); bit++) maskset.setBit(bit, 1); + maskset.setMask(msb + 1 - lsb, lsb); V3Number maskold{nodep, destp->widthMin()}; maskold.opNot(maskset); if (destwide) { @@ -654,7 +654,7 @@ class ExpandVisitor final : public VNVisitor { fixCloneLvalue(oldvalp); V3Number maskwidth{nodep, destp->widthMin()}; - for (int bit = 0; bit < lhsp->widthConst(); bit++) maskwidth.setBit(bit, 1); + maskwidth.setMask(lhsp->widthConst()); if (destp->isQuad() && !rhsp->isQuad()) rhsp = new AstCCast{nfl, rhsp, nodep}; if (!ones) { diff --git a/src/V3Expand.h b/src/V3Expand.h index 249a1dfd3..c97a273f4 100644 --- a/src/V3Expand.h +++ b/src/V3Expand.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Force.h b/src/V3Force.h index 89d678cb9..f1c8fe315 100644 --- a/src/V3Force.h +++ b/src/V3Force.h @@ -21,8 +21,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Fork.cpp b/src/V3Fork.cpp index 05ad1e938..4f0a6490c 100644 --- a/src/V3Fork.cpp +++ b/src/V3Fork.cpp @@ -173,6 +173,12 @@ public: new AstVarRef{varp->fileline(), varp, VAccess::READ}}; initsp = AstNode::addNext(initsp, initAsgnp); } + + if (AstBasicDType* const dtypep = VN_CAST(varp->dtypep()->skipRefp(), BasicDType)) { + v3Global.setAssignsEvents(); + if (dtypep->isEvent()) continue; + } + if (varp->direction().isWritable()) { AstMemberSel* const memberselp = new AstMemberSel{ varp->fileline(), @@ -416,7 +422,12 @@ class DynScopeVisitor final : public VNVisitor { ForkDynScopeFrame* const framep = frameOf(nodep->varp()); if (!framep) return; if (needsDynScope(nodep)) { - if (m_afterTimingControl && nodep->varp()->isWritable() + bool isEvent = false; + if (AstBasicDType* const dtypep = VN_CAST(nodep->dtypep()->skipRefp(), BasicDType)) { + v3Global.setAssignsEvents(); + isEvent = dtypep->isEvent(); + } + if (!isEvent && m_afterTimingControl && nodep->varp()->isWritable() && nodep->access().isWriteOrRW()) { // The output variable may not exist after a delay, so we can't just write to it nodep->v3warn( diff --git a/src/V3Fork.h b/src/V3Fork.h index 02f234989..4671d5901 100644 --- a/src/V3Fork.h +++ b/src/V3Fork.h @@ -21,8 +21,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Gate.h b/src/V3Gate.h index 9314c3cb7..b6d3c66fe 100644 --- a/src/V3Gate.h +++ b/src/V3Gate.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Global.cpp b/src/V3Global.cpp index da0b90b01..bb4170898 100644 --- a/src/V3Global.cpp +++ b/src/V3Global.cpp @@ -26,6 +26,7 @@ #include "V3Parse.h" #include "V3ParseSym.h" #include "V3Stats.h" +#include "V3ThreadPool.h" VL_DEFINE_DEBUG_FUNCTIONS; @@ -39,6 +40,7 @@ void V3Global::boot() { void V3Global::shutdown() { VL_DO_CLEAR(delete m_hierPlanp, m_hierPlanp = nullptr); // delete nullptr is safe + VL_DO_CLEAR(delete m_threadPoolp, m_threadPoolp = nullptr); // delete nullptr is safe #ifdef VL_LEAK_CHECKS if (m_rootp) VL_DO_CLEAR(m_rootp->deleteTree(), m_rootp = nullptr); #endif @@ -56,6 +58,13 @@ void V3Global::readFiles() { V3Parse parser{v3Global.rootp(), &filter, &parseSyms}; + // Read .vlt files + const V3StringSet& vltFiles = v3Global.opt.vltFiles(); + for (const string& filename : vltFiles) { + parser.parseFile(new FileLine{FileLine::commandLineFilename()}, filename, false, + "Cannot find file containing .vlt file: "); + } + // Parse the std package if (v3Global.opt.std()) { parser.parseFile(new FileLine{V3Options::getStdPackagePath()}, diff --git a/src/V3Global.h b/src/V3Global.h index 0826bf994..0b3f755b3 100644 --- a/src/V3Global.h +++ b/src/V3Global.h @@ -30,14 +30,15 @@ #include "V3FileLine.h" #include "V3Mutex.h" #include "V3Options.h" -#include "V3ThreadSafety.h" #include +#include #include #include class AstNetlist; class V3HierBlockPlan; +class V3ThreadPool; //====================================================================== // Restorer @@ -101,6 +102,8 @@ class V3Global final { // created by makeInitNetlist(} so static constructors run first V3HierBlockPlan* m_hierPlanp = nullptr; // Hierarchical Verilation plan, // nullptr unless hier_block, set via hierPlanp(V3HierBlockPlan*} + V3ThreadPool* m_threadPoolp = nullptr; // Thread Pool, + // nullptr unless 'verilatedJobs' is known, set via threadPoolp(V3ThreadPool*) VWidthMinUsage m_widthMinUsage = VWidthMinUsage::LINT_WIDTH; // What AstNode::widthMin() is used for @@ -131,6 +134,9 @@ class V3Global final { // Names of fields that were dumped by dumpJsonPtr() std::unordered_set m_jsonPtrNames; + // Id of the main thread + const std::thread::id m_mainThreadId = std::this_thread::get_id(); + public: // Options V3Options opt; // All options; let user see them directly @@ -142,6 +148,11 @@ public: // ACCESSORS (general) AstNetlist* rootp() const VL_MT_SAFE { return m_rootp; } + V3ThreadPool* threadPoolp() const VL_PURE { return m_threadPoolp; } + void threadPoolp(V3ThreadPool* threadPoolp) { + UASSERT(!m_threadPoolp, "attempted to create multiple threadPool singletons"); + m_threadPoolp = threadPoolp; + } VWidthMinUsage widthMinUsage() const VL_PURE { return m_widthMinUsage; } bool assertDTypesResolved() const { return m_assertDTypesResolved; } bool assertScoped() const { return m_assertScoped; } @@ -196,6 +207,7 @@ public: void ptrNamesDumpJson(std::ostream& os); void idPtrMapDumpJson(std::ostream& os); const std::string& ptrToId(const void* p); + std::thread::id mainThreadId() const { return m_mainThreadId; } }; extern V3Global v3Global; diff --git a/src/V3Graph.h b/src/V3Graph.h index 47515b540..911c909b3 100644 --- a/src/V3Graph.h +++ b/src/V3Graph.h @@ -23,7 +23,6 @@ #include "V3Error.h" #include "V3List.h" #include "V3Rtti.h" -#include "V3ThreadSafety.h" #include #include diff --git a/src/V3GraphPathChecker.h b/src/V3GraphPathChecker.h index dfa043f46..495d8cca8 100644 --- a/src/V3GraphPathChecker.h +++ b/src/V3GraphPathChecker.h @@ -20,7 +20,6 @@ #include "V3Error.h" #include "V3Graph.h" #include "V3GraphAlg.h" -#include "V3ThreadSafety.h" //###################################################################### diff --git a/src/V3Hasher.cpp b/src/V3Hasher.cpp index a74b75419..9b8be0dc3 100644 --- a/src/V3Hasher.cpp +++ b/src/V3Hasher.cpp @@ -33,9 +33,24 @@ class HasherVisitor final : public VNVisitorConst { // STATE V3Hash m_hash; // Hash value accumulator const bool m_cacheInUser4; // Use user4 to cache each V3Hash? + std::set m_visited; // Keeps track of some visited nodes to prevent + // infinite recursion // METHODS + void guardRecursion(AstNode* const nodep, std::function&& f) { + // Guard against infinite recursion if there's no caching + // Otherwise caching does the same but faster + if (!m_cacheInUser4) { + if (m_visited.find(nodep) != m_visited.end()) { + m_hash += V3Hash{nodep->name()}; + return; + } + m_visited.insert(nodep); + } + f(); + } + V3Hash hashNodeAndIterate(AstNode* nodep, bool hashDType, bool hashChildren, std::function&& f) { // See comments in visit(AstCFunc) about this breaking recursion @@ -45,7 +60,7 @@ class HasherVisitor final : public VNVisitorConst { VL_RESTORER(m_hash); // Reset accumulator m_hash = V3Hash{nodep->type()}; // Node type - f(); // Node specific hash + f(); // Node-specific hash if (hashDType && nodep != nodep->dtypep()) iterateConstNull(nodep->dtypep()); // Node dtype if (hashChildren) iterateChildrenConst(nodep); // Children @@ -59,7 +74,7 @@ class HasherVisitor final : public VNVisitorConst { constexpr static bool HASH_DTYPE = true; constexpr static bool HASH_CHILDREN = true; - // Each visitor below contributes to the hash any node specific content + // Each visitor below contributes to the hash any node-specific content // that is not dependent on either of the following, as these are // included by default by hashNode: // - Node type (as given by AstNode::type()) @@ -410,14 +425,16 @@ class HasherVisitor final : public VNVisitorConst { }); } void visit(AstCFunc* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // - // We might be in a recursive function, if so on *second* call - // here we need to break what would be an infinite loop. - nodep->user4(V3Hash{1}.value()); // Set this "first" call - // So that a second call will then exit hashNodeAndIterate - // Having a constant in the hash just means the recursion will - // end, it shouldn't change the CFunc having a unique hash itself. - m_hash += nodep->isLoose(); + guardRecursion(nodep, [this, nodep]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // + // We might be in a recursive function, if so on *second* call + // here we need to break what would be an infinite loop. + if (m_cacheInUser4) nodep->user4(V3Hash{1}.value()); // Set this "first" call + // So that a second call will then exit hashNodeAndIterate + // Having a constant in the hash just means the recursion will + // end, it shouldn't change the CFunc having a unique hash itself. + m_hash += nodep->isLoose(); + }); }); } void visit(AstVar* nodep) override { @@ -469,8 +486,12 @@ class HasherVisitor final : public VNVisitorConst { [this, nodep]() { m_hash += nodep->name(); }); } void visit(AstNodeFTask* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // - m_hash += nodep->name(); + guardRecursion(nodep, [this, nodep]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // + m_hash += nodep->name(); + // See comments in AstCFunc + if (m_cacheInUser4) nodep->user4(V3Hash{1}.value()); + }); }); } void visit(AstModport* nodep) override { diff --git a/src/V3HierBlock.h b/src/V3HierBlock.h index bbbdcf137..d3ac4906c 100644 --- a/src/V3HierBlock.h +++ b/src/V3HierBlock.h @@ -20,7 +20,6 @@ #include "verilatedos.h" #include "V3Options.h" -#include "V3ThreadSafety.h" #include #include diff --git a/src/V3Inline.h b/src/V3Inline.h index be83e68f8..f1d0faad3 100644 --- a/src/V3Inline.h +++ b/src/V3Inline.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Inst.h b/src/V3Inst.h index dc97bfde3..fe23c469f 100644 --- a/src/V3Inst.h +++ b/src/V3Inst.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstAssignW; class AstCell; class AstNetlist; diff --git a/src/V3InstrCount.h b/src/V3InstrCount.h index 614f54e88..143721f49 100644 --- a/src/V3InstrCount.h +++ b/src/V3InstrCount.h @@ -21,8 +21,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNode; class V3InstrCount final { diff --git a/src/V3Interface.h b/src/V3Interface.h index 05ed4678b..2ff3c71a9 100644 --- a/src/V3Interface.h +++ b/src/V3Interface.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Life.h b/src/V3Life.h index a80859a6b..36c6970ac 100644 --- a/src/V3Life.h +++ b/src/V3Life.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3LifePost.h b/src/V3LifePost.h index cf48e2e02..8a4552b00 100644 --- a/src/V3LifePost.h +++ b/src/V3LifePost.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp index 1e543197e..c240cf76a 100644 --- a/src/V3LinkCells.cpp +++ b/src/V3LinkCells.cpp @@ -247,10 +247,30 @@ class LinkCellsVisitor final : public VNVisitor { // Note cannot do modport resolution here; modports are allowed underneath generates } + void visit(AstPackageExport* nodep) override { + // Package Import: We need to do the package before the use of a package + iterateChildren(nodep); + if (!nodep->packagep()) { + AstNodeModule* const modp = resolveModule(nodep, nodep->pkgName()); + if (AstPackage* const pkgp = VN_CAST(modp, Package)) nodep->packagep(pkgp); + if (!nodep->packagep()) { + nodep->v3error("Export package not found: " << nodep->prettyPkgNameQ()); + return; + } + } + } void visit(AstPackageImport* nodep) override { // Package Import: We need to do the package before the use of a package iterateChildren(nodep); - UASSERT_OBJ(nodep->packagep(), nodep, "Unlinked package"); // Parser should set packagep + if (!nodep->packagep()) { + AstNodeModule* const modp = resolveModule(nodep, nodep->pkgName()); + if (AstPackage* const pkgp = VN_CAST(modp, Package)) nodep->packagep(pkgp); + // If not found, V3LinkDot will report errors + if (!nodep->packagep()) { + nodep->v3error("Import package not found: " << nodep->prettyPkgNameQ()); + return; + } + } new V3GraphEdge{&m_graph, vertex(m_modp), vertex(nodep->packagep()), 1, false}; } @@ -490,12 +510,13 @@ class LinkCellsVisitor final : public VNVisitor { nodep->addNextHere(varp); nodep->hasIfaceVar(true); } - if (nodep->hasNoParens()) { - nodep->v3error("Interface instantiation " - << nodep->prettyNameQ() << " requires parenthesis\n" - << nodep->warnMore() << "... Suggest use '" << nodep->prettyName() - << "()'"); - } + } + if (nodep->hasNoParens()) { + // Need in the grammar, otherwise it looks like "id/*data_type*/ id/*new_var*/;" + nodep->v3error("Instantiation " << nodep->prettyNameQ() + << " requires parenthesis (IEEE 1800-2023 23.3.2)\n" + << nodep->warnMore() << "... Suggest use '" + << nodep->prettyName() << "()'"); } if (nodep->modp()) { // iterateChildren(nodep); diff --git a/src/V3LinkCells.h b/src/V3LinkCells.h index 639a71eff..5400ed83b 100644 --- a/src/V3LinkCells.h +++ b/src/V3LinkCells.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; class VInFilter; class V3ParseSym; diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 0cbf72f68..41a449d33 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -69,6 +69,7 @@ #include "V3Graph.h" #include "V3MemberMap.h" #include "V3Parse.h" +#include "V3Randomize.h" #include "V3String.h" #include "V3SymTable.h" @@ -166,6 +167,10 @@ public: const std::unique_ptr logp{V3File::new_ofstream(filename)}; if (logp->fail()) v3fatal("Can't write " << filename); std::ostream& os = *logp; + // TODO the symbol table has node pointers which may be + // dangling, as we call deleteTree in these visitors without + // pushing for later deletion (or deleting from the symbol table) + // So, only completely safe to call this when under --debug or --debug-leak. m_syms.dumpSelf(os); bool first = true; for (int samn = 0; samn < SAMN__MAX; ++samn) { @@ -484,6 +489,15 @@ public: } } else if (ifacerefp->ifaceViaCellp()->dead()) { if (varp->isIfaceRef()) { + if (forPrimary() && !varp->isIfaceParent() + && !v3Global.opt.topIfacesSupported()) { + // Only AstIfaceRefDType's at this point correspond to ports; + // haven't made additional ones for interconnect yet, so assert is simple + // What breaks later is we don't have a Scope/Cell representing + // the interface to attach to + varp->v3warn(E_UNSUPPORTED, + "Unsupported: Interfaced port on top level module"); + } ifacerefp->v3error("Parent instance's interface is not found: " << AstNode::prettyNameQ(ifacerefp->ifaceName())); } else { @@ -577,13 +591,22 @@ private: return findp; } + VSymEnt* findWithAltFlat(VSymEnt* symp, const string& name, const string& altname) { + VSymEnt* findp = symp->findIdFlat(name); + if (findp) return findp; + if (altname != "") { + UINFO(8, " alt flat\n"); + findp = symp->findIdFlat(altname); + } + return findp; + } + public: VSymEnt* findDotted(FileLine* refLocationp, VSymEnt* lookupSymp, const string& dotname, - string& baddot, VSymEnt*& okSymp) { + string& baddot, VSymEnt*& okSymp, bool firstId) { // Given a dotted hierarchy name, return where in scope it is // Note when dotname=="" we just fall through and return lookupSymp UINFO(8, " dottedFind se" << cvtToHex(lookupSymp) << " '" << dotname << "'" << endl); - bool firstId = true; string leftname = dotname; okSymp = lookupSymp; // So can list bad scopes while (leftname != "") { // foreach dotted part of xref name @@ -666,7 +689,7 @@ public: if (!lookupSymp) return nullptr; // Not found } } else { // Searching for middle submodule, must be a cell name - if (VSymEnt* const findSymp = findWithAltFallback(lookupSymp, ident, altIdent)) { + if (VSymEnt* const findSymp = findWithAltFlat(lookupSymp, ident, altIdent)) { lookupSymp = findSymp; } else { return nullptr; // Not found @@ -701,7 +724,8 @@ public: } } - VSymEnt* findSymPrefixed(VSymEnt* lookupSymp, const string& dotname, string& baddot) { + VSymEnt* findSymPrefixed(VSymEnt* lookupSymp, const string& dotname, string& baddot, + bool fallback) { // Find symbol in given point in hierarchy, allowing prefix (post-Inline) // For simplicity lookupSymp may be passed nullptr result from findDotted if (!lookupSymp) return nullptr; @@ -709,11 +733,15 @@ public: << dotname << " under se" << cvtToHex(lookupSymp) << ((lookupSymp->symPrefix() == "") ? "" : " as ") << ((lookupSymp->symPrefix() == "") ? "" : lookupSymp->symPrefix() + dotname) - << " at se" << lookupSymp << endl); + << " at se" << lookupSymp << " fallback=" << fallback << endl); string prefix = lookupSymp->symPrefix(); VSymEnt* foundp = nullptr; while (!foundp) { - foundp = lookupSymp->findIdFallback(prefix + dotname); // Might be nullptr + if (fallback) { + foundp = lookupSymp->findIdFallback(prefix + dotname); // Might be nullptr + } else { + foundp = lookupSymp->findIdFlat(prefix + dotname); // Might be nullptr + } if (prefix.empty()) break; const string nextPrefix = removeLastInlineScope(prefix); if (prefix == nextPrefix) break; @@ -892,8 +920,8 @@ class LinkDotFindVisitor final : public VNVisitor { } else { VSymEnt* const upperSymp = m_statep->dunitEntp(); m_scope = nodep->name(); - m_curSymp = m_modSymp = m_statep->insertBlock( - upperSymp, nodep->name() + "::", nodep, m_classOrPackagep); + m_curSymp = m_modSymp = m_statep->insertBlock(upperSymp, nodep->name(), nodep, + m_classOrPackagep); UINFO(9, "New module scope " << m_curSymp << endl); } } @@ -1000,7 +1028,8 @@ class LinkDotFindVisitor final : public VNVisitor { const string scope = origname.substr(0, pos); string baddot; VSymEnt* okSymp; - aboveSymp = m_statep->findDotted(nodep->fileline(), aboveSymp, scope, baddot, okSymp); + aboveSymp + = m_statep->findDotted(nodep->fileline(), aboveSymp, scope, baddot, okSymp, false); UASSERT_OBJ(aboveSymp, nodep, "Can't find instance insertion point at " << AstNode::prettyNameQ(baddot) << " in: " << nodep->prettyNameQ()); @@ -1025,7 +1054,8 @@ class LinkDotFindVisitor final : public VNVisitor { const string ident = dottedname.substr(pos + std::strlen("__DOT__")); string baddot; VSymEnt* okSymp; - aboveSymp = m_statep->findDotted(nodep->fileline(), aboveSymp, dotted, baddot, okSymp); + aboveSymp = m_statep->findDotted(nodep->fileline(), aboveSymp, dotted, baddot, okSymp, + false); UASSERT_OBJ(aboveSymp, nodep, "Can't find cellinline insertion point at " << AstNode::prettyNameQ(baddot) << " in: " << nodep->prettyNameQ()); @@ -1087,11 +1117,18 @@ class LinkDotFindVisitor final : public VNVisitor { VL_RESTORER(m_curSymp); VSymEnt* upSymp = m_curSymp; { - if (VN_IS(m_curSymp->nodep(), Class) - && VN_AS(m_curSymp->nodep(), Class)->isInterfaceClass() && !nodep->pureVirtual() - && !nodep->isConstructor()) { - nodep->v3error("Interface class functions must be pure virtual" - << " (IEEE 1800-2023 8.26): " << nodep->prettyNameQ()); + if (VN_IS(m_curSymp->nodep(), Class)) { + if (VN_AS(m_curSymp->nodep(), Class)->isInterfaceClass() && !nodep->pureVirtual() + && !nodep->isConstructor()) { + nodep->v3error("Interface class functions must be pure virtual" + << " (IEEE 1800-2023 8.26): " << nodep->prettyNameQ()); + } + if (m_statep->forPrimary() + && (nodep->name() == "randomize" || nodep->name() == "srandom")) { + nodep->v3error(nodep->prettyNameQ() + << " is a predefined class method; redefinition not allowed" + " (IEEE 1800-2023 18.6.3)"); + } } // Change to appropriate package if extern declaration (vs definition) if (nodep->classOrPackagep()) { @@ -1296,9 +1333,10 @@ class LinkDotFindVisitor final : public VNVisitor { } else { findvarp->combineType(nodep); findvarp->fileline()->modifyStateInherit(nodep->fileline()); - if (nodep->getChildDTypep()->numeric().isSigned() - && !findvarp->getChildDTypep()->numeric().isSigned()) { - findvarp->getChildDTypep()->numeric(VSigning{true}); + UASSERT_OBJ(nodep->subDTypep(), nodep, "Var has no type"); + if (nodep->subDTypep()->numeric().isSigned() + && !findvarp->subDTypep()->numeric().isSigned()) { + findvarp->subDTypep()->numeric(VSigning{true}); } AstBasicDType* const bdtypep = VN_CAST(findvarp->childDTypep(), BasicDType); @@ -1459,6 +1497,7 @@ class LinkDotFindVisitor final : public VNVisitor { } void visit(AstPackageImport* nodep) override { UINFO(4, " Link: " << nodep << endl); + if (!nodep->packagep()) return; // Errored in V3LinkCells VSymEnt* const srcp = m_statep->getNodeSym(nodep->packagep()); if (nodep->name() == "*") { if (nodep->packagep() != v3Global.rootp()->stdPackagep()) { @@ -1469,10 +1508,7 @@ class LinkDotFindVisitor final : public VNVisitor { } } else { VSymEnt* const impp = srcp->findIdFlat(nodep->name()); - if (!impp) { - nodep->v3error("Import object not found: '" << nodep->packagep()->prettyName() - << "::" << nodep->prettyName() << "'"); - } + if (!impp) { nodep->v3error("Import object not found: " << nodep->prettyPkgNameQ()); } } m_curSymp->importFromPackage(m_statep->symsp(), srcp, nodep->name()); UINFO(9, " Link Done: " << nodep << endl); @@ -1480,6 +1516,7 @@ class LinkDotFindVisitor final : public VNVisitor { } void visit(AstPackageExport* nodep) override { UINFO(9, " Link: " << nodep << endl); + if (!nodep->packagep()) return; // Errored in V3LinkCells VSymEnt* const srcp = m_statep->getNodeSym(nodep->packagep()); if (nodep->name() != "*") { VSymEnt* const impp = srcp->findIdFlat(nodep->name()); @@ -1857,15 +1894,15 @@ class LinkDotScopeVisitor final : public VNVisitor { string baddot; VSymEnt* okSymp; VSymEnt* cellSymp = m_statep->findDotted(nodep->fileline(), m_modSymp, ifcellname, - baddot, okSymp); + baddot, okSymp, false); UASSERT_OBJ( cellSymp, nodep, "No symbol for interface instance: " << nodep->prettyNameQ(ifcellname)); UINFO(5, " Found interface instance: se" << cvtToHex(cellSymp) << " " << cellSymp->nodep() << endl); if (dtypep->modportName() != "") { - VSymEnt* const mpSymp = m_statep->findDotted(nodep->fileline(), m_modSymp, - ifcellname, baddot, okSymp); + VSymEnt* const mpSymp = m_statep->findDotted( + nodep->fileline(), m_modSymp, ifcellname, baddot, okSymp, false); UASSERT_OBJ(mpSymp, nodep, "No symbol for interface modport: " << nodep->prettyNameQ(dtypep->modportName())); @@ -1926,7 +1963,7 @@ class LinkDotScopeVisitor final : public VNVisitor { string baddot; VSymEnt* okSymp; symp = m_statep->findDotted(nodep->rhsp()->fileline(), m_modSymp, scopename, - baddot, okSymp); + baddot, okSymp, false); if (inl == "") break; inl = LinkDotState::removeLastInlineScope(inl); } @@ -1952,7 +1989,7 @@ class LinkDotScopeVisitor final : public VNVisitor { string baddot; VSymEnt* okSymp; VSymEnt* const symp = m_statep->findDotted(nodep->lhsp()->fileline(), m_modSymp, - scopename, baddot, okSymp); + scopename, baddot, okSymp, false); UASSERT_OBJ(symp, nodep, "No symbol for interface alias lhs"); UINFO(5, " Found a linked scope LHS: " << scopename << " se" << cvtToHex(symp) << " " << symp->nodep() << endl); @@ -2083,12 +2120,14 @@ class LinkDotResolveVisitor final : public VNVisitor { // TYPES enum DotPosition : uint8_t { + // Must match ascii() method below DP_NONE = 0, // Not under a DOT DP_PACKAGE, // {package}:: DOT - DP_SCOPE, // [DOT...] {scope-or-var} DOT + DP_FIRST, // {scope-or-var} DOT + DP_SCOPE, // DOT... {scope-or-var} DOT DP_FINAL, // [DOT...] {var-or-func-or-dtype} with no following dots - DP_MEMBER - }; // DOT {member-name} [DOT...] + DP_MEMBER // DOT {member-name} [DOT...] + }; // STATE LinkDotState* const m_statep; // State, including dotted symbol table @@ -2101,6 +2140,7 @@ class LinkDotResolveVisitor final : public VNVisitor { AstNodeFTask* m_ftaskp = nullptr; // Current function/task AstMethodCall* m_randMethodCallp = nullptr; // Current randomize() method call int m_modportNum = 0; // Uniqueify modport numbers + int m_indent = 0; // Indentation (tree depth) for debug bool m_inSens = false; // True if in senitem bool m_inWith = false; // True if in with std::map m_ifClassImpNames; // Names imported from interface class @@ -2135,14 +2175,18 @@ class LinkDotResolveVisitor final : public VNVisitor { m_unlinkedScopep = nullptr; } string ascii() const { - static const char* const names[] = {"NONE", "PACKAGE", "SCOPE", "FINAL", "MEMBER"}; + static const char* const names[] + = {"DP_NONE", "DP_PACKAGE", "DP_FIRST", "DP_SCOPE", "DP_FINAL", "DP_MEMBER"}; std::ostringstream sstr; sstr << "ds=" << names[m_dotPos]; sstr << " dse" << cvtToHex(m_dotSymp); - sstr << " sup=" << m_super; + sstr << "(" << m_dotSymp->nodep()->typeName() << ")"; + + if (m_dotErr) sstr << " [dotErr]"; + if (m_super) sstr << " [super]"; + if (m_unresolvedCell) sstr << " [unrCell]"; + if (m_unresolvedClass) sstr << " [unrClass]"; sstr << " txt=" << m_dotText; - sstr << " unrCell=" << m_unresolvedCell; - sstr << " unrClass=" << m_unresolvedClass; return sstr.str(); } } m_ds; // State to preserve across recursions @@ -2224,10 +2268,13 @@ class LinkDotResolveVisitor final : public VNVisitor { } void checkNoDot(AstNode* nodep) { if (VL_UNLIKELY(m_ds.m_dotPos != DP_NONE)) { - // UINFO(9, "ds=" << m_ds.ascii() << endl); - nodep->v3error("Syntax error: Not expecting " << nodep->type() << " under a " - << nodep->backp()->type() - << " in dotted expression"); + // UINFO(9, indent() << "ds=" << m_ds.ascii() << endl); + nodep->v3error("Syntax error: Not expecting " + << nodep->type() << " under a " << nodep->backp()->type() + << " in dotted expression\n" + << nodep->warnContextPrimary() << m_ds.m_dotp->warnOther() + << "... Resolving this reference\n" + << m_ds.m_dotp->warnContextSecondary()); m_ds.m_dotErr = true; } } @@ -2250,22 +2297,7 @@ class LinkDotResolveVisitor final : public VNVisitor { } } VSymEnt* getCreateClockingEventSymEnt(AstClocking* clockingp) { - if (!clockingp->eventp()) { - AstVar* const eventp = new AstVar{ - clockingp->fileline(), VVarType::MODULETEMP, clockingp->name(), VFlagChildDType{}, - new AstBasicDType{clockingp->fileline(), VBasicDTypeKwd::EVENT}}; - eventp->lifetime(VLifetime::STATIC); - clockingp->eventp(eventp); - // Trigger the clocking event in Observed (IEEE 1800-2023 14.13) - clockingp->addNextHere(new AstAlwaysObserved{ - clockingp->fileline(), - new AstSenTree{clockingp->fileline(), clockingp->sensesp()->cloneTree(false)}, - new AstFireEvent{clockingp->fileline(), - new AstVarRef{clockingp->fileline(), eventp, VAccess::WRITE}, - false}}); - v3Global.setHasEvents(); - } - AstVar* const eventp = clockingp->eventp(); + AstVar* const eventp = clockingp->ensureEventp(true); if (!eventp->user1p()) eventp->user1p(new VSymEnt{m_statep->symsp(), eventp}); return reinterpret_cast(eventp->user1p()); } @@ -2296,12 +2328,12 @@ class LinkDotResolveVisitor final : public VNVisitor { void importImplementsClass(AstClass* implementsClassp, VSymEnt* interfaceSymp, AstClass* baseClassp) { // Also used for standard 'extends' from a base class - UINFO(8, - "importImplementsClass to " << implementsClassp << " from " << baseClassp << endl); + UINFO(8, indent() << "importImplementsClass to " << implementsClassp << " from " + << baseClassp << endl); for (VSymEnt::const_iterator it = interfaceSymp->begin(); it != interfaceSymp->end(); ++it) { if (AstNode* interfaceSubp = it->second->nodep()) { - UINFO(8, " SymFunc " << interfaceSubp << endl); + UINFO(8, indent() << " SymFunc " << interfaceSubp << endl); if (VN_IS(interfaceSubp, NodeFTask)) { const VSymEnt* const foundp = m_curSymp->findIdFlat(interfaceSubp->name()); const AstNodeFTask* const interfaceFuncp = VN_CAST(interfaceSubp, NodeFTask); @@ -2360,6 +2392,16 @@ class LinkDotResolveVisitor final : public VNVisitor { if (nodep && nodep->isParam()) nodep->usedParam(true); } +#define LINKDOT_VISIT_START() \ + VL_RESTORER(m_indent); \ + ++m_indent; + + string indent() const { + string result = ""; + result.insert(0, m_indent, ':'); + return result + " "; + } + // VISITs void visit(AstNetlist* nodep) override { // Recurse..., backward as must do packages before using packages @@ -2369,8 +2411,9 @@ class LinkDotResolveVisitor final : public VNVisitor { void visit(AstConstPool*) override {} void visit(AstNodeModule* nodep) override { if (nodep->dead()) return; + LINKDOT_VISIT_START(); + UINFO(8, indent() << "visit " << nodep << endl); checkNoDot(nodep); - UINFO(8, " " << nodep << endl); m_ds.init(m_curSymp); m_ds.m_dotSymp = m_curSymp = m_modSymp = m_statep->getNodeSym(nodep); // Until overridden by a SCOPE @@ -2382,7 +2425,8 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotSymp = m_curSymp = m_modSymp = nullptr; } void visit(AstScope* nodep) override { - UINFO(8, " " << nodep << endl); + LINKDOT_VISIT_START(); + UINFO(8, indent() << "visit " << nodep << endl); VL_RESTORER(m_modSymp); VL_RESTORER(m_curSymp); { @@ -2393,6 +2437,7 @@ class LinkDotResolveVisitor final : public VNVisitor { } } void visit(AstCellInline* nodep) override { + LINKDOT_VISIT_START(); checkNoDot(nodep); if (m_statep->forScopeCreation() && !v3Global.opt.vpi()) { nodep->unlinkFrBack(); @@ -2401,7 +2446,10 @@ class LinkDotResolveVisitor final : public VNVisitor { } void visit(AstCell* nodep) override { // Cell: Recurse inside or cleanup not founds + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); checkNoDot(nodep); + VL_RESTORER(m_usedPins); m_usedPins.clear(); UASSERT_OBJ(nodep->modp(), nodep, "Cell has unlinked module"); // V3LinkCell should have errored out @@ -2419,7 +2467,7 @@ class LinkDotResolveVisitor final : public VNVisitor { // instantiator's symbols else { m_pinSymp = m_statep->getNodeSym(nodep->modp()); - UINFO(4, "(Backto) Link Cell: " << nodep << endl); + UINFO(4, indent() << "(Backto) visit " << nodep << endl); // if (debug()) nodep->dumpTree("- linkcell: "); // if (debug()) nodep->modp()->dumpTree("- linkcemd: "); iterateChildren(nodep); @@ -2430,7 +2478,10 @@ class LinkDotResolveVisitor final : public VNVisitor { } void visit(AstClassRefDType* nodep) override { // Cell: Recurse inside or cleanup not founds + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); checkNoDot(nodep); + VL_RESTORER(m_usedPins); m_usedPins.clear(); UASSERT_OBJ(nodep->classp(), nodep, "ClassRef has unlinked class"); UASSERT_OBJ(m_statep->forPrimary() || !nodep->paramsp(), nodep, @@ -2439,7 +2490,7 @@ class LinkDotResolveVisitor final : public VNVisitor { { // ClassRef's have pins, so track m_pinSymp = m_statep->getNodeSym(nodep->classp()); - UINFO(4, "(Backto) Link ClassRefDType: " << nodep << endl); + UINFO(4, indent() << "(Backto) visit " << nodep << endl); // if (debug()) nodep->dumpTree("- linkcell: "); // if (debug()) nodep->modp()->dumpTree("- linkcemd: "); iterateChildren(nodep); @@ -2447,6 +2498,7 @@ class LinkDotResolveVisitor final : public VNVisitor { } void visit(AstPin* nodep) override { // Pin: Link to submodule's port + LINKDOT_VISIT_START(); checkNoDot(nodep); iterateChildren(nodep); if (!nodep->modVarp()) { @@ -2514,7 +2566,9 @@ class LinkDotResolveVisitor final : public VNVisitor { // Dot(Dot(ClassOrPackageRef,ClassOrPackageRef), ParseRef(text)) // Dot(Dot(Dot(ParseRef(text), ... if (nodep->user3SetOnce()) return; - UINFO(8, " " << nodep << endl); + LINKDOT_VISIT_START(); + UINFO(8, indent() << "visit " << nodep << endl); + UINFO(8, indent() << m_ds.ascii() << endl); const DotStates lastStates = m_ds; const bool start = (m_ds.m_dotPos == DP_NONE); // Save, as m_dotp will be changed VL_RESTORER(m_fromSymp); @@ -2524,7 +2578,7 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.init(m_curSymp); // Start from current point } m_ds.m_dotp = nodep; // Always, not just at start - m_ds.m_dotPos = DP_SCOPE; + m_ds.m_dotPos = DP_FIRST; if (VN_IS(nodep->lhsp(), ParseRef) && nodep->lhsp()->name() == "this") { VSymEnt* classSymp = getThisClassSymp(); @@ -2533,7 +2587,7 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotErr = true; } else { m_ds.m_dotSymp = classSymp; - UINFO(8, " this. " << m_ds.ascii() << endl); + UINFO(8, indent() << "this. " << m_ds.ascii() << endl); } } else if (VN_IS(nodep->lhsp(), ParseRef) && nodep->lhsp()->name() == "super") { const VSymEnt* classSymp = getThisClassSymp(); @@ -2555,19 +2609,22 @@ class LinkDotResolveVisitor final : public VNVisitor { UASSERT_OBJ(baseClassp, nodep, "Bad superclass"); m_ds.m_dotSymp = m_statep->getNodeSym(baseClassp); m_ds.m_super = true; - UINFO(8, " super. " << m_ds.ascii() << endl); + UINFO(8, indent() << "super. " << m_ds.ascii() << endl); } } } - } else if (VN_IS(nodep->lhsp(), ClassOrPackageRef)) { + } else if (VN_IS(nodep->lhsp(), ClassOrPackageRef) + || (VN_IS(nodep->lhsp(), Dot) && VN_AS(nodep->lhsp(), Dot)->colon())) { // m_ds.m_dotText communicates the cell prefix between stages - // if (!start) { nodep->lhsp()->v3error("Package reference may not be embedded in - // dotted reference"); m_ds.m_dotErr=true; } m_ds.m_dotPos = DP_PACKAGE; + UINFO(8, indent() << "iter.lhs " << m_ds.ascii() << " " << nodep << endl); iterateAndNextNull(nodep->lhsp()); + UINFO(8, indent() << "iter.ldone " << m_ds.ascii() << " " << nodep << endl); } else { - m_ds.m_dotPos = DP_SCOPE; + m_ds.m_dotPos = DP_FIRST; + UINFO(8, indent() << "iter.lhs " << m_ds.ascii() << " " << nodep << endl); iterateAndNextNull(nodep->lhsp()); + UINFO(8, indent() << "iter.ldone " << m_ds.ascii() << " " << nodep << endl); // if (debug() >= 9) nodep->dumpTree("- dot-lho: "); } if (m_statep->forPrimary() && isParamedClassRef(nodep->lhsp())) { @@ -2578,11 +2635,14 @@ class LinkDotResolveVisitor final : public VNVisitor { && (VN_IS(nodep->lhsp(), CellRef) || VN_IS(nodep->lhsp(), CellArrayRef))) { m_ds.m_unlinkedScopep = nodep->lhsp(); } + if (m_ds.m_dotPos == DP_FIRST) m_ds.m_dotPos = DP_SCOPE; if (!m_ds.m_dotErr) { // Once something wrong, give up // Top 'final' dot RHS is final RHS, else it's a // DOT(DOT(x,*here*),real-rhs) which we consider a RHS if (start && m_ds.m_dotPos == DP_SCOPE) m_ds.m_dotPos = DP_FINAL; + UINFO(8, indent() << "iter.rhs " << m_ds.ascii() << " " << nodep << endl); iterateAndNextNull(nodep->rhsp()); + UINFO(8, indent() << "iter.rdone " << m_ds.ascii() << " " << nodep << endl); // if (debug() >= 9) nodep->dumpTree("- dot-rho: "); } if (!m_ds.m_unresolvedClass) { @@ -2615,15 +2675,19 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotp = lastStates.m_dotp; m_ds.m_unresolvedClass |= unresolvedClass; } + UINFO(8, indent() << "done " << m_ds.ascii() << " " << nodep << endl); } void visit(AstSenItem* nodep) override { + LINKDOT_VISIT_START(); VL_RESTORER(m_inSens); m_inSens = true; iterateChildren(nodep); } void visit(AstParseRef* nodep) override { if (nodep->user3SetOnce()) return; - UINFO(9, " linkPARSEREF " << m_ds.ascii() << " n=" << nodep << endl); + LINKDOT_VISIT_START(); + UINFO(9, indent() << "visit " << nodep << endl); + UINFO(9, indent() << m_ds.ascii() << endl); if (m_ds.m_unresolvedClass) return; // m_curSymp is symbol table of outer expression // m_ds.m_dotSymp is symbol table relative to "."'s above now @@ -2633,10 +2697,11 @@ class LinkDotResolveVisitor final : public VNVisitor { "ParseRefs should no longer exist"); const DotStates lastStates = m_ds; const bool start = (m_ds.m_dotPos == DP_NONE); // Save, as m_dotp will be changed + bool first = start || m_ds.m_dotPos == DP_FIRST; if (start) { m_ds.init(m_curSymp); - // Note m_ds.m_dot remains nullptr; this is a reference not under a dot + // Note m_ds.m_dotp remains nullptr; this is a reference not under a dot } if (nodep->name() == "super") { nodep->v3warn(E_UNSUPPORTED, "Unsupported: super"); @@ -2664,7 +2729,7 @@ class LinkDotResolveVisitor final : public VNVisitor { // m_ds.dotp->lhsp() was checked to know if `index` is directly after lambda arg ref. // If not, treat it as normal member select iterateChildren(nodep); - const auto newp = new AstLambdaArgRef{ + AstLambdaArgRef* const newp = new AstLambdaArgRef{ nodep->fileline(), m_ds.m_dotp->lhsp()->name() + "__DOT__index", true}; nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); @@ -2703,11 +2768,12 @@ class LinkDotResolveVisitor final : public VNVisitor { UASSERT_OBJ(classOrPackagep, m_ds.m_dotp->lhsp(), "Bad package link"); if (cpackagerefp->name() == "local::") { m_fromSymp = nullptr; + first = true; } else { m_ds.m_dotSymp = m_statep->getNodeSym(classOrPackagep); } m_ds.m_dotPos = DP_SCOPE; - } else if (m_ds.m_dotPos == DP_SCOPE) { + } else if (m_ds.m_dotPos == DP_SCOPE || m_ds.m_dotPos == DP_FIRST) { // {a}.{b}, where {a} maybe a module name // or variable, where dotting into structure member expectWhat = "scope/variable"; @@ -2727,6 +2793,7 @@ class LinkDotResolveVisitor final : public VNVisitor { if (m_fromSymp) { foundp = m_fromSymp->findIdFlat(nodep->name()); if (foundp) { + if (!start) m_ds.m_dotPos = DP_MEMBER; if (!m_inWith) { UASSERT_OBJ(m_randMethodCallp, nodep, "Expected to be under randomize()"); // This will start failing once complex expressions are allowed on the LHS @@ -2735,15 +2802,12 @@ class LinkDotResolveVisitor final : public VNVisitor { "Expected simple randomize target"); // A ParseRef is used here so that the dot RHS gets resolved nodep->replaceWith(new AstMemberSel{ - nodep->fileline(), - new AstParseRef{nodep->fileline(), VParseRefExp::PX_TEXT, - m_randMethodCallp->fromp()->name()}, + nodep->fileline(), m_randMethodCallp->fromp()->cloneTree(false), VFlagChildDType{}, nodep->name()}); VL_DO_DANGLING(pushDeletep(nodep), nodep); return; } - UINFO(9, " randomize-with fromSym " << foundp->nodep() << endl); - if (m_ds.m_dotPos != DP_NONE) m_ds.m_dotPos = DP_MEMBER; + UINFO(9, indent() << "randomize-with fromSym " << foundp->nodep() << endl); AstLambdaArgRef* const lambdaRefp = new AstLambdaArgRef{nodep->fileline(), "item", false}; nodep->replaceWith(new AstMemberSel{nodep->fileline(), lambdaRefp, @@ -2754,18 +2818,20 @@ class LinkDotResolveVisitor final : public VNVisitor { } if (allowScope) { foundp = m_statep->findDotted(nodep->fileline(), m_ds.m_dotSymp, nodep->name(), - baddot, okSymp); // Maybe nullptr - } else { + baddot, okSymp, first); // Maybe nullptr + } else if (first) { foundp = m_ds.m_dotSymp->findIdFallback(nodep->name()); + } else { + foundp = m_ds.m_dotSymp->findIdFlat(nodep->name()); } if (foundp) { - UINFO(9, " found=se" << cvtToHex(foundp) << " exp=" << expectWhat - << " n=" << foundp->nodep() << endl); + UINFO(9, indent() << "found=se" << cvtToHex(foundp) << " exp=" << expectWhat + << " n=" << foundp->nodep() << endl); } // What fell out? bool ok = false; // Special case: waiting on clocking event - if (m_inSens && foundp && m_ds.m_dotPos != DP_SCOPE) { + if (m_inSens && foundp && m_ds.m_dotPos != DP_SCOPE && m_ds.m_dotPos != DP_FIRST) { if (AstClocking* const clockingp = VN_CAST(foundp->nodep(), Clocking)) { foundp = getCreateClockingEventSymEnt(clockingp); } @@ -2796,7 +2862,7 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotText = VString::dot(m_ds.m_dotText, ".", nodep->name()); m_ds.m_dotSymp = foundp; m_ds.m_dotPos = DP_SCOPE; - UINFO(9, " cell -> iface varref " << foundp->nodep() << endl); + UINFO(9, indent() << " cell -> iface varref " << foundp->nodep() << endl); AstNode* const newp = new AstVarRef{nodep->fileline(), ifaceRefVarp, VAccess::READ}; nodep->replaceWith(newp); @@ -2815,7 +2881,7 @@ class LinkDotResolveVisitor final : public VNVisitor { } nodep->replaceWith(taskrefp); VL_DO_DANGLING(nodep->deleteTree(), nodep); - if (start) m_ds = lastStates; + m_ds = lastStates; return; } else if (AstVar* const varp = foundToVarp(foundp, nodep, VAccess::READ)) { AstIfaceRefDType* const ifacerefp @@ -2823,7 +2889,8 @@ class LinkDotResolveVisitor final : public VNVisitor { if (ifacerefp && varp->isIfaceRef()) { UASSERT_OBJ(ifacerefp->ifaceViaCellp(), ifacerefp, "Unlinked interface"); // Really this is a scope reference into an interface - UINFO(9, "varref-ifaceref " << m_ds.m_dotText << " " << nodep << endl); + UINFO(9, indent() + << "varref-ifaceref " << m_ds.m_dotText << " " << nodep << endl); m_ds.m_dotText = VString::dot(m_ds.m_dotText, ".", nodep->name()); m_ds.m_dotSymp = m_statep->getNodeSym(ifacerefp->ifaceViaCellp()); m_ds.m_dotPos = DP_SCOPE; @@ -2875,7 +2942,7 @@ class LinkDotResolveVisitor final : public VNVisitor { refp->classOrPackagep(foundp->classOrPackagep()); newp = refp; } - UINFO(9, " new " << newp << endl); + UINFO(9, indent() << "new " << newp << endl); nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); m_ds.m_dotPos = DP_MEMBER; @@ -2884,9 +2951,11 @@ class LinkDotResolveVisitor final : public VNVisitor { } else if (const AstModport* const modportp = VN_CAST(foundp->nodep(), Modport)) { // A scope reference into an interface's modport (not // necessarily at a pin connection) - UINFO(9, "cell-ref-to-modport " << m_ds.m_dotText << " " << nodep << endl); - UINFO(9, "unlinked " << m_ds.m_unlinkedScopep << endl); - UINFO(9, "dotSymp " << m_ds.m_dotSymp << " " << m_ds.m_dotSymp->nodep() << endl); + UINFO(9, indent() << "cell-ref-to-modport " << m_ds.m_dotText << " " << nodep + << endl); + UINFO(9, indent() << "unlinked " << m_ds.m_unlinkedScopep << endl); + UINFO(9, indent() << "dotSymp " << m_ds.m_dotSymp << " " << m_ds.m_dotSymp->nodep() + << endl); // Iface was the previously dotted component if (!m_ds.m_dotSymp || !VN_IS(m_ds.m_dotSymp->nodep(), Cell) || !VN_AS(m_ds.m_dotSymp->nodep(), Cell)->modp() @@ -2913,7 +2982,7 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotText = VString::dot(m_ds.m_dotText, ".", nodep->name()); m_ds.m_dotSymp = foundp; m_ds.m_dotPos = DP_SCOPE; - UINFO(9, " modport -> iface varref " << foundp->nodep() << endl); + UINFO(9, indent() << "modport -> iface varref " << foundp->nodep() << endl); // We lose the modport name here, so we cannot detect mismatched modports. AstNodeExpr* newp = new AstVarRef{nodep->fileline(), ifaceRefVarp, VAccess::READ}; @@ -2921,7 +2990,7 @@ class LinkDotResolveVisitor final : public VNVisitor { if (cellarrayrefp) { // iface[vec].modport became CellArrayRef(iface, lsb) // Convert back to SelBit(iface, lsb) - UINFO(9, " Array modport to SelBit " << cellarrayrefp << endl); + UINFO(9, indent() << "Array modport to SelBit " << cellarrayrefp << endl); newp = new AstSelBit{cellarrayrefp->fileline(), newp, cellarrayrefp->selp()->unlinkFrBack()}; newp->user3(true); // Don't process again @@ -2961,7 +3030,7 @@ class LinkDotResolveVisitor final : public VNVisitor { } else if (VN_IS(foundp->nodep(), Clocking)) { m_ds.m_dotSymp = foundp; if (m_ds.m_dotText != "") m_ds.m_dotText += "." + nodep->name(); - ok = m_ds.m_dotPos == DP_SCOPE; + ok = m_ds.m_dotPos == DP_SCOPE || m_ds.m_dotPos == DP_FIRST; } else if (const AstNodeFTask* const ftaskp = VN_CAST(foundp->nodep(), NodeFTask)) { if (!ftaskp->isFunction() || ftaskp->classMethod()) { @@ -2986,11 +3055,10 @@ class LinkDotResolveVisitor final : public VNVisitor { // Mark that the Dot statement can't be resolved. m_ds.m_unresolvedClass = true; // If the symbol was a scope name, it would be resolved. - if (m_ds.m_dotPos == DP_SCOPE) m_ds.m_dotPos = DP_MEMBER; + m_ds.m_dotPos = DP_MEMBER; } else { // Cells/interfaces can't be implicit - const bool isCell = foundp ? VN_IS(foundp->nodep(), Cell) : false; - const bool checkImplicit = (!m_ds.m_dotp && m_ds.m_dotText == "" && !isCell); + const bool checkImplicit = (!m_ds.m_dotp && m_ds.m_dotText == "" && !foundp); const bool err = !(checkImplicit && m_statep->implicitOk(m_modp, nodep->name())); if (err) { @@ -3001,7 +3069,7 @@ class LinkDotResolveVisitor final : public VNVisitor { << " as a " << foundp->nodep()->typeName() << " but expected a " << expectWhat); } else if (m_ds.m_dotText == "") { - UINFO(7, " ErrParseRef curSymp=se" + UINFO(1, " ErrParseRef curSymp=se" << cvtToHex(m_curSymp) << " ds=" << m_ds.ascii() << endl); const string suggest = m_statep->suggestSymFallback( m_ds.m_dotSymp, nodep->name(), VNodeMatcher{}); @@ -3025,7 +3093,8 @@ class LinkDotResolveVisitor final : public VNVisitor { if (checkImplicit) { // Create if implicit, and also if error (so only complain once) // Else if a scope is allowed, making a signal won't help error cascade - auto varp = createImplicitVar(m_curSymp, nodep, m_modp, m_modSymp, err); + AstVar* const varp + = createImplicitVar(m_curSymp, nodep, m_modp, m_modSymp, err); AstVarRef* const newp = new AstVarRef{nodep->fileline(), varp, VAccess::READ}; nodep->replaceWith(newp); @@ -3039,6 +3108,10 @@ class LinkDotResolveVisitor final : public VNVisitor { void visit(AstClassOrPackageRef* nodep) override { // Class: Recurse inside or cleanup not founds // checkNoDot not appropriate, can be under a dot + LINKDOT_VISIT_START(); + UINFO(8, indent() << "visit " << nodep << endl); + UINFO(9, indent() << m_ds.ascii() << endl); + VL_RESTORER(m_usedPins); m_usedPins.clear(); UASSERT_OBJ(m_statep->forPrimary() || VN_IS(nodep->classOrPackageNodep(), ParamTypeDType) || nodep->classOrPackagep(), @@ -3048,6 +3121,9 @@ class LinkDotResolveVisitor final : public VNVisitor { VL_RESTORER(m_ds); VL_RESTORER(m_pinSymp); + if (nodep->name() == "std" && !nodep->classOrPackagep()) { + nodep->classOrPackagep(v3Global.rootp()->stdPackagep()); + } // ClassRef's have pins, so track if (nodep->classOrPackagep()) { m_pinSymp = m_statep->getNodeSym(nodep->classOrPackagep()); @@ -3057,7 +3133,7 @@ class LinkDotResolveVisitor final : public VNVisitor { if (refClassp && !m_statep->forPrimary()) classExtendImport(refClassp); m_ds.init(m_curSymp); - UINFO(4, "(Backto) Link ClassOrPackageRef: " << nodep << endl); + UINFO(4, indent() << "(Backto) Link ClassOrPackageRef: " << nodep << endl); iterateChildren(nodep); if (nodep->name() == "local::") { @@ -3080,8 +3156,9 @@ class LinkDotResolveVisitor final : public VNVisitor { } void visit(AstConstraintRef* nodep) override { if (nodep->user3SetOnce()) return; - UINFO(8, " " << nodep << endl); - UINFO(8, " " << m_ds.ascii() << endl); + LINKDOT_VISIT_START(); + UINFO(8, indent() << "visit " << nodep << endl); + UINFO(8, indent() << m_ds.ascii() << endl); // No children defined } void visit(AstVarRef* nodep) override { @@ -3089,9 +3166,11 @@ class LinkDotResolveVisitor final : public VNVisitor { // ParseRefs are used the first pass (forPrimary) so we shouldn't get can't find // errors here now that we have a VarRef. // No checkNoDot; created and iterated from a parseRef + LINKDOT_VISIT_START(); iterateChildren(nodep); if (!nodep->varp()) { - UINFO(9, " linkVarRef se" << cvtToHex(m_curSymp) << " n=" << nodep << endl); + UINFO(9, + indent() << "linkVarRef se" << cvtToHex(m_curSymp) << " n=" << nodep << endl); UASSERT_OBJ(m_curSymp, nodep, "nullptr lookup symbol table"); VSymEnt* const foundp = m_curSymp->findIdFallback(nodep->name()); if (AstVar* const varp @@ -3112,7 +3191,8 @@ class LinkDotResolveVisitor final : public VNVisitor { // We always link even if varp() is set, because the module we choose may change // due to creating new modules, flattening, etc. if (nodep->user3SetOnce()) return; - UINFO(8, " " << nodep << endl); + LINKDOT_VISIT_START(); + UINFO(8, indent() << "visit " << nodep << endl); // No checkNoDot; created and iterated from a parseRef if (!m_modSymp) { // Module that is not in hierarchy. We'll be dead code eliminating it later. @@ -3128,15 +3208,16 @@ class LinkDotResolveVisitor final : public VNVisitor { // ignore (t_math_divw) dotSymp = m_modSymp; const string inl = AstNode::dedotName(nodep->inlinedDots()); - dotSymp = m_statep->findDotted(nodep->fileline(), dotSymp, inl, baddot, okSymp); + dotSymp + = m_statep->findDotted(nodep->fileline(), dotSymp, inl, baddot, okSymp, false); UASSERT_OBJ(dotSymp, nodep, "Couldn't resolve inlined scope " << AstNode::prettyNameQ(baddot) << " in: " << nodep->inlinedDots()); } dotSymp = m_statep->findDotted(nodep->fileline(), dotSymp, nodep->dotted(), baddot, - okSymp); // Maybe nullptr + okSymp, true); // Maybe nullptr if (!m_statep->forScopeCreation()) { - VSymEnt* foundp = m_statep->findSymPrefixed(dotSymp, nodep->name(), baddot); + VSymEnt* foundp = m_statep->findSymPrefixed(dotSymp, nodep->name(), baddot, true); if (m_inSens && foundp) { if (AstClocking* const clockingp = VN_CAST(foundp->nodep(), Clocking)) { foundp = getCreateClockingEventSymEnt(clockingp); @@ -3146,7 +3227,7 @@ class LinkDotResolveVisitor final : public VNVisitor { = foundp ? foundToVarp(foundp, nodep, nodep->access()) : nullptr; nodep->varp(varp); updateVarUse(nodep->varp()); - UINFO(7, " Resolved " << nodep << endl); // Also prints varp + UINFO(7, indent() << "Resolved " << nodep << endl); // Also prints varp if (!nodep->varp()) { nodep->v3error("Can't find definition of " << AstNode::prettyNameQ(baddot) << " in dotted signal: '" @@ -3169,7 +3250,8 @@ class LinkDotResolveVisitor final : public VNVisitor { } } } else { - VSymEnt* const foundp = m_statep->findSymPrefixed(dotSymp, nodep->name(), baddot); + VSymEnt* const foundp + = m_statep->findSymPrefixed(dotSymp, nodep->name(), baddot, true); AstVarScope* vscp = foundp ? VN_AS(foundp->nodep(), VarScope) : nullptr; if (!vscp) { nodep->v3error("Can't find varpin scope of " @@ -3178,8 +3260,8 @@ class LinkDotResolveVisitor final : public VNVisitor { okSymp->cellErrorScopes(nodep); } else { while (vscp->user2p()) { // If V3Inline aliased it, pick up the new signal - UINFO(7, " Resolved pre-alias " << vscp - << endl); // Also prints taskp + UINFO(7, indent() << "Resolved pre-alias " << vscp + << endl); // Also prints taskp vscp = VN_AS(vscp->user2p(), VarScope); } // Convert the VarXRef to a VarRef, so we don't need @@ -3187,17 +3269,18 @@ class LinkDotResolveVisitor final : public VNVisitor { nodep->varp(vscp->varp()); nodep->varScopep(vscp); updateVarUse(nodep->varp()); - UINFO(7, " Resolved " << nodep << endl); // Also prints taskp + UINFO(7, indent() << "Resolved " << nodep << endl); // Also prints taskp AstVarRef* const newvscp = new AstVarRef{nodep->fileline(), vscp, nodep->access()}; nodep->replaceWith(newvscp); VL_DO_DANGLING(nodep->deleteTree(), nodep); - UINFO(9, " new " << newvscp << endl); // Also prints taskp + UINFO(9, indent() << "new " << newvscp << endl); // Also prints taskp } } } } void visit(AstEnumDType* nodep) override { + LINKDOT_VISIT_START(); iterateChildren(nodep); AstRefDType* const refdtypep = VN_CAST(nodep->subDTypep(), RefDType); if (refdtypep && (nodep == refdtypep->subDTypep())) { @@ -3206,10 +3289,13 @@ class LinkDotResolveVisitor final : public VNVisitor { } void visit(AstEnumItemRef* nodep) override { // EnumItemRef may be under a dot. Should already be resolved. + LINKDOT_VISIT_START(); iterateChildren(nodep); } void visit(AstMethodCall* nodep) override { // Created here so should already be resolved. + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); VL_RESTORER(m_ds); VL_RESTORER(m_fromSymp); VL_RESTORER(m_randMethodCallp); @@ -3261,6 +3347,7 @@ class LinkDotResolveVisitor final : public VNVisitor { } } void visit(AstVar* nodep) override { + LINKDOT_VISIT_START(); checkNoDot(nodep); iterateChildren(nodep); if (m_statep->forPrimary() && nodep->isIO() && !m_ftaskp && !nodep->user4()) { @@ -3270,8 +3357,9 @@ class LinkDotResolveVisitor final : public VNVisitor { } void visit(AstNodeFTaskRef* nodep) override { if (nodep->user3SetOnce()) return; - UINFO(8, " " << nodep << endl); - UINFO(8, " " << m_ds.ascii() << endl); + LINKDOT_VISIT_START(); + UINFO(8, indent() << "visit " << nodep << endl); + UINFO(8, indent() << m_ds.ascii() << endl); if (m_ds.m_dotPos != DP_MEMBER || nodep->name() != "randomize") { // Visit arguments at the beginning. // They may be visitted even if the current node can't be linked now. @@ -3290,6 +3378,7 @@ class LinkDotResolveVisitor final : public VNVisitor { VL_RESTORER(m_fromSymp); + bool first = !m_ds.m_dotp || m_ds.m_dotPos == DP_FIRST; bool staticAccess = false; if (m_ds.m_unresolvedClass) { // Unable to link before V3Param @@ -3312,12 +3401,12 @@ class LinkDotResolveVisitor final : public VNVisitor { UASSERT_OBJ(cpackagerefp->classOrPackagep(), m_ds.m_dotp->lhsp(), "Bad package link"); if (cpackagerefp->name() == "local::") { m_fromSymp = nullptr; + first = true; } else { nodep->classOrPackagep(cpackagerefp->classOrPackagep()); } // Class/package :: HERE function() . method_called_on_function_return_value() m_ds.m_dotPos = DP_MEMBER; - m_ds.m_dotp = nullptr; } else if (m_ds.m_dotp && m_ds.m_dotPos == DP_FINAL) { nodep->dotted(m_ds.m_dotText); // Maybe "" } else if (m_ds.m_dotp && m_ds.m_dotPos == DP_MEMBER) { @@ -3331,7 +3420,7 @@ class LinkDotResolveVisitor final : public VNVisitor { nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); return; - } else if (m_ds.m_dotp && m_ds.m_dotPos == DP_SCOPE) { + } else if (m_ds.m_dotp && (m_ds.m_dotPos == DP_SCOPE || m_ds.m_dotPos == DP_FIRST)) { // HERE function() . method_called_on_function_return_value() m_ds.m_dotPos = DP_MEMBER; m_ds.m_dotText = ""; @@ -3342,7 +3431,7 @@ class LinkDotResolveVisitor final : public VNVisitor { // References into packages don't care about cell hierarchy. } else if (!m_modSymp) { // Module that is not in hierarchy. We'll be dead code eliminating it later. - UINFO(9, "Dead module for " << nodep << endl); + UINFO(9, indent() << "Dead module for " << nodep << endl); nodep->taskp(nullptr); } else if (nodep->dotted() == "" && nodep->taskp()) { // Earlier should have setup the links @@ -3362,7 +3451,7 @@ class LinkDotResolveVisitor final : public VNVisitor { } if (nodep->classOrPackagep()) { // Look only in specified package dotSymp = m_statep->getNodeSym(nodep->classOrPackagep()); - UINFO(8, " Override classOrPackage " << dotSymp << endl); + UINFO(8, indent() << "Override classOrPackage " << dotSymp << endl); } else { if (nodep->inlinedDots() != "") { // Correct for current scope // Dotted lookup is always relative to module, as maybe @@ -3370,9 +3459,9 @@ class LinkDotResolveVisitor final : public VNVisitor { // to ignore (t_math_divw) dotSymp = m_modSymp; const string inl = AstNode::dedotName(nodep->inlinedDots()); - UINFO(8, " Inlined " << inl << endl); - dotSymp - = m_statep->findDotted(nodep->fileline(), dotSymp, inl, baddot, okSymp); + UINFO(8, indent() << "Inlined " << inl << endl); + dotSymp = m_statep->findDotted(nodep->fileline(), dotSymp, inl, baddot, okSymp, + true); if (!dotSymp) { okSymp->cellErrorScopes(nodep); nodep->v3fatalSrc("Couldn't resolve inlined scope " @@ -3381,12 +3470,12 @@ class LinkDotResolveVisitor final : public VNVisitor { } } dotSymp = m_statep->findDotted(nodep->fileline(), dotSymp, nodep->dotted(), baddot, - okSymp); // Maybe nullptr + okSymp, true); // Maybe nullptr } if (m_fromSymp) { VSymEnt* const foundp = m_fromSymp->findIdFlat(nodep->name()); if (foundp && m_inWith) { - UINFO(9, " randomize-with fromSym " << foundp->nodep() << endl); + UINFO(9, indent() << "randomize-with fromSym " << foundp->nodep() << endl); AstNodeExpr* argsp = nullptr; if (nodep->pinsp()) { iterateAndNextNull(nodep->pinsp()); @@ -3401,7 +3490,16 @@ class LinkDotResolveVisitor final : public VNVisitor { return; } } - VSymEnt* const foundp = m_statep->findSymPrefixed(dotSymp, nodep->name(), baddot); + if (first && nodep->name() == "randomize" && VN_IS(m_modp, Class)) { + // need special handling to avoid falling back to std::randomize + VMemberMap memberMap; + AstFunc* const randFuncp = V3Randomize::newRandomizeFunc( + memberMap, VN_AS(m_modp, Class), nodep->name(), true, true); + nodep->taskp(randFuncp); + m_curSymp = m_statep->insertBlock(m_curSymp, nodep->name(), randFuncp, m_modp); + } + VSymEnt* const foundp + = m_statep->findSymPrefixed(dotSymp, nodep->name(), baddot, first); AstNodeFTask* const taskp = foundp ? VN_CAST(foundp->nodep(), NodeFTask) : nullptr; // Maybe nullptr if (taskp) { @@ -3412,23 +3510,23 @@ class LinkDotResolveVisitor final : public VNVisitor { } nodep->taskp(taskp); nodep->classOrPackagep(foundp->classOrPackagep()); - UINFO(7, " Resolved " << nodep << endl); // Also prints taskp + UINFO(7, indent() << "Resolved " << nodep << endl); // Also prints taskp } else if (m_insideClassExtParam) { // The reference may point to a method declared in a super class, which is proved // by a parameter. In such a case, it can't be linked at the first stage. return; } else { // Note ParseRef has similar error handling/message output - UINFO(7, " ErrFtask curSymp=se" << cvtToHex(m_curSymp) << " dotSymp=se" - << cvtToHex(dotSymp) << endl); + UINFO(7, indent() << " ErrFtask curSymp=se" << cvtToHex(m_curSymp) + << " dotSymp=se" << cvtToHex(dotSymp) << endl); if (foundp) { if (VN_IS(foundp->nodep(), Var) && m_ds.m_dotText == "" && m_ftaskp && m_ftaskp->name() == foundp->nodep()->name()) { // This is a recursive reference to the function itself, not to the var nodep->taskp(m_ftaskp); nodep->classOrPackagep(foundp->classOrPackagep()); - UINFO(7, " Resolved recursive " << nodep - << endl); // Also prints taskp + UINFO(7, indent() << "Resolved recursive " << nodep + << endl); // Also prints taskp } else { nodep->v3error("Found definition of '" << m_ds.m_dotText << (m_ds.m_dotText == "" ? "" : ".") @@ -3504,15 +3602,17 @@ class LinkDotResolveVisitor final : public VNVisitor { } void visit(AstSelBit* nodep) override { if (nodep->user3SetOnce()) return; + LINKDOT_VISIT_START(); iterateAndNextNull(nodep->fromp()); if (m_ds.m_unresolvedClass) { - UASSERT_OBJ(m_ds.m_dotPos != DP_SCOPE, nodep, + UASSERT_OBJ(m_ds.m_dotPos != DP_SCOPE && m_ds.m_dotPos != DP_FIRST, nodep, "Object of unresolved class on scope position in dotted reference"); return; } - if (m_ds.m_dotPos - == DP_SCOPE) { // Already under dot, so this is {modulepart} DOT {modulepart} - UINFO(9, " deferring until after a V3Param pass: " << nodep << endl); + if (m_ds.m_dotPos == DP_SCOPE + || m_ds.m_dotPos + == DP_FIRST) { // Already under dot, so this is {modulepart} DOT {modulepart} + UINFO(9, indent() << "deferring until after a V3Param pass: " << nodep << endl); m_ds.m_dotText += "__BRA__??__KET__"; m_ds.m_unresolvedCell = true; // And pass up m_ds.m_dotText @@ -3527,7 +3627,7 @@ class LinkDotResolveVisitor final : public VNVisitor { iterateAndNextNull(nodep->attrp()); } } - if (m_ds.m_unresolvedCell && m_ds.m_dotPos == DP_SCOPE) { + if (m_ds.m_unresolvedCell && (m_ds.m_dotPos == DP_SCOPE || m_ds.m_dotPos == DP_FIRST)) { AstNodeExpr* const exprp = nodep->bitp()->unlinkFrBack(); AstCellArrayRef* const newp = new AstCellArrayRef{nodep->fileline(), nodep->fromp()->name(), exprp}; @@ -3538,8 +3638,10 @@ class LinkDotResolveVisitor final : public VNVisitor { void visit(AstNodePreSel* nodep) override { // Excludes simple AstSelBit, see above if (nodep->user3SetOnce()) return; - if (m_ds.m_dotPos - == DP_SCOPE) { // Already under dot, so this is {modulepart} DOT {modulepart} + LINKDOT_VISIT_START(); + if (m_ds.m_dotPos == DP_SCOPE + || m_ds.m_dotPos + == DP_FIRST) { // Already under dot, so this is {modulepart} DOT {modulepart} nodep->v3error("Syntax error: Range ':', '+:' etc are not allowed in the instance " "part of a dotted reference"); m_ds.m_dotErr = true; @@ -3560,7 +3662,7 @@ class LinkDotResolveVisitor final : public VNVisitor { AstNode* const basefromp = AstArraySel::baseFromp(nodep, false); if (VN_IS(basefromp, Replicate)) { // From {...}[...] syntax in IEEE 2017 - if (basefromp) UINFO(1, " Related node: " << basefromp << endl); + if (basefromp) UINFO(9, indent() << " Related node: " << basefromp << endl); } else { nodep->attrp(new AstAttrOf{nodep->fileline(), VAttrType::VAR_BASE, basefromp->cloneTree(false)}); @@ -3568,24 +3670,27 @@ class LinkDotResolveVisitor final : public VNVisitor { } void visit(AstMemberSel* nodep) override { // checkNoDot not appropriate, can be under a dot + LINKDOT_VISIT_START(); iterateChildren(nodep); } void visit(AstNodeBlock* nodep) override { - UINFO(5, " " << nodep << endl); + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); checkNoDot(nodep); VL_RESTORER(m_curSymp); { if (nodep->name() != "") { m_ds.m_dotSymp = m_curSymp = m_statep->getNodeSym(nodep); - UINFO(5, " cur=se" << cvtToHex(m_curSymp) << endl); + UINFO(5, indent() << "cur=se" << cvtToHex(m_curSymp) << endl); } iterateChildren(nodep); } m_ds.m_dotSymp = VL_RESTORER_PREV(m_curSymp); - UINFO(5, " cur=se" << cvtToHex(m_curSymp) << endl); + UINFO(5, indent() << "cur=se" << cvtToHex(m_curSymp) << endl); } void visit(AstNodeFTask* nodep) override { - UINFO(5, " " << nodep << endl); + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); checkNoDot(nodep); if (nodep->isExternDef()) { if (const VSymEnt* const foundp @@ -3626,7 +3731,8 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotSymp = VL_RESTORER_PREV(m_curSymp); } void visit(AstNodeForeach* nodep) override { - UINFO(5, " " << nodep << endl); + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); checkNoDot(nodep); VL_RESTORER(m_curSymp); { @@ -3636,7 +3742,8 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotSymp = VL_RESTORER_PREV(m_curSymp); } void visit(AstWith* nodep) override { - UINFO(5, " " << nodep << endl); + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); checkNoDot(nodep); VL_RESTORER(m_curSymp); VL_RESTORER(m_inWith); @@ -3648,7 +3755,8 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotSymp = VL_RESTORER_PREV(m_curSymp); } void visit(AstLambdaArgRef* nodep) override { - UINFO(5, " " << nodep << endl); + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); // No checknodot(nodep), visit(AstScope) will check for LambdaArgRef iterateChildren(nodep); } @@ -3658,6 +3766,7 @@ class LinkDotResolveVisitor final : public VNVisitor { if (nodep->user3SetOnce()) return; // If the class is resolved, there is nothing more to do if (nodep->classOrNullp()) return; + LINKDOT_VISIT_START(); if (m_statep->forPrimary()) { AstNode* cprp = nodep->classOrPkgsp(); VSymEnt* lookSymp = m_curSymp; @@ -3735,7 +3844,8 @@ class LinkDotResolveVisitor final : public VNVisitor { } void visit(AstClass* nodep) override { if (nodep->user3SetOnce()) return; - UINFO(5, " " << nodep << endl); + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); checkNoDot(nodep); VL_RESTORER(m_curSymp); VL_RESTORER(m_modSymp); @@ -3817,7 +3927,8 @@ class LinkDotResolveVisitor final : public VNVisitor { if (AstEnumItem* const aitemp = VN_CAST(itemp, EnumItem)) { AstEnumItemRef* const newp = new AstEnumItemRef{ aitemp->fileline(), aitemp, it->second->classOrPackagep()}; - UINFO(8, "Class import noderef '" << it->first << "' " << newp << endl); + UINFO(8, indent() << "Class import noderef '" << it->first << "' " << newp + << endl); nodep->addMembersp(newp); memberMap.insert(nodep, newp); } @@ -3829,8 +3940,11 @@ class LinkDotResolveVisitor final : public VNVisitor { void visit(AstRefDType* nodep) override { // Resolve its reference if (nodep->user3SetOnce()) return; + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); if (AstNode* const cpackagep = nodep->classOrPackageOpp()) { if (AstClassOrPackageRef* const cpackagerefp = VN_CAST(cpackagep, ClassOrPackageRef)) { + iterate(cpackagerefp); const AstClass* const clsp = VN_CAST(cpackagerefp->classOrPackageNodep(), Class); if (clsp && clsp->isParameterized()) { // Unable to link before the instantiation of parameter classes. @@ -3861,7 +3975,6 @@ class LinkDotResolveVisitor final : public VNVisitor { UASSERT_OBJ(cpackagerefp->classOrPackagep(), m_ds.m_dotp->lhsp(), "Bad package link"); nodep->classOrPackagep(cpackagerefp->classOrPackagep()); m_ds.m_dotPos = DP_SCOPE; - m_ds.m_dotp = nullptr; } else { checkNoDot(nodep); } @@ -3870,8 +3983,10 @@ class LinkDotResolveVisitor final : public VNVisitor { const VSymEnt* foundp; if (nodep->classOrPackagep()) { foundp = m_statep->getNodeSym(nodep->classOrPackagep())->findIdFlat(nodep->name()); - } else { + } else if (m_ds.m_dotPos == DP_FIRST || m_ds.m_dotPos == DP_NONE) { foundp = m_curSymp->findIdFallback(nodep->name()); + } else { + foundp = m_curSymp->findIdFlat(nodep->name()); } if (AstTypedef* const defp = foundp ? VN_CAST(foundp->nodep(), Typedef) : nullptr) { nodep->typedefp(defp); @@ -3888,7 +4003,7 @@ class LinkDotResolveVisitor final : public VNVisitor { nodep->refDTypep(defp); nodep->classOrPackagep(foundp->classOrPackagep()); } - } else if (AstClass* const defp = foundp ? VN_AS(foundp->nodep(), Class) : nullptr) { + } else if (AstClass* const defp = foundp ? VN_CAST(foundp->nodep(), Class) : nullptr) { AstPin* const paramsp = nodep->paramsp(); if (paramsp) paramsp->unlinkFrBackWithNext(); AstClassRefDType* const newp @@ -3901,13 +4016,18 @@ class LinkDotResolveVisitor final : public VNVisitor { return; } else { if (foundp) UINFO(1, "Found sym node: " << foundp->nodep() << endl); - nodep->v3error("Can't find typedef: " << nodep->prettyNameQ()); + if (foundp) { + nodep->v3error("Expecting a data type: " << nodep->prettyNameQ()); + } else { + nodep->v3error("Can't find typedef: " << nodep->prettyNameQ()); + } } } iterateChildren(nodep); } void visit(AstDpiExport* nodep) override { // AstDpiExport: Make sure the function referenced exists, then dump it + LINKDOT_VISIT_START(); iterateChildren(nodep); checkNoDot(nodep); VSymEnt* const foundp = m_curSymp->findIdFallback(nodep->name()); @@ -3926,32 +4046,39 @@ class LinkDotResolveVisitor final : public VNVisitor { } void visit(AstPackageImport* nodep) override { // No longer needed + LINKDOT_VISIT_START(); checkNoDot(nodep); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } void visit(AstPackageExport* nodep) override { // No longer needed + LINKDOT_VISIT_START(); checkNoDot(nodep); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } void visit(AstPackageExportStarStar* nodep) override { // No longer needed + LINKDOT_VISIT_START(); checkNoDot(nodep); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } void visit(AstCellRef* nodep) override { - UINFO(5, " AstCellRef: " << nodep << " " << m_ds.ascii() << endl); + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); iterateChildren(nodep); } void visit(AstCellArrayRef* nodep) override { - UINFO(5, " AstCellArrayRef: " << nodep << " " << m_ds.ascii() << endl); + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); // Expression already iterated } void visit(AstUnlinkedRef* nodep) override { - UINFO(5, " AstCellArrayRef: " << nodep << " " << m_ds.ascii() << endl); + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep << endl); // No need to iterate, if we have a UnlinkedVarXRef, we're already done } void visit(AstStmtExpr* nodep) override { + LINKDOT_VISIT_START(); checkNoDot(nodep); // Check if nodep represents a super.new call; if (VN_IS(nodep->exprp(), New)) { @@ -3966,12 +4093,15 @@ class LinkDotResolveVisitor final : public VNVisitor { } void visit(AstIfaceRefDType* nodep) override { + if (nodep->user3SetOnce()) return; + LINKDOT_VISIT_START(); if (nodep->paramsp()) { // If there is no parameters, there is no need to visit this node. AstIface* const ifacep = nodep->ifacep(); UASSERT_OBJ(ifacep, nodep, "Port parameters of AstIfaceRefDType without ifacep()"); if (ifacep->dead()) return; checkNoDot(nodep); + VL_RESTORER(m_usedPins); m_usedPins.clear(); VL_RESTORER(m_pinSymp); m_pinSymp = m_statep->getNodeSym(ifacep); @@ -3982,6 +4112,7 @@ class LinkDotResolveVisitor final : public VNVisitor { void visit(AstAttrOf* nodep) override { iterateChildren(nodep); } void visit(AstNode* nodep) override { + LINKDOT_VISIT_START(); checkNoDot(nodep); iterateChildren(nodep); } @@ -4014,7 +4145,7 @@ void V3LinkDot::linkDotGuts(AstNetlist* rootp, VLinkDotStep step) { v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("prelinkdot-find.tree")); } if (step == LDS_PRIMARY || step == LDS_PARAMED) { - // Initial link stage, resolve parameters + // Initial link stage, resolve parameters and interfaces const LinkDotParamVisitor visitors{rootp, &state}; if (dumpTreeEitherLevel() >= 9) { V3Global::dumpCheckGlobalTree("prelinkdot-param"); diff --git a/src/V3LinkDot.h b/src/V3LinkDot.h index 351993913..0231c9a64 100644 --- a/src/V3LinkDot.h +++ b/src/V3LinkDot.h @@ -22,7 +22,6 @@ #include "V3Ast.h" #include "V3Error.h" -#include "V3ThreadSafety.h" //============================================================================ diff --git a/src/V3LinkInc.h b/src/V3LinkInc.h index 9a3051da4..920f77c1d 100644 --- a/src/V3LinkInc.h +++ b/src/V3LinkInc.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp index 2bc85cab3..7919b9ecb 100644 --- a/src/V3LinkJump.cpp +++ b/src/V3LinkJump.cpp @@ -202,12 +202,13 @@ class LinkJumpVisitor final : public VNVisitor { // Note var can be signed or unsigned based on original number. AstNodeExpr* const countp = nodep->countp()->unlinkFrBackWithNext(); const string name = "__Vrepeat"s + cvtToStr(m_modRepeatNum++); + AstBegin* const beginp = new AstBegin{nodep->fileline(), "", nullptr, false, true}; // Spec says value is integral, if negative is ignored AstVar* const varp = new AstVar{nodep->fileline(), VVarType::BLOCKTEMP, name, nodep->findSigned32DType()}; varp->lifetime(VLifetime::AUTOMATIC); varp->usedLoopIdx(true); - m_modp->addStmtsp(varp); + beginp->addStmtsp(varp); AstNode* initsp = new AstAssign{ nodep->fileline(), new AstVarRef{nodep->fileline(), varp, VAccess::WRITE}, countp}; AstNode* const decp = new AstAssign{ @@ -222,8 +223,9 @@ class LinkJumpVisitor final : public VNVisitor { AstWhile* const whilep = new AstWhile{nodep->fileline(), condp, bodysp, decp}; if (!m_unrollFull.isDefault()) whilep->unrollFull(m_unrollFull); m_unrollFull = VOptionBool::OPT_DEFAULT_FALSE; - initsp = initsp->addNext(whilep); - nodep->replaceWith(initsp); + beginp->addStmtsp(initsp); + beginp->addStmtsp(whilep); + nodep->replaceWith(beginp); VL_DO_DANGLING(nodep->deleteTree(), nodep); } void visit(AstWhile* nodep) override { diff --git a/src/V3LinkJump.h b/src/V3LinkJump.h index da6b0751d..72a7b7f71 100644 --- a/src/V3LinkJump.h +++ b/src/V3LinkJump.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3LinkLValue.cpp b/src/V3LinkLValue.cpp index 01d207de7..e0d14cdfb 100644 --- a/src/V3LinkLValue.cpp +++ b/src/V3LinkLValue.cpp @@ -311,6 +311,7 @@ class LinkLValueVisitor final : public VNVisitor { } } void visit(AstNodePreSel* nodep) override { + if (AstSelBit* const selbitp = VN_CAST(nodep, SelBit)) selbitp->access(m_setRefLvalue); VL_RESTORER(m_setRefLvalue); { // Only set lvalues on the from iterateAndNextNull(nodep->fromp()); diff --git a/src/V3LinkLValue.h b/src/V3LinkLValue.h index 0d0139890..99cf582a1 100644 --- a/src/V3LinkLValue.h +++ b/src/V3LinkLValue.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; class AstNode; diff --git a/src/V3LinkLevel.h b/src/V3LinkLevel.h index 02e661d9b..dd98ffa2b 100644 --- a/src/V3LinkLevel.h +++ b/src/V3LinkLevel.h @@ -22,7 +22,6 @@ #include "V3Ast.h" #include "V3Error.h" -#include "V3ThreadSafety.h" #include diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index e180141b6..faa31fe0c 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -45,7 +45,6 @@ class LinkParseVisitor final : public VNVisitor { using ImplTypedefMap = std::map, AstTypedef*>; // STATE - AstPackage* const m_stdPackagep; // SystemVerilog std package AstVar* m_varp = nullptr; // Variable we're under ImplTypedefMap m_implTypedef; // Created typedefs for each std::unordered_set m_filelines; // Filelines that have been seen @@ -192,9 +191,7 @@ class LinkParseVisitor final : public VNVisitor { if (!nodep->lifetime().isNone()) { m_lifetime = nodep->lifetime(); } else { - const AstClassOrPackageRef* const classPkgRefp - = VN_AS(nodep->classOrPackagep(), ClassOrPackageRef); - if (classPkgRefp && VN_IS(classPkgRefp->classOrPackageNodep(), Class)) { + if (nodep->classMethod()) { // Class methods are automatic by default m_lifetime = VLifetime::AUTOMATIC; } else if (nodep->dpiImport() || VN_IS(nodep, Property)) { @@ -401,15 +398,6 @@ class LinkParseVisitor final : public VNVisitor { VN_AS(nodep->valuep()->unlinkFrBack(), NodeExpr)}); } } - if (nodep->isIfaceRef() && !nodep->isIfaceParent() && !v3Global.opt.topIfacesSupported()) { - // Only AstIfaceRefDType's at this point correspond to ports; - // haven't made additional ones for interconnect yet, so assert is simple - // What breaks later is we don't have a Scope/Cell representing - // the interface to attach to - if (m_modp->level() <= 2) { - nodep->v3warn(E_UNSUPPORTED, "Unsupported: Interfaced port on top level module"); - } - } } void visit(AstConst* nodep) override { if (nodep->num().autoExtend() && nodep->fileline()->language() < V3LangCode::L1800_2005) { @@ -841,10 +829,8 @@ class LinkParseVisitor final : public VNVisitor { VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } } - void visit(AstClassOrPackageRef* nodep) override { - if (nodep->name() == "std" && !nodep->classOrPackagep()) { - nodep->classOrPackagep(m_stdPackagep); - } + void visit(AstClassOrPackageRef* nodep) override { // + iterateChildren(nodep); } void visit(AstClocking* nodep) override { cleanFileline(nodep); @@ -917,10 +903,7 @@ class LinkParseVisitor final : public VNVisitor { public: // CONSTRUCTORS - explicit LinkParseVisitor(AstNetlist* rootp) - : m_stdPackagep{rootp->stdPackagep()} { - iterate(rootp); - } + explicit LinkParseVisitor(AstNetlist* rootp) { iterate(rootp); } ~LinkParseVisitor() override { V3Stats::addStatSum(V3Stats::STAT_SOURCE_MODULES, m_statModules); } diff --git a/src/V3LinkParse.h b/src/V3LinkParse.h index fc56900ba..12b2f2c11 100644 --- a/src/V3LinkParse.h +++ b/src/V3LinkParse.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index 3d8a270fd..426d7b1ca 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -50,6 +50,7 @@ class LinkResolveVisitor final : public VNVisitor { AstNodeFTask* m_ftaskp = nullptr; // Function or task we're inside AstNodeCoverOrAssert* m_assertp = nullptr; // Current assertion int m_senitemCvtNum = 0; // Temporary signal counter + bool m_underGenFor = false; // Under GenFor bool m_underGenerate = false; // Under GenFor/GenIf // VISITs @@ -105,6 +106,12 @@ class LinkResolveVisitor final : public VNVisitor { void visit(AstNodeVarRef* nodep) override { // VarRef: Resolve its reference if (nodep->varp()) nodep->varp()->usedParam(true); + // TODO should look for where genvar is valid, but for now catch + // just gross errors of using genvar outside any generate + if (nodep->varp() && nodep->varp()->isGenVar() && !m_underGenFor) { + nodep->v3error("Genvar " << nodep->prettyNameQ() + << " used outside generate for loop (IEEE 1800-2023 27.4)"); + } iterateChildren(nodep); } @@ -113,14 +120,7 @@ class LinkResolveVisitor final : public VNVisitor { // NodeTask: Remember its name for later resolution if (m_underGenerate) nodep->underGenerate(true); // Remember the existing symbol table scope - if (m_classp) { - if (nodep->name() == "randomize" || nodep->name() == "srandom") { - nodep->v3error(nodep->prettyNameQ() - << " is a predefined class method; redefinition not allowed" - " (IEEE 1800-2023 18.6.3)"); - } - nodep->classMethod(true); - } + if (m_classp) nodep->classMethod(true); // V3LinkDot moved the isExternDef into the class, the extern proto was // checked to exist, and now isn't needed nodep->isExternDef(false); @@ -376,6 +376,7 @@ class LinkResolveVisitor final : public VNVisitor { expectFormat(nodep, nodep->text(), nodep->exprsp(), true); } void visit(AstSFormatF* nodep) override { + if (nodep->user2SetOnce()) return; iterateChildren(nodep); // Cleanup old-school displays without format arguments if (!nodep->hasFormat()) { @@ -456,7 +457,9 @@ class LinkResolveVisitor final : public VNVisitor { // We keep Modport's themselves around for XML dump purposes void visit(AstGenFor* nodep) override { + VL_RESTORER(m_underGenFor); VL_RESTORER(m_underGenerate); + m_underGenFor = true; m_underGenerate = true; iterateChildren(nodep); } diff --git a/src/V3LinkResolve.h b/src/V3LinkResolve.h index e1eb1f879..c84219fb7 100644 --- a/src/V3LinkResolve.h +++ b/src/V3LinkResolve.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Localize.h b/src/V3Localize.h index e9041b63f..456b90706 100644 --- a/src/V3Localize.h +++ b/src/V3Localize.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3MergeCond.h b/src/V3MergeCond.h index 6e798e8ac..1b78dab0f 100644 --- a/src/V3MergeCond.h +++ b/src/V3MergeCond.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Mutex.h b/src/V3Mutex.h index 03550b48e..77496d752 100644 --- a/src/V3Mutex.h +++ b/src/V3Mutex.h @@ -111,21 +111,6 @@ public: void assumeLocked() VL_ASSERT_CAPABILITY(this) VL_MT_SAFE {} /// Pretend that the mutex is being unlocked. Purely for Clang thread safety analyzer. void pretendUnlock() VL_RELEASE() VL_MT_SAFE {} - /// Acquire/lock mutex and check for stop request - /// It tries to lock the mutex and if it fails, it check if stop request was send. - /// It returns after locking mutex. - /// This function should be extracted to V3ThreadPool, but due to clang thread-safety - /// limitations it needs to be placed here. - void lockCheckStopRequest(std::function checkStopRequestFunction) - VL_ACQUIRE() VL_MT_SAFE { - if (V3MutexConfig::s().enable()) { - while (true) { - checkStopRequestFunction(); - if (m_mutex.try_lock()) return; - VL_CPU_RELAX(); - } - } - } }; /// Lock guard for mutex (ala std::unique_lock), wrapped to allow -fthread_safety checks diff --git a/src/V3Name.h b/src/V3Name.h index df0f9d083..514e6e12f 100644 --- a/src/V3Name.h +++ b/src/V3Name.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Number.cpp b/src/V3Number.cpp index 996de3898..c446947aa 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -198,7 +198,7 @@ void V3Number::create(const char* sourcep) { } // Otherwise... else if (!sized()) { - width(32, false); // Says IEEE 1800-2012 5.7.1 + width(v3Global.opt.maxNumWidth(), false); // Will change width below if (unbased) isSigned(true); // Also says the spec. } @@ -213,6 +213,7 @@ void V3Number::create(const char* sourcep) { } int obit = 0; // Start at LSB + int base_align = 1; if (std::tolower(base) == 'd') { // Ignore leading zeros so we don't issue too many digit errors when lots of leading 0's while (*value_startp == '_' || *value_startp == '0') value_startp++; @@ -247,15 +248,7 @@ void V3Number::create(const char* sourcep) { product.opMul(*this, ten); opAdd(product, addend); if (product.bitsValue(width(), 4)) { // Overflowed - static int warned = 0; - v3error("Too many digits for " - << width() << " bit number: " << sourcep << '\n' - << ((!sized() && !warned++) ? ( - V3Error::warnMore() + "... As that number was unsized" - + " ('d...) it is limited to 32 bits" - " (IEEE 1800-2023 5.7.1)\n" - + V3Error::warnMore() + "... Suggest adding a size to it.") - : "")); + warnTooMany(sourcep); while (*(cp + 1)) cp++; // Skip ahead so don't get multiple warnings } } @@ -266,11 +259,13 @@ void V3Number::create(const char* sourcep) { case 'z': case '?': { got_z = 1; + if (!userSized) width(32, false); setAllBitsZ(); break; } case 'x': { got_x = 1; + if (!userSized) width(32, false); setAllBitsX(); break; } @@ -291,11 +286,12 @@ void V3Number::create(const char* sourcep) { for (const char* cp = value_startp + std::strlen(value_startp) - 1; cp >= value_startp; cp--) { if (*cp != '_' && *cp != '0' && obit >= width()) { - v3error("Too many digits for " << width() << " bit number: " << sourcep); + warnTooMany(sourcep); break; } switch (std::tolower(base)) { case 'b': { + base_align = 1; switch (std::tolower(*cp)) { case '0': setBit(obit++, 0); break; case '1': setBit(obit++, 1); break; @@ -310,6 +306,7 @@ void V3Number::create(const char* sourcep) { case 'o': case 'c': { + base_align = 3; switch (std::tolower(*cp)) { // clang-format off case '0': setBit(obit++, 0); setBit(obit++, 0); setBit(obit++, 0); break; case '1': setBit(obit++, 1); setBit(obit++, 0); setBit(obit++, 0); break; @@ -330,6 +327,7 @@ void V3Number::create(const char* sourcep) { } case 'h': { + base_align = 4; switch (std::tolower(*cp)) { // clang-format off case '0': setBit(obit++,0); setBit(obit++,0); setBit(obit++,0); setBit(obit++,0); break; case '1': setBit(obit++,1); setBit(obit++,0); setBit(obit++,0); setBit(obit++,0); break; @@ -367,6 +365,11 @@ void V3Number::create(const char* sourcep) { } } + // If was unsized, trim width per IEEE 1800-2023 5.7.1 + if (!userSized && !m_data.m_autoExtend) { + width(std::max(32, base_align * ((widthMin() + base_align - 1) / base_align)), false); + } + // Z or X extend specific width values. Spec says we don't 1 extend. // This fixes 2'bx to become 2'bxx. while (obit <= width() && obit && bitIsXZ(obit - 1)) { @@ -379,6 +382,10 @@ void V3Number::create(const char* sourcep) { // m_value[0]); } +void V3Number::warnTooMany(const string& value) { + v3error("Too many digits for " << width() << " bit number: '" << value << "'\n"); +} + void V3Number::nodep(AstNode* nodep) VL_MT_STABLE { m_nodep = nodep; if (!nodep) return; @@ -388,6 +395,17 @@ void V3Number::nodep(AstNode* nodep) VL_MT_STABLE { //====================================================================== // Global +bool V3Number::epsilonEqual(double a, double b) { + return std::fabs(a - b) + <= (std::numeric_limits::epsilon() * std::max(1.0, std::max(a, b))); +} + +bool V3Number::epsilonIntegral(double a) { + const double dint = static_cast(static_cast(a)); + // Check all the rounding possibilities, as we did truncation above rather than rounding + return epsilonEqual(a, dint) || epsilonEqual(a, dint - 1) || epsilonEqual(a, dint + 1); +} + int V3Number::log2b(uint32_t num) { // See also opCLog2 for (int bit = 31; bit > 0; bit--) { @@ -493,9 +511,9 @@ V3Number& V3Number::setValue1() { return *this; } -V3Number& V3Number::setMask(int nbits) { +V3Number& V3Number::setMask(int nbits, int lsb) { setZero(); - for (int bit = 0; bit < nbits; bit++) setBit(bit, 1); + for (int bit = lsb; bit < lsb + nbits; bit++) setBit(bit, 1); return *this; } @@ -2539,3 +2557,37 @@ V3Number& V3Number::opLteN(const V3Number& lhs, const V3Number& rhs) { NUM_ASSERT_STRING_ARGS2(lhs, rhs); return setSingleBits(lhs.toString() <= rhs.toString()); } + +//====================================================================== + +void V3Number::selfTest() { + UINFO(2, __FUNCTION__ << ": " << endl); + FileLine* const fl = new FileLine{FileLine::builtInFilename()}; + V3Number num{fl, 32, 0}; + num.selfTestThis(); +} + +void V3Number::selfTestThis() { + // The self test has a "this" so UASSERT_SELFTEST/errorEndFatal works correctly + + UASSERT_SELFTEST(bool, V3Number::epsilonEqual(0, 0), true); + UASSERT_SELFTEST(bool, V3Number::epsilonEqual(1e19, 1e19), true); + UASSERT_SELFTEST(bool, V3Number::epsilonEqual(9, 0.0001), false); + UASSERT_SELFTEST(bool, V3Number::epsilonEqual(1, 1 + std::numeric_limits::epsilon()), + true); + UASSERT_SELFTEST(bool, V3Number::epsilonEqual(0.009, 0.00899999999999999931998839741709), + true); + + UASSERT_SELFTEST(bool, V3Number::epsilonIntegral(0), true); + UASSERT_SELFTEST(bool, V3Number::epsilonIntegral(1), true); + UASSERT_SELFTEST(bool, V3Number::epsilonIntegral(-1), true); + UASSERT_SELFTEST(bool, V3Number::epsilonIntegral(1.0001), false); + UASSERT_SELFTEST(bool, V3Number::epsilonIntegral(0.9999), false); + UASSERT_SELFTEST(bool, V3Number::epsilonIntegral(-1.0001), false); + UASSERT_SELFTEST(bool, V3Number::epsilonIntegral(-0.9999), false); + + UASSERT_SELFTEST(int, log2b(0), 0); + UASSERT_SELFTEST(int, log2b(1), 0); + UASSERT_SELFTEST(int, log2b(0x40000000UL), 30); + UASSERT_SELFTEST(int, log2bQuad(0x4000000000000000ULL), 62); +} diff --git a/src/V3Number.h b/src/V3Number.h index dd3653383..19b449ca3 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -32,14 +32,6 @@ //============================================================================ -// Return if two numbers within Epsilon of each other -inline bool v3EpsilonEqual(double a, double b) { - return std::fabs(a - b) - <= (std::numeric_limits::epsilon() * std::max(1.0, std::max(a, b))); -} - -//============================================================================ - class AstNode; class AstNodeDType; class FileLine; @@ -533,6 +525,7 @@ public: ~V3Number() {} private: + void selfTestThis(); void create(AstNode* nodep, const char* sourcep) { init(nodep, 0); m_fileline = nullptr; @@ -565,6 +558,7 @@ private: string displayed(const string& vformat) const VL_MT_STABLE { return displayed(m_fileline, vformat); } + void warnTooMany(const string& value); public: void v3errorEnd(const std::ostringstream& sstr) const VL_RELEASE(V3Error::s().m_mutex); @@ -582,7 +576,8 @@ public: V3Number& setAllBits0(); V3Number& setAllBits1(); V3Number& setValue1(); - V3Number& setMask(int nbits); // IE if nbits=1, then 0b1, if 2->0b11, if 3->0b111 etc + // IE if nbits=1, then 0b1, if 2->0b11, if 3->0b111 etc + V3Number& setMask(int nbits, int lsb = 0); // ACCESSORS string ascii(bool prefixed = true, bool cleanVerilog = false) const VL_MT_STABLE; @@ -661,8 +656,11 @@ public: bool operator<(const V3Number& rhs) const { return isLtXZ(rhs); } // STATICS + static bool epsilonEqual(double a, double b); // True if number within Epsilon of the other + static bool epsilonIntegral(double a); // True if number rounds to integer within Epsilon static int log2b(uint32_t num); static int log2bQuad(uint64_t num); + static void selfTest(); // MATH // "this" is the output, as we need the output width before some computations diff --git a/src/V3Number_test.cpp b/src/V3Number_test.cpp deleted file mode 100644 index 45bbc1d82..000000000 --- a/src/V3Number_test.cpp +++ /dev/null @@ -1,147 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -//************************************************************************* -// DESCRIPTION: Verilator: Netlist (top level) functions -// -// Code available from: https://verilator.org -// -//************************************************************************* -// -// Copyright 2003-2024 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -// -//************************************************************************* - -// CHEAT! -#define V3NUMBER_ASCII_BINARY -#define V3ERROR_NO_GLOBAL_ -#define VL_MT_DISABLED_CODE_UNIT 1 - -#include "config_build.h" -#include "verilatedos.h" - -#include "V3Error.cpp" -#include "V3FileLine.cpp" -#include "V3Number.cpp" -#include "V3Number.h" - -#include -#include - -void test(const string& lhss, const string& op, const string& rhss, const string& exps) { - char* l1 = strdup(lhss.c_str()); - char* r1 = strdup(rhss.c_str()); - char* e1 = strdup(exps.c_str()); - - const FileLine fl = new FileLine{FileLine::builtInFinename()}; - - V3Number lhnum{fl, l1}; - V3Number rhnum{fl, r1}; - V3Number expnum{fl, e1}; - V3Number gotnum{fl, expnum.width()}; - - if (op == "redOr") { - gotnum.opRedOr(lhnum); - } else if (op == "redAnd") { - gotnum.opRedAnd(lhnum); - } else if (op == "redXor") { - gotnum.opRedXor(lhnum); - } else if (op == "concat") { - gotnum.opConcat(lhnum, rhnum); - } else if (op == "repl") { - gotnum.opRepl(lhnum, rhnum); - } else if (op == "~") { - gotnum.opNot(lhnum); - } else if (op == "!") { - gotnum.opLogNot(lhnum); - } else if (op == "negate") { - gotnum.opNegate(lhnum); - } else if (op == "+") { - gotnum.opAdd(lhnum, rhnum); - } else if (op == "-") { - gotnum.opSub(lhnum, rhnum); - } else if (op == "*") { - gotnum.opMul(lhnum, rhnum); - } else if (op == "/") { - gotnum.opDiv(lhnum, rhnum); - } else if (op == "%") { - gotnum.opModDiv(lhnum, rhnum); - } else if (op == "&") { - gotnum.opAnd(lhnum, rhnum); - } else if (op == "|") { - gotnum.opOr(lhnum, rhnum); - } else if (op == "<") { - gotnum.opLt(lhnum, rhnum); - } else if (op == ">") { - gotnum.opGt(lhnum, rhnum); - } else if (op == ">>") { - gotnum.opShiftR(lhnum, rhnum); - } else if (op == "<<") { - gotnum.opShiftL(lhnum, rhnum); - } else if (op == "==") { - gotnum.opEq(lhnum, rhnum); - } else if (op == "===") { - gotnum.opCaseEq(lhnum, rhnum); - } else if (op == "==?") { - gotnum.opWildEq(lhnum, rhnum); - } else if (op == "!=") { - gotnum.opNeq(lhnum, rhnum); - } else if (op == "!==") { - gotnum.opCaseNeq(lhnum, rhnum); - } else if (op == "!=?") { - gotnum.opWildNeq(lhnum, rhnum); - } else if (op == "<=") { - gotnum.opLte(lhnum, rhnum); - } else if (op == ">=") { - gotnum.opGte(lhnum, rhnum); - } else if (op == "&&") { - gotnum.opLogAnd(lhnum, rhnum); - } else if (op == "||") { - gotnum.opLogOr(lhnum, rhnum); - } else { - v3fatalSrc("Bad opcode: " << op); - } - - UINFO(0, "------- Test:\n" - << " " << lhnum << " " << op << endl - << " " << rhnum << endl - << " = " << expnum << endl - << " =? " << gotnum << endl); - - V3Number ok{fl, 1}; - ok.opCaseEq(expnum, gotnum); - if (ok.toUInt() != 1) v3fatalSrc("%Error:Test FAILED"); - - free(l1); - free(r1); - free(e1); -} - -int main() { - UINFO(0, "Test starting\n"); - - test("32'b10", "|", "32'b10", "32'b10"); - test("2'bx0", "|", "2'b10", "2'b10"); - test("32'b0x", "|", "32'b10", "32'b1x"); - test("32'b10", "&", "32'b11", "32'b10"); - test("32'b10", "+", "32'b10", "32'b100"); - test("3'b000", "negate", "", "3'b000"); - test("3'b001", "negate", "", "3'b111"); - test("32'b11", "-", "32'b001", "32'b10"); - test("3'b000", "-", "3'b111", "3'b001"); - test("3'b000", "-", "3'b000", "3'b000"); - test("57'h000000010F0CCE7", "*", "57'h10", "57'h10F0CCE70"); - test("57'h000000010F0CCE7", "*", "57'h0DE34E7FFFFFFFF", "57'h02A9D57EF0F3319"); - test("67'h7FFFFFFFFFFFFFFFF", "*", "67'h4000000003C8A8D6A", "67'h3FFFFFFFFC3757296"); - test("99'h7FFFFFFFFFFFFFFFFFFFFFFFF", "*", "99'h0000000000000000091338A80", - "99'h7FFFFFFFFFFFFFFFF6ECC7580"); - - std::cout << "Test completed\n"; -} - -//################################################################### -// Local Variables: -// compile-command: "make V3Number_test && ./V3Number_test " -// End: diff --git a/src/V3OptionParser.h b/src/V3OptionParser.h index 77250b1c7..9b35b9e48 100644 --- a/src/V3OptionParser.h +++ b/src/V3OptionParser.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - #include #include #include diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 4326a4171..dee87bee0 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -395,6 +395,7 @@ void V3Options::addVFile(const string& filename) { // in a specific order and multiple of them. m_vFiles.push_back(filename); } +void V3Options::addVltFile(const string& filename) { m_vltFiles.insert(filename); } void V3Options::addForceInc(const string& filename) { m_forceIncs.push_back(filename); } void V3Options::addLineArg(const string& arg) { m_impp->m_lineArgs.push_back(arg); } @@ -415,8 +416,18 @@ string V3Options::allArgsStringForHierBlock(bool forTop, bool forCMake) const { std::set vFiles; for (const auto& vFile : m_vFiles) vFiles.insert(vFile); string out; + bool stripArg = false; + bool stripArgIfNum = false; for (std::list::const_iterator it = m_impp->m_lineArgs.begin(); it != m_impp->m_lineArgs.end(); ++it) { + if (stripArg) { + stripArg = false; + continue; + } + if (stripArgIfNum) { + stripArgIfNum = false; + if (isdigit((*it)[0])) continue; + } int skip = 0; if (it->length() >= 2 && (*it)[0] == '-' && (*it)[1] == '-') { skip = 2; @@ -427,8 +438,9 @@ string V3Options::allArgsStringForHierBlock(bool forTop, bool forCMake) const { const string opt = it->substr(skip); // Remove '-' in the beginning const int numStrip = stripOptionsForChildRun(opt, forTop); if (numStrip) { - UASSERT(0 <= numStrip && numStrip <= 2, "should be one of 0, 1, 2"); - if (numStrip == 2) ++it; + UASSERT(0 <= numStrip && numStrip <= 3, "should be one of 0, 1, 2, 3"); + if (numStrip == 2) stripArg = true; + if (numStrip == 3) stripArgIfNum = true; continue; } } else { // Not an option @@ -535,10 +547,12 @@ string V3Options::filePathCheckOneDir(const string& modname, const string& dirna // 0: Keep the option including its argument // 1: Delete the option which has no argument // 2: Delete the option and its argument +// 3: Delete the option and its argument if it is a number int V3Options::stripOptionsForChildRun(const string& opt, bool forTop) { - if (opt == "Mdir" || opt == "clk" || opt == "lib-create" || opt == "f" || opt == "j" + if (opt == "j") return 3; + if (opt == "Mdir" || opt == "clk" || opt == "lib-create" || opt == "f" || opt == "v" || opt == "l2-name" || opt == "mod-prefix" || opt == "prefix" || opt == "protect-lib" - || opt == "protect-key" || opt == "threads" || opt == "top-module" || opt == "v") { + || opt == "protect-key" || opt == "threads" || opt == "top-module") { return 2; } if (opt == "build" || (!forTop && (opt == "cc" || opt == "exe" || opt == "sc")) @@ -1407,6 +1421,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, fl->v3error("--output-split-ctrace must be >= 0: " << valp); } }); + DECL_OPTION("-output-groups", CbVal, [this, fl](const char* valp) { + m_outputGroups = std::atoi(valp); + if (m_outputGroups < 0) { fl->v3error("--output-groups must be >= 0: " << valp); } + }); DECL_OPTION("-P", Set, &m_preprocNoLine); DECL_OPTION("-pvalue+", CbPartialMatch, @@ -1772,6 +1790,8 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, || suffixed(filename, ".o") // || suffixed(filename, ".so")) { V3Options::addLdLibs(filename); + } else if (suffixed(filename, ".vlt")) { + V3Options::addVltFile(filename); } else { V3Options::addVFile(filename); } @@ -2032,7 +2052,7 @@ unsigned V3Options::dumpLevel(const string& tag) const VL_MT_SAFE { return iter != m_dumpLevel.end() ? iter->second : 0; } -unsigned V3Options::dumpSrcLevel(const string& srcfile_path) const { +unsigned V3Options::dumpSrcLevel(const string& srcfile_path) const VL_MT_SAFE { // For simplicity, calling functions can just use __FILE__ for srcfile. // That means we need to strip the filenames: ../Foo.cpp -> Foo return dumpLevel(V3Os::filenameNonDirExt(srcfile_path)); diff --git a/src/V3Options.h b/src/V3Options.h index 324247ff5..2ac99bf04 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -22,7 +22,6 @@ #include "V3Error.h" #include "V3LangCode.h" -#include "V3ThreadSafety.h" #include #include @@ -211,6 +210,7 @@ private: V3StringSet m_clockers; // argument: Verilog -clk signals V3StringSet m_noClockers; // argument: Verilog -noclk signals V3StringList m_vFiles; // argument: Verilog files to read + V3StringSet m_vltFiles; // argument: Verilator config files to read V3StringList m_forceIncs; // argument: -FI DebugLevelMap m_debugLevel; // argument: --debugi- DebugLevelMap m_dumpLevel; // argument: --dumpi- @@ -316,6 +316,7 @@ private: VOptionBool m_makeDepend; // main switch: -MMD int m_maxNumWidth = 65536; // main switch: --max-num-width int m_moduleRecursion = 100; // main switch: --module-recursion-depth + int m_outputGroups = 0; // main switch: --output-groups int m_outputSplit = 20000; // main switch: --output-split int m_outputSplitCFuncs = -1; // main switch: --output-split-cfuncs int m_outputSplitCTrace = -1; // main switch: --output-split-ctrace @@ -433,7 +434,7 @@ public: unsigned debugLevel(const string& tag) const VL_MT_SAFE; unsigned debugSrcLevel(const string& srcfile_path) const VL_MT_SAFE; unsigned dumpLevel(const string& tag) const VL_MT_SAFE; - unsigned dumpSrcLevel(const string& srcfile_path) const; + unsigned dumpSrcLevel(const string& srcfile_path) const VL_MT_SAFE; // METHODS void addCppFile(const string& filename); @@ -445,6 +446,7 @@ public: void addClocker(const string& signame); void addNoClocker(const string& signame); void addVFile(const string& filename); + void addVltFile(const string& filename); void addForceInc(const string& filename); bool available() const VL_MT_SAFE { return m_available; } void ccSet(); @@ -521,7 +523,7 @@ public: bool pinsInoutEnables() const { return m_pinsInoutEnables; } bool pinsScUint() const { return m_pinsScUint; } bool pinsScUintBool() const { return m_pinsScUintBool; } - bool pinsScBigUint() const { return m_pinsScBigUint; } + bool pinsScBigUint() const VL_MT_SAFE { return m_pinsScBigUint; } bool pinsUint8() const { return m_pinsUint8; } bool ppComments() const { return m_ppComments; } bool profC() const { return m_profC; } @@ -564,14 +566,15 @@ public: int outputSplit() const { return m_outputSplit; } int outputSplitCFuncs() const { return m_outputSplitCFuncs; } int outputSplitCTrace() const { return m_outputSplitCTrace; } - int pinsBv() const { return m_pinsBv; } + int outputGroups() const { return m_outputGroups; } + int pinsBv() const VL_MT_SAFE { return m_pinsBv; } int publicDepth() const { return m_publicDepth; } int reloopLimit() const { return m_reloopLimit; } VOptionBool skipIdentical() const { return m_skipIdentical; } bool stopFail() const { return m_stopFail; } int threads() const VL_MT_SAFE { return m_threads; } int threadsMaxMTasks() const { return m_threadsMaxMTasks; } - bool mtasks() const { return (m_threads > 1); } + bool mtasks() const VL_MT_SAFE { return (m_threads > 1); } VTimescale timeDefaultPrec() const { return m_timeDefaultPrec; } VTimescale timeDefaultUnit() const { return m_timeDefaultUnit; } VTimescale timeOverridePrec() const { return m_timeOverridePrec; } @@ -597,7 +600,7 @@ public: int verilateJobs() const { return m_verilateJobs; } int compLimitBlocks() const { return m_compLimitBlocks; } - int compLimitMembers() const { return m_compLimitMembers; } + int compLimitMembers() const VL_MT_SAFE { return m_compLimitMembers; } int compLimitParens() const { return m_compLimitParens; } string exeName() const { return m_exeName != "" ? m_exeName : prefix(); } @@ -639,6 +642,7 @@ public: const V3StringList& makeFlags() const { return m_makeFlags; } const V3StringSet& libraryFiles() const { return m_libraryFiles; } const V3StringList& vFiles() const { return m_vFiles; } + const V3StringSet& vltFiles() const { return m_vltFiles; } const V3StringList& forceIncs() const { return m_forceIncs; } bool hasParameter(const string& name); @@ -694,7 +698,7 @@ public: } bool hierarchical() const { return m_hierarchical; } - int hierChild() const { return m_hierChild; } + int hierChild() const VL_MT_SAFE { return m_hierChild; } bool hierTop() const VL_MT_SAFE { return !m_hierChild && !m_hierBlocks.empty(); } const V3HierBlockOptSet& hierBlocks() const { return m_hierBlocks; } // Directory to save .tree, .dot, .dat, .vpp for hierarchical block top diff --git a/src/V3Order.cpp b/src/V3Order.cpp index 980b546b1..431a5f956 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -132,7 +132,7 @@ AstCFunc* V3Order::order(AstNetlist* netlistp, // // Order it orderOrderGraph(*graph, tag); // Assign sensitivity domains to combinational logic - processDomains(netlistp, *graph, tag, trigToSen, externalDomains); + processDomains(netlistp, *graph, tag, externalDomains); if (parallel) { // Construct the parallel ExecGraph diff --git a/src/V3Order.h b/src/V3Order.h index 65ec500b8..cf4c117e2 100644 --- a/src/V3Order.h +++ b/src/V3Order.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - #include #include #include @@ -42,8 +40,8 @@ namespace V3Order { // Callable to add extra external Triggers to a variable using ExternalDomainsProvider = std::function&)>; -// Map from Trigger expression to original Sensitivity tree -using TrigToSenMap = std::unordered_map; +// Map from Trigger Sensitivity tree to original Sensitivity tree +using TrigToSenMap = std::unordered_map; AstCFunc* order( AstNetlist* netlistp, // diff --git a/src/V3OrderGraphBuilder.cpp b/src/V3OrderGraphBuilder.cpp index 633a6b664..d885a399c 100644 --- a/src/V3OrderGraphBuilder.cpp +++ b/src/V3OrderGraphBuilder.cpp @@ -134,9 +134,8 @@ class OrderGraphBuilder final : public VNVisitor { // This is the original sensitivity of the block (i.e.: not the ref into the TRIGGERVEC) - const AstSenTree* const senTreep = nodep->sensesp()->hasCombo() - ? nodep->sensesp() - : m_trigToSen.at(nodep->sensesp()->sensesp()); + const AstSenTree* const senTreep + = nodep->sensesp()->hasCombo() ? nodep->sensesp() : m_trigToSen.at(nodep->sensesp()); m_inClocked = senTreep->hasClocked(); @@ -216,24 +215,20 @@ class OrderGraphBuilder final : public VNVisitor { // Update VarUsage varscp->user2(varscp->user2() | VU_GEN); // Add edges for produced variables - if (!m_inClocked || m_inPost) { - // Combinational logic - OrderVarVertex* const varVxp = getVarVertex(varscp, VarVertexType::STD); - // Add edge from producing LogicVertex -> produced VarStdVertex - if (m_inPost) { - m_graphp->addSoftEdge(m_logicVxp, varVxp, WEIGHT_COMBO); - } else { + if (m_inPost) { + if (!varscp->varp()->ignorePostWrite()) { + // Add edge from producing LogicVertex -> produced VarStdVertex + OrderVarVertex* const varVxp = getVarVertex(varscp, VarVertexType::STD); m_graphp->addHardEdge(m_logicVxp, varVxp, WEIGHT_NORMAL); } - + OrderVarVertex* const postVxp = getVarVertex(varscp, VarVertexType::POST); + // Add edge from produced VarPostVertex -> to producing LogicVertex + m_graphp->addHardEdge(postVxp, m_logicVxp, WEIGHT_POST); + } else if (!m_inClocked) { // Combinational logic + // Add edge from producing LogicVertex -> produced VarStdVertex + OrderVarVertex* const varVxp = getVarVertex(varscp, VarVertexType::STD); + m_graphp->addHardEdge(m_logicVxp, varVxp, WEIGHT_NORMAL); // Add edge from produced VarPostVertex -> to producing LogicVertex - - // For m_inPost: - // Add edge consumed_var_POST->logic_vertex - // This prevents a consumer of the "early" value to be scheduled - // after we've changed to the next-cycle value - // ALWAYS do it: - // There maybe a wire a=b; between the two blocks OrderVarVertex* const postVxp = getVarVertex(varscp, VarVertexType::POST); m_graphp->addHardEdge(postVxp, m_logicVxp, WEIGHT_POST); } else if (m_inPre) { // AstAssignPre diff --git a/src/V3OrderInternal.h b/src/V3OrderInternal.h index 0c5b4cfbe..10bb446f4 100644 --- a/src/V3OrderInternal.h +++ b/src/V3OrderInternal.h @@ -22,7 +22,6 @@ #include "V3Order.h" #include "V3OrderGraph.h" -#include "V3ThreadSafety.h" #include #include @@ -49,7 +48,6 @@ void orderOrderGraph(OrderGraph& graph, const std::string& tag); void processDomains(AstNetlist* netlistp, // OrderGraph& graph, // const std::string& tag, // - const TrigToSenMap& trigToSen, // const ExternalDomainsProvider& externalDomains); std::vector createSerial(OrderGraph& orderGraph, // diff --git a/src/V3OrderMoveGraph.cpp b/src/V3OrderMoveGraph.cpp index bebcd319c..6907e2263 100644 --- a/src/V3OrderMoveGraph.cpp +++ b/src/V3OrderMoveGraph.cpp @@ -111,7 +111,7 @@ class OrderMoveGraphBuilder final { if (senTreep->sensesp()->nextp()) return nullptr; // Find the original AstSenTree - auto it = m_trigToSen.find(senTreep->sensesp()); + auto it = m_trigToSen.find(senTreep); if (it == m_trigToSen.end()) return nullptr; // If more than one AstSenItems on the original, then not a simple AstSenTree diff --git a/src/V3OrderProcessDomains.cpp b/src/V3OrderProcessDomains.cpp index b89c1872f..7a27593fb 100644 --- a/src/V3OrderProcessDomains.cpp +++ b/src/V3OrderProcessDomains.cpp @@ -39,9 +39,6 @@ class V3OrderProcessDomains final { // STATE OrderGraph& m_graph; // The ordering graph - // Map from Trigger reference AstSenItem to the original AstSenTree - const V3Order::TrigToSenMap& m_trigToSen; - // This is a function provided by the invoker of the ordering that can provide additional // sensitivity expression that when triggered indicates the passed AstVarScope might have // changed external to the code being ordered. @@ -165,11 +162,6 @@ class V3OrderProcessDomains final { std::deque report; - // Rebuild the trigger to original AstSenTree map using equality key comparison, as - // merging domains have created new AstSenTree instances which are not in the map - std::unordered_map, const AstSenTree*> trigToSen; - for (const auto& pair : m_trigToSen) trigToSen.emplace(*pair.first, pair.second); - for (V3GraphVertex& vtx : m_graph.vertices()) { if (OrderVarVertex* const vvertexp = vtx.cast()) { string name(vvertexp->vscp()->prettyName()); @@ -190,12 +182,7 @@ class V3OrderProcessDomains final { for (AstSenItem* senItemp = senTreep->sensesp(); senItemp; senItemp = VN_AS(senItemp->nextp(), SenItem)) { if (senItemp != senTreep->sensesp()) os << " or "; - const auto it = trigToSen.find(*senItemp); - if (it != trigToSen.end()) { - V3EmitV::verilogForTree(it->second, os); - } else { - V3EmitV::verilogForTree(senItemp, os); - } + V3EmitV::verilogForTree(senItemp, os); } } report.push_back(os.str()); @@ -209,10 +196,8 @@ class V3OrderProcessDomains final { // CONSTRUCTOR V3OrderProcessDomains(AstNetlist* netlistp, OrderGraph& graph, const string& tag, - const V3Order::TrigToSenMap& trigToSen, const V3Order::ExternalDomainsProvider& externalDomains) : m_graph{graph} - , m_trigToSen{trigToSen} , m_externalDomains{externalDomains} , m_finder{netlistp} , m_tag{tag} { @@ -238,16 +223,14 @@ class V3OrderProcessDomains final { public: // Order the logic static void apply(AstNetlist* netlistp, OrderGraph& graph, const string& tag, - const V3Order::TrigToSenMap& trigToSen, const V3Order::ExternalDomainsProvider& externalDomains) { - V3OrderProcessDomains{netlistp, graph, tag, trigToSen, externalDomains}; + V3OrderProcessDomains{netlistp, graph, tag, externalDomains}; } }; void V3Order::processDomains(AstNetlist* netlistp, // OrderGraph& graph, // const std::string& tag, // - const V3Order::TrigToSenMap& trigToSen, // const ExternalDomainsProvider& externalDomains) { - V3OrderProcessDomains::apply(netlistp, graph, tag, trigToSen, externalDomains); + V3OrderProcessDomains::apply(netlistp, graph, tag, externalDomains); } diff --git a/src/V3Os.cpp b/src/V3Os.cpp index ab0560e51..b11f92e61 100644 --- a/src/V3Os.cpp +++ b/src/V3Os.cpp @@ -253,6 +253,55 @@ string V3Os::filenameRealPath(const string& filename) VL_PURE { } } +string V3Os::filenameRelativePath(const string& filename, const string& base) VL_PURE { + const string a = V3Os::filenameRealPath(filename); + const string b = V3Os::filenameRealPath(base); + string result; + if (a == b) return "."; + + auto aIt = a.begin(); + auto bIt = b.begin(); + while (aIt != a.end() && bIt != b.end()) { + // UINFO(9, "fnrp scan " << (aIt - a.begin()) << " " << a.substr(aIt - a.begin()) << endl); + // UINFO(9, "fnrp scan " << (bIt - b.begin()) << " " << b.substr(bIt - b.begin()) << endl); + auto aWordIt = aIt; // position of next slash + for (; aWordIt != a.end(); ++aWordIt) { + if (isSlash(*aWordIt)) break; + } + + auto bWordIt = bIt; // position of next slash + for (; bWordIt != b.end(); ++bWordIt) { + if (isSlash(*bWordIt)) break; + } + + const string aWord = a.substr(aIt - a.begin(), aWordIt - aIt); + const string bWord = b.substr(bIt - b.begin(), bWordIt - bIt); + if (aWord != bWord) break; + aIt = aWordIt; + bIt = bWordIt; + if (aIt != a.end()) ++aIt; // Skip slash + if (bIt != b.end()) ++bIt; // Skip slash + } + + while (bIt != b.end()) { + for (; bIt != b.end(); ++bIt) { + if (isSlash(*bIt)) { + ++bIt; + break; + } + } + if (!result.empty()) result += "/"; + result += ".."; + } + + const string aLeft = a.substr(aIt - a.begin()); + if (!aLeft.empty()) { + if (!result.empty()) result += "/"; + result += aLeft; + } + return filenameCleanup(result); +} + bool V3Os::filenameIsRel(const string& filename) VL_PURE { #if defined(_MSC_VER) return std::filesystem::path(filename).is_relative(); @@ -452,5 +501,19 @@ void V3Os::selfTest() { UASSERT_SELFTEST(string, filenameExt("a.a/b.b/f"), ""); UASSERT_SELFTEST(string, filenameExt("a.a/b.b/f.e"), ".e"); UASSERT_SELFTEST(string, filenameNonDirExt("a.a/b.b/f.e"), "f"); + UASSERT_SELFTEST(string, filenameRelativePath("/a/b", "/a/b"), "."); + UASSERT_SELFTEST(string, filenameRelativePath("/a/b", "/a/b/c"), ".."); + UASSERT_SELFTEST(string, filenameRelativePath("/a/b", "/a/b/c/d"), "../.."); + UASSERT_SELFTEST(string, filenameRelativePath("/a/b/x", "/a/b/c/d"), "../../x"); + UASSERT_SELFTEST(string, filenameRelativePath("/a/b/x/y", "/"), "a/b/x/y"); + UASSERT_SELFTEST(string, filenameRelativePath("/a/b/x/y", "/a/b"), "x/y"); + UASSERT_SELFTEST(string, filenameRelativePath("/a/b/x/y", "/a/q"), "../b/x/y"); + UASSERT_SELFTEST(string, filenameRelativePath("a/b", "a/b"), "."); + UASSERT_SELFTEST(string, filenameRelativePath("a/b", "a/b/c"), ".."); + UASSERT_SELFTEST(string, filenameRelativePath("a/b", "a/b/c/d"), "../.."); + UASSERT_SELFTEST(string, filenameRelativePath("a/b/x", "a/b/c/d"), "../../x"); + UASSERT_SELFTEST(string, filenameRelativePath("a/b/x/y", ""), "a/b/x/y"); + UASSERT_SELFTEST(string, filenameRelativePath("a/b/x/y", "a/b"), "x/y"); + UASSERT_SELFTEST(string, filenameRelativePath("a/b/x/y", "a/q"), "../b/x/y"); #endif } diff --git a/src/V3Os.h b/src/V3Os.h index f0f281be5..5974dc18b 100644 --- a/src/V3Os.h +++ b/src/V3Os.h @@ -55,6 +55,8 @@ public: static string filenameSubstitute(const string& filename); ///< @return realpath of filename static string filenameRealPath(const string& filename) VL_PURE; + ///< @return relative path of filename, relative to base + static string filenameRelativePath(const string& filename, const string& base) VL_PURE; ///< @return filename is relative static bool filenameIsRel(const string& filename) VL_PURE; diff --git a/src/V3Param.cpp b/src/V3Param.cpp index e5b3d1b6b..fe580f853 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -21,6 +21,7 @@ // (Interfaces also matter, as if a module is parameterized // this effectively changes the width behavior of all that // reference the iface.) +// // Clone module cell calls, renaming with __{par1}_{par2}_... // Substitute constants for cell's module's parameters. // Relink pins and cell and ifacerefdtype to point to new module. @@ -65,7 +66,7 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### -// Hierarchical block and parameter db (modules without parameter is also handled) +// Hierarchical block and parameter db (modules without parameters are also handled) class ParameterizedHierBlocks final { using HierBlockOptsByOrigName = std::multimap; @@ -200,7 +201,7 @@ public: varNum.opIToRD(pinValuep->num()); var = varNum.toDouble(); } - return v3EpsilonEqual(var, hierOptParamp->num().toDouble()); + return V3Number::epsilonEqual(var, hierOptParamp->num().toDouble()); } else { // Now integer type is assumed // Bitwidth of hierOptParamp is accurate because V3Width already calculated in the // previous run. Bitwidth of pinValuep is before width analysis, so pinValuep is casted @@ -231,10 +232,10 @@ class ParamProcessor final { // // (0=not processed, 1=iterated, but no number, // // 65+ parameter numbered) // NODE STATE - Shared with ParamVisitor - // AstClass::user3p() // AstClass* Unchanged copy of the parameterized class node. - // The class node may be modified according to parameter - // values and an unchanged copy is needed to instantiate - // classes with different parameters. + // AstNodeModule::user3p() // AstNodeModule* Unaltered copy of the parameterized module. + // The module/class node may be modified according to parameter + // values and an unchanged copy is needed to instantiate + // modules/classes with different parameters. // AstNodeModule::user2() // bool True if processed // AstGenFor::user2() // bool True if processed // AstVar::user2() // bool True if constant propagated @@ -347,7 +348,24 @@ class ParamProcessor final { if (dtypep->isRanged()) { key += "[" + cvtToStr(dtypep->left()) + ":" + cvtToStr(dtypep->right()) + "]"; } + } else if (const AstPackArrayDType* const dtypep = VN_CAST(nodep, PackArrayDType)) { + key += "["; + key += cvtToStr(dtypep->left()); + key += ":"; + key += cvtToStr(dtypep->right()); + key += "] "; + key += paramValueString(dtypep->subDTypep()); + } else if (const AstInitArray* const initp = VN_CAST(nodep, InitArray)) { + key += "{"; + for (auto it : initp->map()) { + key += paramValueString(it.second->valuep()); + key += ","; + } + key += "}"; + } else if (const AstNodeDType* const dtypep = VN_CAST(nodep, NodeDType)) { + key += dtypep->prettyDTypeName(true); } + UASSERT_OBJ(!key.empty(), nodep, "Parameter yielded no value string"); return key; } @@ -750,7 +768,8 @@ class ParamProcessor final { } } } else if (AstParamTypeDType* const modvarp = pinp->modPTypep()) { - AstNodeDType* const exprp = VN_CAST(pinp->exprp(), NodeDType); + AstNodeDType* rawTypep = VN_CAST(pinp->exprp(), NodeDType); + AstNodeDType* const exprp = rawTypep ? rawTypep->skipRefToEnump() : nullptr; const AstNodeDType* const origp = modvarp->skipRefToEnump(); if (!exprp) { pinp->v3error("Parameter type pin value isn't a type: Param " @@ -962,7 +981,9 @@ public: if (debug() >= 10) nodep->dumpTree("- cell: "); // Evaluate all module constants V3Const::constifyParamsEdit(nodep); - srcModpr->someInstanceName(someInstanceName + "." + nodep->name()); + // Set name for warnings for when we param propagate the module + const string instanceName = someInstanceName + "." + nodep->name(); + srcModpr->someInstanceName(instanceName); if (auto* cellp = VN_CAST(nodep, Cell)) { cellDeparam(cellp, srcModpr); @@ -976,6 +997,9 @@ public: nodep->v3fatalSrc("Expected module parameterization"); } + // Set name for later warnings (if srcModpr changed value due to cloning) + srcModpr->someInstanceName(instanceName); + UINFO(8, " Done with " << nodep << endl); // if (debug() >= 10) // v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("param-out.tree")); @@ -1070,7 +1094,7 @@ class ParamVisitor final : public VNVisitor { UASSERT_OBJ(srcModp, cellp, "Unlinked class ref"); // Update path - string someInstanceName(modp->someInstanceName()); + string someInstanceName = modp->someInstanceName(); if (const string* const genHierNamep = cellp->user2u().to()) { someInstanceName += *genHierNamep; cellp->user2p(nullptr); diff --git a/src/V3Param.h b/src/V3Param.h index f042f788d..0d0c832d0 100644 --- a/src/V3Param.h +++ b/src/V3Param.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Parse.h b/src/V3Parse.h index 3b2457ec1..767467702 100644 --- a/src/V3Parse.h +++ b/src/V3Parse.h @@ -22,7 +22,6 @@ #include "V3Error.h" #include "V3Global.h" -#include "V3ThreadSafety.h" class AstNetlist; class VInFilter; diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp index 5938335eb..6451ba514 100644 --- a/src/V3ParseGrammar.cpp +++ b/src/V3ParseGrammar.cpp @@ -128,6 +128,23 @@ AstRange* V3ParseGrammar::scrubRange(AstNodeRange* nrangep) { return VN_CAST(nrangep, Range); } +AstNodePreSel* V3ParseGrammar::scrubSel(AstNodeExpr* fromp, AstNodePreSel* selp) VL_MT_DISABLED { + // SEL(PARSELVALUE, ...) -> SEL(fromp, ...) + AstNodePreSel* subSelp = selp; + while (true) { + if (VN_IS(subSelp->fromp(), ParseHolder)) break; + if (AstNodePreSel* const lowerSelp = VN_CAST(subSelp->fromp(), NodePreSel)) { + subSelp = lowerSelp; + continue; + } + subSelp->v3fatalSrc("Couldn't find where to insert expression into select"); + } + AstNode* subSelFromp = subSelp->fromp(); + subSelFromp->replaceWith(fromp); + VL_DO_DANGLING(subSelFromp->deleteTree(), subSelFromp); + return selp; +} + AstNodeDType* V3ParseGrammar::createArray(AstNodeDType* basep, AstNodeRange* nrangep, bool isPacked) { // Split RANGE0-RANGE1-RANGE2 @@ -226,8 +243,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name, nodep->ansi(m_pinAnsi); nodep->declTyped(m_varDeclTyped); nodep->lifetime(m_varLifetime); - nodep->delayp(m_netDelayp); - m_netDelayp = nullptr; + nodep->delayp(getNetDelay()); if (GRAMMARP->m_varDecl != VVarType::UNKNOWN) nodep->combineType(GRAMMARP->m_varDecl); if (GRAMMARP->m_varIO != VDirection::NONE) { nodep->declDirection(GRAMMARP->m_varIO); diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp index ea60f2061..1a8076be4 100644 --- a/src/V3ParseImp.cpp +++ b/src/V3ParseImp.cpp @@ -447,6 +447,20 @@ size_t V3ParseImp::tokenPipeScanTypeEq(size_t depth) { return depth; } +int V3ParseImp::tokenPipelineId(int token) { + const V3ParseBisonYYSType* nexttokp = tokenPeekp(0); // First char after yaID + const int nexttok = nexttokp->token; + UASSERT(yylval.token == yaID__LEX, "Start with ID"); + if (nexttok == yP_COLONCOLON) { return yaID__CC; } + VL_RESTORER(yylval); // Remember value, as about to read ahead + if (nexttok == '#') { + VL_RESTORER(yylval); // Remember value, as about to read ahead + const size_t depth = tokenPipeScanParam(0); + if (tokenPeekp(depth)->token == yP_COLONCOLON) return yaID__CC; + } + return token; +} + void V3ParseImp::tokenPipeline() { // called from bison's "yylex", has a "this" if (m_tokensAhead.empty()) tokenPull(); // corrupts yylval @@ -552,13 +566,7 @@ void V3ParseImp::tokenPipeline() { token = yWITH__ETC; } } else if (token == yaID__LEX) { - if (nexttok == yP_COLONCOLON) { - token = yaID__CC; - } else if (nexttok == '#') { - VL_RESTORER(yylval); // Remember value, as about to read ahead - const size_t depth = tokenPipeScanParam(0); - if (tokenPeekp(depth)->token == yP_COLONCOLON) token = yaID__CC; - } + token = tokenPipelineId(token); } // If add to above "else if", also add to "if (token" further above } @@ -656,7 +664,8 @@ int V3ParseImp::tokenToBison() { m_bisonLastFileline = yylval.fl; // yylval.scp = nullptr; // Symbol table not yet needed - no packages - if (debugFlex() >= 6 || debugBison() >= 6) { // --debugi-flex and --debugi-bison + if (debug() >= 6 || debugFlex() >= 6 + || debugBison() >= 6) { // --debugi-flex and --debugi-bison cout << "tokenToBison " << yylval << endl; } return yylval.token; diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h index 4514dbc31..d54b714c9 100644 --- a/src/V3ParseImp.h +++ b/src/V3ParseImp.h @@ -25,7 +25,6 @@ #include "V3Global.h" #include "V3Parse.h" #include "V3ParseSym.h" -#include "V3ThreadSafety.h" #include #include @@ -75,11 +74,19 @@ struct VMemberQualifiers final { if (m_static) nodep->isStatic(true); if (m_virtual) nodep->isVirtual(true); if (m_const || m_rand || m_randc) { - nodep->v3error("Syntax error: 'const'/'rand'/'randc' not allowed before " - "function/task declaration"); + nodep->v3error("Syntax error: 'const'/'rand'/'randc' not allowed " + "before function/task declaration"); } } } + void applyToNodes(AstTypedef* nodep) const { + if (m_local) nodep->isHideLocal(true); + if (m_protected) nodep->isHideProtected(true); + if (m_static || m_virtual || m_rand || m_randc) { + nodep->v3error("Syntax error: 'static'/'virtual'/'rand'/'randc' not allowed " + "before typedef declaration"); + } + } void applyToNodes(AstVar* nodesp) const { for (AstVar* nodep = nodesp; nodep; nodep = VN_AS(nodep->nextp(), Var)) { if (m_rand) nodep->rand(VRandAttr::RAND); @@ -303,6 +310,7 @@ private: void yylexReadTok() VL_MT_DISABLED; void tokenPull() VL_MT_DISABLED; void tokenPipeline() VL_MT_DISABLED; // Internal; called from tokenToBison + int tokenPipelineId(int token) VL_MT_DISABLED; void tokenPipelineSym() VL_MT_DISABLED; size_t tokenPipeScanParam(size_t depth) VL_MT_DISABLED; size_t tokenPipeScanTypeEq(size_t depth) VL_MT_DISABLED; diff --git a/src/V3PchAstMT.h b/src/V3PchAstMT.h index c49e2a546..552c0f452 100644 --- a/src/V3PchAstMT.h +++ b/src/V3PchAstMT.h @@ -35,7 +35,6 @@ #include "V3Options.h" #include "V3StdFuture.h" #include "V3String.h" -#include "V3ThreadSafety.h" #include diff --git a/src/V3PchAstNoMT.h b/src/V3PchAstNoMT.h index 5d158864d..0971316ce 100644 --- a/src/V3PchAstNoMT.h +++ b/src/V3PchAstNoMT.h @@ -37,7 +37,6 @@ #include "V3Options.h" #include "V3StdFuture.h" #include "V3String.h" -#include "V3ThreadSafety.h" #include #include diff --git a/src/V3PreProc.h b/src/V3PreProc.h index f623c0237..2560ce9bd 100644 --- a/src/V3PreProc.h +++ b/src/V3PreProc.h @@ -23,7 +23,6 @@ #include "V3Error.h" #include "V3FileLine.h" #include "V3Global.h" -#include "V3ThreadSafety.h" #include #include diff --git a/src/V3PreShell.cpp b/src/V3PreShell.cpp index 6a1372b59..2b02b658d 100644 --- a/src/V3PreShell.cpp +++ b/src/V3PreShell.cpp @@ -87,7 +87,7 @@ protected: bool preproc(FileLine* fl, const string& modname, VInFilter* filterp, V3ParseImp* parsep, const string& errmsg) { // "" for no error // Preprocess the given module, putting output in vppFilename - UINFONL(1, " Preprocessing " << modname << endl); + UINFO(1, "Preprocessing " << modname << endl); // Preprocess s_filterp = filterp; diff --git a/src/V3PreShell.h b/src/V3PreShell.h index f34b65801..7c15e43fd 100644 --- a/src/V3PreShell.h +++ b/src/V3PreShell.h @@ -22,7 +22,6 @@ #include "V3Error.h" #include "V3FileLine.h" -#include "V3ThreadSafety.h" class V3ParseImp; class VInFilter; diff --git a/src/V3Premit.h b/src/V3Premit.h index ac4c19ac0..82388168f 100644 --- a/src/V3Premit.h +++ b/src/V3Premit.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3ProtectLib.h b/src/V3ProtectLib.h index 5fe6e4b3c..4d4cfe04e 100644 --- a/src/V3ProtectLib.h +++ b/src/V3ProtectLib.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - //============================================================================ class V3ProtectLib final { diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index 4891ef279..49ef24aff 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -122,6 +122,7 @@ class RandomizeMarkVisitor final : public VNVisitor { // randomized variable // AstVar::user1() -> bool. Set true to indicate needs rand_mode // AstVar::user2p() -> AstNodeModule*. Pointer to containing module + // AstNodeFTask::user2p() -> AstNodeModule*. Pointer to containing module const VNUser1InUse m_inuser1; const VNUser2InUse m_inuser2; @@ -144,8 +145,14 @@ class RandomizeMarkVisitor final : public VNVisitor { if (!varp) continue; // If member is randomizable and of class type, mark its class if (varp->rand().isRandomizable()) { - if (const AstClassRefDType* const classRefp - = VN_CAST(varp->dtypep()->skipRefp(), ClassRefDType)) { + const AstNodeDType* const varDtypep = varp->dtypep()->skipRefp(); + const AstClassRefDType* classRefp = VN_CAST(varDtypep, ClassRefDType); + if (!classRefp) { + const AstNodeDType* subDTypep = varDtypep->subDTypep(); + if (subDTypep) subDTypep = subDTypep->skipRefp(); + classRefp = VN_CAST(subDTypep, ClassRefDType); + } + if (classRefp) { AstClass* const rclassp = classRefp->classp(); if (!rclassp->user1()) { rclassp->user1(IS_RANDOMIZED); @@ -223,7 +230,7 @@ class RandomizeMarkVisitor final : public VNVisitor { nodep->v3error("Cannot call 'rand_mode()' on packed array element"); valid = false; } else if (AstCMethodHard* const methodHardp = VN_CAST(fromp, CMethodHard)) { - if (methodHardp->name() == "at" && VN_IS(fromp, CMethodHard)) { + if (methodHardp->name() == "at" || methodHardp->name() == "atWrite") { nodep->v3warn(E_UNSUPPORTED, "Unsupported: 'rand_mode()' on dynamic array element"); valid = false; @@ -427,11 +434,22 @@ class RandomizeMarkVisitor final : public VNVisitor { backp->user1(true); } } + void visit(AstArraySel* nodep) override { + if (!m_constraintExprp) return; + for (AstNode* backp = nodep; backp != m_constraintExprp && !backp->user1(); + backp = backp->backp()) + backp->user1(true); + iterateChildrenConst(nodep); + } void visit(AstNodeModule* nodep) override { VL_RESTORER(m_modp); m_modp = nodep; iterateChildrenConst(nodep); } + void visit(AstNodeFTask* nodep) override { + nodep->user2p(m_modp); + iterateChildrenConst(nodep); + } void visit(AstVar* nodep) override { nodep->user2p(m_modp); iterateChildrenConst(nodep); @@ -546,12 +564,27 @@ class ConstraintExprVisitor final : public VNVisitor { if (!exprsp->nextp()) return exprsp; std::ostringstream fmt; - fmt << "(and"; + fmt << "(bvand"; for (AstNode* itemp = exprsp; itemp; itemp = itemp->nextp()) fmt << " %@"; fmt << ')'; return new AstSFormatF{fl, fmt.str(), false, exprsp}; } + AstNodeExpr* newSel(FileLine* fl, AstNodeExpr* arrayp, AstNodeExpr* idxp) { + // similar to V3WidthSel.cpp + AstNodeDType* const arrDtp = arrayp->unlinkFrBack()->dtypep(); + AstNodeExpr* selp = nullptr; + if (VN_IS(arrDtp, QueueDType) || VN_IS(arrDtp, DynArrayDType)) + selp = new AstCMethodHard{fl, arrayp, "at", idxp}; + else if (VN_IS(arrDtp, UnpackArrayDType)) + selp = new AstArraySel{fl, arrayp, idxp}; + else if (VN_IS(arrDtp, AssocArrayDType)) + selp = new AstAssocSel{fl, arrayp, idxp}; + UASSERT_OBJ(selp, arrayp, "Selecting from non-array?"); + selp->dtypep(arrDtp->subDTypep()); + return selp; + } + // VISITORS void visit(AstNodeVarRef* nodep) override { AstVar* const varp = nodep->varp(); @@ -584,18 +617,30 @@ class ConstraintExprVisitor final : public VNVisitor { new AstVarRef{varp->fileline(), VN_AS(m_genp->user2p(), NodeModule), m_genp, VAccess::READWRITE}, "write_var"}; + uint32_t dimension = 0; + if (VN_IS(varp->dtypep(), UnpackArrayDType)) { + const std::pair dims + = varp->dtypep()->dimensions(/*includeBasic=*/true); + const uint32_t unpackedDimensions = dims.second; + dimension = unpackedDimensions; + } methodp->dtypeSetVoid(); AstClass* const classp = VN_AS(varp->user2p(), Class); AstVarRef* const varRefp = new AstVarRef{varp->fileline(), classp, varp, VAccess::WRITE}; varRefp->classOrPackagep(classOrPackagep); methodp->addPinsp(varRefp); - methodp->addPinsp(new AstConst{varp->dtypep()->fileline(), AstConst::Unsized64{}, - (size_t)varp->width()}); + size_t width = varp->width(); + if (VN_IS(varp->dtypep(), DynArrayDType) || VN_IS(varp->dtypep(), QueueDType)) + width = varp->dtypep()->subDTypep()->width(); + methodp->addPinsp( + new AstConst{varp->dtypep()->fileline(), AstConst::Unsized64{}, width}); AstNodeExpr* const varnamep = new AstCExpr{varp->fileline(), "\"" + smtName + "\"", varp->width()}; varnamep->dtypep(varp->dtypep()); methodp->addPinsp(varnamep); + methodp->addPinsp( + new AstConst{varp->dtypep()->fileline(), AstConst::Unsized64{}, dimension}); if (randMode.usesMode) { methodp->addPinsp( new AstConst{varp->fileline(), AstConst::Unsized64{}, randMode.index}); @@ -632,11 +677,6 @@ class ConstraintExprVisitor final : public VNVisitor { // Fall back to "(ite cond then else)" visit(static_cast(nodep)); } - void visit(AstDist* nodep) override { - nodep->v3warn(CONSTRAINTIGN, "Constraint expression ignored (unsupported)"); - nodep->replaceWith(new AstSFormatF{nodep->fileline(), "true", false, nullptr}); - VL_DO_DANGLING(nodep->deleteTree(), nodep); - } void visit(AstReplicate* nodep) override { // Biop, but RHS is harmful if (editFormat(nodep)) return; @@ -658,6 +698,15 @@ class ConstraintExprVisitor final : public VNVisitor { editSMT(nodep, nodep->fromp(), lsbp, msbp); } + void visit(AstArraySel* nodep) override { + if (editFormat(nodep)) return; + FileLine* const fl = nodep->fileline(); + VNRelinker handle; + AstNodeExpr* const indexp + = new AstSFormatF{fl, "#x%8x", false, nodep->bitp()->unlinkFrBack(&handle)}; + handle.relink(indexp); + editSMT(nodep, nodep->fromp(), indexp); + } void visit(AstSFormatF* nodep) override {} void visit(AstStmtExpr* nodep) override {} void visit(AstConstraintIf* nodep) override { @@ -680,7 +729,7 @@ class ConstraintExprVisitor final : public VNVisitor { } VL_DO_DANGLING(nodep->deleteTree(), nodep); } - void visit(AstForeach* nodep) override {} + void visit(AstBegin* nodep) override {} void visit(AstConstraintForeach* nodep) override { // Convert to plain foreach FileLine* const fl = nodep->fileline(); @@ -690,24 +739,28 @@ class ConstraintExprVisitor final : public VNVisitor { AstNode* const cstmtp = new AstText{fl, "ret += \" \" + "}; cstmtp->addNext(itemp); cstmtp->addNext(new AstText{fl, ";"}); - AstNode* const exprsp = new AstText{fl, "([&]{ std::string ret = \"(and\";"}; + AstNode* const exprsp = new AstText{fl, "([&]{ std::string ret;"}; exprsp->addNext(new AstBegin{ fl, "", new AstForeach{fl, nodep->arrayp()->unlinkFrBack(), new AstCStmt{fl, cstmtp}}, false, true}); - exprsp->addNext(new AstText{fl, "return ret + \")\"; })()"}); + exprsp->addNext( + new AstText{fl, "return ret.empty() ? \"#b1\" : \"(bvand\" + ret + \")\";})()"}); AstNodeExpr* const newp = new AstCExpr{fl, exprsp}; newp->dtypeSetString(); nodep->replaceWith(new AstSFormatF{fl, "%@", false, newp}); } else { iterateAndNextNull(nodep->stmtsp()); - nodep->replaceWith(new AstForeach{fl, nodep->arrayp()->unlinkFrBack(), - nodep->stmtsp()->unlinkFrBackWithNext()}); + nodep->replaceWith( + new AstBegin{fl, "", + new AstForeach{fl, nodep->arrayp()->unlinkFrBack(), + nodep->stmtsp()->unlinkFrBackWithNext()}, + false, true}); } VL_DO_DANGLING(nodep->deleteTree(), nodep); } void visit(AstConstraintBefore* nodep) override { - nodep->v3warn(CONSTRAINTIGN, "Constraint expression ignored (unsupported)"); + nodep->v3warn(CONSTRAINTIGN, "Constraint expression ignored (imperfect distribution)"); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } void visit(AstConstraintUnique* nodep) override { @@ -733,19 +786,51 @@ class ConstraintExprVisitor final : public VNVisitor { } void visit(AstCMethodHard* nodep) override { if (editFormat(nodep)) return; + FileLine* const fl = nodep->fileline(); - UASSERT_OBJ(nodep->name() == "size", nodep, "Non-size method call in constraints"); + if (nodep->name() == "at" && nodep->fromp()->user1()) { + iterateChildren(nodep); + AstNodeExpr* const argsp + = AstNode::addNext(nodep->fromp()->unlinkFrBack(), nodep->pinsp()->unlinkFrBack()); + AstSFormatF* const newp = new AstSFormatF{fl, "(select %@ %@)", false, argsp}; + nodep->replaceWith(newp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + return; + } - AstNode* fromp = nodep->fromp(); - // Warn early while the dtype is still there - fromp->v3warn(E_UNSUPPORTED, "Unsupported: random member variable with type " - << fromp->dtypep()->prettyDTypeNameQ()); + if (nodep->name() == "inside") { + bool randArr = nodep->fromp()->user1(); - iterateChildren(nodep); // Might change fromp - fromp = nodep->fromp()->unlinkFrBack(); - fromp->dtypep(nodep->dtypep()); - nodep->replaceWith(fromp); - VL_DO_DANGLING(pushDeletep(nodep), nodep); + AstVar* const newVarp + = new AstVar{fl, VVarType::BLOCKTEMP, "__Vinside", nodep->findSigned32DType()}; + AstNodeExpr* const idxRefp = new AstVarRef{nodep->fileline(), newVarp, VAccess::READ}; + AstSelLoopVars* const arrayp + = new AstSelLoopVars{fl, nodep->fromp()->cloneTreePure(false), newVarp}; + AstNodeExpr* const selp = newSel(nodep->fileline(), nodep->fromp(), idxRefp); + selp->user1(randArr); + AstNode* const itemp = new AstEq{fl, selp, nodep->pinsp()->unlinkFrBack()}; + itemp->user1(true); + AstNode* const cstmtp = new AstText{fl, "ret += \" \" + "}; + cstmtp->addNext(iterateSubtreeReturnEdits(itemp)); + cstmtp->addNext(new AstText{fl, ";"}); + AstNode* const exprsp = new AstText{fl, "([&]{ std::string ret;"}; + exprsp->addNext(new AstBegin{ + fl, "", new AstForeach{fl, arrayp, new AstCStmt{fl, cstmtp}}, false, true}); + exprsp->addNext( + new AstText{fl, "return ret.empty() ? \"#b0\" : \"(bvor\" + ret + \")\";})()"}); + AstNodeExpr* const newp = new AstCExpr{fl, exprsp}; + newp->dtypeSetString(); + nodep->replaceWith(new AstSFormatF{fl, "%@", false, newp}); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + return; + } + + nodep->v3warn(CONSTRAINTIGN, + "Unsupported: randomizing this expression, treating as state"); + nodep->user1(false); + + if (editFormat(nodep)) return; + nodep->v3fatalSrc("Method not handled in constraints? " << nodep); } void visit(AstNodeExpr* nodep) override { if (editFormat(nodep)) return; @@ -770,63 +855,6 @@ public: } }; -class ClassLookupHelper final { - std::set m_visibleModules; // Modules directly reachable from our lookup point - std::map - m_classMap; // Memoized mapping between nodes and modules that define them - - // BFS search - template - static void foreachSuperClass(AstClass* classp, Action action) { - std::queue classes; - classes.push(classp); - while (!classes.empty()) { - classp = classes.front(); - classes.pop(); - for (AstClassExtends* extendsp = classp->extendsp(); extendsp; - extendsp = VN_AS(extendsp->nextp(), ClassExtends)) { - AstClass* const superClassp - = VN_AS(extendsp->childDTypep(), ClassRefDType)->classp(); - action(superClassp); - classes.push(superClassp); - } - } - } - - static std::set initVisibleModules(AstClass* classp) { - std::set visibleModules = {classp}; - std::vector symLookupOrder = {classp}; - foreachSuperClass(classp, - [&](AstClass* superclassp) { visibleModules.emplace(superclassp); }); - return visibleModules; - } - -public: - bool moduleInClassHierarchy(AstNodeModule* modp) const { - return m_visibleModules.count(modp) != 0; - } - - AstNodeModule* findDeclaringModule(AstNode* nodep, bool classHierarchyOnly = true) { - auto it = m_classMap.find(nodep); - if (it != m_classMap.end()) return it->second; - for (AstNode* backp = nodep; backp; backp = backp->backp()) { - AstNodeModule* const modp = VN_CAST(backp, NodeModule); - if (modp) { - m_classMap.emplace(nodep, modp); - if (classHierarchyOnly) - UASSERT_OBJ(moduleInClassHierarchy(modp), nodep, - "Node does not belong to class"); - return modp; - } - } - return nullptr; - } - - ClassLookupHelper(AstClass* classp) { - if (classp) m_visibleModules = initVisibleModules(classp); - } -}; - enum class CaptureMode : uint8_t { CAP_NO = 0x0, CAP_VALUE = 0x01, @@ -852,7 +880,6 @@ class CaptureVisitor final : public VNVisitor { AstClass* m_targetp; // Module of inner context (for symbol lookup) std::map m_varCloneMap; // Map original var nodes to their clones std::set m_ignore; // Nodes to ignore for capturing - ClassLookupHelper m_lookup; // Util for class lookup AstVar* m_thisp = nullptr; // Variable for outer context's object, if necessary // METHODS @@ -877,7 +904,7 @@ class CaptureVisitor final : public VNVisitor { template void fixupClassOrPackage(AstNode* memberp, NodeT refp) { - AstNodeModule* const declClassp = m_lookup.findDeclaringModule(memberp, false); + AstNodeModule* const declClassp = VN_AS(memberp->user2p(), NodeModule); if (declClassp != m_targetp) refp->classOrPackagep(declClassp); } @@ -907,20 +934,25 @@ class CaptureVisitor final : public VNVisitor { } CaptureMode getVarRefCaptureMode(AstNodeVarRef* varRefp) { - AstNodeModule* const modp = m_lookup.findDeclaringModule(varRefp->varp(), false); + AstNodeModule* const varModp = VN_AS(varRefp->varp()->user2p(), NodeModule); + AstClass* const varClassp = VN_CAST(varModp, Class); + AstClass* const callerClassp = VN_CAST(m_callerp, Class); - const bool callerIsClass = VN_IS(m_callerp, Class); + const bool callerIsClass = callerClassp; const bool refIsXref = VN_IS(varRefp, VarXRef); const bool varIsFuncLocal = varRefp->varp()->isFuncLocal(); const bool varHasAutomaticLifetime = varRefp->varp()->lifetime().isAutomatic(); - const bool varIsDeclaredInCaller = modp == m_callerp; - const bool varIsFieldOfCaller = modp ? m_lookup.moduleInClassHierarchy(modp) : false; - + const bool varIsFieldOfCaller = AstClass::isClassExtendedFrom(callerClassp, varClassp); + const bool varIsParam = varRefp->varp()->isParam(); + const bool varIsConstraintIterator + = VN_IS(varRefp->varp()->firstAbovep(), SelLoopVars) + && VN_IS(varRefp->varp()->firstAbovep()->firstAbovep(), ConstraintForeach); if (refIsXref) return CaptureMode::CAP_VALUE | CaptureMode::CAP_F_XREF; + if (varIsConstraintIterator) return CaptureMode::CAP_NO; if (varIsFuncLocal && varHasAutomaticLifetime) return CaptureMode::CAP_VALUE; + if (varIsParam) return CaptureMode::CAP_VALUE; // Static var in function (will not be inlined, because it's in class) if (callerIsClass && varIsFuncLocal) return CaptureMode::CAP_VALUE; - if (callerIsClass && varIsDeclaredInCaller) return CaptureMode::CAP_THIS; if (callerIsClass && varIsFieldOfCaller) return CaptureMode::CAP_THIS; UASSERT_OBJ(!callerIsClass, varRefp, "Invalid reference?"); return CaptureMode::CAP_VALUE; @@ -983,7 +1015,7 @@ class CaptureVisitor final : public VNVisitor { iterateChildren(nodep); return; } - AstClass* classp = VN_CAST(m_lookup.findDeclaringModule(nodep->taskp(), false), Class); + AstClass* classp = VN_CAST(nodep->taskp()->user2p(), Class); if ((classp == m_callerp) && VN_IS(m_callerp, Class)) { AstNodeExpr* const pinsp = nodep->pinsp(); if (pinsp) pinsp->unlinkFrBack(); @@ -1040,8 +1072,7 @@ public: explicit CaptureVisitor(AstNode* const nodep, AstNodeModule* callerp, AstClass* const targetp) : m_argsp(nullptr) , m_callerp(callerp) - , m_targetp(targetp) - , m_lookup(VN_CAST(callerp, Class)) { + , m_targetp(targetp) { iterateAndNextNull(nodep); } @@ -1072,7 +1103,8 @@ class RandomizeVisitor final : public VNVisitor { // NODE STATE // Cleared on Netlist // AstClass::user1() -> bool. Set true to indicate needs randomize processing - // AstVar::user2p() -> AstClass*. Pointer to containing class + // AstVar::user2p() -> AstNodeModule*. Pointer to containing module + // AstNodeFTask::user2p() -> AstNodeModule*. Pointer to containing module // AstEnumDType::user2() -> AstVar*. Pointer to table with enum values // AstConstraint::user2p() -> AstTask*. Pointer to constraint setup procedure // AstClass::user2p() -> AstVar*. Rand mode state variable @@ -1244,27 +1276,28 @@ class RandomizeVisitor final : public VNVisitor { iterVarp->lifetime(VLifetime::AUTOMATIC); AstCMethodHard* const sizep = new AstCMethodHard{fl, lhsp, "size", nullptr}; sizep->dtypeSetUInt32(); - AstCMethodHard* const atp = new AstCMethodHard{fl, lhsp->cloneTree(false), "at", - new AstVarRef{fl, iterVarp, VAccess::READ}}; - atp->dtypeSetUInt32(); + AstCMethodHard* const setp = new AstCMethodHard{ + fl, lhsp->cloneTree(false), "atWrite", new AstVarRef{fl, iterVarp, VAccess::READ}}; + setp->dtypeSetUInt32(); AstNode* const stmtsp = iterVarp; stmtsp->addNext( new AstAssign{fl, new AstVarRef{fl, iterVarp, VAccess::WRITE}, new AstConst{fl, 0}}); stmtsp->addNext( new AstWhile{fl, new AstLt{fl, new AstVarRef{fl, iterVarp, VAccess::READ}, sizep}, - new AstAssign{fl, atp, rhsp}, + new AstAssign{fl, setp, rhsp}, new AstAssign{fl, new AstVarRef{fl, iterVarp, VAccess::WRITE}, new AstAdd{fl, new AstConst{fl, 1}, new AstVarRef{fl, iterVarp, VAccess::READ}}}}); return new AstBegin{fl, "", stmtsp, false, true}; } static AstNodeStmt* wrapIfRandMode(AstClass* classp, AstVar* const varp, AstNodeStmt* stmtp) { - return VN_AS(wrapIfMode({.asInt = varp->user1()}, getRandModeVar(classp), stmtp), - NodeStmt); + const RandomizeMode rmode = {.asInt = varp->user1()}; + return VN_AS(wrapIfMode(rmode, getRandModeVar(classp), stmtp), NodeStmt); } static AstNode* wrapIfConstraintMode(AstClass* classp, AstConstraint* const constrp, AstNode* stmtp) { - return wrapIfMode({.asInt = constrp->user1()}, getConstraintModeVar(classp), stmtp); + const RandomizeMode rmode = {.asInt = constrp->user1()}; + return wrapIfMode(rmode, getConstraintModeVar(classp), stmtp); } static AstNode* wrapIfMode(const RandomizeMode mode, AstVar* modeVarp, AstNode* stmtp) { FileLine* const fl = stmtp->fileline(); @@ -1346,11 +1379,66 @@ class RandomizeVisitor final : public VNVisitor { UINFO(9, "created " << varp << endl); return newp; } - AstNodeStmt* newRandStmtsp(FileLine* fl, AstNodeExpr* exprp, AstVar* randcVarp, int offset = 0, + AstNodeStmt* createArrayForeachLoop(FileLine* const fl, AstNodeDType* const dtypep, + AstNodeExpr* exprp, AstVar* const outputVarp) { + V3UniqueNames* uniqueNamep = new V3UniqueNames{"__Vrandarr"}; + AstNodeDType* tempDTypep = dtypep; + AstVar* randLoopIndxp = nullptr; + AstNodeStmt* stmtsp = nullptr; + auto createLoopIndex = [&](AstNodeDType* tempDTypep) { + if (VN_IS(tempDTypep, AssocArrayDType)) { + return new AstVar{ + fl, VVarType::VAR, uniqueNamep->get(""), + dtypep->findBasicDType( + ((AstBasicDType*)VN_AS(tempDTypep, AssocArrayDType)->keyDTypep()) + ->keyword())}; + } + return new AstVar{fl, VVarType::VAR, uniqueNamep->get(""), + dtypep->findBasicDType(VBasicDTypeKwd::UINT32)}; + }; + auto createForeachLoop = [&](AstNodeExpr* tempElementp, AstVar* randLoopIndxp) { + AstSelLoopVars* const randLoopVarp + = new AstSelLoopVars{fl, exprp->cloneTree(false), randLoopIndxp}; + return new AstForeach{fl, randLoopVarp, + newRandStmtsp(fl, tempElementp, nullptr, outputVarp)}; + }; + AstNodeExpr* tempElementp = nullptr; + while (VN_IS(tempDTypep, DynArrayDType) || VN_IS(tempDTypep, UnpackArrayDType) + || VN_IS(tempDTypep, AssocArrayDType) || VN_IS(tempDTypep, QueueDType)) { + AstVar* const newRandLoopIndxp = createLoopIndex(tempDTypep); + randLoopIndxp = AstNode::addNext(randLoopIndxp, newRandLoopIndxp); + AstNodeExpr* tempExprp = tempElementp ? tempElementp : exprp; + AstVarRef* tempRefp = new AstVarRef{fl, newRandLoopIndxp, VAccess::READ}; + if (VN_IS(tempDTypep, DynArrayDType)) + tempElementp = new AstCMethodHard{fl, tempExprp, "atWrite", tempRefp}; + else if (VN_IS(tempDTypep, UnpackArrayDType)) { + AstNodeArrayDType* const aryDTypep = VN_CAST(tempDTypep, NodeArrayDType); + // Adjust the bitp to ensure it covers all possible indices + tempElementp = new AstArraySel{ + fl, tempExprp, + new AstSel{ + fl, + new AstSub{fl, tempRefp, + new AstConst{fl, static_cast(aryDTypep->lo())}}, + new AstConst{fl, 0}, + new AstConst{ + fl, static_cast(V3Number::log2b(aryDTypep->hi()) + 1)}}}; + } else if (VN_IS(tempDTypep, AssocArrayDType)) + tempElementp = new AstAssocSel{fl, tempExprp, tempRefp}; + else if (VN_IS(tempDTypep, QueueDType)) + tempElementp = new AstCMethodHard{fl, tempExprp, "atWriteAppend", tempRefp}; + tempElementp->dtypep(tempDTypep->subDTypep()); + tempDTypep = tempDTypep->virtRefDTypep(); + } + stmtsp = createForeachLoop(tempElementp, randLoopIndxp); + return stmtsp; + } + AstNodeStmt* newRandStmtsp(FileLine* fl, AstNodeExpr* exprp, AstVar* randcVarp, + AstVar* const outputVarp, int offset = 0, AstMemberDType* memberp = nullptr) { - if (const auto* const structDtp - = VN_CAST(memberp ? memberp->subDTypep()->skipRefp() : exprp->dtypep()->skipRefp(), - StructDType)) { + AstNodeDType* const memberDtp + = memberp ? memberp->subDTypep()->skipRefp() : exprp->dtypep()->skipRefp(); + if (const auto* const structDtp = VN_CAST(memberDtp, StructDType)) { AstNodeStmt* stmtsp = nullptr; if (structDtp->packed()) offset += memberp ? memberp->lsb() : 0; for (AstMemberDType* smemberp = structDtp->membersp(); smemberp; @@ -1358,21 +1446,43 @@ class RandomizeVisitor final : public VNVisitor { AstNodeStmt* randp = nullptr; if (structDtp->packed()) { randp = newRandStmtsp(fl, stmtsp ? exprp->cloneTree(false) : exprp, nullptr, - offset, smemberp); + outputVarp, offset, smemberp); } else { AstStructSel* structSelp = new AstStructSel{fl, exprp->cloneTree(false), smemberp->name()}; structSelp->dtypep(smemberp->childDTypep()); if (!structSelp->dtypep()) structSelp->dtypep(smemberp->subDTypep()); - randp = newRandStmtsp(fl, structSelp, nullptr); - } - if (stmtsp) { - stmtsp->addNext(randp); - } else { - stmtsp = randp; + randp = newRandStmtsp(fl, structSelp, nullptr, outputVarp); } + stmtsp = stmtsp ? stmtsp->addNext(randp) : randp; } return stmtsp; + } else if (const auto* const unionDtp = VN_CAST(memberDtp, UnionDType)) { + if (!unionDtp->packed()) { + unionDtp->v3error("Unpacked unions shall not be declared as rand or randc." + " (IEEE 1800-2023 18.4)"); + return nullptr; + } + AstMemberDType* const firstMemberp = unionDtp->membersp(); + return newRandStmtsp(fl, exprp, nullptr, outputVarp, offset, firstMemberp); + } else if (const AstClassRefDType* const classRefDtp = VN_CAST(memberDtp, ClassRefDType)) { + AstFunc* const memberFuncp + = V3Randomize::newRandomizeFunc(m_memberMap, classRefDtp->classp()); + AstMethodCall* const callp = new AstMethodCall{fl, exprp, "randomize", nullptr}; + callp->taskp(memberFuncp); + callp->dtypeFrom(memberFuncp); + return new AstAssign{ + fl, new AstVarRef{fl, outputVarp, VAccess::WRITE}, + new AstAnd{fl, new AstVarRef{fl, outputVarp, VAccess::READ}, callp}}; + } else if (AstDynArrayDType* const dynarrayDtp = VN_CAST(memberDtp, DynArrayDType)) { + return createArrayForeachLoop(fl, dynarrayDtp, exprp, outputVarp); + } else if (AstQueueDType* const queueDtp = VN_CAST(memberDtp, QueueDType)) { + return createArrayForeachLoop(fl, queueDtp, exprp, outputVarp); + } else if (AstUnpackArrayDType* const unpackarrayDtp + = VN_CAST(memberDtp, UnpackArrayDType)) { + return createArrayForeachLoop(fl, unpackarrayDtp, exprp, outputVarp); + } else if (AstAssocArrayDType* const assocarrayDtp = VN_CAST(memberDtp, AssocArrayDType)) { + return createArrayForeachLoop(fl, assocarrayDtp, exprp, outputVarp); } else { AstNodeExpr* valp; if (AstEnumDType* const enumDtp = VN_CAST(memberp ? memberp->subDTypep()->subDTypep() @@ -1542,22 +1652,17 @@ class RandomizeVisitor final : public VNVisitor { const RandomizeMode randMode = {.asInt = memberVarp->user1()}; if (randMode.usesMode && !memberVarp->rand().isRand()) { // Not randomizable by default - AstCMethodHard* atp = new AstCMethodHard{ + AstCMethodHard* setp = new AstCMethodHard{ nodep->fileline(), new AstVarRef{fl, VN_AS(randModeVarp->user2p(), NodeModule), randModeVarp, VAccess::WRITE}, - "at", new AstConst{nodep->fileline(), randMode.index}}; - atp->dtypeSetUInt32(); - newp->addStmtsp(new AstAssign{fl, atp, new AstConst{fl, 0}}); + "atWrite", new AstConst{nodep->fileline(), randMode.index}}; + setp->dtypeSetUInt32(); + newp->addStmtsp(new AstAssign{fl, setp, new AstConst{fl, 0}}); } if (memberVarp->user3()) return; // Handled in constraints const AstNodeDType* const dtypep = memberVarp->dtypep()->skipRefp(); - if (VN_IS(dtypep, BasicDType) || VN_IS(dtypep, StructDType)) { - AstVar* const randcVarp = newRandcVarsp(memberVarp); - AstVarRef* const refp = new AstVarRef{fl, classp, memberVarp, VAccess::WRITE}; - AstNodeStmt* const stmtp = newRandStmtsp(fl, refp, randcVarp); - basicRandomizep->addStmtsp(stmtp); - } else if (const AstClassRefDType* const classRefp = VN_CAST(dtypep, ClassRefDType)) { + if (const AstClassRefDType* const classRefp = VN_CAST(dtypep, ClassRefDType)) { if (classRefp->classp() == nodep) { memberVarp->v3warn(E_UNSUPPORTED, "Unsupported: random member variable with the " @@ -1581,8 +1686,10 @@ class RandomizeVisitor final : public VNVisitor { new AstAnd{fl, basicFvarRefReadp, callp}}}; basicRandomizep->addStmtsp(wrapIfRandMode(nodep, memberVarp, assignIfNotNullp)); } else { - memberVarp->v3warn(E_UNSUPPORTED, "Unsupported: random member variable with type " - << memberVarp->dtypep()->prettyDTypeNameQ()); + AstVar* const randcVarp = newRandcVarsp(memberVarp); + AstVarRef* const refp = new AstVarRef{fl, classp, memberVarp, VAccess::WRITE}; + AstNodeStmt* const stmtp = newRandStmtsp(fl, refp, randcVarp, basicFvarp); + basicRandomizep->addStmtsp(new AstBegin{fl, "", stmtp}); } }); } @@ -1610,12 +1717,12 @@ class RandomizeVisitor final : public VNVisitor { if (receiverp) { // Called on a rand member variable/constraint. Set the variable/constraint's // mode - const RandomizeMode mode = {.asInt = receiverp->user1()}; - UASSERT_OBJ(mode.usesMode, ftaskRefp, "Failed to set usesMode"); - AstCMethodHard* const atp - = new AstCMethodHard{fl, lhsp, "at", new AstConst{fl, mode.index}}; - atp->dtypeSetUInt32(); - m_stmtp->replaceWith(new AstAssign{fl, atp, rhsp}); + const RandomizeMode rmode = {.asInt = receiverp->user1()}; + UASSERT_OBJ(rmode.usesMode, ftaskRefp, "Failed to set usesMode"); + AstCMethodHard* const setp + = new AstCMethodHard{fl, lhsp, "atWrite", new AstConst{fl, rmode.index}}; + setp->dtypeSetUInt32(); + m_stmtp->replaceWith(new AstAssign{fl, setp, rhsp}); } else { // For rand_mode: Called on 'this' or a non-rand class instance. // For constraint_mode: Called on a class instance. @@ -1625,12 +1732,12 @@ class RandomizeVisitor final : public VNVisitor { pushDeletep(m_stmtp); } else { UASSERT_OBJ(receiverp, ftaskRefp, "Should have receiver"); - const RandomizeMode mode = {.asInt = receiverp->user1()}; - UASSERT_OBJ(mode.usesMode, ftaskRefp, "Failed to set usesMode"); - AstCMethodHard* const atp - = new AstCMethodHard{fl, lhsp, "at", new AstConst{fl, mode.index}}; - atp->dtypeSetUInt32(); - ftaskRefp->replaceWith(atp); + const RandomizeMode rmode = {.asInt = receiverp->user1()}; + UASSERT_OBJ(rmode.usesMode, ftaskRefp, "Failed to set usesMode"); + AstCMethodHard* const setp + = new AstCMethodHard{fl, lhsp, "atWrite", new AstConst{fl, rmode.index}}; + setp->dtypeSetUInt32(); + ftaskRefp->replaceWith(setp); VL_DO_DANGLING(pushDeletep(ftaskRefp), ftaskRefp); } }; @@ -1696,12 +1803,12 @@ class RandomizeVisitor final : public VNVisitor { tmpVarps = AstNode::addNext(tmpVarps, randModeTmpVarp); } const RandomizeMode randMode = {.asInt = randVarp->user1()}; - AstCMethodHard* atp + AstCMethodHard* setp = new AstCMethodHard{fl, makeSiblingRefp(exprp, randModeVarp, VAccess::WRITE), - "at", new AstConst{fl, randMode.index}}; - atp->dtypeSetUInt32(); + "atWrite", new AstConst{fl, randMode.index}}; + setp->dtypeSetUInt32(); setStmtsp - = AstNode::addNext(setStmtsp, new AstAssign{fl, atp, new AstConst{fl, 1}}); + = AstNode::addNext(setStmtsp, new AstAssign{fl, setp, new AstConst{fl, 1}}); exprp = getFromp(exprp); } pinp->unlinkFrBack()->deleteTree(); @@ -1741,6 +1848,7 @@ class RandomizeVisitor final : public VNVisitor { iterateChildren(nodep); if (!nodep->user1()) return; // Doesn't need randomize, or already processed UINFO(9, "Define randomize() for " << nodep << endl); + nodep->baseMostClassp()->needRNG(true); AstFunc* const randomizep = V3Randomize::newRandomizeFunc(m_memberMap, nodep); AstVar* const fvarp = VN_AS(randomizep->fvarp(), Var); addPrePostCall(nodep, randomizep, "pre_randomize"); @@ -1959,6 +2067,8 @@ class RandomizeVisitor final : public VNVisitor { AstFunc* const randomizeFuncp = V3Randomize::newRandomizeFunc( m_memberMap, classp, m_inlineUniqueNames.get(nodep), false); + addPrePostCall(classp, randomizeFuncp, "pre_randomize"); + // Detach the expression and prepare variable copies const CaptureVisitor captured{withp->exprp(), m_modp, classp}; @@ -2016,6 +2126,8 @@ class RandomizeVisitor final : public VNVisitor { new AstVarRef{nodep->fileline(), VN_AS(randomizeFuncp->fvarp(), Var), VAccess::WRITE}, new AstAnd{nodep->fileline(), basicRandomizeFuncCallp, solverCallp}}); + addPrePostCall(classp, randomizeFuncp, "post_randomize"); + // Replace the node with a call to that function nodep->name(randomizeFuncp->name()); nodep->addPinsp(captured.getArgs()); @@ -2058,26 +2170,30 @@ void V3Randomize::randomizeNetlist(AstNetlist* nodep) { } AstFunc* V3Randomize::newRandomizeFunc(VMemberMap& memberMap, AstClass* nodep, - const std::string& name, bool allowVirtual) { + const std::string& name, bool allowVirtual, + bool childDType) { AstFunc* funcp = VN_AS(memberMap.findMember(nodep, name), Func); if (!funcp) { v3Global.useRandomizeMethods(true); AstNodeDType* const dtypep - = nodep->findBitDType(32, 32, VSigning::SIGNED); // IEEE says int return of 0/1 - AstVar* const fvarp = new AstVar{nodep->fileline(), VVarType::MEMBER, name, dtypep}; + = childDType + ? new AstBasicDType{nodep->fileline(), VBasicDTypeKwd::INT} + : nodep->findBitDType(32, 32, VSigning::SIGNED); // IEEE says int return of 0/1 + AstVar* const fvarp = childDType + ? new AstVar{nodep->fileline(), VVarType::MEMBER, name, + VFlagChildDType{}, dtypep} + : new AstVar{nodep->fileline(), VVarType::MEMBER, name, dtypep}; fvarp->lifetime(VLifetime::AUTOMATIC); fvarp->funcLocal(true); fvarp->funcReturn(true); fvarp->direction(VDirection::OUTPUT); nodep->addMembersp(funcp); funcp = new AstFunc{nodep->fileline(), name, nullptr, fvarp}; - funcp->dtypep(dtypep); + if (!childDType) funcp->dtypep(dtypep); funcp->classMethod(true); funcp->isVirtual(allowVirtual && nodep->isExtended()); nodep->addMembersp(funcp); memberMap.insert(nodep, funcp); - AstClass* const basep = nodep->baseMostClassp(); - basep->needRNG(true); } return funcp; } diff --git a/src/V3Randomize.h b/src/V3Randomize.h index 596fb9b77..896c14895 100644 --- a/src/V3Randomize.h +++ b/src/V3Randomize.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstClass; class AstFunc; class AstNetlist; @@ -34,7 +32,8 @@ public: static AstFunc* newRandomizeFunc(VMemberMap& memberMap, AstClass* nodep, const std::string& name = "randomize", - bool allowVirtual = true) VL_MT_DISABLED; + bool allowVirtual = true, + bool childDType = false) VL_MT_DISABLED; static AstFunc* newSRandomFunc(VMemberMap& memberMap, AstClass* nodep) VL_MT_DISABLED; }; diff --git a/src/V3Reloop.h b/src/V3Reloop.h index 61fbaafcb..756de4dd7 100644 --- a/src/V3Reloop.h +++ b/src/V3Reloop.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Sampled.h b/src/V3Sampled.h index 30d5e94a4..bd24873e3 100644 --- a/src/V3Sampled.h +++ b/src/V3Sampled.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp index 931f5b987..46fb79354 100644 --- a/src/V3Sched.cpp +++ b/src/V3Sched.cpp @@ -100,10 +100,7 @@ void remapSensitivities(const LogicByScope& lbs, void invertAndMergeSenTreeMap( V3Order::TrigToSenMap& result, const std::unordered_map& senTreeMap) { - for (const auto& pair : senTreeMap) { - UASSERT_OBJ(!pair.second->sensesp()->nextp(), pair.second, "Should be single AstSenIem"); - result.emplace(pair.second->sensesp(), pair.first); - } + for (const auto& pair : senTreeMap) result.emplace(pair.second, pair.first); } //============================================================================ @@ -598,9 +595,30 @@ const TriggerKit createTriggers(AstNetlist* netlistp, AstCFunc* const initFuncp, AstScope* const scopeTopp = topScopep->scopep(); FileLine* const flp = scopeTopp->fileline(); + // Gather all the unique SenItems under the SenTrees + // List of unique SenItems used by all 'senTreeps' + std::vector senItemps; + // Map from SenItem to the equivalent index in 'senItemps' + std::unordered_map senItemp2Index; + { + // Set of unique SenItems + std::unordered_set> uniqueSenItemps; + for (const AstSenTree* const senTreep : senTreeps) { + for (const AstSenItem *itemp = senTreep->sensesp(), *nextp; itemp; itemp = nextp) { + nextp = VN_AS(itemp->nextp(), SenItem); + const auto pair = uniqueSenItemps.emplace(*itemp); + if (pair.second) { + senItemp2Index.emplace(itemp, senItemps.size()); + senItemps.push_back(itemp); + } + senItemp2Index.emplace(itemp, senItemp2Index.at(&(pair.first->get()))); + } + } + } + std::unordered_map map; - const uint32_t nTriggers = senTreeps.size() + extraTriggers.size(); + const uint32_t nTriggers = senItemps.size() + extraTriggers.size(); // Create the TRIGGERVEC variable AstBasicDType* const tDtypep @@ -673,19 +691,17 @@ const TriggerKit createTriggers(AstNetlist* netlistp, AstCFunc* const initFuncp, // Add trigger computation uint32_t triggerNumber = extraTriggers.size(); AstNodeStmt* initialTrigsp = nullptr; - for (const AstSenTree* const senTreep : senTreeps) { - UASSERT_OBJ(senTreep->hasClocked() || senTreep->hasHybrid(), senTreep, + std::vector senItemIndex2TriggerIndex; + senItemIndex2TriggerIndex.reserve(senItemps.size()); + for (const AstSenItem* const senItemp : senItemps) { + UASSERT_OBJ(senItemp->isClocked() || senItemp->isHybrid(), senItemp, "Cannot create trigger expression for non-clocked sensitivity"); - // Create the trigger AstSenTrees and associate them with the original AstSenTree - AstNodeExpr* const senp = getTrig(triggerNumber); - AstSenItem* const senItemp = new AstSenItem{flp, VEdgeType::ET_TRUE, senp}; - AstSenTree* const trigpSenp = new AstSenTree{flp, senItemp}; - topScopep->addSenTreesp(trigpSenp); - map[senTreep] = trigpSenp; + // Store the trigger number + senItemIndex2TriggerIndex.push_back(triggerNumber); // Add the trigger computation - const auto& pair = senExprBuilder.build(senTreep); + const auto& pair = senExprBuilder.build(senItemp); funcp->addStmtsp(setTrig(triggerNumber, pair.first)); // Add initialization time trigger @@ -696,12 +712,27 @@ const TriggerKit createTriggers(AstNetlist* netlistp, AstCFunc* const initFuncp, // Add a debug statement for this trigger std::stringstream ss; - V3EmitV::verilogForTree(senTreep, ss); + ss << "@("; + V3EmitV::verilogForTree(senItemp, ss); + ss << ")"; addDebug(triggerNumber, ss.str()); // ++triggerNumber; } + + // Construct the map from old SenTrees to new SenTrees + for (const AstSenTree* const senTreep : senTreeps) { + AstSenTree* const trigpSenp = new AstSenTree{flp, nullptr}; + for (const AstSenItem *itemp = senTreep->sensesp(), *nextp; itemp; itemp = nextp) { + nextp = VN_AS(itemp->nextp(), SenItem); + const uint32_t tiggerIndex = senItemIndex2TriggerIndex.at(senItemp2Index.at(itemp)); + trigpSenp->addSensesp(new AstSenItem{flp, VEdgeType::ET_TRUE, getTrig(tiggerIndex)}); + } + topScopep->addSenTreesp(trigpSenp); + map[senTreep] = trigpSenp; + } + // Add the init and update statements for (AstNodeStmt* const nodep : senExprBuilder.getAndClearInits()) { initFuncp->addStmtsp(nodep); diff --git a/src/V3Sched.h b/src/V3Sched.h index a8da240d9..6e0dd505d 100644 --- a/src/V3Sched.h +++ b/src/V3Sched.h @@ -21,7 +21,6 @@ #include "verilatedos.h" #include "V3Ast.h" -#include "V3ThreadSafety.h" #include #include diff --git a/src/V3SchedTiming.cpp b/src/V3SchedTiming.cpp index d6d763c56..0532ba998 100644 --- a/src/V3SchedTiming.cpp +++ b/src/V3SchedTiming.cpp @@ -300,14 +300,8 @@ void transformForks(AstNetlist* const netlistp) { // If not a fork..join, copy. All write refs should've been handled by V3Fork bool passByValue = !m_forkp->joinType().join(); if (!varp->isFuncLocal()) { - if (VString::startsWith(varp->name(), "__Vintra")) { - // Pass it by value to the new function, as otherwise there are issues with - // -flocalize (see t_timing_intra_assign) - passByValue = true; - } else { - // Not func local. Its lifetime is longer than the forked process. Skip - return; - } + // Not func local. Its lifetime is longer than the forked process. Skip + return; } else if (!varp->user1()) { // Not declared before the fork. It cannot outlive the forked process return; diff --git a/src/V3Scope.h b/src/V3Scope.h index 8c9cd8d27..c7b18e01c 100644 --- a/src/V3Scope.h +++ b/src/V3Scope.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Scoreboard.h b/src/V3Scoreboard.h index 2cc727a8b..34656a4ff 100644 --- a/src/V3Scoreboard.h +++ b/src/V3Scoreboard.h @@ -22,7 +22,6 @@ #include "V3Error.h" #include "V3PairingHeap.h" -#include "V3ThreadSafety.h" //=============================================================================================== // V3Scoreboard is essentially a heap that can be hinted that some elements have changed keys, at diff --git a/src/V3SenExprBuilder.h b/src/V3SenExprBuilder.h index 5e57bcdc6..4ce5f5f86 100644 --- a/src/V3SenExprBuilder.h +++ b/src/V3SenExprBuilder.h @@ -151,7 +151,7 @@ class SenExprBuilder final { return prevp; } - std::pair createTerm(AstSenItem* senItemp) { + std::pair createTerm(const AstSenItem* senItemp) { FileLine* const flp = senItemp->fileline(); AstNodeExpr* const senp = senItemp->sensp(); @@ -192,14 +192,6 @@ class SenExprBuilder final { AstCMethodHard* const clearp = new AstCMethodHard{flp, currp(), "clearFired"}; clearp->dtypeSetVoid(); ifp->addThensp(clearp->makeStmt()); - - // Enqueue for clearing 'triggered' state on next eval - AstTextBlock* const blockp = new AstTextBlock{flp}; - ifp->addThensp(blockp); - const auto add = [&](const string& text) { blockp->addText(flp, text, true); }; - add("vlSymsp->enqueueTriggeredEventForClearing("); - blockp->addNodesp(currp()); - add(");\n"); } // Get 'fired' state @@ -218,6 +210,15 @@ class SenExprBuilder final { public: // Returns the expression computing the trigger, and a bool indicating that // this trigger should be fired on the first evaluation (at initialization) + std::pair build(const AstSenItem* senItemp) { + auto term = createTerm(senItemp); + if (AstNodeExpr* const condp = senItemp->condp()) { + term.first = new AstAnd{senItemp->fileline(), condp->cloneTreePure(false), term.first}; + } + return term; + } + + // Like above, but for a whole SenTree std::pair build(const AstSenTree* senTreep) { FileLine* const flp = senTreep->fileline(); AstNodeExpr* resultp = nullptr; @@ -226,8 +227,6 @@ public: senItemp = VN_AS(senItemp->nextp(), SenItem)) { const auto& pair = createTerm(senItemp); if (AstNodeExpr* termp = pair.first) { - AstNodeExpr* const condp = senItemp->condp(); - if (condp) termp = new AstAnd{flp, condp->cloneTreePure(false), termp}; resultp = resultp ? new AstOr{flp, resultp, termp} : termp; firedAtInitialization |= pair.second; } diff --git a/src/V3Simulate.h b/src/V3Simulate.h index d9b950602..1a96ca74d 100644 --- a/src/V3Simulate.h +++ b/src/V3Simulate.h @@ -108,6 +108,7 @@ private: bool m_anyAssignComb; ///< True if found a non-delayed assignment bool m_inDlyAssign; ///< Under delayed assignment bool m_isImpure; // Not pure + bool m_isCoverage; // Has coverage int m_instrCount; ///< Number of nodes int m_dataCount; ///< Bytes of data AstJumpGo* m_jumpp = nullptr; ///< Jump label we're branching from @@ -215,6 +216,7 @@ public: bool isAssignDly() const { return m_anyAssignDly; } bool isImpure() const { return m_isImpure; } + bool isCoverage() const { return m_isCoverage; } int instrCount() const { return m_instrCount; } int dataCount() const { return m_dataCount; } @@ -258,6 +260,7 @@ public: void newValue(AstNode* nodep, const AstNodeExpr* valuep) { if (const AstConst* const constp = VN_CAST(valuep, Const)) { newConst(nodep)->num().opAssign(constp->num()); + UINFO(9, " new val " << valuep->name() << " on " << nodep << endl); } else if (fetchValueNull(nodep) != valuep) { // const_cast, as clonep() is set on valuep, but nothing should care setValue(nodep, newTrackedClone(const_cast(valuep))); @@ -266,6 +269,7 @@ public: void newOutValue(AstNode* nodep, const AstNodeExpr* valuep) { if (const AstConst* const constp = VN_CAST(valuep, Const)) { newOutConst(nodep)->num().opAssign(constp->num()); + UINFO(9, " new oval " << valuep->name() << " on " << nodep << endl); } else if (fetchOutValueNull(nodep) != valuep) { // const_cast, as clonep() is set on valuep, but nothing should care setOutValue(nodep, newTrackedClone(const_cast(valuep))); @@ -282,7 +286,7 @@ private: // Set a constant value for this node if (!VN_IS(m_varAux(nodep).valuep, Const)) { AstConst* const constp = allocConst(nodep); - setValue(nodep, constp); + m_varAux(nodep).valuep = constp; return constp; } else { return fetchConst(nodep); @@ -292,7 +296,7 @@ private: // Set a var-output constant value for this node if (!VN_IS(m_varAux(nodep).outValuep, Const)) { AstConst* const constp = allocConst(nodep); - setOutValue(nodep, constp); + m_varAux(nodep).outValuep = constp; return constp; } else { return fetchOutConst(nodep); @@ -594,9 +598,18 @@ private: checkNodeInfo(nodep); iterateChildrenConst(nodep); if (!m_checkOnly && optimizable()) { + AstConst* const valuep = newConst(nodep); nodep->numberOperate(newConst(nodep)->num(), fetchConst(nodep->lhsp())->num(), fetchConst(nodep->rhsp())->num(), fetchConst(nodep->thsp())->num()); + // See #5490. 'numberOperate' on partially out of range select yields 'x' bits, + // but in reality it would yield '0's without V3Table, so force 'x' bits to '0', + // to ensure the result is the same with and without V3Table. + if (!m_params && VN_IS(nodep, Sel) && valuep->num().isAnyX()) { + V3Number num{valuep, valuep->width()}; + num.opAssign(valuep->num()); + valuep->num().opBitsOne(num); + } } } void visit(AstNodeQuadop* nodep) override { @@ -1185,8 +1198,7 @@ private: } } - // Ignore coverage - from a function we're inlining - void visit(AstCoverInc* nodep) override {} + void visit(AstCoverInc* nodep) override { m_isCoverage = true; } // ==== // Known Bad @@ -1237,6 +1249,7 @@ public: m_anyAssignDly = false; m_inDlyAssign = false; m_isImpure = false; + m_isCoverage = false; m_instrCount = 0; m_dataCount = 0; m_jumpp = nullptr; diff --git a/src/V3Slice.h b/src/V3Slice.h index c96c482ab..14d2a8de0 100644 --- a/src/V3Slice.h +++ b/src/V3Slice.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Split.h b/src/V3Split.h index d14013df3..d0ef26847 100644 --- a/src/V3Split.h +++ b/src/V3Split.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3SplitAs.h b/src/V3SplitAs.h index b45b263ac..3fe08466a 100644 --- a/src/V3SplitAs.h +++ b/src/V3SplitAs.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3SplitVar.h b/src/V3SplitVar.h index e5ac9e12b..32128ebb6 100644 --- a/src/V3SplitVar.h +++ b/src/V3SplitVar.h @@ -17,9 +17,9 @@ #ifndef VERILATOR_V3SPLITVAR_H_ #define VERILATOR_V3SPLITVAR_H_ -//============================================================================ +#include "verilatedos.h" -#include "V3ThreadSafety.h" +//============================================================================ class AstNetlist; class AstVar; diff --git a/src/V3StackCount.h b/src/V3StackCount.h index 3a8e15d50..468a0d952 100644 --- a/src/V3StackCount.h +++ b/src/V3StackCount.h @@ -21,8 +21,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNode; class V3StackCount final { diff --git a/src/V3StatsReport.cpp b/src/V3StatsReport.cpp index 8b83c501f..5aa2aa159 100644 --- a/src/V3StatsReport.cpp +++ b/src/V3StatsReport.cpp @@ -221,7 +221,7 @@ void V3Stats::statsStage(const string& name) { void V3Stats::infoHeader(std::ofstream& os, const string& prefix) { os << prefix << "Information:\n"; - os << prefix << " " << V3Options::version() << '\n'; + os << prefix << " Version: " << V3Options::version() << '\n'; os << prefix << " Arguments: " << v3Global.opt.allArgsString() << '\n'; os << prefix << " Build jobs: " << v3Global.opt.buildJobs() << '\n'; os << prefix << " Verilate jobs: " << v3Global.opt.verilateJobs() << '\n'; diff --git a/src/V3Subst.h b/src/V3Subst.h index 2d29df8e4..edf07151f 100644 --- a/src/V3Subst.h +++ b/src/V3Subst.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3SymTable.h b/src/V3SymTable.h index 815356fa4..cc6940fe4 100644 --- a/src/V3SymTable.h +++ b/src/V3SymTable.h @@ -64,12 +64,12 @@ public: void dumpIterate(std::ostream& os, VSymConstMap& doneSymsr, const string& indent, int numLevels, const string& searchName) const { - os << indent << "+ " << std::left << std::setw(30) - << (searchName == "" ? "\"\"" : searchName) << std::setw(0) << std::right; + os << indent << "+ " << std::left << std::setw(30) << ("'"s + searchName + "'"s) + << std::setw(0) << std::right; os << " se" << cvtToHex(this) << std::setw(0); os << " fallb=se" << cvtToHex(m_fallbackp); if (m_symPrefix != "") os << " symPrefix=" << m_symPrefix; - os << " n=" << nodep(); + if (nodep()) os << " n=" << nodep(); os << '\n'; if (VL_UNCOVERABLE(!doneSymsr.insert(this).second)) { os << indent << "| ^ duplicate, so no children printed\n"; // LCOV_EXCL_LINE diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp index db7f72c02..e027db84d 100644 --- a/src/V3TSP.cpp +++ b/src/V3TSP.cpp @@ -377,8 +377,8 @@ public: } UINFO(6, "Tour was: "); - for (const Vertex* vxp : tour) UINFONL(6, " " << vxp->key()); - UINFONL(6, "\n"); + for (const Vertex* vxp : tour) UINFONL(6, "- " << vxp->key()); + UINFONL(6, "-\n"); } void dumpGraph(std::ostream& os, const string& nameComment) const { @@ -433,7 +433,7 @@ private: //###################################################################### // Main algorithm -void V3TSP::tspSort(const V3TSP::StateVec& states, V3TSP::StateVec* resultp) { +void V3TSP::tspSort(const V3TSP::StateVec& states, V3TSP::StateVec* resultp) VL_MT_SAFE { UASSERT(resultp->empty(), "Output graph must start empty"); // Make this TSP implementation work for graphs of size 0 or 1 @@ -536,14 +536,14 @@ public: , m_ypos{ypos} , m_serial{++s_serialNext} {} ~TspTestState() override = default; - int cost(const TspStateBase* otherp) const override { + int cost(const TspStateBase* otherp) const override VL_MT_SAFE { return cost(dynamic_cast(otherp)); } - static unsigned diff(unsigned a, unsigned b) { + static unsigned diff(unsigned a, unsigned b) VL_PURE { if (a > b) return a - b; return b - a; } - virtual int cost(const TspTestState* otherp) const { + int cost(const TspTestState* otherp) const VL_PURE { // For test purposes, each TspTestState is merely a point // on the Cartesian plane; cost is the linear distance // between two points. diff --git a/src/V3TSP.h b/src/V3TSP.h index 1288945af..37bfb8891 100644 --- a/src/V3TSP.h +++ b/src/V3TSP.h @@ -22,7 +22,6 @@ #include "verilatedos.h" #include "V3Error.h" -#include "V3ThreadSafety.h" #include @@ -35,7 +34,7 @@ public: // This is the cost function that the TSP sort will minimize. // All costs in V3TSP are int, chosen to match the type of // V3GraphEdge::weight() which will reflect each edge's cost. - virtual int cost(const TspStateBase* otherp) const = 0; + virtual int cost(const TspStateBase* otherp) const VL_MT_SAFE = 0; // This operator< must place a meaningless, arbitrary, but // stable order on all TspStateBase's. It's used only to @@ -50,7 +49,7 @@ using StateVec = std::vector; // Given an unsorted set of TspState's, sort them to minimize // the transition cost for walking the sorted list. -void tspSort(const StateVec& states, StateVec* resultp) VL_MT_DISABLED; +void tspSort(const StateVec& states, StateVec* resultp) VL_MT_SAFE; void selfTest() VL_MT_DISABLED; } // namespace V3TSP diff --git a/src/V3Table.cpp b/src/V3Table.cpp index a7bddd93e..0c356dd38 100644 --- a/src/V3Table.cpp +++ b/src/V3Table.cpp @@ -210,6 +210,9 @@ private: const double time // max(_, 1), so we won't divide by zero = std::max(chkvis.instrCount() * TABLE_BYTES_PER_INST + chkvis.dataCount(), 1); if (chkvis.isImpure()) chkvis.clearOptimizable(nodep, "Table creates side effects"); + if (chkvis.isCoverage()) { + chkvis.clearOptimizable(nodep, "Table removes coverage points"); + } if (!m_outWidthBytes || !m_inWidthBits) { chkvis.clearOptimizable(nodep, "Table has no outputs"); } @@ -315,6 +318,7 @@ private: for (TableOutputVar& tov : m_outVarps) { if (V3Number* const outnump = simvis.fetchOutNumberNull(tov.varScopep())) { UINFO(8, " Output " << tov.name() << " = " << *outnump << endl); + UASSERT_OBJ(!outnump->isAnyXZ(), outnump, "Table should not contain X/Z"); outputAssignedMask.setBit(tov.ord(), 1); // Mark output as assigned tov.addValue(inValue, *outnump); } else { diff --git a/src/V3Table.h b/src/V3Table.h index 9f7db3fec..c6d5a1123 100644 --- a/src/V3Table.h +++ b/src/V3Table.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Task.cpp b/src/V3Task.cpp index ae8a6373b..460647692 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -492,8 +492,13 @@ class TaskVisitor final : public VNVisitor { if (VN_IS(pinp, VarRef) || VN_IS(pinp, MemberSel) || VN_IS(pinp, StructSel) || VN_IS(pinp, ArraySel)) { refArgOk = true; - } else if (const AstCMethodHard* const cMethodp = VN_CAST(pinp, CMethodHard)) { - refArgOk = cMethodp->name() == "at"; + } else if (AstCMethodHard* const cMethodp = VN_CAST(pinp, CMethodHard)) { + if (VN_IS(cMethodp->fromp()->dtypep()->skipRefp(), QueueDType)) { + refArgOk = cMethodp->name() == "atWriteAppend" + || cMethodp->name() == "atWriteAppendBack"; + } else { + refArgOk = cMethodp->name() == "at" || cMethodp->name() == "atBack"; + } } if (refArgOk) { if (AstVarRef* const varrefp = VN_CAST(pinp, VarRef)) { @@ -719,6 +724,14 @@ class TaskVisitor final : public VNVisitor { return dpiproto; } + static void checkLegalCIdentifier(AstNode* nodep, const string& name) { + if (name.end() != std::find_if(name.begin(), name.end(), [](char c) { + return !std::isalnum(c) && c != '_'; + })) { + nodep->v3error("DPI function has illegal characters in C identifier name: " << name); + } + } + static AstNode* createDpiTemp(AstVar* portp, const string& suffix) { const string stmt = portp->dpiTmpVarType(portp->name() + suffix) + ";\n"; return new AstCStmt{portp->fileline(), stmt}; @@ -818,8 +831,11 @@ class TaskVisitor final : public VNVisitor { } AstCFunc* makeDpiExportDispatcher(AstNodeFTask* nodep, AstVar* rtnvarp) { + // Verilog name has __ conversion and other tricks, to match DPI C code, back that out + const string name = AstNode::prettyName(nodep->cname()); + checkLegalCIdentifier(nodep, name); const char* const tmpSuffixp = V3Task::dpiTemporaryVarSuffix(); - AstCFunc* const funcp = new AstCFunc{nodep->fileline(), nodep->cname(), m_scopep, + AstCFunc* const funcp = new AstCFunc{nodep->fileline(), name, m_scopep, (rtnvarp ? rtnvarp->dpiArgType(true, true) : "")}; funcp->dpiExportDispatcher(true); funcp->dpiContext(nodep->dpiContext()); @@ -827,7 +843,7 @@ class TaskVisitor final : public VNVisitor { funcp->entryPoint(true); funcp->isStatic(true); funcp->protect(false); - funcp->cname(nodep->cname()); + funcp->cname(name); // Add DPI Export to top, since it's a global function m_topScopep->scopep()->addBlocksp(funcp); @@ -945,15 +961,14 @@ class TaskVisitor final : public VNVisitor { } AstCFunc* makeDpiImportPrototype(AstNodeFTask* nodep, AstVar* rtnvarp) { - if (nodep->cname() != AstNode::prettyName(nodep->cname())) { - nodep->v3error("DPI function has illegal characters in C identifier name: " - << AstNode::prettyNameQ(nodep->cname())); - } + // Verilog name has __ conversion and other tricks, to match DPI C code, back that out + const string name = AstNode::prettyName(nodep->cname()); + checkLegalCIdentifier(nodep, name); // Tasks (but not void functions) return a boolean 'int' indicating disabled const string rtnType = rtnvarp ? rtnvarp->dpiArgType(true, true) : nodep->dpiTask() ? "int" : ""; - AstCFunc* const funcp = new AstCFunc{nodep->fileline(), nodep->cname(), m_scopep, rtnType}; + AstCFunc* const funcp = new AstCFunc{nodep->fileline(), name, m_scopep, rtnType}; funcp->dpiContext(nodep->dpiContext()); funcp->dpiImportPrototype(true); funcp->dontCombine(true); diff --git a/src/V3Task.h b/src/V3Task.h index f2fa4cf83..5faf2aec4 100644 --- a/src/V3Task.h +++ b/src/V3Task.h @@ -22,7 +22,6 @@ #include "V3Ast.h" #include "V3Error.h" -#include "V3ThreadSafety.h" #include #include diff --git a/src/V3ThreadPool.cpp b/src/V3ThreadPool.cpp index eeaf69aa5..576c9c86a 100644 --- a/src/V3ThreadPool.cpp +++ b/src/V3ThreadPool.cpp @@ -14,139 +14,78 @@ // //************************************************************************* -#include "config_build.h" - #include "V3ThreadPool.h" #include "V3Error.h" +#include "V3Global.h" +#include "V3Mutex.h" -// c++11 requires definition of static constexpr as well as declaration -constexpr unsigned int V3ThreadPool::FUTUREWAITFOR_MS; +V3ThreadPool::V3ThreadPool(int numThreads) { + numThreads = std::max(numThreads, 1); + if (numThreads == 1) return; + for (int i = 0; i < numThreads; ++i) { + m_workers.emplace_back(&V3ThreadPool::startWorker, this); + } +} -void V3ThreadPool::resize(unsigned n) VL_MT_UNSAFE VL_EXCLUDES(m_mutex) - VL_EXCLUDES(m_stoppedJobsMutex) VL_EXCLUDES(V3MtDisabledLock::instance()) { - // At least one thread (main) - n = std::max(1u, n); - if (n == (m_workers.size() + 1)) return; - // This function is not thread-safe and can result in race between threads - UASSERT(V3MutexConfig::s().lockConfig(), - "Mutex config needs to be locked before starting ThreadPool"); +V3ThreadPool::~V3ThreadPool() { { - V3LockGuard stoppedJobsLock{m_stoppedJobsMutex}; - V3LockGuard lock{m_mutex}; - - UASSERT(m_queue.empty(), "Resizing busy thread pool"); - // Shut down old threads + const V3LockGuard lock{m_mutex}; m_shutdown = true; - m_stoppedJobs = 0; - m_cv.notify_all(); - m_stoppedJobsCV.notify_all(); - m_exclusiveAccessThreadCV.notify_all(); - } - while (!m_workers.empty()) { - m_workers.front().join(); - m_workers.pop_front(); - } - if (n > 1) { - V3LockGuard lock{m_mutex}; - // Start new threads - m_shutdown = false; - for (unsigned int i = 1; i < n; ++i) { - m_workers.emplace_back(&V3ThreadPool::startWorker, this, i); - } } + m_cv.notify_all(); + wait(); } -void V3ThreadPool::suspendMultithreading() VL_MT_SAFE VL_EXCLUDES(m_mutex) - VL_EXCLUDES(m_stoppedJobsMutex) { - V3LockGuard stoppedJobsLock{m_stoppedJobsMutex}; - if (!m_workers.empty()) stopOtherThreads(); - - if (!m_mutex.try_lock()) { - v3fatal("Tried to suspend thread pool when other thread uses it."); - } - V3LockGuard lock{m_mutex, std::adopt_lock_t{}}; - - UASSERT(m_queue.empty(), "Thread pool has pending jobs"); - UASSERT(m_jobsInProgress == 0, "Thread pool has jobs in progress"); - m_exclusiveAccess = true; - m_multithreadingSuspended = true; -} - -void V3ThreadPool::resumeMultithreading() VL_MT_SAFE VL_EXCLUDES(m_mutex) - VL_EXCLUDES(m_stoppedJobsMutex) { - if (!m_mutex.try_lock()) v3fatal("Tried to resume thread pool when other thread uses it."); - { - V3LockGuard lock{m_mutex, std::adopt_lock_t{}}; - UASSERT(m_multithreadingSuspended, "Multithreading is not suspended"); - m_multithreadingSuspended = false; - m_exclusiveAccess = false; - } - if (!m_workers.empty()) { - V3LockGuard stoppedJobsLock{m_stoppedJobsMutex}; - resumeOtherThreads(); - } -} - -void V3ThreadPool::startWorker(V3ThreadPool* selfThreadp, int id) VL_MT_SAFE { - selfThreadp->workerJobLoop(id); -} - -void V3ThreadPool::workerJobLoop(int id) VL_MT_SAFE { - while (true) { - // Wait for a notification - waitIfStopRequested(); - VAnyPackagedTask job; +void V3ThreadPool::enqueue(std::function&& f) { + if (m_workers.empty()) { + f(); + } else { { - V3LockGuard lock(m_mutex); - m_cv.wait(m_mutex, [&]() VL_REQUIRES(m_mutex) { - return !m_queue.empty() || m_shutdown || m_stopRequested; - }); - if (m_shutdown) return; // Terminate if requested - if (stopRequested()) continue; - // Get the job - UASSERT(!m_queue.empty(), "Job should be available"); + const V3LockGuard lock{m_mutex}; + m_queue.push(std::move(f)); + } + m_pendingJobs.fetch_add(1, std::memory_order_release); + m_cv.notify_one(); + } +} +void V3ThreadPool::wait() { + while (m_pendingJobs.load(std::memory_order_acquire) > 0 && !m_shutdown) { + std::this_thread::yield(); + } + if (m_shutdown) { + for (auto& worker : m_workers) worker.join(); + } +} + +void V3ThreadPool::startWorker(V3ThreadPool* selfThreadp) { selfThreadp->workerJobLoop(); } + +void V3ThreadPool::workerJobLoop() { + while (true) { + std::function job; + { + // Locking before `condition_variable::wait` is required to ensure that the + // `m_cv` condition will be executed under a lock. Taking a lock + // before `condition_variable::wait` may lead to missed + // `condition_variable::notify_all` notification (when a thread waits at the lock + // before) but, according to C++ standard, the `condition_variable::wait` first checks + // the condition and then waits for the notification, thus even when notification is + // missed, the condition still will be checked. + const V3LockGuard lock{m_mutex}; + m_cv.wait(m_mutex, + [&]() VL_REQUIRES(m_mutex) { return !m_queue.empty() || m_shutdown; }); + if (m_shutdown) return; // Terminate if requested + UASSERT(!m_queue.empty(), "Job should be available"); + if (m_queue.empty()) continue; job = std::move(m_queue.front()); m_queue.pop(); - ++m_jobsInProgress; } - - // Execute the job job(); - // Note that a context switch can happen here. This means `m_jobsInProgress` could still - // contain old value even after the job promise has been fulfilled. - --m_jobsInProgress; + m_pendingJobs.fetch_sub(1, std::memory_order_release); } } -bool V3ThreadPool::waitIfStopRequested() VL_MT_SAFE VL_EXCLUDES(m_stoppedJobsMutex) { - if (!stopRequested()) return false; - V3LockGuard stoppedJobLock(m_stoppedJobsMutex); - waitForResumeRequest(); - return true; -} - -void V3ThreadPool::waitForResumeRequest() VL_REQUIRES(m_stoppedJobsMutex) { - ++m_stoppedJobs; - m_exclusiveAccessThreadCV.notify_one(); - m_stoppedJobsCV.wait(m_stoppedJobsMutex, - [&]() VL_REQUIRES(m_stoppedJobsMutex) { return !m_stopRequested; }); - --m_stoppedJobs; -} - -void V3ThreadPool::stopOtherThreads() VL_MT_SAFE_EXCLUDES(m_mutex) - VL_REQUIRES(m_stoppedJobsMutex) { - m_stopRequested = true; - { - V3LockGuard lock{m_mutex}; - m_cv.notify_all(); - } - m_exclusiveAccessThreadCV.wait(m_stoppedJobsMutex, [&]() VL_REQUIRES(m_stoppedJobsMutex) { - return m_stoppedJobs == m_workers.size(); - }); -} - void V3ThreadPool::selfTestMtDisabled() { // empty } @@ -157,7 +96,7 @@ void V3ThreadPool::selfTest() { auto firstJob = [&](int sleep) -> void { std::this_thread::sleep_for(std::chrono::milliseconds{sleep}); - const V3ThreadPool::ScopedExclusiveAccess exclusiveAccess; + const V3LockGuard lock{commonMutex}; commonValue = 10; std::this_thread::sleep_for(std::chrono::milliseconds{sleep + 10}); UASSERT(commonValue == 10, "unexpected commonValue = " << commonValue); @@ -165,7 +104,6 @@ void V3ThreadPool::selfTest() { auto secondJob = [&](int sleep) -> void { commonMutex.lock(); commonMutex.unlock(); - s().waitIfStopRequested(); V3LockGuard lock{commonMutex}; std::this_thread::sleep_for(std::chrono::milliseconds{sleep}); commonValue = 1000; @@ -175,57 +113,56 @@ void V3ThreadPool::selfTest() { V3LockGuard lock{commonMutex}; std::this_thread::sleep_for(std::chrono::milliseconds{sleep}); } - s().requestExclusiveAccess([&]() { firstJob(sleep); }); + firstJob(sleep); V3LockGuard lock{commonMutex}; - commonValue = 1000; + commonValue = 100; }; - std::list> futures; - - futures.push_back(s().enqueue(std::bind(firstJob, 100))); - futures.push_back(s().enqueue(std::bind(secondJob, 100))); - futures.push_back(s().enqueue(std::bind(firstJob, 100))); - futures.push_back(s().enqueue(std::bind(secondJob, 100))); - futures.push_back(s().enqueue(std::bind(secondJob, 200))); - futures.push_back(s().enqueue(std::bind(firstJob, 200))); - futures.push_back(s().enqueue(std::bind(firstJob, 300))); - while (!futures.empty()) { - s().waitForFuture(futures.front()); - futures.pop_front(); - } - futures.push_back(s().enqueue(std::bind(thirdJob, 100))); - futures.push_back(s().enqueue(std::bind(thirdJob, 100))); - V3ThreadPool::waitForFutures(futures); - - s().waitIfStopRequested(); - s().requestExclusiveAccess(std::bind(firstJob, 100)); - - auto forthJob = [&]() -> int { return 1234; }; - std::list> futuresInt; - futuresInt.push_back(s().enqueue(forthJob)); - auto result = V3ThreadPool::waitForFutures(futuresInt); - UASSERT(result.back() == 1234, "unexpected future result = " << result.back()); { - const V3MtDisabledLockGuard mtDisabler{v3MtDisabledLock()}; - selfTestMtDisabled(); - { - V3LockGuard lock{V3ThreadPool::s().m_mutex}; - UASSERT(V3ThreadPool::s().m_multithreadingSuspended, - "Multithreading should be suspended at this point"); - } + V3ThreadScope scope; + + scope.enqueue(std::bind(firstJob, 100)); + scope.enqueue(std::bind(secondJob, 100)); + scope.enqueue(std::bind(firstJob, 100)); + scope.enqueue(std::bind(secondJob, 100)); + scope.enqueue(std::bind(secondJob, 200)); + scope.enqueue(std::bind(firstJob, 200)); + scope.enqueue(std::bind(firstJob, 300)); + scope.wait(); + + UASSERT(commonValue == 1000 || commonValue == 10, + "unexpected common value = " << commonValue); + + scope.enqueue(std::bind(thirdJob, 100)); + scope.enqueue(std::bind(thirdJob, 100)); } + + UASSERT(commonValue == 100, "unexpected common value = " << commonValue); + { - V3LockGuard lock{V3ThreadPool::s().m_mutex}; - UASSERT(!V3ThreadPool::s().m_multithreadingSuspended, - "Multithreading should not be suspended at this point"); + V3ThreadScope scope; + scope.enqueue(std::bind(firstJob, 100)); } + + UASSERT(commonValue == 10, "unexpected common value = " << commonValue); + + { + int result = 0; + auto forthJob = [&]() -> void { result = 1234; }; + + V3ThreadScope scope; + scope.enqueue(forthJob); + scope.wait(); + UASSERT(result == 1234, "unexpected job result = " << result); + } + selfTestMtDisabled(); } -V3MtDisabledLock V3MtDisabledLock::s_mtDisabledLock; - -void V3MtDisabledLock::lock() VL_ACQUIRE() VL_MT_SAFE { - V3ThreadPool::s().suspendMultithreading(); +V3ThreadScope::V3ThreadScope() { + UASSERT(v3Global.threadPoolp(), "ThreadPool must be initialized before ThreadScope."); + m_pool = v3Global.threadPoolp(); + wait(); } -void V3MtDisabledLock::unlock() VL_RELEASE() VL_MT_SAFE { - V3ThreadPool::s().resumeMultithreading(); -} +void V3ThreadScope::enqueue(std::function&& f) { m_pool->enqueue(std::move(f)); } + +void V3ThreadScope::wait() { m_pool->wait(); } diff --git a/src/V3ThreadPool.h b/src/V3ThreadPool.h index df0077bc3..a2365e6ac 100644 --- a/src/V3ThreadPool.h +++ b/src/V3ThreadPool.h @@ -22,178 +22,36 @@ #endif #include "V3Mutex.h" -#include "V3ThreadSafety.h" +#include #include #include -#include -#include -#include -#include #include #include //============================================================================ -// Callable, type-erased wrapper for std::packaged_task with any Signature. -class VAnyPackagedTask final { - // TYPES - struct PTWrapperBase VL_NOT_FINAL { - virtual ~PTWrapperBase() {} - virtual void operator()() = 0; - }; - - template - struct PTWrapper final : PTWrapperBase { - std::packaged_task m_pt; - - explicit PTWrapper(std::packaged_task&& pt) - : m_pt(std::move(pt)) {} - - void operator()() final override { m_pt(); } - }; - - // MEMBERS - std::unique_ptr m_ptWrapperp = nullptr; // Wrapper to call - -public: - // CONSTRUCTORS - template - // non-explicit: - // cppcheck-suppress noExplicitConstructor - VAnyPackagedTask(std::packaged_task&& pt) - : m_ptWrapperp{std::make_unique>(std::move(pt))} {} - - VAnyPackagedTask() = default; - ~VAnyPackagedTask() = default; - - VAnyPackagedTask(const VAnyPackagedTask&) = delete; - VAnyPackagedTask& operator=(const VAnyPackagedTask&) = delete; - - VAnyPackagedTask(VAnyPackagedTask&&) = default; - VAnyPackagedTask& operator=(VAnyPackagedTask&&) = default; - - // METHODS - // Call the wrapped function - void operator()() { (*m_ptWrapperp)(); } -}; - class V3ThreadPool final { // MEMBERS - static constexpr unsigned int FUTUREWAITFOR_MS = 100; - - // some functions locks both of this mutexes, be careful of lock inversion problems - // 'm_stoppedJobsMutex' mutex should always be locked before 'm_mutex' mutex - // check usage of both of them when you use either of them - V3Mutex m_mutex; // Mutex for use by m_queue - V3Mutex m_stoppedJobsMutex; // Used to signal stopped jobs - std::queue m_queue VL_GUARDED_BY(m_mutex); // Queue of jobs - // We don't need to guard this condition_variable as - // both `notify_one` and `notify_all` functions are atomic, - // `wait` function is not atomic, but we are guarding `m_queue` that is - // used by this condition_variable, so clang checks that we have mutex locked + std::vector m_workers; // Worker threads + std::queue> m_queue VL_GUARDED_BY(m_mutex); // Job queue std::condition_variable_any m_cv; // Conditions to wake up workers - std::list m_workers; // Worker threads - // Number of started and not yet finished jobs. - // Reading is valid only after call to `stopOtherThreads()` or when no worker threads exist. - std::atomic_uint m_jobsInProgress{0}; - // Conditions to wake up stopped jobs - std::condition_variable_any m_stoppedJobsCV VL_GUARDED_BY(m_stoppedJobsMutex); - // Conditions to wake up exclusive access thread - std::condition_variable_any m_exclusiveAccessThreadCV VL_GUARDED_BY(m_stoppedJobsMutex); - std::atomic_uint m_stoppedJobs{0}; // Currently stopped jobs waiting for wake up - std::atomic_bool m_stopRequested{false}; // Signals to resume stopped jobs - std::atomic_bool m_exclusiveAccess{false}; // Signals that all other threads are stopped - - std::atomic_bool m_shutdown{false}; // Termination pending - - // Indicates whether multithreading has been suspended. - // Used for error detection in resumeMultithreading only. You probably should use - // m_exclusiveAccess for information whether something should be run in current thread. - std::atomic_bool m_multithreadingSuspended{false}; - - // CONSTRUCTORS - V3ThreadPool() = default; - ~V3ThreadPool() { - m_shutdown = true; - if (m_multithreadingSuspended) { - // Ideally we shouldn't deal with this and just call the std::abort. However, - // std::exit(0) (which invokes this destructor) is called in multiple places with - // multithreading being suspended. Aborting would change the exit code, what would not - // be acceptable. - resumeMultithreading(); - } - // Unexpected states. Aborting to subtly signal to the outside world that something is - // wrong. This won't make things worse to an user - the program is already terminating at - // this point anyway, most likely as a result of an error. Using if/abort instead of assert - // because assert can be disabled. - if (VL_UNCOVERABLE(m_exclusiveAccess)) { - std::cerr << "%Error: Internal Error: attempted to destroy Thread Pool with active " - "exclusive access mode" - << std::endl; - std::abort(); - } - if (VL_UNCOVERABLE(m_stopRequested)) { - std::cerr << "%Error: Internal Error: attempted to destroy Thread Pool with active " - "stop request" - << std::endl; - std::abort(); - } - - bool m_mutex_locked = m_mutex.try_lock(); - using namespace std::chrono_literals; - // try to obtain lock with timeout - // we need to wait for workers to start waiting - // on condition variable to perform destruction - constexpr int spins = 1s / 1ms; - for (int i = 0; i < spins; ++i) { - if (VL_LIKELY(m_mutex_locked)) break; - std::this_thread::sleep_for(1ms); - - m_mutex_locked = m_mutex.try_lock(); - } - if (VL_UNCOVERABLE(!m_mutex_locked)) { - if (VL_UNCOVERABLE(m_jobsInProgress != 0)) { - // ThreadPool shouldn't be destroyed when jobs are running and mutex is locked, - // something is wrong. Most likely Verilator is exiting as a result of failed - // assert in critical section. Just returning is dangerous, as threads and this - // class' members might keep the program hanging endlessly. - std::cerr << "%Error: Internal Error: attempted to destroy Thread Pool with " - "running jobs" - << std::endl; - std::abort(); - } - // Probably an error happened in a call to some V3ThreadPool's method. We can't just - // unlock m_mutex and be sure that resize(0) handle this well. - std::cerr << "%Error: Internal Error: attempted to destroy locked Thread Pool" - << std::endl; - std::abort(); - } else { - V3LockGuard lock{m_mutex, std::adopt_lock_t{}}; - m_queue = {}; // make sure queue is empty - } - - // This locks mutexes and wakes up threads, so it would be nice to move this to a separate - // method that would be called just before controlled exit. Such method would need to be - // called in quite a few places that call std::exit(0), so leaving it here for now. - resize(0); - } + std::atomic m_shutdown{false}; // Termination pending + std::atomic m_pendingJobs{0}; // Number of started and not yet finished jobs + V3Mutex m_mutex; // Mutex for use by m_queue public: - // Request exclusive access to processing for the object lifetime. - class ScopedExclusiveAccess; + // CONSTRUCTORS + explicit V3ThreadPool(int numThreads); + ~V3ThreadPool() VL_EXCLUDES(m_mutex); + VL_UNCOPYABLE(V3ThreadPool); + VL_UNMOVABLE(V3ThreadPool); + static void selfTest(); + static void selfTestMtDisabled() VL_MT_DISABLED; + +private: // METHODS - // Singleton - static V3ThreadPool& s() VL_MT_SAFE { - static V3ThreadPool s_s; - return s_s; - } - - // Resize thread pool to n workers (queue must be empty) - void resize(unsigned n) VL_MT_UNSAFE VL_EXCLUDES(m_mutex) VL_EXCLUDES(m_stoppedJobsMutex) - VL_EXCLUDES(V3MtDisabledLock::instance()); - // Enqueue a job for asynchronous execution // Due to missing support for lambda annotations in c++11, // `clang_check_attributes` script assumes that if @@ -201,177 +59,40 @@ public: // will call it. `VL_MT_START` here indicates that // every function call inside this `std::function` requires // annotations. - template - auto enqueue(Callable&& f) VL_MT_START; + void enqueue(std::function&& f) VL_MT_START VL_EXCLUDES(m_mutex); - // Request exclusive access to processing. - // It sends request to stop all other threads and waits for them to stop. - // Other threads needs to manually call 'check_stop_requested' in places where - // they can be stopped. - // When all other threads are stopped, this function executes the job - // and resumes execution of other jobs. - template - void requestExclusiveAccess(Callable&& exclusiveAccessJob) VL_MT_SAFE - VL_EXCLUDES(m_stoppedJobsMutex); + // Wait for all enqueued jobs to finish + void wait() VL_MT_SAFE; - // Check if other thread requested exclusive access to processing, - // if so, it waits for it to complete. Afterwards it is resumed. - // Returns true if request was send and we waited, otherwise false - bool waitIfStopRequested() VL_MT_SAFE VL_EXCLUDES(m_stoppedJobsMutex); + // Job execution loop + // Each worker wait for available job and executes it when it is available. + void workerJobLoop() VL_MT_SAFE VL_EXCLUDES(m_mutex); - // Waits for future. - // This function can be interrupted by exclusive access request. - // When other thread requested exclusive access to processing, - // current thread is stopped and waits until it is resumed. - // Returns future result - template - static T waitForFuture(std::future& future) VL_MT_SAFE_EXCLUDES(m_mutex); + // Start worker thread + static void startWorker(V3ThreadPool* selfThreadp) VL_MT_SAFE VL_EXCLUDES(m_mutex); - // Waits for list of futures - // This function can be interrupted by exclusive access request. - // When other thread requested exclusive access to processing, - // current thread is stopped and waits until it is resumed. - // This function uses function overload instead of template - // specialization as C++11 requires them to be inside namespace scope - // Returns list of future result or void - template - static auto waitForFutures(std::list>& futures) { - return waitForFuturesImp(futures); - } - - static void selfTest(); - static void selfTestMtDisabled() VL_MT_DISABLED; - -private: - // For access to suspendMultithreading() and resumeMultithreading() - friend class V3MtDisabledLock; - - // Temporarily suspends multithreading. - // - // Existing worker threads are not terminated. All jobs enqueued when multithreading is - // suspended are executed synchronously. - // Must be called from the main thread. Jobs queue must be empty. Existing worker threads must - // be idle. - // - // Only V3MtDisabledLock class is supposed to use this function. - void suspendMultithreading() VL_MT_SAFE VL_EXCLUDES(m_mutex) VL_EXCLUDES(m_stoppedJobsMutex); - - // Resumes multithreading suspended previously by call tosuspendMultithreading(). - // - // Only V3MtDisabledLock class is supposed to use this function. - void resumeMultithreading() VL_MT_SAFE VL_EXCLUDES(m_mutex) VL_EXCLUDES(m_stoppedJobsMutex); - - template - static std::list waitForFuturesImp(std::list>& futures) { - std::list results; - while (!futures.empty()) { - results.push_back(V3ThreadPool::waitForFuture(futures.front())); - futures.pop_front(); - } - return results; - } - - static void waitForFuturesImp(std::list>& futures) { - while (!futures.empty()) { - V3ThreadPool::waitForFuture(futures.front()); - futures.pop_front(); - } - } - bool willExecuteSynchronously() const VL_MT_SAFE { - return m_workers.empty() || m_exclusiveAccess; - } - - // True when any thread requested exclusive access - bool stopRequested() const VL_MT_SAFE { - if (m_exclusiveAccess) return false; - // don't wait if shutdown already requested - if (m_shutdown) return false; - return m_stopRequested; - } - - // Waits until `resumeOtherThreads()` is called or exclusive access scope end. - void waitForResumeRequest() VL_REQUIRES(m_stoppedJobsMutex); - - // Sends stop request to other threads and waits until they stop. - void stopOtherThreads() VL_MT_SAFE_EXCLUDES(m_mutex) VL_REQUIRES(m_stoppedJobsMutex); - - // Resumes threads stopped through previous call to `stopOtherThreads()`. - void resumeOtherThreads() VL_MT_SAFE_EXCLUDES(m_mutex) VL_REQUIRES(m_stoppedJobsMutex) { - m_stopRequested = false; - m_stoppedJobsCV.notify_all(); - } - - void workerJobLoop(int id) VL_MT_SAFE; - - static void startWorker(V3ThreadPool* selfThreadp, int id) VL_MT_SAFE; + // For access to enqueue() and wait() + friend class V3ThreadScope; }; -class VL_SCOPED_CAPABILITY V3ThreadPool::ScopedExclusiveAccess final { +// The actual interface for submitting jobs and ensuring their completion. +// Ensures that jobs are started and completed within a given scope. +class V3ThreadScope final { + // MEMBERS + V3ThreadPool* m_pool = nullptr; // Global thread pool instance + public: - ScopedExclusiveAccess() VL_ACQUIRE(V3ThreadPool::s().m_stoppedJobsMutex) VL_MT_SAFE { - if (!V3ThreadPool::s().willExecuteSynchronously()) { - V3ThreadPool::s().m_stoppedJobsMutex.lock(); + // CONSTRUCTORS + V3ThreadScope() VL_MT_SAFE VL_ACQUIRE(VlOs::MtScopeMutex::s_haveThreadScope); + ~V3ThreadScope() VL_MT_SAFE VL_RELEASE(VlOs::MtScopeMutex::s_haveThreadScope) { wait(); } + VL_UNCOPYABLE(V3ThreadScope); + VL_UNMOVABLE(V3ThreadScope); - if (V3ThreadPool::s().stopRequested()) V3ThreadPool::s().waitForResumeRequest(); - V3ThreadPool::s().stopOtherThreads(); - V3ThreadPool::s().m_exclusiveAccess = true; - } else { - V3ThreadPool::s().m_stoppedJobsMutex.assumeLocked(); - } - } - ~ScopedExclusiveAccess() VL_RELEASE(V3ThreadPool::s().m_stoppedJobsMutex) VL_MT_SAFE { - // Can't use `willExecuteSynchronously`, we're still in exclusive execution state. - if (V3ThreadPool::s().m_exclusiveAccess) { - V3ThreadPool::s().m_exclusiveAccess = false; - V3ThreadPool::s().resumeOtherThreads(); - - V3ThreadPool::s().m_stoppedJobsMutex.unlock(); - // wait for all threads to resume - while (V3ThreadPool::s().m_stoppedJobs != 0) {} - } else { - V3ThreadPool::s().m_stoppedJobsMutex.pretendUnlock(); - } - } + // METHODS + // Submit job to the thread pool instance + void enqueue(std::function&& f) VL_MT_START; + // Wait for thread pool's jobs completion + void wait() VL_MT_SAFE VL_REQUIRES(VlOs::MtScopeMutex::s_haveThreadScope); }; -template -T V3ThreadPool::waitForFuture(std::future& future) VL_MT_SAFE_EXCLUDES(m_mutex) { - while (true) { - V3ThreadPool::s().waitIfStopRequested(); - { - std::future_status status - = future.wait_for(std::chrono::milliseconds(V3ThreadPool::FUTUREWAITFOR_MS)); - switch (status) { - case std::future_status::deferred: continue; - case std::future_status::timeout: continue; - case std::future_status::ready: return future.get(); - } - } - } -} - -template -auto V3ThreadPool::enqueue(Callable&& f) VL_MT_START { - using result_t = decltype(f()); - auto&& job = std::packaged_task{std::forward(f)}; - auto future = job.get_future(); - if (willExecuteSynchronously()) { - job(); - } else { - { - const V3LockGuard guard{m_mutex}; - m_queue.push(std::move(job)); - } - m_cv.notify_one(); - } - return future; -} - -template -void V3ThreadPool::requestExclusiveAccess(Callable&& exclusiveAccessJob) VL_MT_SAFE - VL_EXCLUDES(m_stoppedJobsMutex) { - ScopedExclusiveAccess exclusive_access; - exclusiveAccessJob(); -} - #endif // Guard diff --git a/src/V3ThreadSafety.h b/src/V3ThreadSafety.h deleted file mode 100644 index 0b62ce9a3..000000000 --- a/src/V3ThreadSafety.h +++ /dev/null @@ -1,73 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -//************************************************************************* -// DESCRIPTION: Verilator: Definitions for thread safety checking -// -// Code available from: https://verilator.org -// -//************************************************************************* -// -// Copyright 2003-2024 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -// -//************************************************************************* - -#ifndef VERILATOR_V3THREADSAFETY_H_ -#define VERILATOR_V3THREADSAFETY_H_ - -#include - -#include - -// A class that works as an indicator of MT_DISABLED context. -// It uses Clang's thread safety analysis (-fthread-safety) to do its work. -// Its use will most likely be optimized out (or at least reduced to a few insignificant symbols -// or instructions) during compilation. -class VL_CAPABILITY("lock") V3MtDisabledLock final { - friend class V3MtDisabledLockInstanceAccessor; - - static V3MtDisabledLock s_mtDisabledLock; - - constexpr V3MtDisabledLock() = default; - ~V3MtDisabledLock() = default; - VL_UNCOPYABLE(V3MtDisabledLock); - VL_UNMOVABLE(V3MtDisabledLock); - -public: - // lock() will disable multithreading while in MT Disabled regions - void lock() VL_ACQUIRE() VL_MT_SAFE; - // unlock() will reenable multithreading while in MT Disabled regions - void unlock() VL_RELEASE() VL_MT_SAFE; - - static constexpr V3MtDisabledLock& instance() - VL_RETURN_CAPABILITY(V3MtDisabledLock::s_mtDisabledLock) { - return s_mtDisabledLock; - } -}; - -// A class providing mutable access to V3MtDisabledLock::s_mtDisabledLock. -// This is a class because VL_RETURN_CAPABILITY works only on methods, not free functions. -// This is not a method in V3MtDisabledLock itself as a method declaration inside #ifdef block -// woudl break ODR. -class V3MtDisabledLockInstanceAccessor final { -public: - constexpr V3MtDisabledLock& operator()() const - VL_RETURN_CAPABILITY(V3MtDisabledLock::s_mtDisabledLock) { - return V3MtDisabledLock::s_mtDisabledLock; - } -}; -// Create a global object which can be called like a function. -static constexpr V3MtDisabledLockInstanceAccessor v3MtDisabledLock VL_ATTR_UNUSED; - -using V3MtDisabledLockGuard = V3LockGuardImp; - -// Annotated function can be called only in MT_DISABLED context, i.e. either in a code unit -// compiled with VL_MT_DISABLED_CODE_UNIT preprocessor definition, or after obtaining a lock on -// v3MtDisabledLock(). -#define VL_MT_DISABLED \ - VL_CLANG_ATTR(annotate("MT_DISABLED")) \ - VL_REQUIRES(V3MtDisabledLock::instance()) - -#endif // guard diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp index f1bbd8988..ff0514d40 100644 --- a/src/V3Timing.cpp +++ b/src/V3Timing.cpp @@ -445,6 +445,8 @@ class TimingControlVisitor final : public VNVisitor { // NODE STATE // Ast{Always,NodeCCall,Fork,NodeAssign}::user1() -> bool. Set true if the node has // been processed. + // AstAssignW::user1() -> bool. Set true if the assignment + // represents the net delay // AstSenTree::user1() -> AstVarScope*. Trigger scheduler assigned // to this sentree // Ast{NodeProcedure,CFunc,Begin}::user2() -> bool. Set true if process/task @@ -471,7 +473,9 @@ class TimingControlVisitor final : public VNVisitor { // Unique names V3UniqueNames m_dlyforkNames{"__Vdlyfork"}; // Names for temp AssignW vars - V3UniqueNames m_contAssignVarNames{"__VassignWtmp"}; // Names for temp AssignW vars + V3UniqueNames m_contAsgnTmpNames{"__VassignWtmp"}; // Names for temp AssignW vars + V3UniqueNames m_contAsgnGenNames{"__VassignWgen"}; // Continuous assign generation name + // generator V3UniqueNames m_intraValueNames{"__Vintraval"}; // Intra assign delay value var names V3UniqueNames m_intraIndexNames{"__Vintraidx"}; // Intra assign delay index var names V3UniqueNames m_intraLsbNames{"__Vintralsb"}; // Intra assign delay LSB var names @@ -493,47 +497,24 @@ class TimingControlVisitor final : public VNVisitor { SenExprBuilder* m_senExprBuilderp = nullptr; // Sens expression builder for current m_scope // METHODS - // Find net delay on the LHS of an assignment - AstDelay* getLhsNetDelayRecurse(const AstNodeExpr* const nodep) const { - if (const AstNodeVarRef* const refp = VN_CAST(nodep, NodeVarRef)) { - if (refp->varp()->delayp()) return refp->varp()->delayp()->unlinkFrBack(); - } else if (const AstSel* const selp = VN_CAST(nodep, Sel)) { - return getLhsNetDelayRecurse(selp->fromp()); - } - return nullptr; - } // Transform an assignment with an intra timing control into a timing control with the // assignment under it AstNode* factorOutTimingControl(AstNodeAssign* nodep) const { AstNode* stmtp = nodep; - AstDelay* delayp = getLhsNetDelayRecurse(nodep->lhsp()); - FileLine* const flp = nodep->fileline(); AstNode* const controlp = nodep->timingControlp(); - if (controlp) { - controlp->unlinkFrBack(); - if (auto* const assignDelayp = VN_CAST(controlp, Delay)) { - if (delayp) { - delayp->lhsp(new AstAdd{flp, delayp->lhsp()->unlinkFrBack(), - assignDelayp->lhsp()->unlinkFrBack()}); - VL_DO_DANGLING(assignDelayp->deleteTree(), nodep); - } else { - delayp = assignDelayp; - } - } - } - if (delayp) { - stmtp->replaceWith(delayp); + if (AstDelay* const delayp = VN_CAST(controlp, Delay)) { + stmtp->replaceWith(delayp->unlinkFrBack()); delayp->addStmtsp(stmtp); stmtp = delayp; - } - if (auto* const sensesp = VN_CAST(controlp, SenTree)) { - auto* const eventControlp = new AstEventControl{flp, sensesp, nullptr}; + } else if (AstSenTree* const sensesp = VN_CAST(controlp, SenTree)) { + AstEventControl* const eventControlp + = new AstEventControl{sensesp->fileline(), sensesp->unlinkFrBack(), nullptr}; stmtp->replaceWith(eventControlp); eventControlp->addStmtsp(stmtp); stmtp = eventControlp; - } else if (auto* const beginp = VN_CAST(controlp, Begin)) { + } else if (AstBegin* const beginp = VN_CAST(controlp, Begin)) { // Begin from V3AssertPre - stmtp->replaceWith(beginp); + stmtp->replaceWith(beginp->unlinkFrBack()); beginp->addStmtsp(stmtp); stmtp = beginp; } @@ -925,12 +906,6 @@ class TimingControlVisitor final : public VNVisitor { // Do not allow waiting on local named events, as they get enqueued for clearing, but can // go out of scope before that happens if (!nodep->sensesp()) nodep->v3warn(E_UNSUPPORTED, "Unsupported: no sense equation (@*)"); - if (nodep->sensesp()->exists([](const AstNodeVarRef* refp) { - AstBasicDType* const dtypep = refp->dtypep()->skipRefp()->basicp(); - return dtypep && dtypep->isEvent() && refp->varp()->isFuncLocal(); - })) { - nodep->v3warn(E_UNSUPPORTED, "Unsupported: waiting on local event variables"); - } FileLine* const flp = nodep->fileline(); // Relink child statements after the event control if (nodep->stmtsp()) nodep->addNextHere(nodep->stmtsp()->unlinkFrBackWithNext()); @@ -1068,58 +1043,106 @@ class TimingControlVisitor final : public VNVisitor { controlp->addHereThisAsNext( new AstAssign{flp, new AstVarRef{flp, newvscp, VAccess::WRITE}, valuep}); }; - // Create the intermediate select vars. Note: because 'foreach' proceeds in - // pre-order, and we replace indices in selects with variables, we cannot - // reach another select under the index position. This is exactly what - // we want as only the top level selects are LValues. As an example, - // this transforms 'x[a[i]][b[j]] = y' - // into 't1 = a[i]; t0 = b[j]; x[t1][t0] = y'. - nodep->lhsp()->foreach([&](AstSel* selp) { - if (VN_IS(selp->lsbp(), Const)) return; - replaceWithIntermediate(selp->lsbp(), m_intraLsbNames.get(nodep)); - // widthp should be const - }); - nodep->lhsp()->foreach([&](AstNodeSel* selp) { - if (VN_IS(selp->bitp(), Const)) return; - replaceWithIntermediate(selp->bitp(), m_intraIndexNames.get(nodep)); - }); + // NBAs with delays evaluate LHS indices immediately + if (inAssignDly) { + // Create the intermediate select vars. Note: because 'foreach' proceeds in pre-order, + // and we replace indices in selects with variables, we cannot reach another select + // under the index position. This is exactly what we want as only the top level selects + // are LValues. As an example, this transforms 'x[a[i]][b[j]] = y' into 't1 = a[i]; t0 + // = b[j]; x[t1][t0] = y'. + nodep->lhsp()->foreach([&](AstSel* selp) { + if (VN_IS(selp->lsbp(), Const)) return; + replaceWithIntermediate(selp->lsbp(), m_intraLsbNames.get(nodep)); + // widthp should be const + }); + nodep->lhsp()->foreach([&](AstNodeSel* selp) { + if (VN_IS(selp->bitp(), Const)) return; + replaceWithIntermediate(selp->bitp(), m_intraIndexNames.get(nodep)); + }); + } // Replace the RHS with an intermediate value var replaceWithIntermediate(nodep->rhsp(), m_intraValueNames.get(nodep)); } void visit(AstAssignW* nodep) override { - AstDelay* const netDelayp = getLhsNetDelayRecurse(nodep->lhsp()); - if (!netDelayp && !nodep->timingControlp()) return; - // This assignment will be converted to an always. In some cases this may generate an - // UNOPTFLAT, e.g.: assign #1 clk = ~clk. We create a temp var for the LHS of this - // assign, to disable the UNOPTFLAT warning for it. - // TODO: Find a way to do this without introducing this var. Perhaps make - // V3SchedAcyclic recognize awaits and prevent it from treating this kind of logic as - // cyclic - AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack(); - std::string varname; - if (auto* const refp = VN_CAST(lhsp, VarRef)) { - varname = m_contAssignVarNames.get(refp->name()); - } else { - varname = m_contAssignVarNames.get(lhsp); - } - auto* const tempvscp = m_scopep->createTemp(varname, lhsp->dtypep()); - tempvscp->varp()->delayp(netDelayp); FileLine* const flp = nodep->fileline(); + // Get the net delay unless this assignment was created for handling the net delay (user1) + AstDelay* const netDelayp = nodep->user1() ? nullptr : nodep->getLhsNetDelay(); + if (netDelayp) { + if (nodep->timingControlp()) { + // If this assignment has a delay, create another one to handle the net delay + AstVarScope* const newvscp + = createTemp(flp, m_contAsgnTmpNames.get(nodep), nodep->dtypep()); + AstAssignW* assignp = new AstAssignW{ + nodep->fileline(), nodep->lhsp()->unlinkFrBack(), + new AstVarRef{flp, newvscp, VAccess::READ}, netDelayp->cloneTree(false)}; + assignp->user1(true); + nodep->addNextHere(assignp); + nodep->lhsp(new AstVarRef{flp, newvscp, VAccess::WRITE}); + } else { + // Else just use this one with the net delay + nodep->timingControlp(netDelayp->cloneTree(false)); + } + } + if (!nodep->timingControlp()) return; + // There will be some circular logic here, suppress the warning for newly created vars flp->modifyWarnOff(V3ErrorCode::UNOPTFLAT, true); - tempvscp->fileline(flp); - tempvscp->varp()->fileline(flp); - // Remap the LHS to the new temp var - nodep->lhsp(new AstVarRef{flp, tempvscp, VAccess::WRITE}); + // Also suppress the warning for the LHS var, for cases like `assign #1 clk = ~clk;` + // TODO: Restore the warning for other, non-delayed drivers + nodep->lhsp()->foreach([](AstVarRef* refp) { + if (refp->access().isWriteOrRW()) { + refp->varp()->fileline()->modifyWarnOff(V3ErrorCode::UNOPTFLAT, true); + } + }); // Convert it to an always; the new assign with intra delay will be handled by // visit(AstNodeAssign*) AstAlways* const alwaysp = nodep->convertToAlways(); - visit(alwaysp); - // Put the LHS back in the AssignW; put the temp var on the RHS - nodep->lhsp(lhsp); - nodep->rhsp(new AstVarRef{flp, tempvscp, VAccess::READ}); - // Put the AssignW right after the always. Different order can produce UNOPTFLAT on the LHS - // var - alwaysp->addNextHere(nodep); + visit(alwaysp); // Visit now as we need to do some post-processing + VL_DO_DANGLING(nodep->deleteTree(), nodep); + // IEEE 1800-2023 10.3.3 - if the RHS value differs from the currently scheduled value to + // be assigned, the currently scheduled assignment is descheduled. To keep track if an + // assignment should be descheduled, each scheduled assignment event has a 'generation', + // and if at assignment time its generation differs from the current generation, it won't + // be performed + AstFork* const forkp = VN_AS(alwaysp->stmtsp(), Fork); + UASSERT_OBJ(forkp, alwaysp, "Fork should be there from convertToAlways()"); + AstBegin* const beginp = VN_AS(forkp->stmtsp(), Begin); + UASSERT_OBJ(beginp, alwaysp, "Begin should be there from convertToAlways()"); + AstAssign* const preAssignp = VN_AS(beginp->stmtsp(), Assign); + UASSERT_OBJ(preAssignp, alwaysp, "Pre-assign should be there from convertToAlways()"); + AstAssign* const postAssignp = VN_AS(preAssignp->nextp()->nextp(), Assign); + UASSERT_OBJ(postAssignp, alwaysp, "Post-assign should be there from convertToAlways()"); + // Increment generation and copy it to a local + AstVarScope* const generationVarp + = createTemp(flp, m_contAsgnGenNames.get(alwaysp), alwaysp->findUInt64DType()); + AstVarScope* const genLocalVarp + = createTemp(flp, generationVarp->varp()->name() + "__local", + alwaysp->findUInt64DType(), preAssignp); + preAssignp->addHereThisAsNext( + new AstAssign{flp, new AstVarRef{flp, generationVarp, VAccess::WRITE}, + new AstAdd{flp, new AstVarRef{flp, generationVarp, VAccess::READ}, + new AstConst{flp, 1}}}); + preAssignp->addHereThisAsNext( + new AstAssign{flp, new AstVarRef{flp, genLocalVarp, VAccess::WRITE}, + new AstVarRef{flp, generationVarp, VAccess::READ}}); + // If the current generation is same as the one saved in the local var, assign + beginp->addStmtsp( + new AstIf{flp, + new AstEq{flp, new AstVarRef{flp, generationVarp, VAccess::READ}, + new AstVarRef{flp, genLocalVarp, VAccess::READ}}, + postAssignp->unlinkFrBack()}); + // Save scheduled RHS value before delay + AstVarScope* const tmpVarp + = createTemp(flp, m_contAsgnTmpNames.get(alwaysp), preAssignp->rhsp()->dtypep()); + AstVarRef* const tmpAssignRhsp = VN_AS(preAssignp->lhsp(), VarRef)->cloneTree(false); + tmpAssignRhsp->access(VAccess::WRITE); + preAssignp->addNextHere( + new AstAssign{flp, new AstVarRef{flp, tmpVarp, VAccess::WRITE}, tmpAssignRhsp}); + // If the RHS is different from the currently scheduled value, schedule the new assignment + // The generation will increase, effectively 'descheduling' the previous assignment. + alwaysp->addStmtsp(new AstIf{flp, + new AstNeq{flp, preAssignp->rhsp()->cloneTree(false), + new AstVarRef{flp, tmpVarp, VAccess::READ}}, + forkp->unlinkFrBack()}); } void visit(AstDisableFork* nodep) override { if (hasFlags(m_procp, T_HAS_PROC)) return; diff --git a/src/V3Timing.h b/src/V3Timing.h index 7d53d456b..f1704d3b1 100644 --- a/src/V3Timing.h +++ b/src/V3Timing.h @@ -21,7 +21,6 @@ #include "verilatedos.h" #include "V3Ast.h" -#include "V3ThreadSafety.h" //============================================================================ diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp index 9bd2e21ad..6022bc377 100644 --- a/src/V3Trace.cpp +++ b/src/V3Trace.cpp @@ -175,6 +175,7 @@ class TraceVisitor final : public VNVisitor { AstScope* const m_topScopep = v3Global.rootp()->topScopep()->scopep(); // The top AstScope AstCFunc* m_cfuncp = nullptr; // C function adding to graph AstCFunc* m_regFuncp = nullptr; // Trace registration function + AstCFunc* m_actAllFuncp = nullptr; // Set all activity function AstTraceDecl* m_tracep = nullptr; // Trace function adding to graph AstVarScope* m_activityVscp = nullptr; // Activity variable uint32_t m_activityNumber = 0; // Count of fields in activity variable @@ -187,8 +188,10 @@ class TraceVisitor final : public VNVisitor { const uint32_t m_parallelism = v3Global.opt.useTraceParallel() ? static_cast(v3Global.opt.threads()) : 1; - VDouble0 m_statUniqSigs; // Statistic tracking + VDouble0 m_statSetters; // Statistic tracking + VDouble0 m_statSettersSlow; // Statistic tracking VDouble0 m_statUniqCodes; // Statistic tracking + VDouble0 m_statUniqSigs; // Statistic tracking // All activity numbers applying to a given trace using ActCodeSet = std::set; @@ -395,25 +398,32 @@ class TraceVisitor final : public VNVisitor { return new AstArraySel(flp, new AstVarRef{flp, m_activityVscp, access}, acode); } - void addActivitySetter(AstNode* insertp, uint32_t code) { + AstNode* newActivitySetter(AstNode* insertp, uint32_t code) { + ++m_statSetters; FileLine* const fl = insertp->fileline(); AstAssign* const setterp = new AstAssign{fl, selectActivity(fl, code, VAccess::WRITE), new AstConst{fl, AstConst::BitTrue{}}}; - if (AstStmtExpr* const stmtp = VN_CAST(insertp, StmtExpr)) { - stmtp->addNextHere(setterp); - } else if (AstCFunc* const funcp = VN_CAST(insertp, CFunc)) { - // If there are awaits, insert the setter after each await - if (funcp->isCoroutine() && funcp->stmtsp()) { - funcp->stmtsp()->foreachAndNext([&](AstCAwait* awaitp) { - AstNode* stmtp = awaitp->backp(); - while (VN_IS(stmtp, NodeExpr)) stmtp = stmtp->backp(); - stmtp->addNextHere(setterp->cloneTree(false)); - }); + return setterp; + } + + AstNode* newActivityAll(AstNode* insertp) { + ++m_statSettersSlow; + if (!m_actAllFuncp) { + FileLine* const flp = m_topScopep->fileline(); + AstCFunc* const funcp = new AstCFunc{flp, "__Vm_traceActivitySetAll", m_topScopep}; + funcp->slow(true); + funcp->isStatic(false); + funcp->isLoose(true); + m_topScopep->addBlocksp(funcp); + for (uint32_t code = 0; code < m_activityNumber; ++code) { + AstNode* const setterp = newActivitySetter(insertp, code); + funcp->addStmtsp(setterp); } - funcp->addStmtsp(setterp); - } else { - insertp->v3fatalSrc("Bad trace activity vertex"); + m_actAllFuncp = funcp; } + AstCCall* const callp = new AstCCall{insertp->fileline(), m_actAllFuncp}; + callp->dtypeSetVoid(); + return callp->makeStmt(); } void createActivityFlags() { @@ -441,14 +451,31 @@ class TraceVisitor final : public VNVisitor { // Insert activity setters for (const V3GraphVertex& vtx : m_graph.vertices()) { if (const TraceActivityVertex* const vtxp = vtx.cast()) { + AstNode* setterp = nullptr; if (vtxp->activitySlow()) { + setterp = newActivityAll(vtxp->insertp()); // Just set all flags in slow code as it should be rare. // This will be rolled up into a loop by V3Reloop. - for (uint32_t code = 0; code < m_activityNumber; ++code) { - addActivitySetter(vtxp->insertp(), code); - } } else if (!vtxp->activityAlways()) { - addActivitySetter(vtxp->insertp(), vtxp->activityCode()); + setterp = newActivitySetter(vtxp->insertp(), vtxp->activityCode()); + } + if (setterp) { + AstNode* const insertp = vtxp->insertp(); + if (AstStmtExpr* const stmtp = VN_CAST(insertp, StmtExpr)) { + stmtp->addNextHere(setterp); + } else if (AstCFunc* const funcp = VN_CAST(insertp, CFunc)) { + // If there are awaits, insert the setter after each await + if (funcp->isCoroutine() && funcp->stmtsp()) { + funcp->stmtsp()->foreachAndNext([&](AstCAwait* awaitp) { + AstNode* stmtp = awaitp->backp(); + while (VN_IS(stmtp, NodeExpr)) stmtp = stmtp->backp(); + stmtp->addNextHere(setterp->cloneTree(false)); + }); + } + funcp->addStmtsp(setterp); + } else { + insertp->v3fatalSrc("Bad trace activity vertex"); + } } } } @@ -681,7 +708,13 @@ class TraceVisitor final : public VNVisitor { // Track splitting due to size UASSERT_OBJ(incFulp->nodeCount() == incChgp->nodeCount(), declp, "Should have equal cost"); - subStmts += incChgp->nodeCount(); + const VNumRange range = declp->arrayRange(); + if (range.ranged()) { + // 2x because each element is a TraceInc and a VarRef + subStmts += range.elements() * 2; + } else { + subStmts += incChgp->nodeCount(); + } // Track partitioning nCodes += declp->codeInc(); @@ -901,8 +934,10 @@ public: iterate(nodep); } ~TraceVisitor() override { - V3Stats::addStat("Tracing, Unique traced signals", m_statUniqSigs); + V3Stats::addStat("Tracing, Activity setters", m_statSetters); + V3Stats::addStat("Tracing, Activity slow blocks", m_statSettersSlow); V3Stats::addStat("Tracing, Unique trace codes", m_statUniqCodes); + V3Stats::addStat("Tracing, Unique traced signals", m_statUniqSigs); } }; diff --git a/src/V3Trace.h b/src/V3Trace.h index bcb884d97..4dc831b33 100644 --- a/src/V3Trace.h +++ b/src/V3Trace.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3TraceDecl.h b/src/V3TraceDecl.h index ff9dacc98..013e625f8 100644 --- a/src/V3TraceDecl.h +++ b/src/V3TraceDecl.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp index 7472770b3..6663c879e 100644 --- a/src/V3Tristate.cpp +++ b/src/V3Tristate.cpp @@ -914,6 +914,51 @@ class TristateVisitor final : public TristateBaseVisitor { || (strength1 <= strength && assignmentOfValueOnAllBits(assignp, 1)); } + AstNodeExpr* newMergeExpr(AstNodeExpr* const lhsp, AstNodeExpr* const rhsp, FileLine* const fl, + bool isWor) { + AstNodeExpr* expr = nullptr; + if (isWor) + expr = new AstOr{fl, lhsp, rhsp}; + else + expr = new AstAnd{fl, lhsp, rhsp}; + return expr; + } + + void mergeWiredNetsAssignments() { + // Support for WOR/TRIOR/WAND/TRIAND, by merging the Assignments for the + // same Net (merge by or for WOR/TIOR and merge by and for WAND/TRIAND). + for (auto& varpAssigns : m_assigns) { + Assigns& assigns = varpAssigns.second; + if (assigns.size() > 1) { + AstVar* varp = varpAssigns.first; + if (varp->isWiredNet()) { + auto it = assigns.begin(); + AstAssignW* const assignWp0 = *it; + FileLine* const fl = assignWp0->fileline(); + AstNodeExpr* wExp = nullptr; + while (++it != assigns.end()) { + AstAssignW* assignWpi = *it; + if (!wExp) { + wExp = newMergeExpr(assignWp0->rhsp()->cloneTreePure(false), + assignWpi->rhsp()->cloneTreePure(false), fl, + varp->isWor()); + } else { + wExp = newMergeExpr(wExp, assignWpi->rhsp()->cloneTreePure(false), fl, + varp->isWor()); + } + VL_DO_DANGLING((assignWpi->unlinkFrBack()->deleteTree()), assignWpi); + } + AstVarRef* const wVarRef = new AstVarRef{fl, varp, VAccess::WRITE}; + AstAssignW* const wAssignp = new AstAssignW{fl, wVarRef, wExp}; + assignWp0->replaceWith(wAssignp); + VL_DO_DANGLING(pushDeletep(assignWp0), assignWp0); + assigns.clear(); + assigns.push_back(wAssignp); + } + } + } + } + void removeNotStrongerAssignments(Assigns& assigns, AstAssignW* strongestp, uint8_t greatestKnownStrength) { // Weaker assignments are these assignments that can't change the final value of the net. @@ -1247,7 +1292,10 @@ class TristateVisitor final : public TristateBaseVisitor { VL_RESTORER(m_alhs); VL_RESTORER(m_currentStrength); if (m_graphing) { - if (AstAssignW* assignWp = VN_CAST(nodep, AssignW)) addToAssignmentList(assignWp); + if (AstAssignW* assignWp = VN_CAST(nodep, AssignW)) { + if (assignWp->timingControlp() || assignWp->getLhsNetDelay()) return; + addToAssignmentList(assignWp); + } if (nodep->user2() & U2_GRAPHING) return; VL_RESTORER(m_logicp); @@ -1385,7 +1433,6 @@ class TristateVisitor final : public TristateBaseVisitor { dropop[1] = VN_IS(nodep->thsp(), Const) && VN_AS(nodep->thsp(), Const)->num().isAnyZ(); dropop[2] = VN_IS(nodep->fhsp(), Const) && VN_AS(nodep->fhsp(), Const)->num().isAnyZ(); UINFO(4, " COUNTBITS(" << dropop[0] << dropop[1] << dropop[2] << " " << nodep << endl); - const AstVarRef* const varrefp = VN_AS(nodep->lhsp(), VarRef); // Input variable if (m_graphing) { iterateAndNextNull(nodep->lhsp()); if (!dropop[0]) iterateAndNextNull(nodep->rhsp()); @@ -1406,7 +1453,8 @@ class TristateVisitor final : public TristateBaseVisitor { // do so at present, we only compare if there is a z in the equation. Otherwise // we'd need to attach an enable to every signal, then optimize them away later // when we determine the signal has no tristate - if (!VN_IS(nodep->lhsp(), VarRef)) { + const AstVarRef* const varrefp = VN_CAST(nodep->lhsp(), VarRef); // Input variable + if (!varrefp) { nodep->v3warn(E_UNSUPPORTED, "Unsupported LHS tristate construct: " << nodep->prettyTypeName()); return; @@ -1773,6 +1821,8 @@ class TristateVisitor final : public TristateBaseVisitor { iterateChildren(nodep); m_graphing = false; } + // Merge the assignments for very Wired net LHS : wor, trior, wand and triand + mergeWiredNetsAssignments(); // Remove all assignments not stronger than the strongest uniform constant removeAssignmentsNotStrongerThanUniformConstant(); // Use graph to find tristate signals diff --git a/src/V3Tristate.h b/src/V3Tristate.h index 98a498bbb..791621668 100644 --- a/src/V3Tristate.h +++ b/src/V3Tristate.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Undriven.h b/src/V3Undriven.h index 1a9c2de65..3dd1a6550 100644 --- a/src/V3Undriven.h +++ b/src/V3Undriven.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp index 632793693..13107c8a4 100644 --- a/src/V3Unknown.cpp +++ b/src/V3Unknown.cpp @@ -48,6 +48,7 @@ class UnknownVisitor final : public VNVisitor { // AstNode::user2p() -> AstIf* Inserted if assignment for conditional const VNUser1InUse m_inuser1; const VNUser2InUse m_inuser2; + static const std::string m_xrandPrefix; // STATE AstNodeModule* m_modp = nullptr; // Current module @@ -58,7 +59,7 @@ class UnknownVisitor final : public VNVisitor { bool m_allowXUnique = true; // Allow unique assignments VDouble0 m_statUnkVars; // Statistic tracking V3UniqueNames m_lvboundNames; // For generating unique temporary variable names - V3UniqueNames m_xrandNames; // For generating unique temporary variable names + std::unique_ptr m_xrandNames; // For generating unique temporary variable names // METHODS @@ -118,6 +119,28 @@ class UnknownVisitor final : public VNVisitor { = new AstVar{fl, VVarType::MODULETEMP, m_lvboundNames.get(prep), prep->dtypep()}; m_modp->addStmtsp(varp); AstNode* const abovep = prep->backp(); // Grab above point before we replace 'prep' + AstNode* currentStmtp = abovep; + while (currentStmtp && !VN_IS(currentStmtp, NodeStmt)) + currentStmtp = currentStmtp->backp(); + VNRelinker linkContext; + currentStmtp = currentStmtp->unlinkFrBackWithNext(&linkContext); + AstNodeExpr* const selExprp = prep->cloneTree(true); + AstNodeExpr* currentExprp = selExprp; + while (AstNodeExpr* itrSelExprp = VN_AS(currentExprp->op1p(), NodeExpr)) { + if (AstVarRef* const selRefp = VN_CAST(itrSelExprp, VarRef)) { + // Mark the variable reference as READ access to avoid assignment issues + selRefp->access(VAccess::READ); + break; + } + currentExprp = itrSelExprp; + } + // Before assigning the value to the temporary variable, first assign the current array + // element to it. This ensures any field modifications happen on the correct instance + // and prevents overwriting other fields. + AstNode* const newAssignp + = new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE}, selExprp}; + newAssignp->addNextStmt(currentStmtp, newAssignp); + linkContext.relink(newAssignp); prep->replaceWith(new AstVarRef{fl, varp, VAccess::WRITE}); if (m_timingControlp) m_timingControlp->unlinkFrBack(); AstIf* const newp = new AstIf{ @@ -141,14 +164,16 @@ class UnknownVisitor final : public VNVisitor { VL_RESTORER(m_modp); VL_RESTORER(m_constXCvt); VL_RESTORER(m_allowXUnique); + auto xrandNames = std::make_unique(m_xrandPrefix); { m_modp = nodep; m_constXCvt = true; // Class X randomization causes Vxrand in strange places, so disable if (VN_IS(nodep, Class)) m_allowXUnique = false; m_lvboundNames.reset(); - m_xrandNames.reset(); + xrandNames.swap(m_xrandNames); iterateChildren(nodep); + xrandNames.swap(m_xrandNames); } } void visit(AstAssignDly* nodep) override { @@ -345,7 +370,7 @@ class UnknownVisitor final : public VNVisitor { // We use the special XTEMP type so it doesn't break pure functions UASSERT_OBJ(m_modp, nodep, "X number not under module"); AstVar* const newvarp - = new AstVar{nodep->fileline(), VVarType::XTEMP, m_xrandNames.get(nodep), + = new AstVar{nodep->fileline(), VVarType::XTEMP, m_xrandNames->get(nodep), VFlagLogicPacked{}, nodep->width()}; newvarp->lifetime(VLifetime::STATIC); ++m_statUnkVars; @@ -410,8 +435,10 @@ class UnknownVisitor final : public VNVisitor { nodep->unlinkFrBack(&replaceHandle); V3Number xnum{nodep, nodep->width()}; xnum.setAllBitsX(); - AstNode* const newp = new AstCondBound{nodep->fileline(), condp, nodep, - new AstConst{nodep->fileline(), xnum}}; + AstNodeExpr* const xexprp = new AstConst{nodep->fileline(), xnum}; + AstNodeExpr* const newp + = condp->isZero() ? xexprp + : new AstCondBound{nodep->fileline(), condp, nodep, xexprp}; if (debug() >= 9) newp->dumpTree("- _new: "); // Link in conditional replaceHandle.relink(newp); @@ -515,7 +542,7 @@ public: // CONSTRUCTORS explicit UnknownVisitor(AstNetlist* nodep) : m_lvboundNames{"__Vlvbound"} - , m_xrandNames{"__Vxrand"} { + , m_xrandNames{std::make_unique(m_xrandPrefix)} { iterate(nodep); } ~UnknownVisitor() override { // @@ -523,6 +550,8 @@ public: } }; +const std::string UnknownVisitor::m_xrandPrefix = "__Vxrand"; + //###################################################################### // Unknown class functions diff --git a/src/V3Unknown.h b/src/V3Unknown.h index 49d2c9ebe..b5967f5a1 100644 --- a/src/V3Unknown.h +++ b/src/V3Unknown.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ diff --git a/src/V3Unroll.h b/src/V3Unroll.h index 88cb4e7fb..f748171ca 100644 --- a/src/V3Unroll.h +++ b/src/V3Unroll.h @@ -22,7 +22,6 @@ #include "V3Ast.h" #include "V3Error.h" -#include "V3ThreadSafety.h" //============================================================================ /// Unroller with saved state, so caller can determine when pushDelete's are executed. diff --git a/src/V3VariableOrder.cpp b/src/V3VariableOrder.cpp index 292ce3dc2..0aad4a3d6 100644 --- a/src/V3VariableOrder.cpp +++ b/src/V3VariableOrder.cpp @@ -20,7 +20,7 @@ // //************************************************************************* -#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT +#include "V3PchAstMT.h" #include "V3VariableOrder.h" @@ -28,6 +28,7 @@ #include "V3EmitCBase.h" #include "V3ExecGraph.h" #include "V3TSP.h" +#include "V3ThreadPool.h" #include @@ -113,10 +114,10 @@ public: } bool operator<(const VarTspSorter& other) const { return m_serial < other.m_serial; } const MTaskIdVec& mTaskIds() const { return m_mTaskIds; } - int cost(const TspStateBase* otherp) const override { + int cost(const TspStateBase* otherp) const override VL_MT_SAFE { return cost(static_cast(otherp)); } - int cost(const VarTspSorter* otherp) const { + int cost(const VarTspSorter* otherp) const VL_MT_SAFE { // Compute the number of MTasks not shared (Hamming distance) int cost = 0; const size_t size = ExecMTask::numUsedIds(); @@ -127,22 +128,20 @@ public: uint32_t VarTspSorter::s_serialNext = 0; +struct VarAttributes final { + uint8_t stratum; // Roughly equivalent to alignment requirement, to avoid padding + bool anonOk; // Can be emitted as part of anonymous structure +}; class VariableOrder final { - // NODE STATE - // AstVar::user1() -> attributes, via m_attributes - const VNUser1InUse m_user1InUse; // AstVar - - struct VarAttributes final { - uint32_t stratum; // Roughly equivalent to alignment requirement, to avoid padding - bool anonOk; // Can be emitted as part of anonymous structure - }; - - AstUser1Allocator m_attributes; // Attributes used for sorting + std::unordered_map m_attributes; const MTaskAffinityMap& m_mTaskAffinity; + std::vector& m_varps; - VariableOrder(AstNodeModule* modp, const MTaskAffinityMap& mTaskAffinity) - : m_mTaskAffinity{mTaskAffinity} { + VariableOrder(AstNodeModule* modp, const MTaskAffinityMap& mTaskAffinity, + std::vector& varps) + : m_mTaskAffinity{mTaskAffinity} + , m_varps{varps} { orderModuleVars(modp); } ~VariableOrder() = default; @@ -157,8 +156,11 @@ class VariableOrder final { if (ap->isStatic() != bp->isStatic()) { // Non-statics before statics return bp->isStatic(); } - const auto& attrA = m_attributes(ap); - const auto& attrB = m_attributes(bp); + UASSERT(m_attributes.find(ap) != m_attributes.end() + && m_attributes.find(bp) != m_attributes.end(), + "m_attributes should be populated for each AstVar"); + const auto& attrA = m_attributes.at(ap); + const auto& attrB = m_attributes.at(bp); if (attrA.anonOk != attrB.anonOk) { // Anons before non-anons return attrA.anonOk; } @@ -209,58 +211,42 @@ class VariableOrder final { } void orderModuleVars(AstNodeModule* modp) { - std::vector varps; - // Unlink all module variables from the module, compute attributes for (AstNode *nodep = modp->stmtsp(), *nextp; nodep; nodep = nextp) { nextp = nodep->nextp(); if (AstVar* const varp = VN_CAST(nodep, Var)) { - // Unlink, add to vector - varp->unlinkFrBack(); - varps.push_back(varp); + m_varps.push_back(varp); + // Compute attributes up front - auto& attributes = m_attributes(varp); // Stratum const int sigbytes = varp->dtypeSkipRefp()->widthAlignBytes(); - attributes.stratum = (v3Global.opt.hierChild() && varp->isPrimaryIO()) ? 0 - : (varp->isUsedClock() && varp->widthMin() == 1) ? 1 - : VN_IS(varp->dtypeSkipRefp(), UnpackArrayDType) ? 9 - : (varp->basicp() && varp->basicp()->isOpaque()) ? 8 - : (varp->isScBv() || varp->isScBigUint()) ? 7 - : (sigbytes == 8) ? 6 - : (sigbytes == 4) ? 5 - : (sigbytes == 2) ? 3 - : (sigbytes == 1) ? 2 - : 10; - // Anonymous structure ok - attributes.anonOk = EmitCBase::isAnonOk(varp); + const uint8_t stratum = (v3Global.opt.hierChild() && varp->isPrimaryIO()) ? 0 + : (varp->isUsedClock() && varp->widthMin() == 1) ? 1 + : VN_IS(varp->dtypeSkipRefp(), UnpackArrayDType) ? 9 + : (varp->basicp() && varp->basicp()->isOpaque()) ? 8 + : (varp->isScBv() || varp->isScBigUint()) ? 7 + : (sigbytes == 8) ? 6 + : (sigbytes == 4) ? 5 + : (sigbytes == 2) ? 3 + : (sigbytes == 1) ? 2 + : 10; + m_attributes.emplace(varp, VarAttributes{stratum, EmitCBase::isAnonOk(varp)}); } } - if (!varps.empty()) { - // Sort variables + if (!m_varps.empty()) { if (!v3Global.opt.mtasks()) { - simpleSortVars(varps); + simpleSortVars(m_varps); } else { - tspSortVars(varps); + tspSortVars(m_varps); } - - // Insert them back under the module, in the new order, but at - // the front of the list so they come out first in dumps/XML. - auto it = varps.cbegin(); - AstVar* const firstp = *it++; - for (; it != varps.cend(); ++it) firstp->addNext(*it); - if (AstNode* const stmtsp = modp->stmtsp()) { - stmtsp->unlinkFrBackWithNext(); - AstNode::addNext(firstp, stmtsp); - } - modp->addStmtsp(firstp); } } public: - static void processModule(AstNodeModule* modp, const MTaskAffinityMap& mTaskAffinity) { - VariableOrder{modp, mTaskAffinity}; + static void processModule(AstNodeModule* modp, const MTaskAffinityMap& mTaskAffinity, + std::vector& varps) VL_MT_STABLE { + VariableOrder{modp, mTaskAffinity, varps}; } }; @@ -280,11 +266,44 @@ void V3VariableOrder::orderAll(AstNetlist* netlistp) { } }); } + if (v3Global.opt.stats()) V3Stats::statsStage("variableorder-gather"); - // Order variables in each module + // Sort variables for each module + std::unordered_map> sortedVars; + { + V3ThreadScope threadScope; + + for (AstNodeModule* modp = v3Global.rootp()->modulesp(); modp; + modp = VN_AS(modp->nextp(), NodeModule)) { + std::vector& varps = sortedVars[modp]; + threadScope.enqueue([modp, mTaskAffinity, &varps]() { + VariableOrder::processModule(modp, mTaskAffinity, varps); + }); + } + } + if (v3Global.opt.stats()) V3Stats::statsStage("variableorder-sort"); + + // Insert them back under the module, in the new order, but at + // the front of the list so they come out first in dumps/XML. for (AstNodeModule* modp = v3Global.rootp()->modulesp(); modp; modp = VN_AS(modp->nextp(), NodeModule)) { - VariableOrder::processModule(modp, mTaskAffinity); + const std::vector& varps = sortedVars[modp]; + + if (!varps.empty()) { + auto it = varps.cbegin(); + AstVar* const firstp = *it++; + firstp->unlinkFrBack(); + for (; it != varps.cend(); ++it) { + AstVar* const varp = *it; + varp->unlinkFrBack(); + firstp->addNext(varp); + } + if (AstNode* const stmtsp = modp->stmtsp()) { + stmtsp->unlinkFrBackWithNext(); + AstNode::addNext(firstp, stmtsp); + } + modp->addStmtsp(firstp); + } } // Done diff --git a/src/V3VariableOrder.h b/src/V3VariableOrder.h index 1a23b62ca..3816ca3a0 100644 --- a/src/V3VariableOrder.h +++ b/src/V3VariableOrder.h @@ -20,15 +20,13 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; //============================================================================ class V3VariableOrder final { public: - static void orderAll(AstNetlist*) VL_MT_DISABLED; + static void orderAll(AstNetlist*); }; #endif // Guard diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 46f44bf86..1f7c25235 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -111,8 +111,7 @@ std::ostream& operator<<(std::ostream& str, const Determ& rhs) { v3errorEnd( \ v3errorBuildMessage(V3Error::v3errorPrep((lhs) < (rhs) ? V3ErrorCode::WIDTHTRUNC \ : (lhs) > (rhs) ? V3ErrorCode::WIDTHEXPAND \ - : V3ErrorCode::WIDTH, \ - VL_MT_DISABLED_CODE_UNIT), \ + : V3ErrorCode::WIDTH), \ msg)) //###################################################################### @@ -610,13 +609,14 @@ class WidthVisitor final : public VNVisitor { if (vdtypep && vdtypep->isString()) { iterateCheckString(nodep, "LHS", nodep->lhsp(), BOTH); iterateCheckString(nodep, "RHS", nodep->rhsp(), BOTH); + nodep->dtypeSetString(); } else { iterateCheckSizedSelf(nodep, "LHS", nodep->lhsp(), SELF, BOTH); iterateCheckSizedSelf(nodep, "RHS", nodep->rhsp(), SELF, BOTH); + nodep->dtypeSetLogicUnsized(nodep->lhsp()->width() + nodep->rhsp()->width(), + nodep->lhsp()->widthMin() + nodep->rhsp()->widthMin(), + VSigning::UNSIGNED); } - nodep->dtypeSetLogicUnsized(nodep->lhsp()->width() + nodep->rhsp()->width(), - nodep->lhsp()->widthMin() + nodep->rhsp()->widthMin(), - VSigning::UNSIGNED); // Cleanup zero width Verilog2001 {x,{0{foo}}} now, // otherwise having width(0) will cause later assertions to fire if (const AstReplicate* const repp = VN_CAST(nodep->lhsp(), Replicate)) { @@ -653,6 +653,7 @@ class WidthVisitor final : public VNVisitor { } } void visit(AstConcatN* nodep) override { + if (nodep->didWidth()) return; // String concatenate. // Already did AstConcat simplifications if (m_vup->prelim()) { @@ -661,6 +662,7 @@ class WidthVisitor final : public VNVisitor { nodep->dtypeSetString(); } if (m_vup->final()) { + nodep->didWidth(true); if (!nodep->dtypep()->widthSized()) { // See also error in V3Number nodeForUnsizedWarning(nodep)->v3warn( @@ -1496,6 +1498,7 @@ class WidthVisitor final : public VNVisitor { } } void visit(AstCvtPackString* nodep) override { + if (nodep->didWidthAndSet()) return; // Opaque returns, so arbitrary userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p()); // Type set in constructor @@ -1507,9 +1510,9 @@ class WidthVisitor final : public VNVisitor { const AstConst* const constp = VN_CAST(nodep->lhsp(), Const); UASSERT_OBJ(constp && constp->isDouble(), nodep, "Times should be doubles"); UASSERT_OBJ(!nodep->timeunit().isNone(), nodep, "$time import no units"); - double time = constp->num().toDouble(); + const double timePrescale = constp->num().toDouble(); UASSERT_OBJ(!v3Global.rootp()->timeprecision().isNone(), nodep, "Never set precision?"); - time /= nodep->timeunit().multiplier(); + const double time = timePrescale / nodep->timeunit().multiplier(); // IEEE claims you should round to time precision here, but no simulator seems to do this AstConst* const newp = new AstConst{nodep->fileline(), AstConst::RealDouble{}, time}; nodep->replaceWith(newp); @@ -1850,13 +1853,11 @@ class WidthVisitor final : public VNVisitor { if (AstNodeDType* typeofDtp = VN_CAST(nodep->typeofp(), NodeDType)) { // It's directly a type, e.g. "type(int)" typeofDtp = iterateEditMoveDTypep(nodep, typeofDtp); // Changes typeofp - nodep->typedefp(nullptr); nodep->refDTypep(typeofDtp); } else { // Type comes from expression's type, e.g. "type(variable)" userIterateAndNext(nodep->typeofp(), WidthVP{SELF, BOTH}.p()); AstNode* const typeofp = nodep->typeofp(); - nodep->typedefp(nullptr); nodep->refDTypep(typeofp->dtypep()); VL_DO_DANGLING(typeofp->unlinkFrBack()->deleteTree(), typeofp); } @@ -1870,7 +1871,6 @@ class WidthVisitor final : public VNVisitor { // this node's childDTypep userIterate(nodep->subDTypep(), nullptr); nodep->refDTypep(iterateEditMoveDTypep(nodep, nodep->subDTypep())); - nodep->typedefp(nullptr); // Note until line above subDTypep() may have followed this // Widths are resolved, but special iterate to check for recursion userIterate(nodep->subDTypep(), nullptr); } @@ -1880,6 +1880,7 @@ class WidthVisitor final : public VNVisitor { nodep->dtypeFrom(nodep->subDTypep()); nodep->widthFromSub(nodep->subDTypep()); UINFO(4, "dtWidthed " << nodep << endl); + // No nodep->typedefp(nullptr) for now; V3WidthCommit needs to check accesses nodep->doingWidth(false); } void visit(AstTypedef* nodep) override { @@ -1920,32 +1921,12 @@ class WidthVisitor final : public VNVisitor { // elimination should do much the same // Form: "( ((v > size) ? false : enum_valid[v[N:0]]) // ? ExprStmt(ExprAssign(out, Cast(v, type)), 1) : 0)" - auto* const enumDtp = VN_AS(toDtp, EnumDType); + AstEnumDType* const enumDtp = VN_AS(toDtp, EnumDType); UASSERT_OBJ(enumDtp, nodep, "$cast determined as enum, but not enum type"); - const uint64_t maxval = enumMaxValue(nodep, enumDtp); - const bool assoc = maxval > ENUM_LOOKUP_BITS; - AstNodeExpr* testp = nullptr; + AstNodeExpr* const testp + = enumTestValid(nodep->fromp()->cloneTreePure(false), enumDtp); FileLine* const fl_novalue = new FileLine{fl}; fl_novalue->warnOff(V3ErrorCode::ENUMVALUE, true); - if (assoc) { - AstVar* const varp = enumVarp(enumDtp, VAttrType::ENUM_VALID, true, 0); - testp = new AstAssocSel{fl_novalue, newVarRefDollarUnit(varp), - nodep->fromp()->cloneTreePure(false)}; - } else { - const int selwidth = V3Number::log2b(maxval) + 1; // Width to address a bit - AstVar* const varp - = enumVarp(enumDtp, VAttrType::ENUM_VALID, false, (1ULL << selwidth) - 1); - FileLine* const fl_nowidth = new FileLine{fl}; - fl_nowidth->warnOff(V3ErrorCode::WIDTH, true); - testp = new AstCond{ - fl, - new AstGt{fl_nowidth, nodep->fromp()->cloneTreePure(false), - new AstConst{fl_nowidth, AstConst::Unsized64{}, maxval}}, - new AstConst{fl, AstConst::BitFalse{}}, - new AstArraySel{fl, newVarRefDollarUnit(varp), - new AstSel{fl_novalue, nodep->fromp()->cloneTreePure(false), 0, - selwidth}}}; - } newp = new AstCond{ fl, testp, new AstExprStmt{fl, @@ -2615,6 +2596,8 @@ class WidthVisitor final : public VNVisitor { } } void visit(AstDist* nodep) override { + // x dist {a :/ p, b :/ q} --> (p > 0 && x == a) || (q > 0 && x == b) + nodep->v3warn(CONSTRAINTIGN, "Constraint expression ignored (imperfect distribution)"); userIterateAndNext(nodep->exprp(), WidthVP{CONTEXT_DET, PRELIM}.p()); for (AstNode *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) { nextip = itemp->nextp(); // iterate may cause the node to get replaced @@ -2644,14 +2627,31 @@ class WidthVisitor final : public VNVisitor { iterateCheck(nodep, "Dist expression", nodep->exprp(), CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP); - for (AstDistItem *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) { - nextip - = VN_AS(itemp->nextp(), DistItem); // iterate may cause the node to get replaced - iterateCheck(nodep, "Dist Item", itemp, CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP); + for (AstNode *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) { + nextip = itemp->nextp(); + itemp = VN_AS(itemp, DistItem)->rangep(); + // InsideRange will get replaced with Lte&Gte and finalized later + if (!VN_IS(itemp, InsideRange)) + iterateCheck(nodep, "Dist Item", itemp, CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP); } + AstNodeExpr* newp = nullptr; + for (AstDistItem* itemp = nodep->itemsp(); itemp; + itemp = VN_AS(itemp->nextp(), DistItem)) { + AstNodeExpr* inewp = insideItem(nodep, nodep->exprp(), itemp->rangep()); + if (!inewp) continue; + AstNodeExpr* const cmpp + = new AstGt{itemp->fileline(), itemp->weightp()->unlinkFrBack(), + new AstConst{itemp->fileline(), 0}}; + cmpp->fileline()->modifyWarnOff(V3ErrorCode::UNSIGNED, true); + cmpp->fileline()->modifyWarnOff(V3ErrorCode::CMPCONST, true); + inewp = new AstLogAnd{itemp->fileline(), cmpp, inewp}; + newp = newp ? new AstLogOr{nodep->fileline(), newp, inewp} : inewp; + } + if (!newp) newp = new AstConst{nodep->fileline(), AstConst::BitFalse{}}; if (debug() >= 9) nodep->dumpTree("- dist-out: "); - nodep->dtypep(subDTypep); + nodep->replaceWith(newp); + VL_DO_DANGLING(pushDeletep(nodep), nodep); } void visit(AstInside* nodep) override { @@ -2697,41 +2697,40 @@ class WidthVisitor final : public VNVisitor { AstNodeExpr* newp = nullptr; for (AstNodeExpr *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) { nextip = VN_AS(itemp->nextp(), NodeExpr); // Will be unlinking - AstNodeExpr* inewp; - const AstNodeDType* const itemDtp = itemp->dtypep()->skipRefp(); - if (AstInsideRange* const irangep = VN_CAST(itemp, InsideRange)) { - // Similar logic in V3Case - inewp = irangep->newAndFromInside(nodep->exprp(), irangep->lhsp()->unlinkFrBack(), - irangep->rhsp()->unlinkFrBack()); - } else if (VN_IS(itemDtp, UnpackArrayDType) || VN_IS(itemDtp, DynArrayDType) - || VN_IS(itemDtp, QueueDType)) { - // Unsupported in parameters - AstNodeExpr* exprp = nodep->exprp()->cloneTreePure(true); - inewp = new AstCMethodHard{nodep->fileline(), itemp->unlinkFrBack(), "inside", - exprp}; - iterateCheckTyped(nodep, "inside value", exprp, itemDtp->subDTypep(), BOTH); - VL_DANGLING(exprp); // Might have been replaced - inewp->dtypeSetBit(); - inewp->didWidth(true); - } else if (VN_IS(itemDtp, AssocArrayDType)) { - nodep->v3error("Inside operator not specified on associative arrays " - "(IEEE 1800-2023 11.4.13)"); - continue; - } else { - inewp = AstEqWild::newTyped(itemp->fileline(), nodep->exprp()->cloneTreePure(true), - itemp->unlinkFrBack()); - } - if (newp) { - newp = new AstLogOr{nodep->fileline(), newp, inewp}; - } else { - newp = inewp; - } + AstNodeExpr* const inewp = insideItem(nodep, nodep->exprp(), itemp); + if (!inewp) continue; + newp = newp ? new AstLogOr{nodep->fileline(), newp, inewp} : inewp; } if (!newp) newp = new AstConst{nodep->fileline(), AstConst::BitFalse{}}; if (debug() >= 9) newp->dumpTree("- inside-out: "); nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); } + AstNodeExpr* insideItem(AstNode* nodep, AstNodeExpr* exprp, AstNodeExpr* itemp) { + const AstNodeDType* const itemDtp = itemp->dtypep()->skipRefp(); + if (AstInsideRange* const irangep = VN_CAST(itemp, InsideRange)) { + // Similar logic in V3Case + return irangep->newAndFromInside(exprp, irangep->lhsp()->unlinkFrBack(), + irangep->rhsp()->unlinkFrBack()); + } else if (VN_IS(itemDtp, UnpackArrayDType) || VN_IS(itemDtp, DynArrayDType) + || VN_IS(itemDtp, QueueDType)) { + // Unsupported in parameters + AstNodeExpr* const cexprp = exprp->cloneTreePure(true); + AstNodeExpr* const inewp + = new AstCMethodHard{nodep->fileline(), itemp->unlinkFrBack(), "inside", cexprp}; + iterateCheckTyped(nodep, "inside value", cexprp, itemDtp->subDTypep(), BOTH); + VL_DANGLING(cexprp); // Might have been replaced + inewp->dtypeSetBit(); + inewp->didWidth(true); + return inewp; + } else if (VN_IS(itemDtp, AssocArrayDType)) { + nodep->v3error("Inside operator not specified on associative arrays " + "(IEEE 1800-2023 11.4.13)"); + return nullptr; + } + return AstEqWild::newTyped(itemp->fileline(), exprp->cloneTreePure(true), + itemp->unlinkFrBack()); + } void visit(AstInsideRange* nodep) override { // Just do each side; AstInside will rip these nodes out later userIterateAndNext(nodep->lhsp(), m_vup); @@ -2767,7 +2766,7 @@ class WidthVisitor final : public VNVisitor { << " in packed struct/union (IEEE 1800-2023 7.2.1)"); if ((VN_IS(nodep, UnionDType) || nodep->packed()) && itemp->valuep()) { itemp->v3error("Initial values not allowed in packed struct/union" - " (IEEE 1800-2023 7.2.1)"); + " (IEEE 1800-2023 7.2.2)"); pushDeletep(itemp->valuep()->unlinkFrBack()); } else if (itemp->valuep()) { itemp->valuep()->v3warn(E_UNSUPPORTED, @@ -2912,27 +2911,8 @@ class WidthVisitor final : public VNVisitor { if (memberSelClass(nodep, adtypep)) return; } else if (AstIfaceRefDType* const adtypep = VN_CAST(fromDtp, IfaceRefDType)) { if (AstNode* foundp = memberSelIface(nodep, adtypep)) { - if (AstClocking* const clockingp = VN_CAST(foundp, Clocking)) { - foundp = clockingp->eventp(); - if (!foundp) { - AstVar* const eventp = new AstVar{ - clockingp->fileline(), VVarType::MODULETEMP, clockingp->name(), - clockingp->findBasicDType(VBasicDTypeKwd::EVENT)}; - eventp->lifetime(VLifetime::STATIC); - clockingp->eventp(eventp); - // Trigger the clocking event in Observed (IEEE 1800-2023 14.13) - clockingp->addNextHere(new AstAlwaysObserved{ - clockingp->fileline(), - new AstSenTree{clockingp->fileline(), - clockingp->sensesp()->cloneTree(false)}, - new AstFireEvent{ - clockingp->fileline(), - new AstVarRef{clockingp->fileline(), eventp, VAccess::WRITE}, - false}}); - v3Global.setHasEvents(); - foundp = eventp; - } - } + if (AstClocking* const clockingp = VN_CAST(foundp, Clocking)) + foundp = clockingp->ensureEventp(); if (AstVar* const varp = VN_CAST(foundp, Var)) { if (!varp->didWidth()) userIterate(varp, nullptr); nodep->dtypep(foundp->dtypep()); @@ -3326,27 +3306,9 @@ class WidthVisitor final : public VNVisitor { } } } - // Need a runtime lookup table. Yuk. - const uint64_t msbdim = enumMaxValue(nodep, adtypep); - const bool assoc = msbdim > ENUM_LOOKUP_BITS; - if (assoc) { - AstVar* const varp = enumVarp(adtypep, attrType, true, 0); - AstNode* const newp = new AstAssocSel{nodep->fileline(), newVarRefDollarUnit(varp), - nodep->fromp()->unlinkFrBack()}; - newp->dtypeFrom(adtypep); // To prevent a later ENUMVALUE - nodep->replaceWith(newp); - } else { - const int selwidth = V3Number::log2b(msbdim) + 1; // Width to address a bit - AstVar* const varp = enumVarp(adtypep, attrType, false, (1ULL << selwidth) - 1); - AstNode* const newp = new AstArraySel{ - nodep->fileline(), newVarRefDollarUnit(varp), - // Select in case widths are off due to msblen!=width - // We return "random" values if outside the range, which is fine - // as next/previous on illegal values just need something good out - new AstSel{nodep->fileline(), nodep->fromp()->unlinkFrBack(), 0, selwidth}}; - newp->dtypeFrom(adtypep); // To prevent a later ENUMVALUE - nodep->replaceWith(newp); - } + AstNodeExpr* const newp + = enumSelect(nodep->fromp()->unlinkFrBack(), adtypep, attrType); + nodep->replaceWith(newp); VL_DO_DANGLING(nodep->deleteTree(), nodep); } else { nodep->v3error("Unknown built-in enum method " << nodep->prettyNameQ()); @@ -3452,6 +3414,7 @@ class WidthVisitor final : public VNVisitor { || nodep->name() == "prev") { methodOkArguments(nodep, 1, 1); AstNodeExpr* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep); + methodCallLValueRecurse(nodep, index_exprp, VAccess::READWRITE); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name(), // first/last/next/prev index_exprp->unlinkFrBack()}; @@ -3557,8 +3520,19 @@ class WidthVisitor final : public VNVisitor { return VN_AS(nodep->pinsp(), Arg)->exprp(); } void methodCallLValueRecurse(AstMethodCall* nodep, AstNode* childp, const VAccess& access) { - if (const AstCMethodHard* const ichildp = VN_CAST(childp, CMethodHard)) { - if (ichildp->name() == "at") { + if (AstCMethodHard* const ichildp = VN_CAST(childp, CMethodHard)) { + const std::string name = ichildp->name(); + if (name == "at" || name == "atWrite" || name == "atBack" || name == "atWriteAppend" + || name == "atWriteAppendBack") { + const AstNodeDType* const fromDtypep = ichildp->fromp()->dtypep()->skipRefp(); + if (VN_IS(fromDtypep, QueueDType) || VN_IS(fromDtypep, DynArrayDType)) { + // Change access methods to writable ones + if (name == "at") { + ichildp->name("atWrite"); + } else if (name == "atBack") { + ichildp->name("atWriteAppendBack"); + } + } methodCallLValueRecurse(nodep, ichildp->fromp(), access); return; } @@ -3639,9 +3613,14 @@ class WidthVisitor final : public VNVisitor { AstCMethodHard* newp = nullptr; if (nodep->name() == "at") { // Created internally for [] methodOkArguments(nodep, 1, 1); - methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), "at"}; newp->dtypeFrom(adtypep->subDTypep()); + } else if (nodep->name() == "atWrite") { // Created internally for [] + methodOkArguments(nodep, 1, 1); + methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); + newp + = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), "atWrite"}; + newp->dtypeFrom(adtypep->subDTypep()); } else if (nodep->name() == "size") { methodOkArguments(nodep, 0, 0); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size"}; @@ -3678,10 +3657,17 @@ class WidthVisitor final : public VNVisitor { } void methodCallQueue(AstMethodCall* nodep, AstQueueDType* adtypep) { AstCMethodHard* newp = nullptr; - if (nodep->name() == "at") { // Created internally for [] + if (nodep->name() == "at" || nodep->name() == "atBack") { // Created internally for [] + methodOkArguments(nodep, 1, 1); + newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), + nodep->name()}; + newp->dtypeFrom(adtypep->subDTypep()); + } else if (nodep->name() == "atWriteAppend" + || nodep->name() == "atWriteAppendBack") { // Created internally for [] methodOkArguments(nodep, 1, 1); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); - newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), "at"}; + newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), + nodep->name()}; newp->dtypeFrom(adtypep->subDTypep()); } else if (nodep->name() == "num" // function int num() || nodep->name() == "size") { @@ -3782,10 +3768,10 @@ class WidthVisitor final : public VNVisitor { } void methodCallIfaceRef(AstMethodCall* nodep, AstIfaceRefDType* adtypep) { AstIface* const ifacep = adtypep->ifacep(); - UINFO(1, __FUNCTION__ << ":" << nodep << endl); + UINFO(5, __FUNCTION__ << ":" << nodep << endl); if (AstNodeFTask* const ftaskp = VN_CAST(m_memberMap.findMember(ifacep, nodep->name()), NodeFTask)) { - UINFO(1, __FUNCTION__ << "AstNodeFTask" << nodep << endl); + UINFO(5, __FUNCTION__ << "AstNodeFTask" << nodep << endl); userIterate(ftaskp, nullptr); if (ftaskp->isStatic()) { AstNodeExpr* argsp = nullptr; @@ -4392,9 +4378,9 @@ class WidthVisitor final : public VNVisitor { } memp = VN_AS(memp->nextp(), MemberDType); } - } else if (const AstNodeDType* nodedtypep - = VN_CAST(patp->keyp(), NodeDType)) { + } else if (AstNodeDType* nodedtypep = VN_CAST(patp->keyp(), NodeDType)) { // data_type: default_value + userIterate(nodedtypep, WidthVP{SELF, BOTH}.p()); const string dtype = nodedtypep->dtypep()->prettyDTypeName(true); const auto pair = dtypemap.emplace(dtype, patp); if (!pair.second) { @@ -4646,9 +4632,12 @@ class WidthVisitor final : public VNVisitor { for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp; patp = VN_AS(patp->nextp(), PatMember)) { patp->dtypep(arrayp->subDTypep()); - AstNodeExpr* const valuep = patternMemberValueIterate(patp); + AstNodeExpr* const rhsp = patternMemberValueIterate(patp); + const bool rhsIsValue + = AstNode::computeCastable(rhsp->dtypep(), arrayp->subDTypep(), nullptr) + .isAssignable(); AstConsDynArray* const newap - = new AstConsDynArray{nodep->fileline(), true, valuep, false, newp}; + = new AstConsDynArray{nodep->fileline(), rhsIsValue, rhsp, false, newp}; newap->dtypeFrom(arrayp); newp = newap; } @@ -4662,9 +4651,12 @@ class WidthVisitor final : public VNVisitor { for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp; patp = VN_AS(patp->nextp(), PatMember)) { patp->dtypep(arrayp->subDTypep()); - AstNodeExpr* const valuep = patternMemberValueIterate(patp); + AstNodeExpr* const rhsp = patternMemberValueIterate(patp); + const bool rhsIsValue + = AstNode::computeCastable(rhsp->dtypep(), arrayp->subDTypep(), nullptr) + .isAssignable(); AstConsQueue* const newap - = new AstConsQueue{nodep->fileline(), true, valuep, false, newp}; + = new AstConsQueue{nodep->fileline(), rhsIsValue, rhsp, false, newp}; newap->dtypeFrom(arrayp); newp = newap; } @@ -5034,17 +5026,17 @@ class WidthVisitor final : public VNVisitor { assertAtStatement(nodep); // if (debug()) nodep->dumpTree("- AssignPre: "); { - if (debug()) nodep->dumpTree("- assin:: "); + // if (debug()) nodep->dumpTree("- assin:: "); userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p()); UASSERT_OBJ(nodep->lhsp()->dtypep(), nodep, "How can LHS be untyped?"); UASSERT_OBJ(nodep->lhsp()->dtypep()->widthSized(), nodep, "How can LHS be unsized?"); nodep->dtypeFrom(nodep->lhsp()); // // AstPattern needs to know the proposed data type of the lhs, so pass on the prelim - if (debug()) nodep->dumpTree("- assrhs: "); + // if (debug()) nodep->dumpTree("- assrhs: "); userIterateAndNext(nodep->rhsp(), WidthVP{nodep->dtypep(), PRELIM}.p()); // - if (debug()) nodep->dumpTree("- assign: "); + // if (debug()) nodep->dumpTree("- assign: "); AstNodeDType* const lhsDTypep = nodep->lhsp()->dtypep(); // Note we use rhsp for context determined iterateCheckAssign(nodep, "Assign RHS", nodep->rhsp(), FINAL, lhsDTypep); @@ -5187,7 +5179,7 @@ class WidthVisitor final : public VNVisitor { ch = 'g'; } else if (argp && argp->isString()) { ch = '@'; - } else if (nodep->missingArgChar() == 'd' && argp->isSigned()) { + } else if (argp && nodep->missingArgChar() == 'd' && argp->isSigned()) { ch = '~'; } else if (basicp) { ch = nodep->missingArgChar(); @@ -5313,6 +5305,10 @@ class WidthVisitor final : public VNVisitor { nodep->text(newFormat); UINFO(9, " Display out " << nodep->text() << endl); } + void visit(AstCReturn* nodep) override { + assertAtStatement(nodep); + userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p()); + } void visit(AstConstraintRef* nodep) override { userIterateChildren(nodep, nullptr); } void visit(AstDisplay* nodep) override { assertAtStatement(nodep); @@ -5548,7 +5544,7 @@ class WidthVisitor final : public VNVisitor { userIterate(modVarp->childDTypep(), WidthVP{SELF, BOTH}.p()); // May relink pointed to node AstNodeDType* const setDtp = modVarp->childDTypep()->cloneTree(false); - patternp->childDTypep(setDtp); + if (!patternp->childDTypep()) patternp->childDTypep(setDtp); userIterateChildren(nodep, WidthVP{setDtp, BOTH}.p()); didWidth = true; } @@ -6031,7 +6027,6 @@ class WidthVisitor final : public VNVisitor { } UASSERT_OBJ(classp, nodep, "Should have failed in V3LinkDot"); if (nodep->name() == "randomize") { - nodep->taskp(V3Randomize::newRandomizeFunc(m_memberMap, classp)); AstClassRefDType* const adtypep = new AstClassRefDType{nodep->fileline(), classp, nullptr}; v3Global.rootp()->typeTablep()->addTypesp(adtypep); @@ -6968,7 +6963,7 @@ class WidthVisitor final : public VNVisitor { // Check using assignment-like context rules // if (debug()) nodep->dumpTree("- checkass: "); UASSERT_OBJ(stage == FINAL, nodep, "Bad width call"); - // Create unpacked byte from string perl IEEE 1800-2023 5.9 + // Create unpacked byte from string see IEEE 1800-2023 5.9 if (AstConst* constp = VN_CAST(rhsp, Const)) { if (const AstUnpackArrayDType* const arrayp = VN_CAST(lhsDTypep->skipRefp(), UnpackArrayDType)) { @@ -7116,7 +7111,7 @@ class WidthVisitor final : public VNVisitor { << " (IEEE 1800-2023 6.19.3)\n" << nodep->warnMore() << "... Suggest use enum's mnemonic, or static cast"); - if (debug()) nodep->backp()->dumpTree("- back: "); + // if (debug()) nodep->backp()->dumpTree("- back: "); } } AstNodeDType* subDTypep = expDTypep; @@ -7218,6 +7213,9 @@ class WidthVisitor final : public VNVisitor { underp = nullptr; // Changes underp return; } + // If user has a sizing cast, assume they know what they are doing + // (for better or worse) + if (VN_IS(nodep->backp(), CastSize)) warnOn = false; if (VN_IS(underp, Const) && VN_AS(underp, Const)->num().isFromString() && expWidth > underp->width() && (((expWidth - underp->width()) % 8) == 0)) { // At least it's character sized @@ -7306,10 +7304,7 @@ class WidthVisitor final : public VNVisitor { if (const AstConst* const constp = VN_CAST(nodep, Const)) { // We convert to/from int32_t rather than use floor() as want to make sure is // representable in integer's number of bits - if (constp->isDouble() - && v3EpsilonEqual( - constp->num().toDouble(), - static_cast(static_cast(constp->num().toDouble())))) { + if (constp->isDouble() && V3Number::epsilonIntegral(constp->num().toDouble())) { warnOn = false; } } @@ -7639,7 +7634,7 @@ class WidthVisitor final : public VNVisitor { } return pair.first->second; } - uint64_t enumMaxValue(const AstNode* errNodep, const AstEnumDType* adtypep) { + static uint64_t enumMaxValue(const AstNode* errNodep, const AstEnumDType* adtypep) { // Most enums unless overridden are 32 bits, so we size array // based on max enum value used. // Ideally we would have a fast algorithm when a number is @@ -7648,9 +7643,10 @@ class WidthVisitor final : public VNVisitor { uint64_t maxval = 0; for (const AstEnumItem* itemp = adtypep->itemsp(); itemp; itemp = VN_AS(itemp->nextp(), EnumItem)) { - const AstConst* const vconstp = VN_AS(itemp->valuep(), Const); + const AstConst* const vconstp = VN_CAST(itemp->valuep(), Const); UASSERT_OBJ(vconstp, errNodep, "Enum item without constified value"); - if (vconstp->toUQuad() >= maxval) maxval = vconstp->toUQuad(); + if (!vconstp->num().isAnyXZ() && vconstp->toUQuad() >= maxval) + maxval = vconstp->toUQuad(); } if (adtypep->itemsp()->width() > 64) { errNodep->v3warn(E_UNSUPPORTED, @@ -7659,7 +7655,8 @@ class WidthVisitor final : public VNVisitor { } return maxval; } - AstVar* enumVarp(AstEnumDType* const nodep, VAttrType attrType, bool assoc, uint32_t msbdim) { + static AstVar* enumVarp(AstEnumDType* const nodep, VAttrType attrType, bool assoc, + uint32_t msbdim) { // Return a variable table which has specified dimension properties for this variable const auto pair = nodep->tableMap().emplace(attrType, nullptr); if (pair.second) { @@ -7688,7 +7685,7 @@ class WidthVisitor final : public VNVisitor { v3Global.rootp()->typeTablep()->addTypesp(vardtypep); AstVar* const varp = new AstVar{nodep->fileline(), VVarType::MODULETEMP, "__Venumtab_" + VString::downcase(attrType.ascii()) - + cvtToStr(m_dtTables++), + + cvtToStr(nodep->uniqueNum()), vardtypep}; varp->lifetime(VLifetime::STATIC); varp->isConst(true); @@ -7720,19 +7717,21 @@ class WidthVisitor final : public VNVisitor { AstEnumItem* const nextp = VN_AS(itemp->nextp(), EnumItem); const AstConst* const vconstp = VN_AS(itemp->valuep(), Const); UASSERT_OBJ(vconstp, nodep, "Enum item without constified value"); - const uint64_t i = vconstp->toUQuad(); - if (attrType == VAttrType::ENUM_NAME) { - values[i] - = new AstConst{nodep->fileline(), AstConst::String{}, itemp->name()}; - } else if (attrType == VAttrType::ENUM_NEXT) { - values[i] - = (nextp ? nextp : firstp)->valuep()->cloneTree(false); // A const - } else if (attrType == VAttrType::ENUM_PREV) { - values[i] = prevp->valuep()->cloneTree(false); // A const - } else if (attrType == VAttrType::ENUM_VALID) { - values[i] = new AstConst{nodep->fileline(), AstConst::BitTrue{}}; - } else { - nodep->v3fatalSrc("Bad case"); + if (!vconstp->num().isAnyXZ()) { // Can 2-state runtime decode + const uint64_t i = vconstp->toUQuad(); + if (attrType == VAttrType::ENUM_NAME) { + values[i] = new AstConst{nodep->fileline(), AstConst::String{}, + itemp->name()}; + } else if (attrType == VAttrType::ENUM_NEXT) { + values[i] + = (nextp ? nextp : firstp)->valuep()->cloneTree(false); // A const + } else if (attrType == VAttrType::ENUM_PREV) { + values[i] = prevp->valuep()->cloneTree(false); // A const + } else if (attrType == VAttrType::ENUM_VALID) { + values[i] = new AstConst{nodep->fileline(), AstConst::BitTrue{}}; + } else { + nodep->v3fatalSrc("Bad case"); + } } prevp = itemp; itemp = nextp; @@ -7746,12 +7745,67 @@ class WidthVisitor final : public VNVisitor { if (values[i]) initp->addIndexValuep(i, values[i]); } } - userIterate(varp, nullptr); // May have already done $unit so must do this var + varp->didWidth(true); // May have already done $unit so must do this var pair.first->second = varp; } return pair.first->second; } + static AstNodeExpr* enumSelect(AstNodeExpr* nodep, AstEnumDType* adtypep, VAttrType attrType) { + // Return expression to get given attrType information from a enum's value (nodep) + // Need a runtime lookup table. Yuk. + const uint64_t msbdim = enumMaxValue(nodep, adtypep); + const bool assoc = msbdim > ENUM_LOOKUP_BITS; + AstNodeExpr* newp; + if (assoc) { + AstVar* const varp = enumVarp(adtypep, attrType, true, 0); + newp = new AstAssocSel{nodep->fileline(), newVarRefDollarUnit(varp), nodep}; + } else { + const int selwidth = V3Number::log2b(msbdim) + 1; // Width to address a bit + AstVar* const varp = enumVarp(adtypep, attrType, false, (1ULL << selwidth) - 1); + newp = new AstArraySel{ + nodep->fileline(), newVarRefDollarUnit(varp), + // Select in case widths are off due to msblen!=width + // We return "random" values if outside the range, which is fine + // as next/previous on illegal values just need something good out + new AstSel{nodep->fileline(), nodep, 0, selwidth}}; + } + if (attrType == VAttrType::ENUM_NAME) { + newp->dtypeSetString(); + } else if (attrType == VAttrType::ENUM_VALID) { + newp->dtypeSetBit(); + } else { + newp->dtypeFrom(adtypep); // To prevent a later ENUMVALUE + } + return newp; + } + static AstNodeExpr* enumTestValid(AstNodeExpr* valp, AstEnumDType* enumDtp) { + const uint64_t maxval = enumMaxValue(valp, enumDtp); + const bool assoc = maxval > ENUM_LOOKUP_BITS; + AstNodeExpr* testp = nullptr; + FileLine* const fl_novalue = new FileLine{valp->fileline()}; + fl_novalue->warnOff(V3ErrorCode::ENUMVALUE, true); + fl_novalue->warnOff(V3ErrorCode::CMPCONST, true); + if (assoc) { + AstVar* const varp = enumVarp(enumDtp, VAttrType::ENUM_VALID, true, 0); + testp = new AstAssocSel{fl_novalue, newVarRefDollarUnit(varp), valp}; + } else { + const int selwidth = V3Number::log2b(maxval) + 1; // Width to address a bit + AstVar* const varp + = enumVarp(enumDtp, VAttrType::ENUM_VALID, false, (1ULL << selwidth) - 1); + FileLine* const fl_nowidth = new FileLine{fl_novalue}; + fl_nowidth->warnOff(V3ErrorCode::WIDTH, true); + testp = new AstCond{ + fl_novalue, + new AstGt{fl_nowidth, valp->cloneTreePure(false), + new AstConst{fl_nowidth, AstConst::Unsized64{}, maxval}}, + new AstConst{fl_novalue, AstConst::BitFalse{}}, + new AstArraySel{fl_novalue, newVarRefDollarUnit(varp), + new AstSel{fl_novalue, valp->cloneTreePure(false), 0, selwidth}}}; + } + return testp; + } + PatVecMap patVectorMap(AstPattern* nodep, const VNumRange& range) { PatVecMap patmap; int element = range.left(); @@ -7851,7 +7905,7 @@ class WidthVisitor final : public VNVisitor { VL_DO_DANGLING(pushDeletep(nodep), nodep); } } - AstVarRef* newVarRefDollarUnit(AstVar* nodep) { + static AstVarRef* newVarRefDollarUnit(AstVar* nodep) { AstVarRef* const varrefp = new AstVarRef{nodep->fileline(), nodep, VAccess::READ}; varrefp->classOrPackagep(v3Global.rootp()->dollarUnitPkgAddp()); return varrefp; diff --git a/src/V3Width.h b/src/V3Width.h index 6d3da85cd..f7aa836bc 100644 --- a/src/V3Width.h +++ b/src/V3Width.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - class AstNetlist; class AstNode; class AstNodeDType; diff --git a/src/V3WidthCommit.cpp b/src/V3WidthCommit.cpp index bb5bad534..1c9e1640f 100644 --- a/src/V3WidthCommit.cpp +++ b/src/V3WidthCommit.cpp @@ -85,12 +85,15 @@ private: "Only rand_mode() and constraint_mode() can have no def"); return; } - if (const auto varp = VN_CAST(defp, Var)) { - local = varp->isHideLocal(); - prot = varp->isHideProtected(); - } else if (const auto ftaskp = VN_CAST(defp, NodeFTask)) { - local = ftaskp->isHideLocal(); - prot = ftaskp->isHideProtected(); + if (const auto anodep = VN_CAST(defp, Var)) { + local = anodep->isHideLocal(); + prot = anodep->isHideProtected(); + } else if (const auto anodep = VN_CAST(defp, NodeFTask)) { + local = anodep->isHideLocal(); + prot = anodep->isHideProtected(); + } else if (const auto anodep = VN_CAST(defp, Typedef)) { + local = anodep->isHideLocal(); + prot = anodep->isHideProtected(); } else { nodep->v3fatalSrc("ref to unhandled definition type " << defp->prettyTypeName()); } @@ -178,6 +181,12 @@ private: nodep->unlinkFrBack(); // Make non-child v3Global.rootp()->typeTablep()->addTypesp(nodep); } + void visit(AstRefDType* nodep) override { + visitIterateNodeDType(nodep); + if (!nodep->typedefp()) return; // Already checked and cleared + classEncapCheck(nodep, nodep->typedefp(), VN_CAST(nodep->classOrPackagep(), Class)); + nodep->typedefp(nullptr); // No longer needed + } void visitIterateNodeDType(AstNodeDType* nodep) { // Rather than use dtypeChg which may make new nodes, we edit in place, // as we don't need to preserve any widthMin's, and every dtype with the same width diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp index 7fea7c2a4..1ebfa828a 100644 --- a/src/V3WidthSel.cpp +++ b/src/V3WidthSel.cpp @@ -282,7 +282,9 @@ class WidthSelVisitor final : public VNVisitor { VL_DO_DANGLING(pushDeletep(nodep), nodep); } else if (const AstDynArrayDType* const adtypep = VN_CAST(ddtypep, DynArrayDType)) { // SELBIT(array, index) -> CMETHODCALL(queue, "at", index) - AstCMethodHard* const newp = new AstCMethodHard{nodep->fileline(), fromp, "at", rhsp}; + const char* methodName = nodep->access().isWriteOrRW() ? "atWrite" : "at"; + AstCMethodHard* const newp + = new AstCMethodHard{nodep->fileline(), fromp, methodName, rhsp}; newp->dtypeFrom(adtypep->subDTypep()); // Need to strip off queue reference if (debug() >= 9) newp->dumpTree("- SELBTq: "); nodep->replaceWith(newp); @@ -290,10 +292,12 @@ class WidthSelVisitor final : public VNVisitor { } else if (const AstQueueDType* const adtypep = VN_CAST(ddtypep, QueueDType)) { // SELBIT(array, index) -> CMETHODCALL(queue, "at", index) AstCMethodHard* newp; + const char* methodName = nodep->access().isWriteOrRW() ? "atWriteAppend" : "at"; if (AstNodeExpr* const backnessp = selQueueBackness(rhsp)) { - newp = new AstCMethodHard{nodep->fileline(), fromp, "atBack", backnessp}; + newp = new AstCMethodHard{nodep->fileline(), fromp, + std::string(methodName) + "Back", backnessp}; } else { - newp = new AstCMethodHard{nodep->fileline(), fromp, "at", rhsp}; + newp = new AstCMethodHard{nodep->fileline(), fromp, methodName, rhsp}; } newp->dtypeFrom(adtypep->subDTypep()); // Need to strip off queue reference if (debug() >= 9) newp->dumpTree("- SELBTq: "); diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 93167376c..d6b58ea9c 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -136,7 +136,6 @@ static void emitXmlOrJson() VL_MT_DISABLED { static void process() { { - const V3MtDisabledLockGuard mtDisabler{v3MtDisabledLock()}; VlOs::DeltaWallTime elabWallTime{true}; // Sort modules by level so later algorithms don't need to care @@ -600,48 +599,43 @@ static void process() { && !v3Global.opt.dpiHdrOnly()) { // Unfortunately we have some lint checks in emitcImp. V3EmitC::emitcImp(); } - { - const V3MtDisabledLockGuard mtDisabler{v3MtDisabledLock()}; - if (v3Global.opt.serializeOnly()) { - emitXmlOrJson(); - } else if (v3Global.opt.debugCheck() && !v3Global.opt.lintOnly() - && !v3Global.opt.dpiHdrOnly()) { - // Check XML/JSON when debugging to make sure no missing node types - V3EmitXml::emitxml(); - emitJson(); - } - - // Output DPI protected library files - if (!v3Global.opt.libCreate().empty()) { - if (v3Global.rootp()->delaySchedulerp()) { - v3warn(E_UNSUPPORTED, "Unsupported: --lib-create with --timing and delays"); - } - V3ProtectLib::protect(); - V3EmitV::emitvFiles(); - V3EmitC::emitcFiles(); - } - - if (!v3Global.opt.lintOnly() && !v3Global.opt.serializeOnly() - && !v3Global.opt.dpiHdrOnly()) { - if (v3Global.opt.main()) V3EmitCMain::emit(); - - // V3EmitMk/V3EmitCMake must be after all other emitters, - // as they and below code visits AstCFiles added earlier - size_t src_f_cnt = 0; - for (AstNode* nodep = v3Global.rootp()->filesp(); nodep; nodep = nodep->nextp()) { - if (const AstCFile* cfilep = VN_CAST(nodep, CFile)) - src_f_cnt += cfilep->source() ? 1 : 0; - } - if (src_f_cnt >= V3EmitMk::PARALLEL_FILE_CNT_THRESHOLD) - v3Global.useParallelBuild(true); - if (v3Global.opt.cmake()) V3EmitCMake::emit(); - if (v3Global.opt.gmake()) V3EmitMk::emitmk(); - } - - // Final statistics - if (v3Global.opt.stats()) V3Stats::statsStage("emit"); - reportStatsIfEnabled(); + if (v3Global.opt.serializeOnly()) { + emitXmlOrJson(); + } else if (v3Global.opt.debugCheck() && !v3Global.opt.lintOnly() + && !v3Global.opt.dpiHdrOnly()) { + // Check XML/JSON when debugging to make sure no missing node types + V3EmitXml::emitxml(); + emitJson(); } + + // Output DPI protected library files + if (!v3Global.opt.libCreate().empty()) { + if (v3Global.rootp()->delaySchedulerp()) { + v3warn(E_UNSUPPORTED, "Unsupported: --lib-create with --timing and delays"); + } + V3ProtectLib::protect(); + V3EmitV::emitvFiles(); + V3EmitC::emitcFiles(); + } + + if (!v3Global.opt.lintOnly() && !v3Global.opt.serializeOnly() && !v3Global.opt.dpiHdrOnly()) { + if (v3Global.opt.main()) V3EmitCMain::emit(); + + // V3EmitMk/V3EmitCMake must be after all other emitters, + // as they and below code visits AstCFiles added earlier + size_t src_f_cnt = 0; + for (AstNode* nodep = v3Global.rootp()->filesp(); nodep; nodep = nodep->nextp()) { + if (const AstCFile* cfilep = VN_CAST(nodep, CFile)) + src_f_cnt += cfilep->source() ? 1 : 0; + } + if (src_f_cnt >= V3EmitMk::PARALLEL_FILE_CNT_THRESHOLD) v3Global.useParallelBuild(true); + if (v3Global.opt.cmake()) V3EmitCMake::emit(); + if (v3Global.opt.gmake()) V3EmitMk::emitmk(); + } + + // Final statistics + if (v3Global.opt.stats()) V3Stats::statsStage("emit"); + reportStatsIfEnabled(); } static void verilate(const string& argString) { @@ -664,8 +658,9 @@ static void verilate(const string& argString) { // Disable mutexes in single-thread verilation V3MutexConfig::s().configure(v3Global.opt.verilateJobs() > 1 /*enable*/); - // Adjust thread pool size - V3ThreadPool::s().resize(v3Global.opt.verilateJobs()); + + // Initialize thread pool + v3Global.threadPoolp(new V3ThreadPool{v3Global.opt.verilateJobs()}); // --FRONTEND------------------ @@ -680,31 +675,24 @@ static void verilate(const string& argString) { // and after removing files as may make debug output) VBasicDTypeKwd::selfTest(); if (v3Global.opt.debugSelfTest()) { - { - const V3MtDisabledLockGuard mtDisabler{v3MtDisabledLock()}; - - V3Os::selfTest(); - VHashSha256::selfTest(); - VSpellCheck::selfTest(); - V3Graph::selfTest(); - V3TSP::selfTest(); - V3ScoreboardBase::selfTest(); - V3Order::selfTestParallel(); - V3ExecGraph::selfTest(); - V3PreShell::selfTest(); - V3Broken::selfTest(); - } + V3Os::selfTest(); + V3Number::selfTest(); + VHashSha256::selfTest(); + VSpellCheck::selfTest(); + V3Graph::selfTest(); + V3TSP::selfTest(); + V3ScoreboardBase::selfTest(); + V3Order::selfTestParallel(); + V3ExecGraph::selfTest(); + V3PreShell::selfTest(); + V3Broken::selfTest(); V3ThreadPool::selfTest(); UINFO(2, "selfTest done\n"); } - { - const V3MtDisabledLockGuard mtDisabler{v3MtDisabledLock()}; - - // Read first filename - v3Global.readFiles(); - v3Global.removeStd(); - } + // Read first filename + v3Global.readFiles(); + v3Global.removeStd(); // Link, etc, if needed if (!v3Global.opt.preprocOnly()) { // @@ -731,8 +719,6 @@ static void verilate(const string& argString) { V3Error::abortIfWarnings(); if (v3Global.hierPlanp()) { // This run is for just write a makefile - const V3MtDisabledLockGuard mtDisabler{v3MtDisabledLock()}; - UASSERT(v3Global.opt.hierarchical(), "hierarchical must be set"); UASSERT(!v3Global.opt.hierChild(), "This must not be a hierarchical-child run"); UASSERT(v3Global.opt.hierBlocks().empty(), "hierarchical-block must not be set"); @@ -832,24 +818,21 @@ int main(int argc, char** argv) { srand(static_cast(randseed)); const string argString = V3Options::argString(argc - 1, argv + 1); - { - const V3MtDisabledLockGuard mtDisabler{v3MtDisabledLock()}; - // Post-constructor initialization of netlists - v3Global.boot(); + // Post-constructor initialization of netlists + v3Global.boot(); - // Preprocessor - // Before command parsing so we can handle -Ds on command line. - V3PreShell::boot(); + // Preprocessor + // Before command parsing so we can handle -Ds on command line. + V3PreShell::boot(); - // Command option parsing - v3Global.opt.buildDepBin(V3Os::filenameCleanup(argv[0])); - v3Global.opt.parseOpts(new FileLine{FileLine::commandLineFilename()}, argc - 1, argv + 1); + // Command option parsing + v3Global.opt.buildDepBin(V3Os::filenameCleanup(argv[0])); + v3Global.opt.parseOpts(new FileLine{FileLine::commandLineFilename()}, argc - 1, argv + 1); - // Validate settings (aka Boost.Program_options) - v3Global.opt.notify(); - v3Global.rootp()->timeInit(); - } + // Validate settings (aka Boost.Program_options) + v3Global.opt.notify(); + v3Global.rootp()->timeInit(); V3Error::abortIfErrors(); @@ -865,14 +848,10 @@ int main(int argc, char** argv) { execBuildJob(); } - { - const V3MtDisabledLockGuard mtDisabler{v3MtDisabledLock()}; - - // Explicitly release resources - V3PreShell::shutdown(); - v3Global.shutdown(); - FileLine::deleteAllRemaining(); - } + // Explicitly release resources + V3PreShell::shutdown(); + v3Global.shutdown(); + FileLine::deleteAllRemaining(); if (!v3Global.opt.quietStats() && !v3Global.opt.preprocOnly()) { V3Stats::addStatPerf(V3Stats::STAT_CPUTIME, cpuTimeTotal.deltaTime()); diff --git a/src/VlcOptions.h b/src/VlcOptions.h index 2784dde03..02671951d 100644 --- a/src/VlcOptions.h +++ b/src/VlcOptions.h @@ -20,8 +20,6 @@ #include "config_build.h" #include "verilatedos.h" -#include "V3ThreadSafety.h" - #include "config_rev.h" #include @@ -65,6 +63,7 @@ public: string annotateOut() const { return m_annotateOut; } bool annotateAll() const { return m_annotateAll; } int annotateMin() const { return m_annotateMin; } + bool countOk(uint64_t count) const { return count >= static_cast(m_annotateMin); } bool annotatePoints() const { return m_annotatePoints; } bool rank() const { return m_rank; } bool unlink() const { return m_unlink; } diff --git a/src/VlcSource.h b/src/VlcSource.h index 3d6b55e9b..35a99a065 100644 --- a/src/VlcSource.h +++ b/src/VlcSource.h @@ -20,6 +20,8 @@ #include "config_build.h" #include "verilatedos.h" +#include "VlcPoint.h" + #include #include #include @@ -37,8 +39,8 @@ class VlcSourceCount final { // MEMBERS const int m_lineno; ///< Line number - uint64_t m_count = std::numeric_limits::max(); ///< Count - bool m_ok = false; ///< Coverage is above threshold + uint64_t m_maxCount = 0; ///< Max count + uint64_t m_minCount = std::numeric_limits::max(); ///< Min count PointsSet m_points; // Points on this line public: @@ -49,19 +51,16 @@ public: // ACCESSORS int lineno() const { return m_lineno; } - uint64_t count() const { return m_count; } - bool ok() const { return m_ok; } + uint64_t maxCount() const { return m_maxCount; } + uint64_t minCount() const { return m_minCount; } // METHODS - void incCount(uint64_t count, bool ok) { - if (m_count == std::numeric_limits::max()) - m_ok = ok; - else - m_ok = m_ok && ok; - m_count = std::min(m_count, count); + void insertPoint(const VlcPoint* pointp) { + m_maxCount = std::max(m_maxCount, pointp->count()); + m_minCount = std::min(m_minCount, pointp->count()); + m_points.emplace(pointp); } - void insertPoint(const VlcPoint* pointp) { m_points.emplace(pointp); } - PointsSet& points() { return m_points; } + const PointsSet& points() { return m_points; } }; //******************************************************************** @@ -91,9 +90,8 @@ public: LinenoMap& lines() { return m_lines; } // METHODS - void lineIncCount(int lineno, uint64_t count, bool ok, const VlcPoint* pointp) { + void insertPoint(int lineno, const VlcPoint* pointp) { VlcSourceCount& sc = m_lines.emplace(lineno, lineno).first->second; - sc.incCount(count, ok); sc.insertPoint(pointp); } }; diff --git a/src/VlcTop.cpp b/src/VlcTop.cpp index d936e5cd5..55a5753e7 100644 --- a/src/VlcTop.cpp +++ b/src/VlcTop.cpp @@ -116,10 +116,28 @@ void VlcTop::writeInfo(const string& filename) { VlcSource& source = si.second; os << "SF:" << source.name() << '\n'; VlcSource::LinenoMap& lines = source.lines(); + int branchesFound = 0; + int branchesHit = 0; for (auto& li : lines) { - const VlcSourceCount& sc = li.second; - os << "DA:" << sc.lineno() << "," << sc.count() << "\n"; + VlcSourceCount& sc = li.second; + os << "DA:" << sc.lineno() << "," << sc.maxCount() << "\n"; + int num_branches = sc.points().size(); + if (num_branches == 1) continue; + branchesFound += num_branches; + int point_num = 0; + for (const auto& point : sc.points()) { + os << "BRDA:" << sc.lineno() << ","; + os << "0,"; + os << point_num << ","; + os << point->count() << "\n"; + + branchesHit += opt.countOk(point->count()); + ++point_num; + } } + os << "BRF:" << branchesFound << '\n'; + os << "BRH:" << branchesHit << '\n'; + os << "end_of_record\n"; } } @@ -195,11 +213,10 @@ void VlcTop::annotateCalc() { const int lineno = point.lineno(); if (!filename.empty() && lineno != 0) { VlcSource& source = sources().findNewSource(filename); - const bool ok = point.ok(opt.annotateMin()); UINFO(9, "AnnoCalc count " << filename << ":" << lineno << ":" << point.column() << " " << point.count() << " " << point.linescov() << '\n'); // Base coverage - source.lineIncCount(lineno, point.count(), ok, &point); + source.insertPoint(lineno, &point); // Additional lines covered by this statement bool range = false; int start = 0; @@ -208,7 +225,7 @@ void VlcTop::annotateCalc() { for (const char* covp = linescov.c_str(); true; ++covp) { if (!*covp || *covp == ',') { // Ending for (int lni = start; start && lni <= end; ++lni) { - source.lineIncCount(lni, point.count(), ok, &point); + source.insertPoint(lni, &point); } if (!*covp) break; start = 0; // Prep for next @@ -242,7 +259,7 @@ void VlcTop::annotateCalcNeeded() { VlcSourceCount& sc = li.second; // UINFO(0, "Source "<second; // UINFO(0,"Source // "<dumpAnnotate(os, opt.annotateMin()); diff --git a/src/astgen b/src/astgen index 942dc6747..238216720 100755 --- a/src/astgen +++ b/src/astgen @@ -65,9 +65,9 @@ class Node: assert not self.isCompleted self._subClasses.append(subClass) - def addOp(self, n, name, monad, kind): + def addOp(self, n, name, monad, kind, legals): assert 1 <= n <= 4 - self._ops[n] = (name, monad, kind) + self._ops[n] = (name, monad, kind, legals) self._arity = max(self._arity, n) def getOp(self, n): @@ -79,9 +79,9 @@ class Node: return self.superClass.getOp(n) return None - def addPtr(self, name, monad, kind): + def addPtr(self, name, monad, kind, legals): name = re.sub(r'^m_', '', name) - self._ptrs.append({'name': name, 'monad': monad, 'kind': kind}) + self._ptrs.append({'name': name, 'monad': monad, 'kind': kind, 'legals': legals}) # Computes derived properties over entire class hierarchy. # No more changes to the hierarchy are allowed once this was called @@ -89,8 +89,7 @@ class Node: assert not self.isCompleted # Sort sub-classes and convert to tuple, which marks completion self._subClasses = tuple( - sorted(self._subClasses, - key=lambda _: (bool(_._subClasses), _.name))) # pylint: disable=protected-access + sorted(self._subClasses, key=lambda _: (bool(_._subClasses), _.name))) # pylint: disable=protected-access self._ordIdx = ordIdx ordIdx = ordIdx + 1 @@ -128,8 +127,7 @@ class Node: if self.superClass is None: self._allSuperClasses = () else: - self._allSuperClasses = self.superClass.allSuperClasses + ( - self.superClass, ) + self._allSuperClasses = self.superClass.allSuperClasses + (self.superClass, ) return self._allSuperClasses @property @@ -139,9 +137,8 @@ class Node: if self.isLeaf: self._allSubClasses = () else: - self._allSubClasses = self.subClasses + tuple( - _ for subClass in self.subClasses - for _ in subClass.allSubClasses) + self._allSubClasses = self.subClasses + tuple(_ for subClass in self.subClasses + for _ in subClass.allSubClasses) return self._allSubClasses @property @@ -210,8 +207,7 @@ class Cpt: self._exec_syms = {} def error(self, txt): - sys.exit("%%Error: %s:%d: %s" % - (self.in_filename, self.in_linenum, txt)) + sys.exit("%%Error: %s:%d: %s" % (self.in_filename, self.in_linenum, txt)) def print(self, txt): self.out_lines.append(txt) @@ -220,8 +216,7 @@ class Cpt: self.out_lines.append(func) def _output_line(self): - self.print("#line " + str(self.out_linenum + 2) + " \"" + - self.out_filename + "\"\n") + self.print("#line " + str(self.out_linenum + 2) + " \"" + self.out_filename + "\"\n") def process(self, in_filename, out_filename): self.in_filename = in_filename @@ -234,8 +229,7 @@ class Cpt: for line in fhi: ln += 1 if not didln: - self.print("#line " + str(ln) + " \"" + self.in_filename + - "\"\n") + self.print("#line " + str(ln) + " \"" + self.in_filename + "\"\n") didln = True match = re.match(r'^\s+(TREE.*)$', line) if match: @@ -245,8 +239,8 @@ class Cpt: self.output_func(lambda self: self._output_line()) self.tree_line(func) didln = False - elif not re.match(r'^\s*(#define|/[/\*])\s*TREE', - line) and re.search(r'\s+TREE', line): + elif not re.match(r'^\s*(#define|/[/\*])\s*TREE', line) and re.search( + r'\s+TREE', line): self.error("Unknown astgen line: " + line) else: self.print(line) @@ -275,8 +269,7 @@ class Cpt: # 1 2 3 4 r'TREEOP(1?)([ACSV]?)\s*\(\s*\"([^\"]*)\"\s*,\s*\"([^\"]*)\"\s*\)', func) - match_skip = re.search(r'TREE_SKIP_VISIT\s*\(\s*\"([^\"]*)\"\s*\)', - func) + match_skip = re.search(r'TREE_SKIP_VISIT\s*\(\s*\"([^\"]*)\"\s*\)', func) if match: order = match.group(1) @@ -314,20 +307,18 @@ class Cpt: if re.match(r'^\$([a-zA-Z0-9]+)$', subnode): continue # "$lhs" is just a comment that this op has a lhs subnodeif = subnode - subnodeif = re.sub( - r'\$([a-zA-Z0-9]+)\.cast([A-Z][A-Za-z0-9]+)$', - r'VN_IS(nodep->\1(),\2)', subnodeif) - subnodeif = re.sub(r'\$([a-zA-Z0-9]+)\.([a-zA-Z0-9]+)$', - r'nodep->\1()->\2()', subnodeif) + subnodeif = re.sub(r'\$([a-zA-Z0-9]+)\.cast([A-Z][A-Za-z0-9]+)$', + r'VN_IS(nodep->\1(),\2)', subnodeif) + subnodeif = re.sub(r'\$([a-zA-Z0-9]+)\.([a-zA-Z0-9]+)$', r'nodep->\1()->\2()', + subnodeif) subnodeif = self.add_nodep(subnodeif) if mif != "" and subnodeif != "": mif += " && " mif += subnodeif exec_func = self.treeop_exec_func(to) - exec_func = re.sub( - r'([-()a-zA-Z0-9_>]+)->cast([A-Z][A-Za-z0-9]+)\(\)', - r'VN_CAST(\1,\2)', exec_func) + exec_func = re.sub(r'([-()a-zA-Z0-9_>]+)->cast([A-Z][A-Za-z0-9]+)\(\)', + r'VN_CAST(\1,\2)', exec_func) if typen not in self.treeop: self.treeop[typen] = [] @@ -431,14 +422,12 @@ class Cpt: self._exec_nsyms = 0 self._exec_syms_recurse(aref) - for sym in sorted(self._exec_syms.keys(), - key=lambda val: self._exec_syms[val]): + for sym in sorted(self._exec_syms.keys(), key=lambda val: self._exec_syms[val]): argnp = self._exec_syms[sym] arg = self.add_nodep(sym) out += "AstNodeExpr* " + argnp + " = " + arg + "->unlinkFrBack();\n" - out += "AstNodeExpr* newp = " + self._exec_new_recurse( - aref) + ";\n" + out += "AstNodeExpr* newp = " + self._exec_new_recurse(aref) + ";\n" out += "nodep->replaceWith(newp);" out += "VL_DO_DANGLING(nodep->deleteTree(), nodep);" elif func == "NEVER": @@ -454,19 +443,15 @@ class Cpt: self.tree_base() def tree_match(self): - self.print( - " // TREEOP functions, each return true if they matched & transformed\n" - ) + self.print(" // TREEOP functions, each return true if they matched & transformed\n") for base in sorted(self.treeop.keys()): for typefunc in self.treeop[base]: self.print(" // Generated by astgen\n") - self.print(" bool " + typefunc['match_func'] + "(Ast" + - base + "* nodep) {\n") + self.print(" bool " + typefunc['match_func'] + "(Ast" + base + "* nodep) {\n") self.print("\t// " + typefunc['comment'] + "\n") self.print("\tif (" + typefunc['match_if'] + ") {\n") - self.print("\t UINFO(" + str(typefunc['uinfo_level']) + - ", cvtToHex(nodep)" + " << \" " + - typefunc['uinfo'] + "\\n\");\n") + self.print("\t UINFO(" + str(typefunc['uinfo_level']) + ", cvtToHex(nodep)" + + " << \" " + typefunc['uinfo'] + "\\n\");\n") self.print("\t " + typefunc['exec_func'] + "\n") self.print("\t return true;\n") self.print("\t}\n") @@ -475,9 +460,7 @@ class Cpt: def tree_base(self): self.print(" // TREEOP visitors, call each base type's match\n") - self.print( - " // Bottom class up, as more simple transforms are generally better\n" - ) + self.print(" // Bottom class up, as more simple transforms are generally better\n") for node in AstNodeList: out_for_type_sc = [] out_for_type = [] @@ -488,15 +471,11 @@ class Cpt: if base not in self.treeop: continue for typefunc in self.treeop[base]: - lines = [ - " if (" + typefunc['match_func'] + - "(nodep)) return;\n" - ] + lines = [" if (" + typefunc['match_func'] + "(nodep)) return;\n"] if typefunc['short_circuit']: # short-circuit match fn out_for_type_sc.extend(lines) else: # Standard match fn - if typefunc[ - 'order']: # TREEOP1's go in front of others + if typefunc['order']: # TREEOP1's go in front of others out_for_type = lines + out_for_type else: out_for_type.extend(lines) @@ -509,32 +488,26 @@ class Cpt: # For types without short-circuits, we just use iterateChildren, which # saves one comparison. if len(out_for_type_sc) > 0: # Short-circuited types - self.print( - " // Generated by astgen with short-circuiting\n" + - " void visit(Ast" + node.name + - "* nodep) override {\n" + - " iterateAndNextNull(nodep->{op1}());\n".format( - op1=node.getOp(1)[0]) + "".join(out_for_type_sc)) + self.print(" // Generated by astgen with short-circuiting\n" + + " void visit(Ast" + node.name + "* nodep) override {\n" + + " iterateAndNextNull(nodep->{op1}());\n".format( + op1=node.getOp(1)[0]) + "".join(out_for_type_sc)) if out_for_type[0]: self.print( - " iterateAndNextNull(nodep->{op2}());\n".format( - op2=node.getOp(2)[0])) + " iterateAndNextNull(nodep->{op2}());\n".format(op2=node.getOp(2)[0])) if node.isSubClassOf(AstNodes["NodeTriop"]): - self.print( - " iterateAndNextNull(nodep->{op3}());\n". - format(op3=node.getOp(3)[0])) + self.print(" iterateAndNextNull(nodep->{op3}());\n".format( + op3=node.getOp(3)[0])) self.print("".join(out_for_type) + " }\n") elif len(out_for_type) > 0: # Other types with something to print skip = node.name in self.tree_skip_visit gen = "Gen" if skip else "" virtual = "virtual " if skip else "" override = "" if skip else " override" - self.print( - " // Generated by astgen\n" + " " + virtual + - "void visit" + gen + "(Ast" + node.name + "* nodep)" + - override + " {\n" + - ("" if skip else " iterateChildren(nodep);\n") + - ''.join(out_for_type) + " }\n") + self.print(" // Generated by astgen\n" + " " + virtual + "void visit" + gen + + "(Ast" + node.name + "* nodep)" + override + " {\n" + + ("" if skip else " iterateChildren(nodep);\n") + + ''.join(out_for_type) + " }\n") ###################################################################### @@ -546,7 +519,8 @@ def partitionAndStrip(string, separator): def parseOpType(string): - match = re.match(r'^(\w+)\[(\w+)\]$', string) + # Return [Optional/List, AstNodeKind, LegalAstKinds] + match = re.match(r'^(\w+)\[(.*?)\]$', string) if match: monad, kind = match.groups() if monad not in ("Optional", "List"): @@ -554,9 +528,16 @@ def parseOpType(string): kind = parseOpType(kind) if not kind or kind[0]: return None - return monad, kind[1] - if re.match(r'^Ast(\w+)$', string): - return "", string[3:] + return monad, kind[1], kind[2] + match = re.match(r'^Ast(\w+)<(.*?)>$', string) + if match: + kind = match.group(1) + legals = match.group(2) + legals = re.sub(r'\bAst', '', legals) + return "", kind, legals + match = re.match(r'^Ast(\w+)$', string) + if match: + return "", match.group(1), match.group(1) return None @@ -565,8 +546,7 @@ def read_types(filename, Nodes, prefix): def error(lineno, message): nonlocal hasErrors - print(filename + ":" + str(lineno) + ": %Error: " + message, - file=sys.stderr) + print(filename + ":" + str(lineno) + ": %Error: " + message, file=sys.stderr) hasErrors = True node = None @@ -579,8 +559,7 @@ def read_types(filename, Nodes, prefix): if not hasAstgenMembers: error( node.lineno, - "'{p}{n}' does not contain 'ASTGEN_MEMBERS_{p}{n};'".format( - p=prefix, n=node.name)) + "'{p}{n}' does not contain 'ASTGEN_MEMBERS_{p}{n};'".format(p=prefix, n=node.name)) hasAstgenMembers = False with open(filename, "r", encoding="utf8") as fh: @@ -598,8 +577,7 @@ def read_types(filename, Nodes, prefix): classn = re.sub(r'^' + prefix, '', classn) supern = re.sub(r'^' + prefix, '', supern) if not supern: - sys.exit("%Error: '{p}{c}' has no super-class".format( - p=prefix, c=classn)) + sys.exit("%Error: '{p}{c}' has no super-class".format(p=prefix, c=classn)) checkFinishedNode(node) superClass = Nodes[supern] node = Node(classn, superClass, filename, lineno) @@ -608,8 +586,7 @@ def read_types(filename, Nodes, prefix): if not node: continue - if re.match(r'^\s*ASTGEN_MEMBERS_' + prefix + node.name + ';', - line): + if re.match(r'^\s*ASTGEN_MEMBERS_' + prefix + node.name + ';', line): hasAstgenMembers = True if prefix != "Ast": @@ -631,36 +608,29 @@ def read_types(filename, Nodes, prefix): ident = ident.strip() if not sep or not re.match(r'^\w+$', ident): error( - lineno, "Malformed '@astgen " + what + - "' directive (expecting '" + what + - " := : ': " + decl) + lineno, "Malformed '@astgen " + what + "' directive (expecting '" + + what + " := : ': " + decl) else: kind = parseOpType(kind) if not kind: error( lineno, "Bad type for '@astgen " + what + - "' (expecting Ast*, Optional[Ast*], or List[Ast*]):" - + decl) + "' (expecting Ast*, Optional[Ast*], or List[Ast*]):" + decl) elif node.getOp(n) is not None: - error( - lineno, "Already defined " + what + " for " + - node.name) + error(lineno, "Already defined " + what + " for " + node.name) else: node.addOp(n, ident, *kind) - elif what in ("alias op1", "alias op2", "alias op3", - "alias op4"): + elif what in ("alias op1", "alias op2", "alias op3", "alias op4"): n = int(what[-1]) ident = rest.strip() if not re.match(r'^\w+$', ident): error( - lineno, "Malformed '@astgen " + what + - "' directive (expecting '" + what + - " := ': " + decl) + lineno, "Malformed '@astgen " + what + "' directive (expecting '" + + what + " := ': " + decl) else: op = node.getOp(n) if op is None: - error(lineno, - "Aliased op" + str(n) + " is not defined") + error(lineno, "Aliased op" + str(n) + " is not defined") else: node.addOp(n, ident, *op[1:]) elif what == "ptr": @@ -670,8 +640,7 @@ def read_types(filename, Nodes, prefix): if not kind: error( lineno, "Bad type for '@astgen " + what + - "' (expecting Ast*, Optional[Ast*], or List[Ast*]):" - + decl) + "' (expecting Ast*, Optional[Ast*], or List[Ast*]):" + decl) if not re.match(r'^m_(\w+)$', ident): error( lineno, "Malformed '@astgen ptr'" @@ -680,20 +649,15 @@ def read_types(filename, Nodes, prefix): node.addPtr(ident, *kind) else: error( - lineno, - "Malformed @astgen what (expecting 'op1'..'op4'," + + lineno, "Malformed @astgen what (expecting 'op1'..'op4'," + " 'alias op1'.., 'ptr'): " + what) else: line = re.sub(r'//.*$', '', line) if re.match(r'.*[Oo]p[1-9].*', line): - error(lineno, - "Use generated accessors to access op operands") + error(lineno, "Use generated accessors to access op operands") - if re.match( - r'^\s*Ast[A-Z][A-Za-z0-9_]+\s*\*(\s*const)?\s+m_[A-Za-z0-9_]+\s*;', - line): - error(lineno, - "Use '@astgen ptr' for Ast pointer members: " + line) + if re.match(r'^\s*Ast[A-Z][A-Za-z0-9_]+\s*\*(\s*const)?\s+m_[A-Za-z0-9_]+\s*;', line): + error(lineno, "Use '@astgen ptr' for Ast pointer members: " + line) checkFinishedNode(node) if hasErrors: @@ -707,33 +671,24 @@ def check_types(sortedTypes, prefix, abstractPrefix): for node in sortedTypes: if re.match(r'^' + abstractPrefix, node.name): if node.isLeaf: - sys.exit( - "%Error: Final {b} subclasses must not be named {b}*: {p}{n}" - .format(b=baseClass, p=prefix, n=node.name)) + sys.exit("%Error: Final {b} subclasses must not be named {b}*: {p}{n}".format( + b=baseClass, p=prefix, n=node.name)) else: if not node.isLeaf: - sys.exit( - "%Error: Non-final {b} subclasses must be named {b}*: {p}{n}" - .format(b=baseClass, p=prefix, n=node.name)) + sys.exit("%Error: Non-final {b} subclasses must be named {b}*: {p}{n}".format( + b=baseClass, p=prefix, n=node.name)) # Check ordering of node definitions hasOrderingError = False - files = tuple( - sorted(set(_.file for _ in sortedTypes if _.file is not None))) + files = tuple(sorted(set(_.file for _ in sortedTypes if _.file is not None))) for file in files: nodes = tuple(filter(lambda _, f=file: _.file == f, sortedTypes)) expectOrder = tuple(sorted(nodes, key=lambda _: (_.isLeaf, _.ordIdx))) actualOrder = tuple(sorted(nodes, key=lambda _: _.lineno)) - expect = { - node: pred - for pred, node in zip((None, ) + expectOrder[:-1], expectOrder) - } - actual = { - node: pred - for pred, node in zip((None, ) + actualOrder[:-1], actualOrder) - } + expect = {node: pred for pred, node in zip((None, ) + expectOrder[:-1], expectOrder)} + actual = {node: pred for pred, node in zip((None, ) + actualOrder[:-1], actualOrder)} for node in nodes: if expect[node] != actual[node]: hasOrderingError = True @@ -749,8 +704,7 @@ def check_types(sortedTypes, prefix, abstractPrefix): file=sys.stderr) if hasOrderingError: - sys.exit( - "%Error: Stopping due to out of order definitions listed above") + sys.exit("%Error: Stopping due to out of order definitions listed above") def read_stages(filename): @@ -783,8 +737,7 @@ def read_refs(filename): if ref not in ClassRefs: ClassRefs[ref] = {'newed': {}, 'used': {}} ClassRefs[ref]['used'][basename] = 1 - for match in re.finditer( - r'(VN_IS|VN_AS|VN_CAST)\([^.]+, ([A-Za-z0-9_]+)', line): + for match in re.finditer(r'(VN_IS|VN_AS|VN_CAST)\([^.]+, ([A-Za-z0-9_]+)', line): ref = "Ast" + match.group(2) if ref not in ClassRefs: ClassRefs[ref] = {'newed': {}, 'used': {}} @@ -796,9 +749,7 @@ def open_file(filename): if re.search(r'\.txt$', filename): fh.write("// Generated by astgen\n") else: - fh.write( - '// Generated by astgen // -*- mode: C++; c-file-style: "cc-mode" -*-' - + "\n") + fh.write('// Generated by astgen // -*- mode: C++; c-file-style: "cc-mode" -*-' + "\n") return fh @@ -808,9 +759,7 @@ def open_file(filename): def write_report(filename): with open_file(filename) as fh: - fh.write( - "Processing stages (approximate, based on order in Verilator.cpp):\n" - ) + fh.write("Processing stages (approximate, based on order in Verilator.cpp):\n") for classn in sorted(Stages.keys(), key=lambda val: Stages[val]): fh.write(" " + classn + "\n") @@ -831,14 +780,12 @@ def write_report(filename): refs = ClassRefs["Ast" + node.name] fh.write(" newed: ") for stage in sorted(refs['newed'].keys(), - key=lambda val: Stages[val] - if (val in Stages) else -1): + key=lambda val: Stages[val] if (val in Stages) else -1): fh.write(stage + " ") fh.write("\n") fh.write(" used: ") for stage in sorted(refs['used'].keys(), - key=lambda val: Stages[val] - if (val in Stages) else -1): + key=lambda val: Stages[val] if (val in Stages) else -1): fh.write(stage + " ") fh.write("\n") fh.write("\n") @@ -852,8 +799,7 @@ def write_report(filename): def write_forward_class_decls(prefix, nodeList): with open_file("V3{p}__gen_forward_class_decls.h".format(p=prefix)) as fh: for node in nodeList: - fh.write("class {p}{n:<17} // ".format(p=prefix, - n=node.name + ";")) + fh.write("class {p}{n:<17} // ".format(p=prefix, n=node.name + ";")) for superClass in node.allSuperClasses: fh.write("{p}{n:<12} ".format(p=prefix, n=superClass.name)) fh.write("\n") @@ -863,8 +809,7 @@ def write_visitor_decls(prefix, nodeList): with open_file("V3{p}__gen_visitor_decls.h".format(p=prefix)) as fh: for node in nodeList: if not node.isRoot: - fh.write("virtual void visit({p}{n}*);\n".format(p=prefix, - n=node.name)) + fh.write("virtual void visit({p}{n}*);\n".format(p=prefix, n=node.name)) def write_visitor_defns(prefix, nodeList, visitor): @@ -873,13 +818,8 @@ def write_visitor_defns(prefix, nodeList, visitor): for node in nodeList: base = node.superClass if base is not None: - fh.write( - "void {c}::visit({p}{n}* {v}) {{ visit(static_cast<{p}{b}*>({v})); }}\n" - .format(c=visitor, - p=prefix, - n=node.name, - b=base.name, - v=variable)) + fh.write("void {c}::visit({p}{n}* {v}) {{ visit(static_cast<{p}{b}*>({v})); }}\n". + format(c=visitor, p=prefix, n=node.name, b=base.name, v=variable)) def write_type_enum(prefix, nodeList): @@ -887,27 +827,21 @@ def write_type_enum(prefix, nodeList): with open_file("V3{p}__gen_type_enum.h".format(p=prefix)) as fh: fh.write(" enum en : uint16_t {\n") - for node in sorted(filter(lambda _: _.isLeaf, nodeList), - key=lambda _: _.typeId): - fh.write(" at{t} = {n},\n".format(t=node.name, - n=node.typeId)) + for node in sorted(filter(lambda _: _.isLeaf, nodeList), key=lambda _: _.typeId): + fh.write(" at{t} = {n},\n".format(t=node.name, n=node.typeId)) fh.write(" _ENUM_END = {n}\n".format(n=root.typeIdMax + 1)) fh.write(" };\n") fh.write(" enum bounds : uint16_t {\n") - for node in sorted(filter(lambda _: not _.isLeaf, nodeList), - key=lambda _: _.typeIdMin): - fh.write(" first{t} = {n},\n".format(t=node.name, - n=node.typeIdMin)) - fh.write(" last{t} = {n},\n".format(t=node.name, - n=node.typeIdMax)) + for node in sorted(filter(lambda _: not _.isLeaf, nodeList), key=lambda _: _.typeIdMin): + fh.write(" first{t} = {n},\n".format(t=node.name, n=node.typeIdMin)) + fh.write(" last{t} = {n},\n".format(t=node.name, n=node.typeIdMax)) fh.write(" _BOUNDS_END\n") fh.write(" };\n") fh.write(" const char* ascii() const VL_MT_SAFE {\n") fh.write(" static const char* const names[_ENUM_END + 1] = {\n") - for node in sorted(filter(lambda _: _.isLeaf, nodeList), - key=lambda _: _.typeId): + for node in sorted(filter(lambda _: _.isLeaf, nodeList), key=lambda _: _.typeId): fh.write(' "{T}",\n'.format(T=node.name.upper())) fh.write(" \"_ENUM_END\"\n") fh.write(" };\n") @@ -926,10 +860,14 @@ def write_type_tests(prefix, nodeList): base = "DfgVertex" variable = "vtxp" enum = "VDfgType" + else: + base = None + variable = None + enum = None for node in nodeList: fh.write( - "template<> inline bool {b}::privateTypeTest<{p}{n}>(const {b}* {v}) {{ " - .format(b=base, p=prefix, n=node.name, v=variable)) + "template<> inline bool {b}::privateTypeTest<{p}{n}>(const {b}* {v}) {{ ".format( + b=base, p=prefix, n=node.name, v=variable)) if node.isRoot: fh.write("return true;") elif not node.isLeaf: @@ -937,8 +875,9 @@ def write_type_tests(prefix, nodeList): "return static_cast({v}->type()) >= static_cast({e}::first{t}) && static_cast({v}->type()) <= static_cast({e}::last{t});" .format(v=variable, e=enum, t=node.name)) else: - fh.write("return {v}->type() == {e}::at{t};".format( - v=variable, e=enum, t=node.name)) + fh.write("return {v}->type() == {e}::at{t};".format(v=variable, + e=enum, + t=node.name)) fh.write(" }\n") @@ -949,8 +888,7 @@ def write_type_tests(prefix, nodeList): def write_ast_type_info(filename): with open_file(filename) as fh: - for node in sorted(filter(lambda _: _.isLeaf, AstNodeList), - key=lambda _: _.typeId): + for node in sorted(filter(lambda _: _.isLeaf, AstNodeList), key=lambda _: _.typeId): opTypeList = [] opNameList = [] for n in range(1, 5): @@ -959,7 +897,7 @@ def write_ast_type_info(filename): opTypeList.append('OP_UNUSED') opNameList.append('op{0}p'.format(n)) else: - name, monad, _ = op + name, monad, _, _ = op if not monad: opTypeList.append('OP_USED') elif monad == "Optional": @@ -968,12 +906,11 @@ def write_ast_type_info(filename): opTypeList.append('OP_LIST') opNameList.append(name) # opTypeStr = ', '.join(opTypeList) - opTypeStr = ', '.join( - ['VNTypeInfo::{0}'.format(s) for s in opTypeList]) + opTypeStr = ', '.join(['VNTypeInfo::{0}'.format(s) for s in opTypeList]) opNameStr = ', '.join(['"{0}"'.format(s) for s in opNameList]) fh.write( - ' {{ "Ast{name}", {{{opTypeStr}}}, {{{opNameStr}}}, sizeof(Ast{name}) }},\n' - .format( + ' {{ "Ast{name}", {{{opTypeStr}}}, {{{opNameStr}}}, sizeof(Ast{name}) }},\n'. + format( name=node.name, opTypeStr=opTypeStr, opNameStr=opNameStr, @@ -984,34 +921,58 @@ def write_ast_impl(filename): with open_file(filename) as fh: def emitBlock(pattern, **fmt): - fh.write( - textwrap.indent(textwrap.dedent(pattern), - " ").format(**fmt)) + fh.write(pattern.format(**fmt)) for node in AstNodeList: if node.name == "Node": continue - emitBlock("const char* Ast{t}::brokenGen() const {{\n", - t=node.name) + emitBlock("const char* Ast{t}::brokenGen() const {{\n", t=node.name) if node.superClass.name != 'Node': emitBlock(" BROKEN_BASE_RTN(Ast{base}::brokenGen());\n", base=node.superClass.name) for ptr in node.ptrs: if ptr['monad'] == 'Optional': - emitBlock( - " BROKEN_RTN(m_{name} && !m_{name}->brokeExists());\n", - name=ptr['name']) + emitBlock(" BROKEN_RTN(m_{name} && !m_{name}->brokeExists());\n", + name=ptr['name']) else: emitBlock(" BROKEN_RTN(!m_{name});\n" + " BROKEN_RTN(!m_{name}->brokeExists());\n", name=ptr['name']) + if ptr['legals'] != '': + emitBlock(" BROKEN_RTN(m_{name} && !(", name=ptr['name']) + eor = "" + for legal in ptr['legals'].split('|'): + # We use privateTypeTest, as VN_IS would assert that we know + # the type is correct, but we want to check regardless, + # to find errors after raw node edits/replacements + emitBlock("{eor}privateTypeTest(m_{name})", + eor=eor, + name=ptr['name'], + legal=legal) + eor = " || " + emitBlock("));\n") + for i in range(1, 5): + op = node.getOp(i) + if op is None: + continue + name, _, _, legals = op + if legals != '': + emitBlock(" BROKEN_RTN({name}() && !(", name=name) + eor = "" + for legal in legals.split('|'): + emitBlock("{eor}privateTypeTest({name}())", + eor=eor, + name=name, + legal=legal) + eor = " || " + emitBlock("));\n") # Node's broken rules can be specialized by declaring broken() - emitBlock(" return Ast{t}::broken(); }}\n", t=node.name) + emitBlock(" return Ast{t}::broken();\n", t=node.name) + emitBlock("}}\n", t=node.name) emitBlock("void Ast{t}::cloneRelinkGen() {{\n", t=node.name) if node.superClass.name != 'Node': - emitBlock(" Ast{base}::cloneRelinkGen();\n", - base=node.superClass.name) + emitBlock(" Ast{base}::cloneRelinkGen();\n", base=node.superClass.name) for ptr in node.ptrs: emitBlock( " if (m_{name} && m_{name}->clonep()) m_{name} = m_{name}->clonep();\n", @@ -1020,14 +981,11 @@ def write_ast_impl(filename): emitBlock("}}\n") - emitBlock("void Ast{t}::dumpJsonGen(std::ostream& str) const {{\n", - t=node.name) + emitBlock("void Ast{t}::dumpJsonGen(std::ostream& str) const {{\n", t=node.name) if node.superClass.name != 'Node': - emitBlock(" Ast{base}::dumpJson(str);\n", - base=node.superClass.name) + emitBlock(" Ast{base}::dumpJson(str);\n", base=node.superClass.name) for ptr in node.ptrs: - emitBlock(" dumpJsonPtr(str, \"{name}\", m_{name});\n", - name=ptr['name']) + emitBlock(" dumpJsonPtr(str, \"{name}\", m_{name});\n", name=ptr['name']) emitBlock("}}\n") emitBlock( @@ -1037,10 +995,8 @@ def write_ast_impl(filename): op = node.getOp(i) if op is None: continue - name, _, _ = op - emitBlock( - " dumpNodeListJson(str, {name}(), \"{name}\", indent);\n", - name=name) + name, _, _, _ = op + emitBlock(" dumpNodeListJson(str, {name}(), \"{name}\", indent);\n", name=name) emitBlock("}}\n") @@ -1059,9 +1015,7 @@ def write_ast_macros(filename): if not any_ptr: fh.write("private: \\\n") any_ptr = True - emitBlock("Ast{kind}* m_{name} = nullptr;", - name=ptr['name'], - kind=ptr['kind']) + emitBlock("Ast{kind}* m_{name} = nullptr;", name=ptr['name'], kind=ptr['kind']) if any_ptr: fh.write("public: \\\n") # TODO pointer accessors @@ -1107,9 +1061,9 @@ def write_ast_macros(filename): op = node.getOp(n) if not op: continue - name, monad, kind = op - retrieve = ("VN_DBG_AS(op{n}p(), {kind})" if kind != "Node" - else "op{n}p()").format(n=n, kind=kind) + name, monad, kind, _ = op + retrieve = ("VN_DBG_AS(op{n}p(), {kind})" + if kind != "Node" else "op{n}p()").format(n=n, kind=kind) superOp = node.superClass.getOp(n) superName = None if superOp: @@ -1126,8 +1080,7 @@ def write_ast_macros(filename): n=n, retrieve=retrieve) if superOp: - hiddenMethods.append("add" + superName[0].upper() + - superName[1:]) + hiddenMethods.append("add" + superName[0].upper() + superName[1:]) elif monad == "Optional": emitBlock('''\ Ast{kind}* {name}() const VL_MT_STABLE {{ return {retrieve}; }} @@ -1150,27 +1103,24 @@ def write_ast_macros(filename): if hiddenMethods: fh.write("private: \\\n") for method in hiddenMethods: - fh.write(" using Ast{sup}::{method}; \\\n".format( - sup=node.superClass.name, method=method)) + fh.write(" using Ast{sup}::{method}; \\\n".format(sup=node.superClass.name, + method=method)) fh.write("public: \\\n") - fh.write( - " static_assert(true, \"\")\n") # Swallowing the semicolon + fh.write(" static_assert(true, \"\")\n") # Swallowing the semicolon # Only care about leaf classes for the rest if node.isLeaf: fh.write( - "#define ASTGEN_SUPER_{t}(...) Ast{b}(VNType::at{t}, __VA_ARGS__)\n" - .format(t=node.name, b=node.superClass.name)) + "#define ASTGEN_SUPER_{t}(...) Ast{b}(VNType::at{t}, __VA_ARGS__)\n".format( + t=node.name, b=node.superClass.name)) fh.write("\n") def write_ast_yystype(filename): with open_file(filename) as fh: for node in AstNodeList: - fh.write("Ast{t}* {m}p;\n".format(t=node.name, - m=node.name[0].lower() + - node.name[1:])) + fh.write("Ast{t}* {m}p;\n".format(t=node.name, m=node.name[0].lower() + node.name[1:])) ################################################################################ @@ -1199,7 +1149,7 @@ def write_dfg_macros(filename): s=node.superClass.name) for n in range(1, node.arity + 1): - name, _, _ = node.getOp(n) + name, _, _, _ = node.getOp(n) emitBlock('''\ DfgVertex* {name}() const {{ return source<{n}>(); }} void {name}(DfgVertex* vtxp) {{ relinkSource<{n}>(vtxp); }} @@ -1207,8 +1157,7 @@ def write_dfg_macros(filename): name=name, n=n - 1) - operandNames = tuple( - node.getOp(n)[0] for n in range(1, node.arity + 1)) + operandNames = tuple(node.getOp(n)[0] for n in range(1, node.arity + 1)) if operandNames: emitBlock('''\ const std::string srcName(size_t idx) const override {{ @@ -1217,10 +1166,8 @@ def write_dfg_macros(filename): }} ''', a=node.arity, - ns=", ".join( - map(lambda _: '"' + _ + '"', operandNames))) - fh.write( - " static_assert(true, \"\")\n") # Swallowing the semicolon + ns=", ".join(map(lambda _: '"' + _ + '"', operandNames))) + fh.write(" static_assert(true, \"\")\n") # Swallowing the semicolon def write_dfg_auto_classes(filename): @@ -1254,11 +1201,8 @@ def write_dfg_ast_to_dfg(filename): if (node.file is not None) or (not node.isLeaf): continue - fh.write( - "void visit(Ast{t}* nodep) override {{\n".format(t=node.name)) - fh.write( - ' UASSERT_OBJ(!nodep->user1p(), nodep, "Already has Dfg vertex");\n\n' - ) + fh.write("void visit(Ast{t}* nodep) override {{\n".format(t=node.name)) + fh.write(' UASSERT_OBJ(!nodep->user1p(), nodep, "Already has Dfg vertex");\n\n') fh.write(" if (unhandled(nodep)) return;\n\n") for i in range(node.arity): fh.write(" iterate(nodep->op{j}p());\n".format(j=i + 1)) @@ -1267,9 +1211,8 @@ def write_dfg_ast_to_dfg(filename): ' UASSERT_OBJ(nodep->op{j}p()->user1p(), nodep, "Child {j} missing Dfg vertex");\n' .format(j=i + 1)) fh.write("\n") - fh.write( - " Dfg{t}* const vtxp = makeVertex(nodep, *m_dfgp);\n" - .format(t=node.name)) + fh.write(" Dfg{t}* const vtxp = makeVertex(nodep, *m_dfgp);\n".format( + t=node.name)) fh.write(" if (!vtxp) {\n") fh.write(" m_foundUnhandled = true;\n") fh.write(" ++m_ctx.m_nonRepNode;\n") @@ -1277,8 +1220,8 @@ def write_dfg_ast_to_dfg(filename): fh.write(" }\n\n") for i in range(node.arity): fh.write( - " vtxp->relinkSource<{i}>(nodep->op{j}p()->user1u().to());\n" - .format(i=i, j=i + 1)) + " vtxp->relinkSource<{i}>(nodep->op{j}p()->user1u().to());\n". + format(i=i, j=i + 1)) fh.write("\n") fh.write(" m_uncommittedVertices.push_back(vtxp);\n") fh.write(" nodep->user1p(vtxp);\n") @@ -1292,14 +1235,12 @@ def write_dfg_dfg_to_ast(filename): if (node.file is not None) or (not node.isLeaf): continue - fh.write( - "void visit(Dfg{t}* vtxp) override {{\n".format(t=node.name)) + fh.write("void visit(Dfg{t}* vtxp) override {{\n".format(t=node.name)) for i in range(node.arity): fh.write( " AstNodeExpr* const op{j}p = convertDfgVertexToAstNodeExpr(vtxp->source<{i}>());\n" .format(i=i, j=i + 1)) - fh.write( - " m_resultp = makeNode(vtxp".format(t=node.name)) + fh.write(" m_resultp = makeNode(vtxp".format(t=node.name)) for i in range(node.arity): fh.write(", op{j}p".format(j=i + 1)) fh.write(");\n") @@ -1313,8 +1254,7 @@ parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Generate V3Ast headers to reduce C++ code duplication.""", - epilog= - """Copyright 2002-2024 by Wilson Snyder. This program is free software; you + epilog="""Copyright 2002-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. @@ -1322,15 +1262,9 @@ Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('-I', action='store', help='source code include directory') -parser.add_argument('--astdef', - action='append', - help='add AST definition file (relative to -I)') -parser.add_argument('--dfgdef', - action='append', - help='add DFG definition file (relative to -I)') -parser.add_argument('--classes', - action='store_true', - help='makes class declaration files') +parser.add_argument('--astdef', action='append', help='add AST definition file (relative to -I)') +parser.add_argument('--dfgdef', action='append', help='add DFG definition file (relative to -I)') +parser.add_argument('--classes', action='store_true', help='makes class declaration files') parser.add_argument('--debug', action='store_true', help='enable debug') parser.add_argument('infiles', nargs='*', help='list of input .cpp filenames') @@ -1402,15 +1336,14 @@ for node in AstNodeList: for n in range(1, node.arity + 1): op = node.getOp(n) if op is not None: - name, monad, kind = op + name, monad, kind, legals = op assert monad == "", "Cannot represent AstNode as DfgVertex" - vertex.addOp(n, name, "", "") + vertex.addOp(n, name, "", "", "") # Compute derived properties over the whole DfgVertex hierarchy DfgVertices["Vertex"].complete() -DfgVertexList = tuple(map(lambda _: DfgVertices[_], - sorted(DfgVertices.keys()))) +DfgVertexList = tuple(map(lambda _: DfgVertices[_], sorted(DfgVertices.keys()))) check_types(DfgVertexList, "Dfg", "Vertex") @@ -1457,8 +1390,7 @@ for cpt in Args.infiles: if not re.search(r'.cpp$', cpt): sys.exit("%Error: Expected argument to be .cpp file: " + cpt) cpt = re.sub(r'.cpp$', '', cpt) - Cpt().process(in_filename=Args.I + "/" + cpt + ".cpp", - out_filename=cpt + "__gen.cpp") + Cpt().process(in_filename=Args.I + "/" + cpt + ".cpp", out_filename=cpt + "__gen.cpp") ###################################################################### # Local Variables: diff --git a/src/bisonpre b/src/bisonpre index 3f97f0f2c..8c505c312 100755 --- a/src/bisonpre +++ b/src/bisonpre @@ -11,11 +11,12 @@ import sys ###################################################################### +Bison_Version = None + def process(): unlink_outputs() - bison_version_check() supports_report = Bison_Version >= 2.3 # supports_counter_examples = Bison_Version >= 3.8 @@ -28,15 +29,14 @@ def process(): + (" -d" if Args.definitions else "") # + (" -k" if Args.token_table else "") # + (" -v" if Args.verbose else "") # - + (" --report=itemset --report=lookahead" if - (Args.verbose and supports_report) else "") + + (" -Wcounterexamples" if Args.Wcounterexamples else "") # + + (" --report=itemset --report=lookahead" if (Args.verbose and supports_report) else "") # Useful but slow: # (" -Wcounterexamples" if # (Args.verbose and supports_counter_examples) else "") # # -p required for GLR parsers; they write to -p basename, not -o - + ((" -p " + Args.name_prefix) if Args.name_prefix else "") + " -b " + - tmp_prefix() # + + ((" -p " + Args.name_prefix) if Args.name_prefix else "") + " -b " + tmp_prefix() # + " -o " + tmp_prefix() + ".c" # + " " + tmp_prefix() + ".y") @@ -44,11 +44,10 @@ def process(): status = subprocess.call(command, shell=True) if status != 0: unlink_outputs() - sys.exit("bisonpre: %Error: " + Args.yacc + " version " + - str(Bison_Version) + " run failed due to errors\n") + sys.exit("bisonpre: %Error: " + Args.yacc + " version " + str(Bison_Version) + + " run failed due to errors\n") - clean_output(tmp_prefix() + ".output", - output_prefix() + ".output", True, False) + clean_output(tmp_prefix() + ".output", output_prefix() + ".output", True, False) warning_check(output_prefix() + ".output") clean_output(tmp_prefix() + ".c", output_prefix() + ".c", False, True) @@ -88,9 +87,7 @@ def unlink_outputs(): def bison_version_check(): - with subprocess.Popen(Args.yacc + " --version", - shell=True, - stdout=subprocess.PIPE) as sp: + with subprocess.Popen(Args.yacc + " --version", shell=True, stdout=subprocess.PIPE) as sp: out = str(sp.stdout.read()) match = re.search(r'([0-9]+\.[0-9]+)', out) if match: @@ -98,12 +95,9 @@ def bison_version_check(): if v < 1.875: sys.exit("bisonpre: %Error: '" + Args.yacc + "' is version " + v + "; version 1.875 or newer is required\n") - global Bison_Version # pylint: disable=global-variable-undefined - Bison_Version = v - return + return v - sys.exit("bisonpre: %Error: '" + Args.yacc + - "' is not installed, or not working\n") + sys.exit("bisonpre: %Error: '" + Args.yacc + "' is not installed, or not working\n") def clean_output(filename, outname, is_output, is_c): @@ -141,8 +135,7 @@ def clean_output(filename, outname, is_output, is_c): if is_c: token_values = {} for line in lines: - if re.search(r'enum\s+yytokentype', - line) and not re.search(r';', line): + if re.search(r'enum\s+yytokentype', line) and not re.search(r';', line): match = re.search(r'\b(\S+) = (\d+)', line) if match: token_values[match.group(2)] = match.group(1) @@ -151,8 +144,7 @@ def clean_output(filename, outname, is_output, is_c): if _enaline(line) and re.search(r'BISONPRE_TOKEN_NAMES', line): out.append(line) for tv in sorted(token_values.keys()): - out.append("\tcase %d: return \"%s\";\n" % - (tv, token_values[tv])) + out.append("\tcase %d: return \"%s\";\n" % (tv, token_values[tv])) continue out.append(line) lines = out @@ -165,8 +157,7 @@ def clean_output(filename, outname, is_output, is_c): # Fix bison 2.3 and GCC 4.2.1 line = re.sub(r'\(YY_\("', '(YY_((char*)"', line) # Fix bison 2.3 glr-parser warning about yyerrorloc.YYTYPE::yydummy uninit - line = re.sub(r'(YYLTYPE yyerrloc;)', - r'\1 yyerrloc.yydummy=0;/*bisonpre*/', line) + line = re.sub(r'(YYLTYPE yyerrloc;)', r'\1 yyerrloc.yydummy=0;/*bisonpre*/', line) # Fix bison 3.6.1 unexpected nested-comment line = re.sub(r'/\* "/\*.*\*/" \*/', '', line) fh.write(line) @@ -177,11 +168,8 @@ def warning_check(filename): linenum = 0 for line in fh: linenum += 1 - if re.search(r'(conflicts|warning:|^useless)', - line, - flags=re.IGNORECASE): - sys.exit("%Error: " + filename + ":" + str(linenum) + ": " + - line + "\n") + if re.search(r'(conflicts|warning:|^useless)', line, flags=re.IGNORECASE): + sys.exit("%Error: " + filename + ":" + str(linenum) + ": " + line + "\n") ###################################################################### @@ -214,12 +202,9 @@ def clean_input(filename, outname): # ^/ to prevent comments from matching if re.match(r'^[a-zA-Z0-9_<>]+:[^/]*[a-zA-Z]', line): sys.exit("%Error: " + filename + ":" + str(lineno) + - ": Move text on rule line to next line: " + line + - "\n") + ": Move text on rule line to next line: " + line + "\n") - matcha = re.match(r'^([a-zA-Z0-9_]+)<(\S*)>(.*)$', - line, - flags=re.DOTALL) + matcha = re.match(r'^([a-zA-Z0-9_]+)<(\S*)>(.*)$', line, flags=re.DOTALL) matchb = re.match(r'^([a-zA-Z0-9_]+):', line) if re.match(r'^%%', line): @@ -231,8 +216,8 @@ def clean_input(filename, outname): dtype = matcha.group(2) line = name + matcha.group(3) if name in Rules: - sys.exit("%Error: " + filename + ":" + str(lineno) + - ": Redeclaring '" + name + "': " + line) + sys.exit("%Error: " + filename + ":" + str(lineno) + ": Redeclaring '" + name + + "': " + line) if dtype not in types: types[dtype] = {} types[dtype][name] = 1 @@ -250,8 +235,8 @@ def clean_input(filename, outname): name = matchb.group(1) if name not in ('public', 'private'): if name in Rules: - sys.exit("%Error: " + filename + ":" + str(lineno) + - ": Redeclaring '" + name + "': " + line) + sys.exit("%Error: " + filename + ":" + str(lineno) + ": Redeclaring '" + + name + "': " + line) Rules[name] = { 'name': name, 'type': "", @@ -268,8 +253,7 @@ def clean_input(filename, outname): cline = re.sub(r'//.*$', '\n', line) if re.match(r'^\s*;', cline): if not last_rule: - sys.exit("%Error: " + filename + ":" + str(lineno) + - ": Stray semicolon\n") + sys.exit("%Error: " + filename + ":" + str(lineno) + ": Stray semicolon\n") last_rule = None elif last_rule: Rules[last_rule]['rules_and_productions'] += cline @@ -279,8 +263,8 @@ def clean_input(filename, outname): dtype = match.group(1) tok = match.group(2) if tok in tokens: - sys.exit("%Error: " + filename + ":" + str(lineno) + - ": Redeclaring '" + tok + "': " + line) + sys.exit("%Error: " + filename + ":" + str(lineno) + ": Redeclaring '" + tok + + "': " + line) tokens[tok] = dtype for tok in re.split(r'[^a-zA-Z0-9_]+', cline): @@ -299,17 +283,16 @@ def clean_input(filename, outname): lineno += 1 if _enaline(line) and re.search(r'BISONPRE_VERSION', line): # 1 2 3 4 - match = re.search( - r'BISONPRE_VERSION\((\S+)\s*,\s*((\S+)\s*,)?\s*([^\),]+)\)\s*$', - line) + match = re.search(r'BISONPRE_VERSION\((\S+)\s*,\s*((\S+)\s*,)?\s*([^\),]+)\)\s*$', + line) if not match: sys.exit("%Error: " + filename + ":" + str(lineno) + ": Bad form of BISONPRE_VERSION: " + line) ver = match.group(1) ver_max = match.group(3) cmd = match.group(4) - if Bison_Version >= float(ver) and ( - not ver_max or Bison_Version <= float(ver_max)): + if Bison_Version >= float(ver) and (not ver_max + or Bison_Version <= float(ver_max)): line = cmd + "\n" else: line = "//NOP: " + line @@ -323,10 +306,9 @@ def clean_input(filename, outname): for line in linesin: lineno += 1 if _enaline(line) and re.search(r'BISONPRE_NOT', line): - match = re.search( - r'(.*)BISONPRE_NOT\((\S+)\)\s*(\{[^}]+})\s*(.*)$', - line, - flags=re.DOTALL) + match = re.search(r'(.*)BISONPRE_NOT\((\S+)\)\s*(\{[^}]+})\s*(.*)$', + line, + flags=re.DOTALL) if not match: sys.exit("%Error: " + filename + ":" + str(lineno) + ": Bad form of BISONPRE_NOT: " + line) @@ -337,8 +319,7 @@ def clean_input(filename, outname): for etok in endtoks: if etok not in tokens: sys.exit("%Error: " + filename + ":" + str(lineno) + - ": Can't find definition for token: " + etok + - "\n") + ": Can't find definition for token: " + etok + "\n") # Push it all onto one line to avoid error messages changing pipe = "" for tok in sorted(tokens.keys()): @@ -397,10 +378,8 @@ def clean_input(filename, outname): # Bison doesn't have a #line directive, so we need somewhere to insert into line = re.sub(r'^\s*//.*$', '', line) if not re.match(r'^\s*$', line): - sys.exit( - "%Error: " + filename + ":" + str(lineno) + ": Need " + - str(needmore) + - " more blank lines to keep line numbers constant\n") + sys.exit("%Error: " + filename + ":" + str(lineno) + ": Need " + + str(needmore) + " more blank lines to keep line numbers constant\n") needmore -= 1 else: lines.append(line) @@ -418,8 +397,8 @@ def _bisonpre_copy(text, lineno, depth): text, flags=re.DOTALL) if not match: - sys.exit("%Error: " + Filename + ":" + str(lineno) + - ": Bad form of BISONPRE_NOT: " + text) + sys.exit("%Error: " + Filename + ":" + str(lineno) + ": Bad form of BISONPRE_NOT: " + + text) text = match.group(1) + '{HERE}' + match.group(5) once = match.group(2) rule = match.group(3) @@ -448,8 +427,7 @@ def _bisonpre_copy(text, lineno, depth): insert = re.sub(left, right, insert) insert = re.sub(r'[ \t\n]+\n', "\n", insert) - insert = re.sub(r'\n', " ", - insert) # Optional - preserve line numbering + insert = re.sub(r'\n', " ", insert) # Optional - preserve line numbering text = re.sub(r'{HERE}', insert, text) depth += 1 return text @@ -465,8 +443,7 @@ def _enaline(line): parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, - description= - """Bisonpre is a wrapper for the Bison YACC replacement. Input to Bison is + description="""Bisonpre is a wrapper for the Bison YACC replacement. Input to Bison is preprocessed with substitution as described below under EXTENSIONS. Output from Bison is checked for additional errors, and corrected to work around various compile warnings.""", @@ -522,40 +499,25 @@ parser.add_argument('--yacc', help='name of the bison executable, defaults to "bison"') # Arguments passed through to bison -parser.add_argument('-b', - '--file-prefix', - action='store', - help='Passed to bison.') -parser.add_argument('-d', - '--definitions', - action='store_true', - help='Passed to bison.') -parser.add_argument('-k', - '--token-table', - action='store_true', - help='Passed to bison.') +parser.add_argument('-b', '--file-prefix', action='store', help='Passed to bison.') +parser.add_argument('-d', '--definitions', action='store_true', help='Passed to bison.') +parser.add_argument('-k', '--token-table', action='store_true', help='Passed to bison.') parser.add_argument('-o', '--output', action='store', required=True, help='Passed to bison. Sets output file name') -parser.add_argument('-p', - '--name-prefix', - action='store', - help='Passed to bison.') -parser.add_argument('-t', - '--debug', - action='store_true', - help='Passed to bison.') -parser.add_argument('-v', - '--verbose', - action='store_true', - help='Passed to bison.') +parser.add_argument('-p', '--name-prefix', action='store', help='Passed to bison.') +parser.add_argument('-t', '--debug', action='store_true', help='Passed to bison.') +parser.add_argument('-v', '--verbose', action='store_true', help='Passed to bison.') +parser.add_argument('-Wcounterexamples', action='store_true', help='Passed to bison.') parser.add_argument('input', help='Passed to bison. Input grammar file.') Args = parser.parse_args() +Bison_Version = bison_version_check() + process() ###################################################################### diff --git a/src/cppcheck_filtered b/src/cppcheck_filtered index b158f724e..894c1aad7 100755 --- a/src/cppcheck_filtered +++ b/src/cppcheck_filtered @@ -115,11 +115,9 @@ def _suppress(filename, linenum, eid): return True if eid == 'constParameter' and re.search(r'gtkwave/', filename): return True - if eid == 'ctuOneDefinitionRuleViolation' and re.search( - r'vltstd/', filename): + if eid == 'ctuOneDefinitionRuleViolation' and re.search(r'vltstd/', filename): return True - if eid == 'duplicateConditionalAssign' and re.search( - r'gtkwave/', filename): + if eid == 'duplicateConditionalAssign' and re.search(r'gtkwave/', filename): return True if eid == 'knownConditionTrueFalse' and re.search(r'gtkwave/', filename): return True @@ -151,8 +149,7 @@ def _suppress(filename, linenum, eid): return True if not os.path.exists(filename): - print("%Warning: " + filename + " does not exist, ignored", - file=sys.stderr) + print("%Warning: " + filename + " does not exist, ignored", file=sys.stderr) return False with open(filename, "r", encoding="utf8") as fh: @@ -160,13 +157,11 @@ def _suppress(filename, linenum, eid): for line in fh: lineno += 1 if (lineno + 1) == linenum: - match = re.search( - r'(cppcheck|cppcheck-has-bug|cppverilator)-suppress((\s+\S+)+)', - line) + match = re.search(r'(cppcheck|cppcheck-has-bug|cppverilator)-suppress((\s+\S+)+)', + line) if match: for supid in match.group(2).split(): - if (supid == eid or (eid in SuppressMap - and supid == SuppressMap[eid])): + if (supid == eid or (eid in SuppressMap and supid == SuppressMap[eid])): return True return False @@ -182,8 +177,7 @@ filters out unnecessary warnings related to Verilator. Run as: cd $VERILATOR_ROOT make -k cppcheck""", - epilog= - """Copyright 2014-2024 by Wilson Snyder. This program is free software; you + epilog="""Copyright 2014-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/src/flexfix b/src/flexfix index 64f95a385..13abaec70 100755 --- a/src/flexfix +++ b/src/flexfix @@ -16,23 +16,19 @@ import sys for line in sys.stdin: # Fix flex 2.6.1 warning - line = re.sub( - r'for \( i = 0; i < _yybytes_len; \+\+i \)', - r'for ( i = 0; (yy_size_t)(i) < (yy_size_t)(_yybytes_len); ++i )', - line) + line = re.sub(r'for \( i = 0; i < _yybytes_len; \+\+i \)', + r'for ( i = 0; (yy_size_t)(i) < (yy_size_t)(_yybytes_len); ++i )', line) # Fix flex 2.6.0 warning line = re.sub( r'\(\(int\) \(\(yy_n_chars\) \+ number_to_move\) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size\)', r'((int) ((yy_n_chars) + number_to_move) > (int) YY_CURRENT_BUFFER_LVALUE->yy_buf_size)', line) - line = re.sub(r' number_to_move == YY_MORE_ADJ ', - r' (int)number_to_move == (int)YY_MORE_ADJ ', line) - # Fix flex 2.5.4 namespace omission - line = re.sub(r'^class istream;', - '#include \nusing namespace std;\n', line) - # Fix flex 2.5.31 redefinition - line = re.sub(r'(\#define\s+yyFlexLexer\s+yyFlexLexer)', r'//flexfix: \1', + line = re.sub(r' number_to_move == YY_MORE_ADJ ', r' (int)number_to_move == (int)YY_MORE_ADJ ', line) + # Fix flex 2.5.4 namespace omission + line = re.sub(r'^class istream;', '#include \nusing namespace std;\n', line) + # Fix flex 2.5.31 redefinition + line = re.sub(r'(\#define\s+yyFlexLexer\s+yyFlexLexer)', r'//flexfix: \1', line) # Fix flex 2.5.1 yytext_ptr undef line = re.sub(r'(\#undef\s+yytext_ptr)', r'//flexfix: \1', line) # Fix flex 2.5.4 and GCC 4.1.0 warn_unused_result @@ -41,8 +37,7 @@ for line in sys.stdin: line = re.sub(r'for \( n = 0; n < max_size && ', r'for ( n = 0; ((size_t)n < (size_t)max_size) && ', line) # Fix flex 2.5.4 and GCC 4.0.2 under FLEX_DEBUG - line = re.sub(r'--accepting rule at line %d ', - r'--accepting rule at line %ld ', line) + line = re.sub(r'--accepting rule at line %d ', r'--accepting rule at line %ld ', line) # Fix compiler warning filenames line = re.sub(r'(#line \d+ ".*)_pretmp', r'\1', line) # Fix 'register' storage class specifier is deprecated and incompatible with C++17 diff --git a/src/verilog.y b/src/verilog.y index 0f265688e..9fbf16bde 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -83,7 +83,8 @@ public: AstCase* m_caseAttrp = nullptr; // Current case statement for attribute adding AstNodeDType* m_varDTypep = nullptr; // Pointer to data type for next signal declaration AstNodeDType* m_memDTypep = nullptr; // Pointer to data type for next member declaration - AstDelay* m_netDelayp = nullptr; // Pointer to delay for next signal declaration + std::unique_ptr m_netDelayp = nullptr; // Pointer to delay for next signal + // declaration AstStrengthSpec* m_netStrengthp = nullptr; // Pointer to strength for next net declaration FileLine* m_instModuleFl = nullptr; // Fileline of module referenced for instantiations AstPin* m_instParamp = nullptr; // Parameters for instantiations @@ -124,6 +125,7 @@ public: return v3Global.opt.trace() && m_tracingParse && fl->tracingOn(); } AstRange* scrubRange(AstNodeRange* rangep) VL_MT_DISABLED; + AstNodePreSel* scrubSel(AstNodeExpr* fromp, AstNodePreSel* selp) VL_MT_DISABLED; AstNodeDType* createArray(AstNodeDType* basep, AstNodeRange* rangep, bool isPacked) VL_MT_DISABLED; AstVar* createVariable(FileLine* fileline, const string& name, AstNodeRange* arrayp, @@ -162,7 +164,7 @@ public: } AstDisplay* createDisplayError(FileLine* fileline) { AstDisplay* nodep = new AstDisplay{fileline, VDisplayType::DT_ERROR, "", nullptr, nullptr}; - AstNode::addNext(nodep, new AstStop{fileline, true}); + AstNode::addNext(nodep, new AstStop{fileline, false}); return nodep; } AstNodeExpr* createGatePin(AstNodeExpr* exprp) { @@ -184,14 +186,14 @@ public: } AstNode* createTypedef(FileLine* fl, const string& name, AstNode* attrsp, AstNodeDType* basep, AstNodeRange* rangep) { - AstNode* const nodep = new AstTypedef{fl, name, attrsp, VFlagChildDType{}, - GRAMMARP->createArray(basep, rangep, false)}; + AstTypedef* const nodep = new AstTypedef{fl, name, attrsp, VFlagChildDType{}, + GRAMMARP->createArray(basep, rangep, false)}; SYMP->reinsert(nodep); PARSEP->tagNodep(nodep); return nodep; } AstNode* createTypedefFwd(FileLine* fl, const string& name) { - AstNode* const nodep = new AstTypedefFwd{fl, name}; + AstTypedefFwd* const nodep = new AstTypedefFwd{fl, name}; SYMP->reinsert(nodep); PARSEP->tagNodep(nodep); return nodep; @@ -211,7 +213,8 @@ public: if (m_varDTypep) VL_DO_CLEAR(m_varDTypep->deleteTree(), m_varDTypep = nullptr); m_varDTypep = dtypep; } - void setNetDelay(AstDelay* netDelayp) { m_netDelayp = netDelayp; } + void setNetDelay(AstDelay* netDelayp) { m_netDelayp.reset(netDelayp); } + AstDelay* getNetDelay() { return m_netDelayp.release(); } void setNetStrength(AstStrengthSpec* netStrengthp) { m_netStrengthp = netStrengthp; } void pinPush() { m_pinStack.push(m_pinNum); @@ -1179,6 +1182,13 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) // Blank lines for type insertion // Blank lines for type insertion // Blank lines for type insertion +// Blank lines for type insertion +// Blank lines for type insertion +// Blank lines for type insertion +// Blank lines for type insertion +// Blank lines for type insertion +// Blank lines for type insertion +// Blank lines for type insertion %start source_text @@ -1315,7 +1325,7 @@ package_import_item: // ==IEEE: package_import_item $$ = nullptr; $1->v3error("Importing from missing package '" << *$1 << "'"); } else { - $$ = new AstPackageImport{$2, VN_CAST($1, Package), *$3}; + $$ = new AstPackageImport{$2, *$1, *$3}; SYMP->importItem($1, *$3); } } ; @@ -1338,7 +1348,7 @@ package_export_itemList: package_export_item: // ==IEEE: package_export_item idCC yP_COLONCOLON package_import_itemObj - { $$ = new AstPackageExport{$3, VN_CAST($1, Package), *$3}; + { $$ = new AstPackageExport{$3, *$1, *$3}; if ($1) SYMP->exportItem($1, *$3); } ; @@ -1402,12 +1412,17 @@ udpFront: SYMP->pushNew($$); } ; -parameter_value_assignmentE: // IEEE: [ parameter_value_assignment ] +parameter_value_assignmentInstE: // IEEE: [ parameter_value_assignment ] for instance /* empty */ { $$ = nullptr; } - | parameter_value_assignment { $$ = $1; } + | parameter_value_assignmentInst { $$ = $1; } ; -parameter_value_assignment: // IEEE: parameter_value_assignment +parameter_value_assignmentClassE: // IEEE: [ parameter_value_assignment ] for classes + /* empty */ { $$ = nullptr; } + | parameter_value_assignmentClass { $$ = $1; } + ; + +parameter_value_assignmentInst: // IEEE: parameter_value_assignment for instance '#' '(' cellparamListE ')' { $$ = $3; } // // Parentheses are optional around a single parameter | '#' yaINTNUM { $$ = new AstPin{$2, 1, "", new AstConst{$2, *$2}}; } @@ -1979,12 +1994,12 @@ net_type: // ==IEEE: net_type | yTRI { VARDECL(TRIWIRE); } | yTRI0 { VARDECL(TRI0); } | yTRI1 { VARDECL(TRI1); } - | yTRIAND { VARDECL(WIRE); BBUNSUP($1, "Unsupported: triand"); } - | yTRIOR { VARDECL(WIRE); BBUNSUP($1, "Unsupported: trior"); } + | yTRIAND { VARDECL(TRIAND); } + | yTRIOR { VARDECL(TRIOR); } | yTRIREG { VARDECL(WIRE); BBUNSUP($1, "Unsupported: trireg"); } - | yWAND { VARDECL(WIRE); BBUNSUP($1, "Unsupported: wand"); } + | yWAND { VARDECL(TRIAND); } | yWIRE { VARDECL(WIRE); } - | yWOR { VARDECL(WIRE); BBUNSUP($1, "Unsupported: wor"); } + | yWOR { VARDECL(TRIOR); } // // VAMS - somewhat hackish | yWREAL { VARDECL(WREAL); } ; @@ -2127,6 +2142,26 @@ data_type: // ==IEEE: data_type $$ = GRAMMARP->createArray(refp, $4, true); } ; +data_typeAny: // ==IEEE: data_type (accepting idAny) + // // IEEE: data_type_or_incomplete_class_scoped_type parses same as this + // // as can't tell them apart until link + // // This expansion also replicated elsewhere, IE data_type__AndID + data_typeNoRef { $$ = $1; } + // + // // REFERENCES + // + // // IEEE: [ class_scope | package_scope ] type_identifier { packed_dimension } + // // IEEE: class_type + // // IEEE: ps_covergroup_identifier + // // Don't distinguish between types and classes so all these combined + | packageClassScopeE idAny packed_dimensionListE + { AstRefDType* const refp = new AstRefDType{$2, *$2, $1, nullptr}; + $$ = GRAMMARP->createArray(refp, $3, true); } + | packageClassScopeE idAny parameter_value_assignmentClass packed_dimensionListE + { AstRefDType* const refp = new AstRefDType{$2, *$2, $1, $3}; + $$ = GRAMMARP->createArray(refp, $4, true); } + ; + data_typeBasic: // IEEE: part of data_type integer_vector_type signingE rangeListE { $1->setSignedState($2); $$ = GRAMMARP->addRange($1, $3, true); } | integer_atom_type signingE { $1->setSignedState($2); $$ = $1; } @@ -2182,7 +2217,7 @@ data_typeVirtual: // ==IEEE: data_type after yVIRTUAL [ yI ; data_type_or_void: // ==IEEE: data_type_or_void - data_type { $$ = $1; } + data_typeAny { $$ = $1; } | yVOID { $$ = new AstBasicDType{$1, LOGIC_IMPLICIT}; BBUNSUP($1, "Unsupported: void (for tagged unions)"); } @@ -2213,18 +2248,28 @@ struct_unionDecl: // IEEE: part of data_type // // packedSigningE is NOP for unpacked ySTRUCT packedSigningE '{' /*mid*/ { $$ = new AstStructDType{$1, $2}; SYMP->pushNew($$); } - /*cont*/ struct_union_memberList '}' + /*cont*/ struct_union_memberListEnd { $$ = $4; $$->addMembersp($5); SYMP->popScope($$); } | yUNION taggedSoftE packedSigningE '{' /*mid*/ { $$ = new AstUnionDType{$1, $3}; SYMP->pushNew($$); } - /*cont*/ struct_union_memberList '}' + /*cont*/ struct_union_memberListEnd { $$ = $5; $$->addMembersp($6); SYMP->popScope($$); } ; +struct_union_memberListEnd: // IEEE: { struct_union_member } '}' + struct_union_memberList '}' { $$ = $1; } + // + | struct_union_memberList error '}' { $$ = $1; } + | error '}' { $$ = nullptr; } + ; + struct_union_memberList: // IEEE: { struct_union_member } struct_union_member { $$ = $1; } | struct_union_memberList struct_union_member { $$ = addNextNull($1, $2); } + // + | struct_union_memberList error ';' { $$ = $1; } + | error ';' { $$ = nullptr; } ; struct_union_member: // ==IEEE: struct_union_member @@ -2267,9 +2312,6 @@ member_decl_assignment: // Derived from IEEE: variable_decl_assi // // IEEE: "class_variable_identifier [ '=' class_new ]" // // variable_dimensionE must be empty // // Pushed into variable_declExpr:dynamic_array_new - // - // // IEEE: "[ covergroup_variable_identifier ] '=' class_new - // // Pushed into variable_declExpr:class_new ; list_of_variable_decl_assignments: // ==IEEE: list_of_variable_decl_assignments @@ -2289,11 +2331,6 @@ variable_decl_assignment: // ==IEEE: variable_decl_assignment // // IEEE: "class_variable_identifier [ '=' class_new ]" // // variable_dimensionE must be empty // // Pushed into variable_declExpr:dynamic_array_new - // - // // IEEE: "[ covergroup_variable_identifier ] '=' class_new - // // Pushed into variable_declExpr:class_new - | '=' class_new - { $$ = nullptr; BBUNSUP($1, "Unsupported: declaration assignment with new()"); } ; list_of_tf_variable_identifiers: // ==IEEE: list_of_tf_variable_identifiers @@ -2442,11 +2479,13 @@ data_declaration: // ==IEEE: data_declaration ; class_property: // ==IEEE: class_property, which is {property_qualifier} data_declaration - memberQualListE data_declarationVarClass { $$ = $2; $1.applyToNodes($2); } + memberQualListE data_declarationVarClass + { $$ = $2; $1.applyToNodes($2); } + | memberQualListE type_declaration + { $$ = $2; if (VN_IS($2, Typedef)) $1.applyToNodes(VN_AS($2, Typedef)); } // // UNSUP: Import needs to apply local/protected from memberQualList, and error on others - | memberQualListE type_declaration { $$ = $2; } - // // UNSUP: Import needs to apply local/protected from memberQualList, and error on others - | memberQualListE package_import_declaration { $$ = $2; } + | memberQualListE package_import_declaration + { $$ = $2; } // // IEEE: virtual_interface_declaration // // "yVIRTUAL yID yID" looks just like a data_declaration // // Therefore the virtual_interface_declaration term isn't used @@ -2530,16 +2569,28 @@ data_declarationVarFrontClass: // IEEE: part of data_declaration (for class_pro ; nettype_declaration: // IEEE: nettype_declaration/net_type_declaration - yNETTYPE data_type idAny/*nettype_identifier*/ ';' + // // Union of data_typeAny and nettype_identifier matching + yNETTYPE data_typeNoRef + /*cont*/ idAny/*nettype_identifier*/ ';' { $$ = nullptr; BBUNSUP($1, "Unsupported: nettype"); } - // // package_scope part of data_type - | yNETTYPE data_type idAny yWITH__ETC packageClassScopeE id/*tf_identifier*/ ';' - { $$ = nullptr; BBUNSUP($1, "Unsupported: nettype"); } - | yNETTYPE packageClassScopeE id/*nettype_identifier*/ idAny/*nettype_identifier*/ ';' - { $$ = nullptr; BBUNSUP($1, "Unsupported: nettype"); } - | yNETTYPE packageClassScopeE id/*nettype_identifier*/ idAny/*nettype_identifier*/ + | yNETTYPE data_typeNoRef + /*cont*/ idAny/*nettype_identifier*/ /*cont*/ yWITH__ETC packageClassScopeE id/*tf_identifier*/ ';' + { $$ = nullptr; BBUNSUP($1, "Unsupported: nettype with"); } + | yNETTYPE packageClassScopeE idAny packed_dimensionListE + /*cont*/ idAny/*nettype_identifier*/ ';' { $$ = nullptr; BBUNSUP($1, "Unsupported: nettype"); } + | yNETTYPE packageClassScopeE idAny packed_dimensionListE + /*cont*/ idAny/*nettype_identifier*/ + /*cont*/ yWITH__ETC packageClassScopeE id/*tf_identifier*/ ';' + { $$ = nullptr; BBUNSUP($1, "Unsupported: nettype with"); } + | yNETTYPE packageClassScopeE idAny parameter_value_assignmentClass packed_dimensionListE + /*cont*/ idAny/*nettype_identifier*/ ';' + { $$ = nullptr; BBUNSUP($1, "Unsupported: nettype"); } + | yNETTYPE packageClassScopeE idAny parameter_value_assignmentClass packed_dimensionListE + /*cont*/ idAny/*nettype_identifier*/ + /*cont*/ yWITH__ETC packageClassScopeE id/*tf_identifier*/ ';' + { $$ = nullptr; BBUNSUP($1, "Unsupported: nettype with"); } ; implicit_typeE: // IEEE: part of *data_type_or_implicit @@ -2595,6 +2646,8 @@ type_declaration: // ==IEEE: type_declaration | yTYPEDEF yUNION idAny ';' { $$ = GRAMMARP->createTypedefFwd($3, *$3); } | yTYPEDEF yCLASS idAny ';' { $$ = GRAMMARP->createTypedefFwd($3, *$3); } | yTYPEDEF yINTERFACE yCLASS idAny ';' { $$ = GRAMMARP->createTypedefFwd($4, *$4); } + // + | yTYPEDEF error idAny ';' { $$ = GRAMMARP->createTypedefFwd($3, *$3); } ; dtypeAttrListE: @@ -2864,7 +2917,7 @@ c_generate_item: // IEEE: generate_item (for checkers) ; conditional_generate_construct: // ==IEEE: conditional_generate_construct - yCASE '(' exprTypeCompare ')' ~c~case_generate_itemListE yENDCASE + yCASE '(' exprTypeCompare ')' ~c~case_generate_itemList yENDCASE { $$ = new AstGenCase{$1, $3, $5}; } | yIF '(' exprTypeCompare ')' ~c~generate_block_or_null %prec prLOWER_THAN_ELSE { $$ = new AstGenIf{$1, $3, $5, nullptr}; } @@ -2955,15 +3008,6 @@ genvar_iteration: // ==IEEE: genvar_iteration new AstConst{$2, AstConst::StringToParse{}, "'b1"}}}; } ; -case_generate_itemListE: // IEEE: [{ case_generate_itemList }] - /* empty */ { $$ = nullptr; } - | ~c~case_generate_itemList { $$ = $1; } - ; - -c_case_generate_itemListE: // IEEE: { case_generate_item } (for checkers) - BISONPRE_COPY(case_generate_itemListE,{s/~c~/c_/g}) // {copied} - ; - case_generate_itemList: // IEEE: { case_generate_itemList } ~c~case_generate_item { $$ = $1; } | ~c~case_generate_itemList ~c~case_generate_item { $$ = $1; $1->addNext($2); } @@ -3045,8 +3089,10 @@ netSig: // IEEE: net_decl_assignment - one element from netId sigAttrListE { $$ = VARDONEA($1, *$1, nullptr, $2); } | netId sigAttrListE '=' expr - { $$ = VARDONEA($1, *$1, nullptr, $2); - auto* const assignp = new AstAssignW{$3, new AstParseRef{$1, VParseRefExp::PX_TEXT, *$1}, $4}; + { AstDelay* const delayp = GRAMMARP->getNetDelay(); + AstAssignW* const assignp = new AstAssignW{$3, new AstParseRef{$1, VParseRefExp::PX_TEXT, *$1}, $4, delayp}; + $$ = VARDONEA($1, *$1, nullptr, $2); + if (delayp) GRAMMARP->setNetDelay(delayp->cloneTree(false)); if (GRAMMARP->m_netStrengthp) assignp->strengthSpecp(GRAMMARP->m_netStrengthp->cloneTree(false)); AstNode::addNext($$, assignp); } | netId variable_dimensionList sigAttrListE @@ -3108,13 +3154,26 @@ rangeList: // IEEE: {packed_dimension} | rangeList anyrange { $$ = $1->addNext($2); } ; -// IEEE: select -// Merged into more general idArray - anyrange: '[' constExpr ':' constExpr ']' { $$ = new AstRange{$1, $2, $4}; } ; +part_select_rangeList: // IEEE: part_select_range (as used after function calls) + part_select_range { $$ = $1; } + | part_select_rangeList part_select_range { $$ = GRAMMARP->scrubSel($1, $2); } + ; + +part_select_range: + '[' expr ']' + { $$ = new AstSelBit{$1, new AstParseHolder{$1}, $2}; } + | '[' constExpr ':' constExpr ']' + { $$ = new AstSelExtract{$1, new AstParseHolder{$1}, $2, $4}; } + | '[' expr yP_PLUSCOLON constExpr ']' + { $$ = new AstSelPlus{$1, new AstParseHolder{$1}, $2, $4}; } + | '[' expr yP_MINUSCOLON constExpr ']' + { $$ = new AstSelMinus{$1, new AstParseHolder{$1}, $2, $4}; } + ; + packed_dimensionListE: // IEEE: [{ packed_dimension }] /* empty */ { $$ = nullptr; } | packed_dimensionList { $$ = $1; } @@ -3151,18 +3210,20 @@ type_assignment: // ==IEEE: type_assignment // // note exptOrDataType being a data_type is only for yPARAMETER yTYPE idAny/*new-parameter*/ sigAttrListE { $$ = VARDONEA($1, *$1, nullptr, $2); } - | idAny/*new-parameter*/ sigAttrListE '=' data_type + | idAny/*new-parameter*/ sigAttrListE '=' data_typeAny { $$ = VARDONEA($1, *$1, nullptr, $2); $$->valuep($4); } ; list_of_type_assignments: // ==IEEE: list_of_type_assignments type_assignment { $$ = $1; } - | list_of_type_assignments ',' type_assignment { $$ = $1->addNext($3); } + | list_of_type_assignments ',' type_assignment + { $$ = addNextNull($1, $3); } ; list_of_defparam_assignments: //== IEEE: list_of_defparam_assignments defparam_assignment { $$ = $1; } - | list_of_defparam_assignments ',' defparam_assignment { $$ = $1->addNext($3); } + | list_of_defparam_assignments ',' defparam_assignment + { $$ = addNextNull($1, $3); } ; defparam_assignment: // ==IEEE: defparam_assignment @@ -3191,7 +3252,9 @@ instDecl: // // Currently disambiguated from data_declaration based on // // VARs being type, and cells non-type. // // IEEE requires a '(' to disambiguate, we need TODO force this - id parameter_value_assignmentE {INSTPREP($1, *$1, $2);} instnameList ';' + id parameter_value_assignmentInstE + /*mid*/ { INSTPREP($1, *$1, $2); } + /*cont*/ instnameList ';' { $$ = $4; GRAMMARP->m_impliedDecl = false; if (GRAMMARP->m_instParamp) { @@ -3206,6 +3269,12 @@ instDecl: /*cont*/ mpInstnameList ';' { $$ = VARDONEP($5, nullptr, nullptr); } //UNSUP: strengthSpecE for udp_instantiations + // // IEEE: part of udp_instance when no name_of_instance + // // Note no unpacked dimension nor list of instances + | id + /*mid*/ { INSTPREP($1, *$1, nullptr); } + /*cont*/ instnameParenUdpn ';' + { $$ = $3; GRAMMARP->m_impliedDecl = false; } ; mpInstnameList: // Similar to instnameList, but for modport instantiations which have no parenthesis @@ -3227,7 +3296,10 @@ instnameParen: { $$ = GRAMMARP->createCellOrIfaceRef($1, *$1, $4, $2, true); } | id instRangeListE { $$ = GRAMMARP->createCellOrIfaceRef($1, *$1, nullptr, $2, false); } - | '(' cellpinListE ')' // When UDP has empty name, unpacked dimensions must not be used + ; + +instnameParenUdpn: // IEEE: part of udp_instance when no name_of_instance + '(' cellpinListE ')' // When UDP has empty name, unpacked dimensions must not be used { $$ = GRAMMARP->createCellOrIfaceRef($1, "", $2, nullptr, true); } ; @@ -3501,6 +3573,9 @@ blockDeclStmtListE: // IEEE: [ { block_item_declaration } { statemen block_item_declarationList: // IEEE: [ block_item_declaration ] block_item_declaration { $$ = $1; } | block_item_declarationList block_item_declaration { $$ = addNextNull($1, $2); } + // + | block_item_declarationList error ';' { $$ = $1; } + | error ';' { $$ = nullptr; } ; block_item_declaration: // ==IEEE: block_item_declaration @@ -3512,6 +3587,8 @@ block_item_declaration: // ==IEEE: block_item_declaration stmtList: stmtBlock { $$ = $1; } | stmtList stmtBlock { $$ = addNextNull($1, $2); } + // + | stmtList error ';' { $$ = $1; } ; stmt: // IEEE: statement_or_null == function_statement_or_null @@ -3554,15 +3631,15 @@ statement_item: // IEEE: statement_item { $$ = new AstRelease{$1, $2}; v3Global.setHasForceableSignals(); } // // // IEEE: case_statement - | unique_priorityE caseStart caseAttrE case_itemListE yENDCASE + | unique_priorityE caseStart caseAttrE case_itemList yENDCASE { $$ = $2; if ($4) $2->addItemsp($4); if ($1 == uniq_UNIQUE) $2->uniquePragma(true); if ($1 == uniq_UNIQUE0) $2->unique0Pragma(true); if ($1 == uniq_PRIORITY) $2->priorityPragma(true); } - // &&& is part of expr so case_patternListE aliases to case_itemListE - | unique_priorityE caseStart caseAttrE yMATCHES case_patternListE yENDCASE + // &&& is part of expr so case_patternList aliases to case_itemList + | unique_priorityE caseStart caseAttrE yMATCHES case_itemList yENDCASE { $$ = nullptr; BBUNSUP($4, "Unsupported: matches (for tagged union)"); } - | unique_priorityE caseStart caseAttrE yINSIDE case_insideListE yENDCASE + | unique_priorityE caseStart caseAttrE yINSIDE case_inside_itemList yENDCASE { $$ = $2; if ($5) $2->addItemsp($5); if (!$2->caseSimple()) $4->v3error("Illegal to have inside on a casex/casez"); $2->caseInsideSet(); @@ -3694,8 +3771,6 @@ statement_item: // IEEE: statement_item { $$ = nullptr; BBUNSUP($1, "Unsupported: expect"); } | yEXPECT '(' property_spec ')' yELSE stmt { $$ = nullptr; BBUNSUP($1, "Unsupported: expect"); } - // - | error ';' { $$ = nullptr; } ; statementFor: // IEEE: part of statement @@ -3820,20 +3895,6 @@ caseAttrE: | caseAttrE yVL_PARALLEL_CASE { GRAMMARP->m_caseAttrp->parallelPragma(true); } ; -case_patternListE: // IEEE: case_pattern_item - case_itemListE { $$ = $1; } - ; - -case_itemListE: // IEEE: [ { case_item } ] - /* empty */ { $$ = nullptr; } - | case_itemList { $$ = $1; } - ; - -case_insideListE: // IEEE: [ { case_inside_item } ] - /* empty */ { $$ = nullptr; } - | case_inside_itemList { $$ = $1; } - ; - case_itemList: // IEEE: { case_item + ... } caseCondList colon stmtBlock { $$ = new AstCaseItem{$2, $1, $3}; } | yDEFAULT colon stmtBlock { $$ = new AstCaseItem{$1, nullptr, $3}; } @@ -4091,7 +4152,7 @@ task_subroutine_callNoMethod: // function_subroutine_callNoMethod // // IEEE: randomize_call // // We implement randomize as a normal funcRef, since randomize isn't a keyword // // Note yNULL is already part of expressions, so they come for free - //UNSUP funcRef yWITH__CUR constraint_block { } + | funcRef yWITH__CUR constraint_block { $$ = new AstWithParse{$2, $1, $3}; } ; function_subroutine_callNoMethod: // IEEE: function_subroutine_call (as function) @@ -4211,16 +4272,16 @@ system_t_call: // IEEE: system_tf_call (as task) | yD_ERROR parenE { $$ = GRAMMARP->createDisplayError($1); } | yD_ERROR '(' commasE exprDispList ')' { $$ = new AstDisplay{$1, VDisplayType::DT_ERROR, nullptr, $4}; - $$->addNext(new AstStop{$1, true}); } + $$->addNext(new AstStop{$1, false}); } | yD_FATAL parenE { $$ = new AstDisplay{$1, VDisplayType::DT_FATAL, nullptr, nullptr}; - $$->addNext(new AstStop{$1, false}); } + $$->addNext(new AstStop{$1, true}); } | yD_FATAL '(' expr ')' { $$ = new AstDisplay{$1, VDisplayType::DT_FATAL, nullptr, nullptr}; - $$->addNext(new AstStop{$1, false}); DEL($3); } + $$->addNext(new AstStop{$1, true}); DEL($3); } | yD_FATAL '(' expr ',' exprDispList ')' { $$ = new AstDisplay{$1, VDisplayType::DT_FATAL, nullptr, $5}; - $$->addNext(new AstStop{$1, false}); DEL($3); } + $$->addNext(new AstStop{$1, true}); DEL($3); } // | yD_ASSERTCTL '(' expr ')' { $$ = new AstAssertCtl{$1, $3}; } | yD_ASSERTCTL '(' expr ',' exprE ')' { $$ = new AstAssertCtl{$1, $3, $5}; } @@ -4444,7 +4505,14 @@ property_actual_arg: // ==IEEE: property_actual_arg exprOrDataType: // expr | data_type: combined to prevent conflicts expr { $$ = $1; } // // data_type includes id that overlaps expr, so special flavor - | data_type { $$ = $1; } + // // data_type expanded: + | data_typeNoRef { $$ = $1; } + | packageClassScopeE idType packed_dimensionListE + { AstRefDType* const refp = new AstRefDType{$2, *$2, $1, nullptr}; + $$ = GRAMMARP->createArray(refp, $3, true); } + | packageClassScopeE idType parameter_value_assignmentClass packed_dimensionListE + { AstRefDType* const refp = new AstRefDType{$2, *$2, $1, $3}; + $$ = GRAMMARP->createArray(refp, $4, true); } // // not in spec, but needed for $past(sig,1,,@(posedge clk)) //UNSUP event_control { } ; @@ -4552,10 +4620,11 @@ taskId: | packageClassScope id { $$ = new AstTask{$$, *$2, nullptr}; $$->classOrPackagep($1); + $$->classMethod(true); SYMP->pushNewUnderNodeOrCurrent($$, $1); } ; -funcId: // IEEE: function_data_type_or_implicit + part of function_body_declaration +funcId: // IEEE: function_data_type_or_implicit + part of function_body_declaration // // IEEE: function_data_type_or_implicit must be expanded here to prevent conflict // // function_data_type expanded here to prevent conflicts with // // implicit_type:empty vs data_type:ID @@ -4571,10 +4640,20 @@ funcId: // IEEE: function_data_type_or_implicit { $$ = $2; $$->fvarp(new AstBasicDType{$2, LOGIC_IMPLICIT, $1}); SYMP->pushNewUnderNodeOrCurrent($$, $2); } - | data_type fIdScoped + | data_typeNoRef fIdScoped { $$ = $2; $$->fvarp($1); SYMP->pushNewUnderNodeOrCurrent($$, $2); } + | packageClassScopeE idType packed_dimensionListE fIdScoped + { AstRefDType* const refp = new AstRefDType{$2, *$2, $1, nullptr}; + $$ = $4; + $$->fvarp(GRAMMARP->createArray(refp, $3, true)); + SYMP->pushNewUnderNodeOrCurrent($$, $4); } + | packageClassScopeE idType parameter_value_assignmentClass packed_dimensionListE fIdScoped + { AstRefDType* const refp = new AstRefDType{$2, *$2, $1, $3}; + $$ = $5; + $$->fvarp(GRAMMARP->createArray(refp, $4, true)); + SYMP->pushNewUnderNodeOrCurrent($$, $5); } // // To verilator tasks are the same as void functions (we separately detect time passing) | yVOID taskId { $$ = $2; } @@ -4593,6 +4672,7 @@ funcIdNew: // IEEE: from class_constructor_declaration { $$ = new AstFunc{$2, "new", nullptr, nullptr}; $$->classOrPackagep($1); $$->isConstructor(true); + $$->classMethod(true); SYMP->pushNewUnderNodeOrCurrent($$, $1); } ; @@ -4613,6 +4693,7 @@ fIdScoped: // IEEE: part of function_body_declaration/task_ { $$ = $1; $$ = $1; $$ = new AstFunc{$$, *$2, nullptr, nullptr}; + $$->classMethod(true); $$->classOrPackagep($1); } ; @@ -4960,38 +5041,22 @@ expr: // IEEE: part of expression/constant_expression/ { $$ = new AstSelMinus{$7, new AstReplicate{$3, $4, $2}, $8, $10}; } // // UNSUP some other rules above // + // // IEEE grammar error: function_subroutine_call [ range_expression ] + // // should be instead: function_subroutine_call [ part_select_range ] | function_subroutine_callNoMethod { $$ = $1; } - | function_subroutine_callNoMethod '[' expr ']' - { $$ = new AstSelBit{$2, $1, $3}; } - | function_subroutine_callNoMethod '[' constExpr ':' constExpr ']' - { $$ = new AstSelExtract{$2, $1, $3, $5}; } - | function_subroutine_callNoMethod '[' expr yP_PLUSCOLON constExpr ']' - { $$ = new AstSelPlus{$2, $1, $3, $5}; } - | function_subroutine_callNoMethod '[' expr yP_MINUSCOLON constExpr ']' - { $$ = new AstSelMinus{$2, $1, $3, $5}; } + | function_subroutine_callNoMethod part_select_rangeList + { $$ = GRAMMARP->scrubSel($1, $2); } // // method_call | ~l~expr '.' function_subroutine_callNoMethod { $$ = new AstDot{$2, false, $1, $3}; } - | ~l~expr '.' function_subroutine_callNoMethod '[' expr ']' - { $$ = new AstSelBit{$4, new AstDot{$2, false, $1, $3}, $5}; } - | ~l~expr '.' function_subroutine_callNoMethod '[' constExpr ':' constExpr ']' - { $$ = new AstSelExtract{$4, new AstDot{$2, false, $1, $3}, $5, $7}; } - | ~l~expr '.' function_subroutine_callNoMethod '[' expr yP_PLUSCOLON constExpr ']' - { $$ = new AstSelPlus{$4, new AstDot{$2, false, $1, $3}, $5, $7}; } - | ~l~expr '.' function_subroutine_callNoMethod '[' expr yP_MINUSCOLON constExpr ']' - { $$ = new AstSelMinus{$4, new AstDot{$2, false, $1, $3}, $5, $7}; } + | ~l~expr '.' function_subroutine_callNoMethod part_select_rangeList + { $$ = GRAMMARP->scrubSel(new AstDot{$2, false, $1, $3}, $4); } // // method_call:array_method requires a '.' | ~l~expr '.' array_methodWith { $$ = new AstDot{$2, false, $1, $3}; } - | ~l~expr '.' array_methodWith '[' expr ']' - { $$ = new AstSelBit{$4, new AstDot{$2, false, $1, $3}, $5}; } - | ~l~expr '.' array_methodWith '[' constExpr ':' constExpr ']' - { $$ = new AstSelExtract{$4, new AstDot{$2, false, $1, $3}, $5, $7}; } - | ~l~expr '.' array_methodWith '[' expr yP_PLUSCOLON constExpr ']' - { $$ = new AstSelPlus{$4, new AstDot{$2, false, $1, $3}, $5, $7}; } - | ~l~expr '.' array_methodWith '[' expr yP_MINUSCOLON constExpr ']' - { $$ = new AstSelMinus{$4, new AstDot{$2, false, $1, $3}, $5, $7}; } + | ~l~expr '.' array_methodWith part_select_rangeList + { $$ = GRAMMARP->scrubSel(new AstDot{$2, false, $1, $3}, $4); } // // // IEEE: let_expression // // see funcRef @@ -5606,7 +5671,7 @@ gateXorPinList: ; gateUnsupPinList: gatePinExpr { $$ = $1; } - | gateUnsupPinList ',' gatePinExpr { $$ = $1->addNext($3); } + | gateUnsupPinList ',' gatePinExpr { $$ = addNextNull($1, $3); } ; gatePinExpr: @@ -6514,9 +6579,6 @@ boolean_abbrev: // ==IEEE: boolean_abbrev { $$ = $2; BBUNSUP($1, "Unsupported: [-> boolean abbrev expression"); } ; -//************************************************ -// Let - //************************************************ // Covergroup @@ -6542,12 +6604,11 @@ covergroup_declaration: // ==IEEE: covergroup_declaration GRAMMARP->endLabel($7, $1, $7); } ; -covergroup_declarationFront: // IEEE: part of covergroup_declaration +covergroup_declarationFront: // IEEE: part of covergroup_declaration yCOVERGROUP idAny - { $$ = new AstClass{$2, *$2}; + { $$ = new AstConstraint{$2, *$2, nullptr}; BBUNSUP($1, "Unsupported: covergroup"); - SYMP->pushNew($$); - v3Global.setHasClasses(); } + SYMP->pushNew($$); } ; cgexpr: // IEEE-2012: covergroup_expression, before that just expression @@ -6611,11 +6672,17 @@ bins_or_empty: // ==IEEE: bins_or_empty '{' bins_or_optionsList '}' { $$ = $2; } | '{' '}' { $$ = nullptr; } | ';' { $$ = nullptr; } + // + | '{' bins_or_optionsList error '}' { $$ = $2; } + | '{' error '}' { $$ = nullptr; } ; bins_or_optionsList: // IEEE: { bins_or_options ';' } bins_or_options ';' { $$ = $1; } | bins_or_optionsList bins_or_options ';' { $$ = addNextNull($1, $2); } + // + | bins_or_optionsList error ';' { $$ = $1; } + | error ';' { $$ = nullptr; } ; bins_or_options: // ==IEEE: bins_or_options @@ -6720,11 +6787,17 @@ cross_body: // ==IEEE: cross_body // // IEEE-2012: No semicolon here, mistake in spec | '{' cross_body_itemSemiList '}' { $$ = $2; } | ';' { $$ = nullptr; } + // + | '{' cross_body_itemSemiList error '}' { $$ = $2; } + | '{' error '}' { $$ = nullptr; } ; cross_body_itemSemiList: // IEEE: part of cross_body cross_body_item ';' { $$ = $1; } | cross_body_itemSemiList cross_body_item ';' { $$ = addNextNull($1, $2); } + // + | error ';' { $$ = nullptr; } + | cross_body_itemSemiList error ';' { $$ = $1; } ; cross_body_item: // ==IEEE: cross_body_item @@ -7020,14 +7093,14 @@ class_declaration: // ==IEEE: part of class_declaration /*mid*/ { // Allow resolving types declared in base extends class if ($3) SYMP->importExtends($3); } - /*cont*/ class_itemListE yENDCLASS endLabelE + /*cont*/ class_itemListEnd endLabelE { $$ = $1; $1->addMembersp($2); if ($2) $1->isParameterized(true); $1->addExtendsp($3); $1->addExtendsp($4); $1->addMembersp($7); SYMP->popScope($$); - GRAMMARP->endLabel($9, $1, $9); } + GRAMMARP->endLabel($8, $1, $8); } ; classFront: // IEEE: part of class_declaration @@ -7104,12 +7177,12 @@ class_typeExtImpOne: // part of IEEE: class_type, where we either ge // // If idAny below is otherwise, not legal idAny /*mid*/ { /* no nextId as not refing it above this*/ } - /*cont*/ parameter_value_assignmentE + /*cont*/ parameter_value_assignmentClassE { $$ = new AstClassOrPackageRef{$1, *$1, $1, $3}; $$ = $1; } | idCC /*mid*/ { /* no nextId as not refing it above this*/ } - /*cont*/ parameter_value_assignmentE + /*cont*/ parameter_value_assignmentClassE { $$ = new AstClassOrPackageRef{$1, *$1, $1, $3}; $$ = $1; } // @@ -7180,7 +7253,7 @@ packageClassScopeItem: // IEEE: package_scope or [package_scope]::[ /*cont*/ yP_COLONCOLON { $$ = new AstClassOrPackageRef{$1, *$1, $1, nullptr}; $$ = $1; } // - | idCC parameter_value_assignment + | idCC parameter_value_assignmentClass /*mid*/ { SYMP->nextId($1); } // Change next *after* we handle parameters, not before /*cont*/ yP_COLONCOLON { $$ = new AstClassOrPackageRef{$1, *$1, $1, $2}; $$ = $1; } @@ -7206,9 +7279,11 @@ localNextId: // local //^^^========= -class_itemListE: - /* empty */ { $$ = nullptr; } - | class_itemList { $$ = $1; } +class_itemListEnd: + yENDCLASS { $$ = nullptr; } + | class_itemList yENDCLASS { $$ = $1; } + | error yENDCLASS { $$ = nullptr; } + | class_itemList error yENDCLASS { $$ = $1; } ; class_itemList: @@ -7298,8 +7373,6 @@ memberQualOne: // IEEE: property_qualifier + me class_constraint: // ==IEEE: class_constraint // // IEEE: constraint_declaration - // // UNSUP: We have the unsupported warning on the randomize() call, so don't bother on - // // constraint blocks. When we support randomize we need to make AST nodes for below rules constraintStaticE yCONSTRAINT dynamic_override_specifiersE constraintIdNew constraint_block { $$ = $4; $$->isStatic($1); $$->addItemsp($5); SYMP->popScope($$); } | constraintStaticE yCONSTRAINT dynamic_override_specifiersE constraintIdNew '{' '}' @@ -7323,6 +7396,9 @@ constraintIdNew: // IEEE: id part of class_constraint constraint_block: // ==IEEE: constraint_block '{' constraint_block_itemList '}' { $$ = $2; } + // + | '{' error '}' { $$ = nullptr; } + | '{' constraint_block_itemList error '}' { $$ = $2; } ; constraint_block_itemList: // IEEE: { constraint_block_item } @@ -7379,11 +7455,17 @@ constraint_expression: // ==IEEE: constraint_expression { AstConstraintExpr* const newp = new AstConstraintExpr{$1, $3}; newp->isDisableSoft(true); $$ = newp; } + // + | error ';' + { $$ = nullptr; } ; constraint_set: // ==IEEE: constraint_set constraint_expression { $$ = $1; } | '{' constraint_expressionList '}' { $$ = $2; } + // + | '{' error '}' { $$ = nullptr; } + | '{' constraint_expressionList error '}' { $$ = $2; } ; dist_list: // ==IEEE: dist_list diff --git a/src/vlcovgen b/src/vlcovgen index 960b9c691..819556b6f 100755 --- a/src/vlcovgen +++ b/src/vlcovgen @@ -19,11 +19,9 @@ def read_keys(filename): if re.match(r'^\s*$', line): continue if re.search(r'^\s*VLCOVGEN_ITEM', line): - match = re.search(r'^\s*VLCOVGEN_ITEM *\( *"([^"]+)" *\)', - line) + match = re.search(r'^\s*VLCOVGEN_ITEM *\( *"([^"]+)" *\)', line) if not match: - sys.exit("%Error: " + filename + - ": vlcovgen misformed VLCOVGEN_ITEM line") + sys.exit("%Error: " + filename + ": vlcovgen misformed VLCOVGEN_ITEM line") code = "{" + match.group(1) + "}" data = eval(code) # pprint(data) @@ -59,9 +57,8 @@ def write_keys(filename): deleting = True out.append(line) for keyref in sorted(Items, key=lambda a: a['name']): - out.append( - " if (key == \"%s\") return VL_CIK_%s;\n" % - (keyref['name'], keyref['name'].upper())) + out.append(" if (key == \"%s\") return VL_CIK_%s;\n" % + (keyref['name'], keyref['name'].upper())) elif re.search(r'VLCOVGEN_.*AUTO_EDIT_END', line): deleting = False out.append(line) @@ -80,19 +77,15 @@ def write_keys(filename): parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, - description= - """Generate verilated_cov headers to reduce C++ code duplication.""", - epilog= - """Copyright 2002-2024 by Wilson Snyder. This program is free software; you + description="""Generate verilated_cov headers to reduce C++ code duplication.""", + epilog="""Copyright 2002-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") -parser.add_argument('--srcdir', - action='store', - help='directory containing Verilator sources') +parser.add_argument('--srcdir', action='store', help='directory containing Verilator sources') parser.set_defaults(srcdir=".") diff --git a/test_regress/CMakeLists.txt b/test_regress/CMakeLists.txt index ad09a1282..bc75319c7 100644 --- a/test_regress/CMakeLists.txt +++ b/test_regress/CMakeLists.txt @@ -14,19 +14,31 @@ cmake_minimum_required(VERSION 3.12) cmake_policy(SET CMP0074 NEW) -set(TEST_REQUIRED_VARS NAME CSOURCES OPT_FAST OPT_GLOBAL - VERILATOR_ROOT VERILATOR_ARGS - VERILATOR_SOURCES SYSTEMC VERBOSE VERILATION) +set(TEST_REQUIRED_VARS + NAME + CSOURCES + OPT_FAST + OPT_GLOBAL + VERILATOR_ROOT + VERILATOR_ARGS + VERILATOR_SOURCES + SYSTEMC + VERBOSE + VERILATION +) foreach(var ${TEST_REQUIRED_VARS}) - if (NOT DEFINED TEST_${var}) - message(FATAL_ERROR "TEST_${var} not defined. This CMakeLists.txt file is meant to be run by driver.pl.") - endif() + if(NOT DEFINED TEST_${var}) + message( + FATAL_ERROR + "TEST_${var} not defined. This CMakeLists.txt file is meant to be run by driver.py." + ) + endif() endforeach() project("${TEST_NAME}") if(TEST_VERBOSE) - add_definitions(-DTEST_VERBOSE=1) + add_definitions(-DTEST_VERBOSE=1) endif() separate_arguments(TEST_VERILATOR_ARGS UNIX_COMMAND "${TEST_VERILATOR_ARGS}") @@ -38,33 +50,49 @@ set(TEST_PREFIX ${TEST_NAME}) # If --ARG is present, set OUT = function(getarg LST ARG OUT) - list(FIND ${LST} ${ARG} _INDEX) - if(NOT _INDEX EQUAL -1) - list(REMOVE_AT ${LST} ${_INDEX}) - list(GET ${LST} ${_INDEX} VAL) - set(${OUT} ${VAL} PARENT_SCOPE) - endif() + list(FIND ${LST} ${ARG} _INDEX) + if(NOT _INDEX EQUAL -1) + list(REMOVE_AT ${LST} ${_INDEX}) + list(GET ${LST} ${_INDEX} VAL) + set(${OUT} ${VAL} PARENT_SCOPE) + endif() endfunction() # Normalise -- to - -string(REGEX REPLACE "(^|;)--" "\\1-" - TEST_VERILATOR_ARGS_NORM - "${TEST_VERILATOR_ARGS}") +string( + REGEX REPLACE + "(^|;)--" + "\\1-" + TEST_VERILATOR_ARGS_NORM + "${TEST_VERILATOR_ARGS}" +) getarg(TEST_VERILATOR_ARGS_NORM "-prefix" TEST_PREFIX) getarg(TEST_VERILATOR_ARGS_NORM "-threads" TEST_THREADS) getarg(TEST_VERILATOR_ARGS_NORM "-trace-threads" TEST_TRACE_THREADS) # Strip unwanted args with 1 parameter -string(REGEX REPLACE "(^|;)--?(Mdir|make|prefix|threads|trace-threads);[^;]*" "" - TEST_VERILATOR_ARGS - "${TEST_VERILATOR_ARGS}") +string( + REGEX REPLACE + "(^|;)--?(Mdir|make|prefix|threads|trace-threads);[^;]*" + "" + TEST_VERILATOR_ARGS + "${TEST_VERILATOR_ARGS}" +) # Strip unwanted args -string(REGEX REPLACE "(^|;)--?(sc|cc)" "" - TEST_VERILATOR_ARGS - "${TEST_VERILATOR_ARGS}") +string( + REGEX REPLACE + "(^|;)--?(sc|cc)" + "" + TEST_VERILATOR_ARGS + "${TEST_VERILATOR_ARGS}" +) -separate_arguments(TEST_VERILATOR_SOURCES UNIX_COMMAND "${TEST_VERILATOR_SOURCES}") +separate_arguments( + TEST_VERILATOR_SOURCES + UNIX_COMMAND + "${TEST_VERILATOR_SOURCES}" +) # filter out empty sources list(FILTER TEST_VERILATOR_SOURCES EXCLUDE REGEX "$^") @@ -72,22 +100,22 @@ find_package(verilator REQUIRED HINTS ${TEST_VERILATOR_ROOT}) set(verilate_ARGS MAIN) if(TEST_PREFIX) - list(APPEND verilate_ARGS PREFIX ${TEST_PREFIX}) + list(APPEND verilate_ARGS PREFIX ${TEST_PREFIX}) endif() if(TEST_OPT_FAST) - list(APPEND verilate_ARGS OPT_FAST ${TEST_OPT_FAST}) + list(APPEND verilate_ARGS OPT_FAST ${TEST_OPT_FAST}) endif() if(TEST_OPT_GLOBAL) - list(APPEND verilate_ARGS OPT_GLOBAL ${TEST_OPT_GLOBAL}) + list(APPEND verilate_ARGS OPT_GLOBAL ${TEST_OPT_GLOBAL}) endif() if(TEST_THREADS) - list(APPEND verilate_ARGS THREADS ${TEST_THREADS}) + list(APPEND verilate_ARGS THREADS ${TEST_THREADS}) endif() if(TEST_TRACE_THREADS) - list(APPEND verilate_ARGS TRACE_THREADS ${TEST_TRACE_THREADS}) + list(APPEND verilate_ARGS TRACE_THREADS ${TEST_TRACE_THREADS}) endif() if(TEST_SYSTEMC) - list(APPEND verilate_ARGS SYSTEMC) + list(APPEND verilate_ARGS SYSTEMC) endif() set(TARGET_NAME "V${TEST_NAME}") @@ -95,21 +123,24 @@ set(TARGET_NAME "V${TEST_NAME}") add_executable(${TARGET_NAME} ${TEST_CSOURCES}) if(TEST_VERILATION) - verilate(${TARGET_NAME} ${verilate_ARGS} - VERILATOR_ARGS ${TEST_VERILATOR_ARGS} - DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - SOURCES ${TEST_VERILATOR_SOURCES}) + verilate(${TARGET_NAME} ${verilate_ARGS} + VERILATOR_ARGS ${TEST_VERILATOR_ARGS} + DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + SOURCES ${TEST_VERILATOR_SOURCES} + ) endif() if(TEST_SYSTEMC) - verilator_link_systemc("${TARGET_NAME}") + verilator_link_systemc("${TARGET_NAME}") endif() string(TOUPPER "${TEST_NAME}" TEST_NAME_UC) -target_compile_definitions(${TARGET_NAME} PRIVATE - "TEST_OBJ_DIR=${CMAKE_CURRENT_BINARY_DIR}" - "VM_PREFIX=${TEST_PREFIX}" - "VM_PREFIX_INCLUDE=<${TEST_PREFIX}.h>" - "${TEST_NAME_UC}" +target_compile_definitions( + ${TARGET_NAME} + PRIVATE + "TEST_OBJ_DIR=${CMAKE_CURRENT_BINARY_DIR}" + "VM_PREFIX=${TEST_PREFIX}" + "VM_PREFIX_INCLUDE=<${TEST_PREFIX}.h>" + "${TEST_NAME_UC}" ) diff --git a/test_regress/Makefile b/test_regress/Makefile index 0497590c1..509d2624a 100644 --- a/test_regress/Makefile +++ b/test_regress/Makefile @@ -48,30 +48,30 @@ DRIVER_HASHSET ?= .PHONY: test test: - $(PERL) driver.pl $(DRIVER_FLAGS) $(SCENARIOS) $(DRIVER_HASHSET) + $(PYTHON3) driver.py $(DRIVER_FLAGS) $(SCENARIOS) $(DRIVER_HASHSET) ###################################################################### vcs: - $(PERL) driver.pl $(DRIVER_FLAGS) --vcs --stop + $(PYTHON3) driver.py $(DRIVER_FLAGS) --vcs --stop ###################################################################### nc: - $(PERL) driver.pl $(DRIVER_FLAGS) --nc --stop + $(PYTHON3) driver.py $(DRIVER_FLAGS) --nc --stop ###################################################################### vlt: - $(PERL) driver.pl $(DRIVER_FLAGS) --vlt --stop + $(PYTHON3) driver.py $(DRIVER_FLAGS) --vlt --stop vltmt: - $(PERL) driver.pl $(DRIVER_FLAGS) --vltmt --stop + $(PYTHON3) driver.py $(DRIVER_FLAGS) --vltmt --stop ###################################################################### random: - $(PERL) driver.pl $(DRIVER_FLAGS) --optimize : --stop + $(PYTHON3) driver.py $(DRIVER_FLAGS) --optimize : --stop random_forever: while ( VERILATOR_NO_DEBUG=1 CPPFLAGS_ADD=-Wno-error $(MAKE) random ) ; do \ diff --git a/test_regress/driver.pl b/test_regress/driver.pl deleted file mode 100755 index 6638e02d8..000000000 --- a/test_regress/driver.pl +++ /dev/null @@ -1,2888 +0,0 @@ -#!/usr/bin/env perl -# See copyright, etc in below POD section. -###################################################################### - -require 5.006_001; -use warnings; -use Cwd; - -BEGIN { - if (!$ENV{VERILATOR_ROOT} && -x "../bin/verilator") { - $ENV{VERILATOR_ROOT} = Cwd::getcwd() . "/.."; - } - $ENV{MAKE} ||= "make"; - $ENV{CXX} ||= "c++"; - !defined $ENV{TEST_REGRESS} or die "TEST_REGRESS environment variable is already set"; - $ENV{TEST_REGRESS} = Cwd::getcwd(); -} - -use Getopt::Long; -use IO::File; -use Pod::Usage; -use Data::Dumper; $Data::Dumper::Sortkeys = 1; -use FindBin qw($RealBin); -use strict; -use vars qw($Debug %Vars $Driver $Fork); -use version; -use POSIX qw(strftime); -use lib "."; -use Time::HiRes qw(usleep); -use Digest::MD5 qw(md5); -use POSIX; - -$::Driver = 1; -$::Have_Forker = 0; - -eval "use Parallel::Forker; \$Fork=Parallel::Forker->new(use_sig_child=>1, poll_interval=>10*1000); \$::Have_Forker=1;"; -$Fork = Forker->new(use_sig_child => 1) if !$Fork; -my $forker_Min_Version = 1.258; -if ($::Have_Forker && $Parallel::Forker::VERSION < $forker_Min_Version) { - print STDERR "driver.pl: Parallel::Forker is older than $forker_Min_Version, suggest 'cpan install Parallel::Forker'\n"; - $::Have_Forker = 0; -} -$SIG{CHLD} = sub { $Fork->sig_child() if $Fork; }; -$SIG{TERM} = sub { $Fork->kill_tree_all('TERM') if $Fork; die "Quitting...\n"; }; - -#====================================================================== - -# Map of all scenarios, with the names used to enable them -our %All_Scenarios - = (dist => [ "dist"], - atsim => [ "simulator", "simulator_st", "atsim"], - ghdl => ["linter", "simulator", "simulator_st", "ghdl"], - iv => [ "simulator", "simulator_st", "iv"], - ms => ["linter", "simulator", "simulator_st", "ms"], - nc => ["linter", "simulator", "simulator_st", "nc"], - vcs => ["linter", "simulator", "simulator_st", "vcs"], - xrun => ["linter", "simulator", "simulator_st", "xrun"], - xsim => ["linter", "simulator", "simulator_st", "xsim"], - vlt => ["linter", "simulator", "simulator_st", "vlt_all", "vlt"], - vltmt => [ "simulator", "vlt_all", "vltmt"], - ); - -#====================================================================== -# main - -autoflush STDOUT 1; -autoflush STDERR 1; - -our @Orig_ARGV = @ARGV; -our @Orig_ARGV_Sw; foreach (@Orig_ARGV) { push @Orig_ARGV_Sw, $_ if /^-/ && !/^-j/; } -our $Start = time(); -our $Vltmt_threads = 3; - -$Debug = 0; -my $opt_benchmark; -our $Opt_Fail_Max = 20; -my @opt_tests; -my $opt_dist; -my $opt_gdb; -my $opt_rr; -my $opt_gdbbt; -my $opt_gdbsim; -my $opt_hashset; -my $opt_jobs = 1; -my $opt_quiet; -my $opt_rerun; -my $opt_rrsim; -my $opt_sanitize; -my %opt_scenarios; -my $opt_site; -my $opt_stop; -my $opt_trace; -my $opt_verbose; -my $Opt_Verilated_Debug; -our $Opt_Verilation = 1; -our @Opt_Driver_Verilator_Flags; - -Getopt::Long::config("pass_through"); -if (! GetOptions( - "benchmark:i" => sub { $opt_benchmark = $_[1] ? $_[1] : 1; }, - "debug" => \&debug, - #debugi see parameter() - "fail-max=i" => \$Opt_Fail_Max, - "gdb!" => \$opt_gdb, - "gdbbt!" => \$opt_gdbbt, - "gdbsim!" => \$opt_gdbsim, - "golden!" => sub { $ENV{HARNESS_UPDATE_GOLDEN} = 1; }, - "hashset=s" => \$opt_hashset, - "help" => \&usage, - "j=i" => \$opt_jobs, - "quiet!" => \$opt_quiet, - "rerun!" => \$opt_rerun, - "rr!" => \$opt_rr, - "rrsim!" => \$opt_rrsim, - "sanitize!" => \$opt_sanitize, - "site!" => \$opt_site, - "stop!" => \$opt_stop, - "trace!" => \$opt_trace, - "verbose!" => \$opt_verbose, - "verilation!" => \$Opt_Verilation, # Undocumented debugging - "verilated-debug!" => \$Opt_Verilated_Debug, - #W see parameter() - # Scenarios - "atsim|athdl!"=> sub { $opt_scenarios{atsim} = $_[1]; }, - "dist!" => sub { $opt_scenarios{dist} = $_[1]; }, - "ghdl!" => sub { $opt_scenarios{ghdl} = $_[1]; }, - "iv!" => sub { $opt_scenarios{iv} = $_[1]; }, - "ms!" => sub { $opt_scenarios{ms} = $_[1]; }, - "nc!" => sub { $opt_scenarios{nc} = $_[1]; }, - "vlt!" => sub { $opt_scenarios{vlt} = $_[1]; }, - "vltmt!" => sub { $opt_scenarios{vltmt} = $_[1]; }, - "vcs!" => sub { $opt_scenarios{vcs} = $_[1]; }, - "xrun!" => sub { $opt_scenarios{xrun} = $_[1]; }, - "xsim!" => sub { $opt_scenarios{xsim} = $_[1]; }, - "<>" => \¶meter, - )) { - die "%Error: Bad usage, try '$0 --help'\n"; -} - -$opt_jobs = calc_jobs() if defined $opt_jobs && $opt_jobs == 0; -$Fork->max_proc($opt_jobs); - -my $interactive_debugger = $opt_gdb || $opt_gdbsim || $opt_rr || $opt_rrsim; -if ($opt_jobs > 1 && $interactive_debugger) { - die "%Error: Unable to use -j > 1 with --gdb* and --rr* options" -} - -if ((scalar keys %opt_scenarios) < 1) { - $opt_scenarios{dist} = 1; - $opt_scenarios{vlt} = 1; -} - -our @Test_Dirs = "t"; -push @Test_Dirs, split(/:/, $ENV{VERILATOR_TESTS_SITE}) - if (($#opt_tests < 0 ? $opt_site : 1) && $ENV{VERILATOR_TESTS_SITE}); - -if ($#opt_tests < 0) { # Run everything - my %uniq; - foreach my $dir (@Test_Dirs) { - my @stats = stat($dir); # Uniquify by inode, so different paths to same place get combined - next if !$stats[1] || $uniq{$stats[1]}++; - push @opt_tests, sort(glob("${dir}/t_*.pl")); - } -} -@opt_tests = _calc_hashset(@opt_tests) if $opt_hashset; - -if ($#opt_tests >= 2 && $opt_jobs >= 2) { - # Read supported into master process, so don't call every subprocess - _have_coroutines(); - _have_sc(); - # Without this tests such as t_debug_sigsegv_bt_bad.pl will occasionally - # block on input and cause a SIGSTOP, then a "fg" was needed to resume testing. - if (!$::Have_Forker) { - print STDERR "driver.pl: NO_FORKER: For faster testing 'sudo cpan install Parallel::Forker'\n"; - } - print STDERR "== Many jobs; redirecting STDIN\n"; - open(STDIN, "+>/dev/null"); -} - -mkdir "obj_dist"; -my $timestart = strftime("%Y%m%d_%H%M%S", localtime); - -my $runner; -{ - $runner = Runner->new( - driver_log_filename => "obj_dist/driver_${timestart}.log", - quiet => $opt_quiet); - foreach my $testpl (@opt_tests) { - foreach my $scenario (sort keys %opt_scenarios) { - next if !$opt_scenarios{$scenario}; - $runner->one_test(pl_filename => $testpl, - $scenario => 1); - } - } - $runner->wait_and_report; -} - -if ($opt_rerun && $runner->fail_count) { - print("=" x 70, "\n"); - print("=" x 70, "\n"); - print("RERUN ==\n\n"); - - # Avoid parallel run to ensure that isn't causing problems - # If > 10 failures something more wrong and get results quickly - $Fork->max_proc(1) unless $runner->fail_count > 10; - - my $orig_runner = $runner; - $runner = Runner->new( - driver_log_filename => "obj_dist/driver_${timestart}_rerun.log", - quiet => 0, - fail1_cnt => $orig_runner->fail_count, - ok_cnt => $orig_runner->{ok_cnt}, - skip_cnt => $orig_runner->{skip_cnt}); - foreach my $test (@{$orig_runner->{fail_tests}}) { - # Reschedule test - $test->clean if $test->rerunnable; - $runner->one_test(pl_filename => $test->{pl_filename}, - $test->{scenario} => 1, - rerun_skipping => !$test->rerunnable); - } - $runner->wait_and_report; -} - -exit(10) if $runner->fail_count; - -#---------------------------------------------------------------------- - -sub usage { - pod2usage(-verbose => 2, -exitval => 0, -output => \*STDOUT); - exit(1); # Unreachable -} - -sub debug { - $Debug = 1; - push @Opt_Driver_Verilator_Flags, "--debug --no-skip-identical"; -} - -our $_Parameter_Next_Level; - -sub parameter { - my $param = shift; - if ($_Parameter_Next_Level) { - ($param =~ /^(\d+)$/) - or die "%Error: Expected number following $_Parameter_Next_Level: $param\n"; - push @Opt_Driver_Verilator_Flags, $param; - $_Parameter_Next_Level = undef; - } - elsif ($param =~ /\.pl/) { - push @opt_tests, $param; - } - elsif ($param =~ /^-?(-debugi|-dumpi)/) { - push @Opt_Driver_Verilator_Flags, $param; - $_Parameter_Next_Level = $param; - } - elsif ($param =~ /^-?(-W||-debug-check)/) { - push @Opt_Driver_Verilator_Flags, $param; - } - else { - die "%Error: Unknown parameter: $param\n"; - } -} - -our $_Max_Procs; - -sub max_procs { - if (!defined $_Max_Procs) { - $_Max_Procs = `python3 -c 'import multiprocessing\nprint(multiprocessing.cpu_count())'`; - chomp $_Max_Procs; - if ($_Max_Procs < 2) { - $_Max_Procs = 2; - warn "driver.pl: Python didn't find at least two CPUs\n"; - } - } - return $_Max_Procs; -} - -sub calc_threads { - my $default = shift; - my $ok = max_procs(); - $ok && !$@ or return $default; - return ($ok < $default) ? $ok : $default; -} - -sub calc_jobs { - my $ok = max_procs(); - $ok && !$@ or die "%Error: Can't use -j: $@\n"; - print "driver.pl: Found $ok cores, using -j ", $ok, "\n"; - return $ok; -} - -sub _calc_hashset { - my @in = @_; - return @in if !$opt_hashset; - $opt_hashset =~ m!^(\d+)/(\d+)$! - or die "%Error: Need number/number format for --hashset: $opt_hashset\n"; - my ($set, $nsets) = ($1, $2); - my @new; - foreach my $t (@opt_tests) { - my $checksum = unpack('L', substr(md5($t), 0, 4)); - if (($set % $nsets) == ($checksum % $nsets)) { - push @new, $t; - } - } - return @new; -} - -####################################################################### -# Verilator utilities - -our %_Verilator_Supported; -sub _verilator_get_supported { - my $feature = shift; - # Returns if given feature is supported - if (!defined $_Verilator_Supported{$feature}) { - my @args = ("perl", "$ENV{VERILATOR_ROOT}/bin/verilator", "-get-supported", $feature); - my $args = join(' ', @args); - my $out = `$args`; - $out or die "couldn't run: $! " . join(' ', @args); - chomp $out; - $_Verilator_Supported{$feature} = ($out =~ /1/ ? 1 : 0); - } - return $_Verilator_Supported{$feature}; -} - -sub _have_coroutines { - return 1 if _verilator_get_supported('COROUTINES'); - return 0; -} - -sub _have_sc { - return 1 if (defined $ENV{SYSTEMC} || defined $ENV{SYSTEMC_INCLUDE} || $ENV{CFG_HAVE_SYSTEMC}); - return 1 if _verilator_get_supported('SYSTEMC'); - return 0; -} - -####################################################################### -####################################################################### -####################################################################### -####################################################################### -# Runner class - -package Runner; -use strict; - -sub new { - my $class = shift; - my $self = { - # Arguments - driver_log_filename => undef, - quiet => 0, - # Counts - all_cnt => 0, - left_cnt => 0, - ok_cnt => 0, # Argument passed when rerunning - fail1_cnt => 0, # Argument passed when rerunning - fail_cnt => 0, - skip_cnt => 0, # Argument passed when rerunning - skip_msgs => [], - fail_msgs => [], - fail_tests => [], - # Per-task identifiers - running_ids => {}, - @_ # All legal arguments shown immediately above - }; - bless $self, $class; - return $self; -} - -sub fail_count { return $_[0]->{fail_cnt}; } - -sub one_test { - my $self = shift; - my @params = (# Parameters: - # pl_filename => - # rerun_skipping => - # {scenario_name} => 1 - @_); # All legal arguments shown immediately above - my %params = (@params); - $self->{all_cnt}++; - $self->{left_cnt}++; - $::Fork->schedule - ( - test_pl_filename => $params{pl_filename}, - run_pre_start => sub { - my $process = shift; - # Running in context of parent, before run_on_start - # Make an identifier that is unique across all current running jobs - my $i = 1; while (exists $self->{running_ids}{$i}) { ++$i; } - $process->{running_id} = $i; - if ($::Opt_Fail_Max && $::Opt_Fail_Max <= $self->fail_count) { - print STDERR "== Too many test failures; exceeded --fail-max\n" - if !$self->{_msg_fail_max_skip}++; - $process->{fail_max_skip} = 1; - } - $self->{running_ids}{$process->{running_id}} = 1; - }, - run_on_start => sub { - my $process = shift; - # Running in context of child, so can't pass data to parent directly - if ($self->{quiet}) { - open(STDOUT, ">/dev/null"); - open(STDERR, ">&STDOUT"); - } - print("=" x 70, "\n"); - my $test = VTest->new(@params, - running_id => $process->{running_id}); - $test->oprint("=" x 50, "\n"); - $test->_prep; - if ($params{rerun_skipping}) { - print " ---------- Earlier logfiles below; test was rerunnable = 0\n"; - system("cat $test->{obj_dir}/*.log"); - print " ---------- Earlier logfiles above; test was rerunnable = 0\n"; - } elsif ($process->{fail_max_skip}) { - $test->skip("Too many test failures; exceeded --fail-max"); - } else { - unlink $test->{status_filename}; - $test->_read; - } - # Don't put anything other than _exit after _read, - # as may call _exit via another path - $test->_exit; - }, - run_on_finish => sub { - # Running in context of parent - my $process = shift; - my $test = VTest->new(@params, - running_id => $process->{running_id}); - $test->_read_status; - if ($test->ok) { - $self->{ok_cnt}++; - } elsif ($test->scenario_off && !$test->errors) { - } elsif ($test->skips && !$test->errors) { - push @{$self->{skip_msgs}}, - ("\t#" . $test->soprint("-Skip: $test->{skips}\n")); - $self->{skip_cnt}++; - } else { - $test->oprint("FAILED: $test->{errors}\n"); - my $j = ($opt_jobs > 1 ? " -j" : ""); - my $makecmd = $ENV{VERILATOR_MAKE} || "$ENV{MAKE}$j &&"; - my $upperdir = (Cwd::getcwd() =~ /test_regress/ - ? 'test_regress/' : ''); - push @{$self->{fail_msgs}}, - ("\t#" . $test->soprint("%Error: $test->{errors}\n") - . "\t\t$makecmd " - . $upperdir . $test->{pl_filename} - . " " . join(' ', _manual_args()) - . " --" . $test->{scenario} . "\n"); - push @{$self->{fail_tests}}, $test; - $self->{fail_cnt}++; - $self->report($self->{driver_log_filename}); - my $other = ""; - foreach my $proc ($::Fork->running) { - $other .= " " . $proc->{test_pl_filename}; - } - $test->oprint("Simultaneous running tests:", $other, "\n") - if $other && !$opt_quiet; - if ($opt_stop) { die "%Error: --stop and errors found\n"; } - } - $self->{left_cnt}--; - $self->print_summary; - delete $self->{running_ids}{$process->{running_id}} if $process->{running_id}; - }, - )->ready(); -} - -sub wait_and_report { - my $self = shift; - $self->print_summary(force => 1); - # Wait for all children to finish - while ($::Fork->is_any_left) { - $::Fork->poll; - if ((time() - ($self->{_last_summary_time} || 0) >= 30) - && !$interactive_debugger) { # Don't show for interactive gdb etc - $self->print_summary(force => 1, show_running => 1); - } - Time::HiRes::usleep 100 * 1000; - } - $runner->report(undef); - $runner->report($self->{driver_log_filename}); -} - -sub report { - my $self = shift; - my $filename = shift; - - my $fh = \*STDOUT; - if ($filename) { - $fh = IO::File->new(">$filename") or die "%Error: $! writing $filename,"; - } - - $fh->print("\n"); - $fh->print("=" x 70, "\n"); - foreach my $f (sort @{$self->{fail_msgs}}) { - chomp $f; - $fh->print("$f\n"); - } - foreach my $f (sort @{$self->{skip_msgs}}) { - chomp $f; - $fh->print("$f\n"); - } - my $sum = ($self->{fail_cnt} && "FAILED" - || $self->{skip_cnt} && "PASSED w/SKIPS" - || "PASSED"); - $fh->print("==TESTS DONE, $sum: " . $self->sprint_summary . "\n"); -} - -sub print_summary { - my $self = shift; - my %params = (force => 0, # Force printing - show_running => 0, # Show running processes - @_); # All legal arguments shown immediately above - if (!$self->{quiet} || $params{force} - || ($self->{left_cnt} < 5) - || (time() - ($self->{_last_summary_time} || 0) >= 15)) { - $self->{_last_summary_time} = time(); - print STDERR ("==SUMMARY: " . $self->sprint_summary . "\n"); - if ($params{show_running}) { - my $other; - foreach my $proc ($::Fork->running) { - $other .= " " . $proc->{test_pl_filename}; - } - print STDERR ("==STILL RUNNING: " . $other . "\n"); - } - } -} - -sub sprint_summary { - my $self = shift; - - my $delta = time() - $::Start; - my $leftmsg = $::Have_Forker ? $self->{left_cnt} : "NO-FORKER"; - my $pct = int(100 * ($self->{left_cnt} / ($self->{all_cnt} + 0.001)) + 0.999); - # Fudge of 120% works out about right so ETA correctly predicts completion time - my $eta = 1.2 * (($self->{all_cnt} - * ($delta / (($self->{all_cnt} - $self->{left_cnt})+0.001))) - - $delta); - $eta = 0 if $delta < 10; - my $out = ""; - $out .= "Left $leftmsg " if $self->{left_cnt}; - $out .= "Passed $self->{ok_cnt}"; - # Ordered below most severe to least severe - $out .= " Failed $self->{fail_cnt}"; - $out .= " Failed-First $self->{fail1_cnt}" if $self->{fail1_cnt}; - $out .= " Skipped $self->{skip_cnt}" if $self->{skip_cnt}; - $out .= sprintf(" Eta %d:%02d", int($eta / 60), $eta % 60) if $self->{left_cnt} > 10 && $eta > 10; - $out .= sprintf(" Time %d:%02d", int($delta / 60), $delta % 60); - return $out; -} - -sub _manual_args { - # Return command line with scenarios stripped - my @out; - arg: - foreach my $arg (@Orig_ARGV_Sw) { - foreach my $allsc (keys %All_Scenarios) { - foreach my $allscarg (@{$All_Scenarios{$allsc}}) { - next arg if ("--$allscarg" eq $arg); - } - } - # Also strip certain flags that per-test debugging won't want - next arg if $arg eq '--rerun'; - next arg if $arg eq '--quiet'; - push @out, $arg; - } - return @out; -} - -####################################################################### -####################################################################### -####################################################################### -####################################################################### -# Test class - -package VTest; -use Carp; -use Cwd; -use Data::Dumper; -use File::Spec; -use File::Path qw(mkpath); - -use vars qw($Self $Self); -use strict; - -sub defineOpt { - my $xsim = shift; - return $xsim ? "--define " : "+define+"; -} - -sub new { - my $class = shift; - my $self = {@_}; # Supports arbitrary arguments - - $self->{name} ||= $2 if $self->{pl_filename} =~ m!^(.*/)?([^/]*)\.pl$!; - - $self->{scenario} = ""; - $self->{scenario} ||= "dist" if $self->{dist}; - $self->{scenario} ||= "atsim" if $self->{atsim}; - $self->{scenario} ||= "ghdl" if $self->{ghdl}; - $self->{scenario} ||= "vcs" if $self->{vcs}; - $self->{scenario} ||= "vlt" if $self->{vlt}; - $self->{scenario} ||= "vltmt" if $self->{vltmt}; - $self->{scenario} ||= "nc" if $self->{nc}; - $self->{scenario} ||= "ms" if $self->{ms}; - $self->{scenario} ||= "iv" if $self->{iv}; - $self->{scenario} ||= "xrun" if $self->{xrun}; - $self->{scenario} ||= "xsim" if $self->{xsim}; - - foreach my $dir (@::Test_Dirs) { - # t_dir used both absolutely and under obj_dir - if (-e "$dir/$self->{name}.pl") { - # Note most tests require error messages of the form t/x.v - # Therefore pl_filename must be t/ for local tests - $self->{pl_filename} = File::Spec->abs2rel("$dir/$self->{name}.pl"); - # t_dir must be absolute - used under t or under obj_dir - $self->{t_dir} ||= File::Spec->rel2abs($dir); - last; - } - } - $self->{t_dir} or die "%Error: Can't locate dir for $self->{name},"; - - if (!$self->{obj_dir}) { - my $scen_dir = File::Spec->abs2rel("$self->{t_dir}/../obj_$self->{scenario}"); - $scen_dir =~ s!^t/\.\./!!; # Simplify filenames on local runs - mkdir $scen_dir; # Not a mkpath so find out if trying to build somewhere odd - $self->{obj_dir} = "$scen_dir/$self->{name}"; - } - - my $define_opt = defineOpt($self->{xsim}); - - $self = { - name => undef, # Set below, name of this test - pl_filename => undef, # Name of .pl file to get setup from - make_top_shell => 1, # Make a default __top.v file - make_main => 1, # Make __main.cpp - make_pli => 0, # need to compile pli - sc_time_resolution => "SC_PS", # Keep - PS is SystemC default - sim_time => 1100, - threads => -1, # --threads (negative means auto based on scenario) - context_threads => 0, # Number of threads to allocate in the context - benchmark => $opt_benchmark, - verbose => $opt_verbose, - rerunnable => 1, # Rerun if fails - run_env => '', - # All compilers - v_flags => [split(/\s+/, - (($self->{xsim} ? " -f input.xsim.vc " : - (-r 'input.vc' ? " -f input.vc " : "")) - .($self->{t_dir} !~ m!/test_regress! # Don't include standard dir, only site's - ? " +incdir+$self->{t_dir} -y $self->{t_dir}" : "") - . " " . $define_opt . "TEST_OBJ_DIR=$self->{obj_dir}" - .($opt_verbose ? " " . $define_opt . "TEST_VERBOSE=1" : "") - .($opt_benchmark ? " " . $define_opt . "TEST_BENCHMARK=$opt_benchmark" : "") - .($opt_trace ? " " . $define_opt . "WAVES=1" : "") - ))], - v_flags2 => [], # Overridden in some sim files - v_other_filenames => [], # After the filename so we can spec multiple files - all_run_flags => [], - pli_flags => ["-I$ENV{VERILATOR_ROOT}/include/vltstd -fPIC -shared" - . (($^O eq "darwin" ) - ? " -Wl,-undefined,dynamic_lookup" - : " -export-dynamic") - . ($opt_verbose ? " -DTEST_VERBOSE=1" : "") - . " -o $self->{obj_dir}/libvpi.so"], - tool_c_flags => [], - # ATSIM - atsim => 0, - atsim_define => 'ATSIM', - atsim_flags => [split(/\s+/, "-c +sv +define+ATSIM"), - "+sv_dir+$self->{obj_dir}/.athdl_compile"], - atsim_flags2 => [], # Overridden in some sim files - atsim_run_flags => [], - # GHDL - ghdl => 0, - ghdl_define => 'GHDL', - ghdl_work_dir => "$self->{obj_dir}/ghdl_compile", - ghdl_flags => [($::Debug ? "-v" : ""), - "--workdir=$self->{obj_dir}/ghdl_compile", ], - ghdl_flags2 => [], # Overridden in some sim files - ghdl_run_flags => [], - # IV - iv => 0, - iv_define => 'IVERILOG', - iv_flags => [split(/\s+/, "+define+IVERILOG -g2012 -o $self->{obj_dir}/simiv")], - iv_flags2 => [], # Overridden in some sim files - iv_pli => 0, # need to use pli - iv_run_flags => [], - # VCS - vcs => 0, - vcs_define => 'VCS', - vcs_flags => [split(/\s+/, "+vcs+lic+wait +cli -debug_access +define+VCS+1 -q -sverilog -CFLAGS '-DVCS' ")], - vcs_flags2 => [], # Overridden in some sim files - vcs_run_flags => [split(/\s+/, "+vcs+lic_wait")], - # NC - nc => 0, - nc_define => 'NC', - nc_flags => [split(/\s+/, ("+licqueue +nowarn+LIBNOU +define+NC=1 -q +assert +sv -c " - . ($opt_trace ? " +access+r" : "")))], - nc_flags2 => [], # Overridden in some sim files - nc_run_flags => [split(/\s+/, "+licqueue -q +assert +sv -R")], - # ModelSim - ms => 0, - ms_define => 'MS', - ms_flags => [split(/\s+/, ("-sv -work $self->{obj_dir}/work +define+MS=1 -ccflags \"-DMS=1\""))], - ms_flags2 => [], # Overridden in some sim files - ms_pli => 1, # need to use pli - ms_run_flags => [split(/\s+/, "-lib $self->{obj_dir}/work -c -do 'run -all;quit' ")], - # Xcelium (xrun) - xrun => 0, - xrun_define => 'XRUN', - xrun_flags => [], # doesn't really have a compile step - xrun_flags2 => [], # Overridden in some sim files - xrun_run_flags => [split(/\s+/, "-64 -access +rwc -newsv -sv -xmlibdirname $self->{obj_dir}/work -l $self->{obj_dir}/history -quiet -plinowarn ")], - # XSim - xsim => 0, - xsim_define => 'XSIM', - xsim_flags => [split(/\s+/, ("--nolog --sv --define XSIM --work $self->{name}=$self->{obj_dir}/xsim"))], - xsim_flags2 => [], # Overridden in some sim files - xsim_run_flags => [split(/\s+/, ("--nolog --runall --lib $self->{name}=$self->{obj_dir}/xsim" - .($opt_trace ? " --debug all" : "")))], - xsim_run_flags2 => [], # Overridden in some sim files - # Verilator - vlt => 0, - vltmt => 0, - verilator_define => 'VERILATOR', - verilator_flags => ["-cc", - "-Mdir $self->{obj_dir}", - "--fdedup", # As currently disabled unless -O3 - "--debug-check", - "--comp-limit-members 10", ], - verilator_flags2 => [], - verilator_flags3 => ["--clk clk"], - verilator_make_gmake => 1, - verilator_make_cmake => 0, - verilated_debug => $Opt_Verilated_Debug, - stdout_filename => undef, # Redirect stdout - %$self}; - bless $self, $class; - - $self->{vlt_all} = $self->{vlt} || $self->{vltmt}; # Any Verilator scenario - - $self->{vm_prefix} ||= "V" . $self->{name}; - $self->{stats} ||= "$self->{obj_dir}/V" . $self->{name} . "__stats.txt"; - $self->{status_filename} ||= "$self->{obj_dir}/V" . $self->{name} . ".status"; - $self->{run_log_filename} ||= "$self->{obj_dir}/vlt_sim.log"; - $self->{coverage_filename} ||= "$self->{obj_dir}/coverage.dat"; - $self->{main_filename} ||= "$self->{obj_dir}/$self->{vm_prefix}__main.cpp"; - ($self->{top_filename} ||= $self->{pl_filename}) =~ s/\.pl$//; - ($self->{golden_filename} ||= $self->{pl_filename}) =~ s/\.pl$/.out/; - if (-e ($self->{top_filename} . ".vhd")) { # If VHDL file exists - $self->{vhdl} = 1; - $self->{top_filename} .= ".vhd"; - } else { - $self->{top_filename} .= ".v"; - } - if (!$self->{make_top_shell}) { - $self->{top_shell_filename} = $self->{top_filename}; - } else { - $self->{top_shell_filename} = "$self->{obj_dir}/$self->{vm_prefix}__top.v"; - } - $self->{pli_filename} ||= $self->{name} . ".cpp"; - - return $self; -} - -sub benchmarksim_filename { - my $self = (ref $_[0] ? shift : $Self); - return $self->{obj_dir} . "/$self->{name}_benchmarksim.csv"; -} - -sub init_benchmarksim { - my $self = (ref $_[0] ? shift : $Self); - # Simulations with benchmarksim enabled append to the same file between runs. - # Test files must ensure a clean benchmark data file before executing tests. - my $filename = $self->benchmarksim_filename(); - my $fh = IO::File->new(">" . $filename) or die "%Error: $! " . $filename; - print $fh "# Verilator simulation benchmark data\n"; - print $fh "# Test name: " . $self->{name} . "\n"; - print $fh "# Top file: " . $self->{top_filename} . "\n"; - print $fh "evals, time[s]\n"; -} - -sub soprint { - my $self = (ref $_[0] ? shift : $Self); - my $str = "$self->{scenario}/$self->{name}: " . join('', @_); - $str =~ s/\n\n+$/\n/s; - return $str; -} - -sub oprint { - my $self = (ref $_[0] ? shift : $Self); - print $self->soprint(@_); -} - -sub error { - my $self = (ref $_[0] ? shift : $Self); - my $msg = join('', @_); - # Called from tests as: error("Reason message"[, ...]); - warn "%Warning: $self->{scenario}/$self->{name}: " . $msg . "\n"; - $self->{errors} ||= $msg; -} - -sub error_keep_going { - my $self = (ref $_[0] ? shift : $Self); - my $msg = join('', @_); - # Called from tests as: error_keep_going("Reason message"[, ...]); - warn "%Warning: $self->{scenario}/$self->{name}: " . $msg . "\n"; - $self->{errors_keep_going} ||= $msg; -} - -sub skip { - my $self = (ref $_[0] ? shift : $Self); - my $msg = join('', @_); - # Called from tests as: skip("Reason message"[, ...]); - warn "-Skip: $self->{scenario}/$self->{name}: " . $msg . "\n"; - $self->{skips} ||= "Skip: " . $msg; -} - -sub scenarios { - my $self = (ref $_[0] ? shift : $Self); - my %params = (@_); # Called from tests as: scenarios(...); - # to specify which scenarios this test runs under. - # Where ... is one cases listed in All_Scenarios - if ((scalar keys %params) < 1) { - $params{simulators} = 1; - } - my %enabled_scenarios; - foreach my $scenario (keys %params) { - my $value = $params{$scenario}; - my $hit = 0; - foreach my $allsc (keys %All_Scenarios) { - foreach my $allscarg (@{$All_Scenarios{$allsc}}) { - if ($scenario eq $allscarg) { - $hit = 1; - $enabled_scenarios{$allsc} = 1; - } - } - } - if (!$hit) { - $self->error("scenarios('$scenario' => ...) has unknown scenario '$scenario',"); - } - } - - if (!$enabled_scenarios{$self->{scenario}}) { - $self->skip("scenario '$self->{scenario}' not enabled for test"); - $self->{scenario_off} ||= 1; - $self->_exit(); - } -} - -sub _prep { - my $self = shift; - mkdir $self->{obj_dir}; # Ok if already exists -} - -sub _read { - my $self = shift; - # Read the control file - (-r $self->{pl_filename}) - or return $self->error("Can't open $self->{pl_filename}\n"); - $Self = $self; - delete $INC{$self->{pl_filename}}; - require $self->{pl_filename}; -} - -sub _exit { - my $self = shift; - if ($self->ok) { - $self->oprint("Self PASSED\n"); - } elsif ($self->skips && !$self->errors) { - $self->oprint("-Skip: $self->{skips}\n"); - } else { - $self->error("Missing ok\n") if !$self->errors; - $self->oprint("%Error: $self->{errors}\n"); - } - $self->_write_status; - exit(0); -} - -sub _write_status { - my $self = shift; - my $filename = $self->{status_filename}; - my $fh = IO::File->new(">$filename") or die "%Error: $! $filename,"; - $Data::Dumper::Indent = 1; - $Data::Dumper::Sortkeys = 1; - print $fh Dumper($self); - print $fh "1;"; - $fh->close(); -} - -sub _read_status { - my $self = shift; - my $filename = $self->{status_filename}; - use vars qw($VAR1); - local $VAR1; - if (!-r $filename) { - $self->error("driver.pl _read_status file missing: $filename"); - return; - } - { - local %INC = (); - require $filename or die "%Error: $! $filename,"; - } - if ($VAR1) { - %{$self} = %{$VAR1}; - } else { - $self->error("driver.pl _read_status file empty: $filename"); - return; - } -} - -#---------------------------------------------------------------------- -# Methods invoked by tests - -sub clean { - my $self = (ref $_[0] ? shift : $Self); - # Called on a rerun to cleanup files - if ($self->{clean_command}) { - system($self->{clean_command}); - } - if (1) { - # Prevents false-failures when switching compilers - # Remove old results to force hard rebuild - system("rm", "-rf", "$self->{obj_dir}__fail1"); - system("mv", "$self->{obj_dir}", "$self->{obj_dir}__fail1"); - } -} - -sub clean_objs { - my $self = (ref $_[0] ? shift : $Self); - system("rm", "-rf", glob("$self->{obj_dir}/*")); -} - -sub _checkflags { - my $self = shift; - my %param = (@_); - my $checkflags = (' '.join(' ', - @{$param{v_flags}}, - @{$param{v_flags2}}, - @{$param{verilator_flags}}, - @{$param{verilator_flags2}}, - @{$param{verilator_flags3}}) - .' '); - return $checkflags; -} - -sub compile_vlt_cmd { - my $self = (ref $_[0] ? shift : $Self); - my %param = (%{$self}, # Default arguments are from $self - @_); # Supports arbitrary arguments - return 1 if $self->errors || $self->skips; - - my @vlt_cmd = ( - "perl", "$ENV{VERILATOR_ROOT}/bin/verilator", - $self->_compile_vlt_flags(%param), - $param{top_filename}, - @{$param{v_other_filenames}}, - $param{stdout_filename} ? "> " . $param{stdout_filename} : "" - ); - return @vlt_cmd; -} - -sub _compile_vlt_flags { - my $self = shift; - my %param = (@_); # Supports arbitrary arguments from compile_vlt_cmd - return 1 if $self->errors || $self->skips; - - my $checkflags = $self->_checkflags(%param); - die "%Error: specify threads via 'threads =>' argument, not as a command line option" unless ($checkflags !~ /(^|\s)-?-threads\s/); - $self->{coverage} = 1 if ($checkflags =~ /-coverage\b/); - my $driver_verilator_flags = ' '.join(' ', driver_verilator_flags()).' '; - $self->{pins_sc_uint_bool} = 1 if (($checkflags =~ /-pins-sc-uint-bool\b/) - || ($driver_verilator_flags =~ /-pins-sc-uint-bool\b/)); - - $self->{savable} = 1 if ($checkflags =~ /-savable\b/); - $self->{sc} = 1 if ($checkflags =~ /-sc\b/); - $self->{timing} = 1 if ($checkflags =~ / -?-timing\b/ || $checkflags =~ / -?-binary\b/ ); - $self->{trace} = ($opt_trace || $checkflags =~ /-trace\b/ - || $checkflags =~ /-trace-fst\b/); - $self->{trace_format} = (($checkflags =~ /-trace-fst/ && $self->{sc} && 'fst-sc') - || ($checkflags =~ /-trace-fst/ && !$self->{sc} && 'fst-c') - || ($self->{sc} && 'vcd-sc') - || (!$self->{sc} && 'vcd-c')); - $self->{sanitize} = $opt_sanitize unless exists($self->{sanitize}); - $self->{benchmarksim} = 1 if ($param{benchmarksim}); - - my @verilator_flags = @{$param{verilator_flags}}; - unshift @verilator_flags, "--gdb" if $opt_gdb; - unshift @verilator_flags, "--gdbbt" if $opt_gdbbt; - unshift @verilator_flags, "--rr" if $opt_rr; - unshift @verilator_flags, "--x-assign unique"; # More likely to be buggy - unshift @verilator_flags, "--trace" if $opt_trace; - unshift @verilator_flags, "--threads $param{threads}" if $param{threads} >= 0; - unshift @verilator_flags, "--trace-threads 2" if $param{vltmt} && $checkflags =~ /-trace-fst /; - unshift @verilator_flags, "--debug-partition" if $param{vltmt}; - unshift @verilator_flags, "-CFLAGS -ggdb -LDFLAGS -ggdb" if $opt_gdbsim || $opt_rrsim; - unshift @verilator_flags, "-CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined" if $param{sanitize}; - unshift @verilator_flags, "--make gmake" if $param{verilator_make_gmake}; - unshift @verilator_flags, "--make cmake" if $param{verilator_make_cmake}; - unshift @verilator_flags, "--exe" if - $param{make_main} && $param{verilator_make_gmake}; - unshift @verilator_flags, "../" . $self->{main_filename} if - $param{make_main} && $param{verilator_make_gmake}; - - my @cmdargs = ( - "--prefix " . $param{vm_prefix}, - @verilator_flags, - @{$param{verilator_flags2}}, - @{$param{verilator_flags3}}, - @{$param{v_flags}}, - @{$param{v_flags2}}, - # Flags from driver cmdline override default flags and - # flags from the test itself - driver_verilator_flags(), - ); - return @cmdargs; -} - -sub driver_verilator_flags { - # my $self = (ref $_[0] ? shift : $Self); - return @Opt_Driver_Verilator_Flags; -} - -sub lint { - my $self = (ref $_[0] ? shift : $Self); - my %param = (# - %{$self}, # Default arguments are from $self - # Lint specific default overrides - make_main => 0, - make_top_shell => 0, - verilator_flags2 => ["--lint-only"], - verilator_make_gmake => 0, - @_); # Supports arbitrary arguments - $self->compile(%param); -} - -sub compile { - my $self = (ref $_[0] ? shift : $Self); - my %param = (tee => 1, - %{$self}, # Default arguments are from $self - @_); # Supports arbitrary arguments - return 1 if $self->errors || $self->skips; - $self->oprint("Compile\n") if $self->{verbose}; - - die "%Error: 'threads =>' argument must be <= 1 for vlt scenario" if $param{vlt} && $param{threads} > 1; - # Compute automatic parameter values - my $checkflags = $self->_checkflags(%param); - $param{threads} = ::calc_threads($Vltmt_threads) if $param{threads} < 0 && $param{vltmt}; - $param{context_threads} = $param{threads} >= 1 ? $param{threads} : 1 if !$param{context_threads}; - $param{make_main} = 0 if ($checkflags =~ / -?-main\b/ || $checkflags =~ / -?-binary\b/); - if ($checkflags =~ / -?-build\b/ || $checkflags =~ / -?-binary\b/) { - $param{verilator_make_cmake} = 0; - $param{verilator_make_gmake} = 0; - } - - $self->{threads} = $param{threads}; - $self->{context_threads} = $param{context_threads}; - - $self->compile_vlt_cmd(%param); - - my $define_opt = defineOpt($self->{xsim}); - if (join(' ', @{$self->{v_flags}}) !~ /TEST_DUMPFILE/) { - push @{$self->{v_flags}}, ($define_opt . "TEST_DUMPFILE=" . $self->trace_filename); - } - - if (!$param{make_top_shell}) { - $param{top_shell_filename} - = $self->{top_shell_filename} = ""; - } else { - $param{top_shell_filename} - = $self->{top_shell_filename} = "$self->{obj_dir}/$self->{vm_prefix}__top." . $self->v_suffix; - } - - if ($param{atsim}) { - $param{tool_define} ||= $param{atsim_define}; - $self->_make_top() if $param{make_top_shell}; - $self->_run(logfile=>"$self->{obj_dir}/atsim_compile.log", - fails=>$param{fails}, - cmd=>[($ENV{VERILATOR_ATSIM} || "atsim"), - @{$param{atsim_flags}}, - @{$param{atsim_flags2}}, - @{$param{v_flags}}, - @{$param{v_flags2}}, - $param{top_filename}, - $param{top_shell_filename}, - @{$param{v_other_filenames}}, - ]); - } - elsif ($param{ghdl}) { - $param{tool_define} ||= $param{ghdl_define}; - mkdir $self->{ghdl_work_dir}; - $self->_make_top() if $param{make_top_shell}; - $self->_run(logfile=>"$self->{obj_dir}/ghdl_compile.log", - fails=>$param{fails}, - cmd=>[($ENV{VERILATOR_GHDL} || "ghdl"), - # Add -c here, as having -c twice freaks it out - ((($ENV{VERILATOR_GHDL} || ' ') =~ / -c\b/) ? "" : "-c"), - @{$param{ghdl_flags}}, - @{$param{ghdl_flags2}}, - #@{$param{v_flags}}, # Not supported - #@{$param{v_flags2}}, # Not supported - $param{top_filename}, - $param{top_shell_filename}, - @{$param{v_other_filenames}}, - "-e t", - ]); - } - elsif ($param{vcs}) { - $param{tool_define} ||= $param{vcs_define}; - $self->_make_top() if $param{make_top_shell}; - $self->_run(logfile=>"$self->{obj_dir}/vcs_compile.log", - fails=>$param{fails}, - cmd=>[($ENV{VERILATOR_VCS} || "vcs"), - @{$param{vcs_flags}}, - @{$param{vcs_flags2}}, - ($opt_verbose ? " -CFLAGS -DTEST_VERBOSE=1" : ""), - @{$param{v_flags}}, - @{$param{v_flags2}}, - $param{top_filename}, - $param{top_shell_filename}, - @{$param{v_other_filenames}}, - ]); - } - elsif ($param{nc}) { - $param{tool_define} ||= $param{nc_define}; - $self->_make_top() if $param{make_top_shell}; - my @more_args; - if ($self->vhdl) { - ((my $ts = $param{top_shell_filename}) =~ s!\.v!!); - $ts =~ s!.*/!!; - push @more_args, "-vhdltop", $ts; - } - $self->_run(logfile=>"$self->{obj_dir}/nc_compile.log", - fails=>$param{fails}, - cmd=>[($ENV{VERILATOR_NCVERILOG} || "ncverilog"), - @{$param{nc_flags}}, - @{$param{nc_flags2}}, - @{$param{v_flags}}, - @{$param{v_flags2}}, - $param{top_filename}, - $param{top_shell_filename}, - @{$param{v_other_filenames}}, - @more_args - ]); - } - elsif ($param{ms}) { - $param{tool_define} ||= $param{ms_define}; - $self->_make_top() if $param{make_top_shell}; - $self->_run(logfile=>"$self->{obj_dir}/ms_compile.log", - fails=>$param{fails}, - cmd=>[("vlib $self->{obj_dir}/work && "), - ($ENV{VERILATOR_MODELSIM} || "vlog"), - @{$param{ms_flags}}, - @{$param{ms_flags2}}, - @{$param{v_flags}}, - @{$param{v_flags2}}, - $param{top_filename}, - $param{top_shell_filename}, - @{$param{v_other_filenames}} - ]); - } - elsif ($param{iv}) { - $param{tool_define} ||= $param{iv_define}; - $self->_make_top() if $param{make_top_shell}; - my @cmd = (($ENV{VERILATOR_IVERILOG} || "iverilog"), - @{$param{iv_flags}}, - @{$param{iv_flags2}}, - @{$param{v_flags}}, - @{$param{v_flags2}}, - $param{top_filename}, - $param{top_shell_filename}, - @{$param{v_other_filenames}}); - @cmd = grep { s/\+define\+/-D /g; $_; } @cmd; - - $self->_run(logfile=>"$self->{obj_dir}/iv_compile.log", - fails=>$param{fails}, - cmd=>\@cmd); - } - elsif ($param{xrun}) { - $param{tool_define} ||= $param{xrun_define}; - $self->_make_top() if $param{make_top_shell}; - } - elsif ($param{xsim}) { - $param{tool_define} ||= $param{xsim_define}; - $self->_make_top() if $param{make_top_shell}; - $self->_run(logfile=>"$self->{obj_dir}/xsim_compile.log", - fails=>$param{fails}, - cmd=>[($ENV{VERILATOR_XVLOG} || "xvlog"), - @{$param{xsim_flags}}, - @{$param{xsim_flags2}}, - @{$param{v_flags}}, - @{$param{v_flags2}}, - $param{top_filename}, - $param{top_shell_filename}, - @{$param{v_other_filenames}} - ]); - } - elsif ($param{vlt_all}) { - $param{tool_define} ||= $param{verilator_define}; - - if ($self->sc && !$self->have_sc) { - $self->skip("Test requires SystemC; ignore error since not installed\n"); - return 1; - } - if ($self->{timing} && !$self->have_coroutines) { - $self->skip("Test requires Coroutines; ignore error since not available\n"); - return 1; - } - if ($param{verilator_make_cmake} && !$self->have_cmake) { - $self->skip("Test requires CMake; ignore error since not available or version too old\n"); - return 1; - } - - if (!$param{fails} && $param{make_main}) { - $self->_make_main($param{timing_loop}); - } - - if ($param{verilator_make_gmake} - || (!$param{verilator_make_gmake} && !$param{verilator_make_cmake})) { - my @vlt_cmd = $self->compile_vlt_cmd(%param); - $self->oprint("Running Verilator (gmake)\n") if $self->{verbose}; - $self->_run(logfile => "$self->{obj_dir}/vlt_compile.log", - fails => $param{fails}, - tee => $param{tee}, - expect => $param{expect}, - expect_filename => $param{expect_filename}, - verilator_run => 1, - cmd => \@vlt_cmd) if $::Opt_Verilation; - return 1 if $self->errors || $self->skips; - } - - if ($param{verilator_make_cmake}) { - my @vlt_args = $self->_compile_vlt_flags(%param); - $self->oprint("Running cmake\n") if $self->{verbose}; - mkdir $self->{obj_dir}; - my @csources = (); - unshift @csources, $self->{main_filename} if $param{make_main}; - $self->_run(logfile => "$self->{obj_dir}/vlt_cmake.log", - fails => $param{fails}, - tee => $param{tee}, - expect => $param{expect}, - expect_filename => $param{expect_filename}, - verilator_run => 1, - cmd => ["cd \"" . $self->{obj_dir} . "\" && cmake", - "\"" . $self->{t_dir} . "/..\"", - "-DTEST_VERILATOR_ROOT=$ENV{VERILATOR_ROOT}", - "-DTEST_NAME=$self->{name}", - "-DTEST_CSOURCES=\"@csources\"", - "-DTEST_VERILATOR_ARGS=\"@vlt_args\"", - "-DTEST_VERILATOR_SOURCES=\"$param{top_filename} @{$param{v_other_filenames}}\"", - "-DTEST_VERBOSE=\"" . ($self->{verbose} ? 1 : 0) . "\"", - "-DTEST_SYSTEMC=\"" . ($self->sc ? 1 : 0) . "\"", - "-DCMAKE_PREFIX_PATH=\"" . (($ENV{SYSTEMC_INCLUDE} || $ENV{SYSTEMC} || '') . "/..\""), - "-DTEST_OPT_FAST=\"" . ($param{benchmark} ? "-Os" : "-O0") . "\"", - "-DTEST_OPT_GLOBAL=\"" . ($param{benchmark} ? "-Os" : "-O0") . "\"", - "-DTEST_VERILATION=\"" . $::Opt_Verilation . "\"", - ]); - return 1 if $self->errors || $self->skips; - } - - if (!$param{fails} && $param{verilator_make_gmake}) { - $self->oprint("Running make (gmake)\n") if $self->{verbose}; - $self->_run(logfile => "$self->{obj_dir}/vlt_gcc.log", - entering => "$self->{obj_dir}", - cmd => [$ENV{MAKE}, - "-C " . $self->{obj_dir}, - "-f " . $FindBin::RealBin . "/Makefile_obj", - ($self->{verbose} ? "" : "--no-print-directory"), - "VM_PREFIX=$self->{vm_prefix}", - "TEST_OBJ_DIR=$self->{obj_dir}", - "CPPFLAGS_DRIVER=-D" . uc($self->{name}), - ($self->{verbose} ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" : ""), - ($param{benchmark} ? "" : "OPT_FAST=-O0"), - ($param{benchmark} ? "" : "OPT_GLOBAL=-O0"), - "$self->{vm_prefix}", # bypass default rule, as we don't need archive - ($param{make_flags} || ""), - ]); - } - - if (!$param{fails} && $param{verilator_make_cmake}) { - $self->oprint("Running cmake --build\n") if $self->{verbose}; - $self->_run(logfile => "$self->{obj_dir}/vlt_cmake_build.log", - cmd => ["cmake", - "--build", $self->{obj_dir}, - ($self->{verbose} ? "--verbose" : ""), - ]); - } - } - else { - $self->error("No compile step defined for '$self->{scenario}' scenario"); - } - - if ($param{make_pli}) { - # if make_pli is a string and not one - if ($param{make_pli} ne "1") { - $self->{pli_filename} = $param{make_pli}; - } - $self->oprint("Compile vpi\n") if $self->{verbose}; - my @cmd = ($ENV{CXX}, @{$param{pli_flags}}, - "-D" . $param{tool_define}, - "-DIS_VPI", ($ENV{CFLAGS} || ''), - "$self->{t_dir}/$self->{pli_filename}"); - - $self->_run(logfile=>"$self->{obj_dir}/pli_compile.log", - fails=>$param{fails}, - cmd=>\@cmd); - } - - return 1; -} - -sub execute { - my $self = (ref $_[0] ? shift : $Self); - return 1 if $self->errors || $self->skips; - my %param = (%{$self}, # Default arguments are from $self - @_); # Supports arbitrary arguments - # params may be expect or {tool}_expect - $self->oprint("Run\n") if $self->{verbose}; - - delete $ENV{SYSTEMC_DISABLE_COPYRIGHT_MESSAGE}; - $ENV{SYSTEMC_DISABLE_COPYRIGHT_MESSAGE} = "DISABLE" if !$self->{verbose}; - - $ENV{VERILATOR_SOLVER} = "test.pl-file-needs-have_solver()-call" - if !$self->{_have_solver_called}; - - my $run_env = $param{run_env}; - $run_env .= ' ' if $run_env; - - if ($param{atsim}) { - $self->_run(logfile=>"$self->{obj_dir}/atsim_sim.log", - fails=>$param{fails}, - cmd=>["echo q | " . $run_env . "$self->{obj_dir}/athdl_sv", - @{$param{atsim_run_flags}}, - @{$param{all_run_flags}}, - ], - %param, - expect=>$param{atsim_run_expect}, # non-verilator expect isn't the same - expect_filename=>$param{atsim_run_expect_filename}, - ); - } - elsif ($param{ghdl}) { - $self->_run(logfile=>"$self->{obj_dir}/ghdl_sim.log", - fails=>$param{fails}, - cmd=>[$run_env . "$self->{obj_dir}/simghdl", - @{$param{ghdl_run_flags}}, - @{$param{all_run_flags}}, - ], - %param, - expect=>$param{ghdl_run_expect}, # non-verilator expect isn't the same - expect_filename=>$param{ghdl_run_expect_filename}, - ); - } - elsif ($param{iv}) { - my @cmd = ($run_env . "$self->{obj_dir}/simiv", - @{$param{iv_run_flags}}, - @{$param{all_run_flags}}, - ); - if ($param{use_libvpi}) { - # don't enter command line on $stop, include vpi - unshift @cmd, "vvp -n -m $self->{obj_dir}/libvpi.so"; - } - $self->_run(logfile=>"$self->{obj_dir}/iv_sim.log", - fails=>$param{fails}, - cmd=> \@cmd, - %param, - expect=>$param{iv_run_expect}, # non-verilator expect isn't the same - expect_filename=>$param{iv_run_expect_filename}, - ); - } - elsif ($param{ms}) { - my @pli_opt = (); - if ($param{use_libvpi}) { - unshift @pli_opt, "-pli $self->{obj_dir}/libvpi.so"; - } - $self->_run(logfile=>"$self->{obj_dir}/ms_sim.log", - fails=>$param{fails}, - cmd=>["echo q | " . $run_env . ($ENV{VERILATOR_MODELSIM} || "vsim"), - @{$param{ms_run_flags}}, - @{$param{all_run_flags}}, - @{pli_opt}, - (" top") - ], - %param, - expect=>$param{ms_run_expect}, # non-verilator expect isn't the same - expect_filename=>$param{ms_expect_filename}, - ); - } - elsif ($param{nc}) { - $self->_run(logfile=>"$self->{obj_dir}/nc_sim.log", - fails=>$param{fails}, - cmd=>["echo q | " . $run_env . ($ENV{VERILATOR_NCVERILOG} || "ncverilog"), - @{$param{nc_run_flags}}, - @{$param{all_run_flags}}, - ], - %param, - expect=>$param{nc_run_expect}, # non-verilator expect isn't the same - expect_filename=>$param{nc_run_expect_filename}, - ); - } - elsif ($param{vcs}) { - #my $fh = IO::File->new(">simv.key") or die "%Error: $! simv.key,"; - #$fh->print("quit\n"); $fh->close; - $self->_run(logfile=>"$self->{obj_dir}/vcs_sim.log", - cmd=>["echo q | " . $run_env . "./simv", - @{$param{vcs_run_flags}}, - @{$param{all_run_flags}}, - ], - %param, - expect=>$param{vcs_run_expect}, # non-verilator expect isn't the same - expect_filename=>$param{vcs_run_expect_filename}, - ); - } - elsif ($param{xrun}) { - my @pli_opt = (); - if ($param{use_libvpi}) { - unshift @pli_opt, "-loadvpi $self->{obj_dir}/libvpi.so:vpi_compat_bootstrap"; - } - $self->_run(logfile=>"$self->{obj_dir}/xrun_sim.log", - fails=>$param{fails}, - cmd=>["echo q | " . $run_env . ($ENV{VERILATOR_XRUN} || "xrun "), - @{$param{xrun_run_flags}}, - @{$param{xrun_flags2}}, - @{$param{all_run_flags}}, - @{pli_opt}, - $param{top_filename}, - ], - %param, - expect=>$param{xrun_run_expect}, # non-verilator expect isn't the same - expect_filename=>$param{xrun_run_expect_filename}, - ); - } - elsif ($param{xsim}) { - $self->_run(logfile=>"$self->{obj_dir}/xsim_sim.log", - fails=>$param{fails}, - cmd=>[$run_env.($ENV{VERILATOR_XELAB} || "xelab"), - @{$param{xsim_run_flags}}, - @{$param{xsim_run_flags2}}, - @{$param{all_run_flags}}, - (" $self->{name}.top") - ], - %param, - expect=>$param{xsim_run_expect}, # non-verilator expect isn't the same - expect_filename=>$param{xsim_expect_filename}, - ); - } - elsif ($param{vlt_all} - #&& (!$param{needs_v4} || -r "$ENV{VERILATOR_ROOT}/src/V3Gate.cpp") - ) { - $param{executable} ||= "$self->{obj_dir}/$param{vm_prefix}"; - my $debugger = ""; - if ($opt_gdbsim) { - $debugger = ($ENV{VERILATOR_GDB} || "gdb") . " "; - } elsif ($opt_rrsim) { - $debugger = "rr record "; - } - $self->_run(logfile=>"$self->{obj_dir}/vlt_sim.log", - cmd=>[($run_env - .$debugger - .$param{executable} - .($opt_gdbsim ? " -ex 'run " : "")), - @{$param{all_run_flags}}, - ($opt_gdbsim ? "'" : ""), - ], - %param, - expect=>$param{expect}, # backward compatible name - expect_filename=>$param{expect_filename}, # backward compatible name - ); - } - else { - $self->error("No execute step for this simulator"); - } -} - -sub setenv { - my $self = (ref $_[0] ? shift : $Self); - my $var = shift; - my $val = shift; - print "\texport $var='$val'\n"; - $ENV{$var} = $val; -} - -sub inline_checks { - my $self = (ref $_[0] ? shift : $Self); - return 1 if $self->errors || $self->skips; - return 1 if !$self->{vlt_all}; - - my $covfn = $Self->{coverage_filename}; - my $contents = $self->file_contents($covfn); - - $self->oprint("Extract checks\n") if $self->{verbose}; - my $fh = IO::File->new("<$self->{top_filename}"); - while (defined(my $line = $fh->getline)) { - if ($line =~ /CHECK/) { - if ($line =~ /CHECK_COVER *\( *([---0-9]+) *, *"([^"]+)" *, *("([^"]+)" *,|) *(\d+) *\)/) { - my $lineno = ($. + $1); my $hier = $2; my $comment = $4; my $count = $5; - my $regexp = "\001l\002" . $lineno; - $regexp .= ".*\001o\002" . quotemeta($comment) if $comment; - $regexp .= ".*\001h\002" . quotemeta($hier) if $hier; - $regexp .= ".*' " . $count; - if ($contents !~ /$regexp/) { - $self->error("CHECK_COVER: $covfn: Regexp not found: $regexp\n" . - "From $self->{top_filename}:$.: $line"); - } - } - elsif ($line =~ /CHECK_COVER_MISSING *\( *([---0-9]+) *\)/) { - my $lineno = ($. + $1); - my $regexp = "\001l\002" . $lineno; - if ($contents =~ /$regexp/) { - $self->error("CHECK_COVER_MISSING: $covfn: Regexp found: $regexp\n" . - "From $self->{top_filename}:$.: $line"); - } - } - else { - $self->error("$self->{top_filename}:$.: Unknown CHECK request: $line"); - } - } - } - $fh->close; -} - -#---------------------------------------------------------------------- -# Accessors - -sub ok { - my $self = (ref $_[0] ? shift : $Self); - $self->{ok} = $_[0] if defined $_[0]; - $self->{ok} = 0 if $self->{errors} || $self->{errors_keep_going} || $self->{skips}; - return $self->{ok}; -} - -sub continuing { - my $self = (ref $_[0] ? shift : $Self); - return !($self->errors || $self->skips); -} - -sub errors { - my $self = (ref $_[0] ? shift : $Self); - return $self->{errors}; -} - -sub golden_filename { - my $self = (ref $_[0] ? shift : $Self); - $self->{golden_filename} = shift if defined $_[0]; - return $self->{golden_filename}; -} - -sub scenario_off { - my $self = (ref $_[0] ? shift : $Self); - return $self->{scenario_off}; -} - -sub skips { - my $self = (ref $_[0] ? shift : $Self); - return $self->{skips}; -} - -sub top_filename { - my $self = (ref $_[0] ? shift : $Self); - $self->{top_filename} = shift if defined $_[0]; - return $self->{top_filename}; -} - -sub vhdl { - my $self = (ref $_[0] ? shift : $Self); - $self->{vhdl} = shift if defined $_[0]; - if ($self->{vhdl}) { - $self->{top_filename} =~ s/\.v$/\.vhdl/; - } - return $self->{vhdl}; -} - -sub v_suffix { - my $self = (ref $_[0] ? shift : $Self); - # Suffix for file type, e.g. .vhdl or .v - return $self->{vhdl} ? "vhdl" : "v"; -} - -sub sc { - my $self = (ref $_[0] ? shift : $Self); - return $self->{sc}; -} - -sub have_sc { - return ::_have_sc(); -} - -sub have_coroutines { - return ::_have_coroutines(); -} - -sub make_version { - my $ver = `$ENV{MAKE} --version`; - if ($ver =~ /make ([0-9]+\.[0-9]+)/i) { - return $1; - } else { - return -1; - } -} - -sub have_cmake { - return cmake_version() >= version->declare("3.8"); -} - -sub cmake_version { - chomp(my $cmake_bin = `which cmake`); - if (!$cmake_bin) { - return undef; - } - my $cmake_version = `cmake --version`; - if ($cmake_version !~ /cmake version (\d+)\.(\d+)/) { - return undef; - } - $cmake_version = "$1.$2"; - return version->declare($cmake_version); -} - -our $_have_solver = undef; -sub have_solver { - my $self = (ref $_[0] ? shift : $Self); - $self->{_have_solver_called} = 1; - if (!defined($_have_solver)) { - my $ok = `(z3 --help || cvc5 --help || cvc4 --help) 2>/dev/null`; - $ok ||= ""; - if ($ok =~ /usage/i) { - $_have_solver = 1; - } else { - $_have_solver = 0; - } - } - return $_have_solver; -} - -our $_aslr_off = undef; -sub aslr_off { - if (!defined($_aslr_off)) { - my $ok = `setarch --addr-no-randomize echo ok 2>/dev/null` || ""; - if ($ok =~ /ok/) { - $_aslr_off = "setarch --addr-no-randomize "; - } else { - $_aslr_off = ""; - } - } - return $_aslr_off; -} - -sub trace_filename { - my $self = shift; - return "$self->{obj_dir}/simx.fst" if $self->{trace_format} =~ /^fst/; - return "$self->{obj_dir}/simx.vcd"; -} - -sub obj_dir { - my $self = shift; - return $self->{obj_dir}; -} - -sub get_default_vltmt_threads { - return $Vltmt_threads; -} - -sub pli_filename { - my $self = (ref $_[0] ? shift : $Self); - $self->{pli_filename} = shift if defined $_[0]; - return $self->{pli_filename}; -} - -sub rerunnable { - my $self = (ref $_[0] ? shift : $Self); - $self->{rerunnable} = shift if defined $_[0]; - return $self->{rerunnable}; -} - -sub too_few_cores { - my $threads = ::calc_threads($Vltmt_threads); - return $threads < $Vltmt_threads; -} - -sub skip_if_too_few_cores { - my $self = (ref $_[0] ? shift : $Self); - if (too_few_cores()) { - $self->skip("Skipping due to too few cores\n"); - } -} - -sub wno_unopthreads_for_few_cores { - if (too_few_cores()) { - warn "Too few cores, using -Wno-UNOPTTHREADS\n"; - return "-Wno-UNOPTTHREADS"; - } - return ""; -} - -sub vm_prefix { - my $self = (ref $_[0] ? shift : $Self); - $self->{vm_prefix} = shift if defined $_[0]; - return $self->{vm_prefix}; -} - -#---------------------------------------------------------------------- - -sub run { - my $self = (ref $_[0] ? shift : $Self); - $self->_run(@_); # See _run() for arguments -} - -sub _run { - my $self = (ref $_[0] ? shift : $Self); - my %param = (tee => 1, - # cmd => [...] - # aslr_off => # Disable address space layour randomization - # check_finished => 0 # Check for All Finished - # entering => # Print entering directory information - # expect => # Regexp to expect in output - # expect_filename => # Filename that should match logfile - # fails => 0 # Command should fail - # logfile => # Filename to write putput to - # verilator_run => # Move gcov data to parallel area - @_); # All legal arguments shown immediately above - - my $command = join(' ', @{$param{cmd}}); - - if ($param{aslr_off}) { - if (my $prefix = aslr_off()) { - $command = "$prefix $command"; - } - } - - $command = "time $command" if $opt_benchmark && $command !~ /^cd /; - - if ($param{verilator_run}) { - # Gcov fails when parallel jobs write same data file, - # so we make sure .gcda output dir is unique across all running jobs. - # We can't just put each one in an unique obj_dir as it uses too much disk. - # Must use absolute path as some execute()s have different PWD - $ENV{GCOV_PREFIX_STRIP} = 99; - $ENV{GCOV_PREFIX} = File::Spec->rel2abs("$FindBin::RealBin/obj_dist/gcov_$self->{running_id}"); - mkdir $ENV{GCOV_PREFIX}; - print "export GCOV_PREFIX_STRIP=99 GCOV_PREFIX=$ENV{GCOV_PREFIX}\n" if $self->{verbose}; - } else { - delete $ENV{GCOV_PREFIX_STRIP}; - delete $ENV{GCOV_PREFIX}; - } - - print "\t$command"; - print " > $param{logfile}" if $param{logfile}; - print "\n"; - - # Execute command redirecting output, keeping order between stderr and stdout. - # Must do low-level IO so GCC interaction works (can't be line-based) - my $status; - { - pipe(PARENTRD, CHILDWR) or die "%Error: Can't Pipe, stopped"; - autoflush PARENTRD 1; - autoflush CHILDWR 1; - my $logfh; - if ($param{logfile}) { - $logfh = IO::File->new(">$param{logfile}") or die "%Error: Can't open $param{logfile}"; - } - my $backup_fg_group = POSIX::tcgetpgrp(0); - my $pid = fork(); - if ($pid) { # Parent - if ($interactive_debugger) { - # Let gdb take care of signals send from keyboard - POSIX::setpgid($pid, 0); # Put child in separate process group - POSIX::tcsetpgrp(0, $pid); # Make this group a foreground one - } - close CHILDWR; - print "driver: Entering directory '", - File::Spec->rel2abs($param{entering}), "'\n" if $param{entering}; - while (1) { - my $buf = ''; - my $got = sysread PARENTRD, $buf, 10000; - last if defined $got && $got == 0; - print $buf if $param{tee}; - print $logfh $buf if $logfh; - } - close PARENTRD; - close $logfh if $logfh; - print "driver: Leaving directory '", - File::Spec->rel2abs($param{entering}), "'\n" if $param{entering}; - } - else { # Child - close PARENTRD; - close $logfh if $logfh; - # Reset signals - $SIG{ALRM} = 'DEFAULT'; - $SIG{CHLD} = 'DEFAULT'; - # Logging - if (!$opt_gdb) { - # Redirecting the stdout of GDB prevents output syntax colors - # and the use of the TUI, so only redirect when not --gdb - open(STDOUT, ">&CHILDWR") or croak "%Error: Can't redirect stdout, stopped"; - open(STDERR, ">&STDOUT") or croak "%Error: Can't dup stdout, stopped"; - autoflush STDOUT 1; - autoflush STDERR 1; - } - system "$command"; - my $status = $?; - if (($status & 127) == 4 # SIGILL - || ($status & 127) == 8 # SIGFPA - || ($status & 127) == 11) { # SIGSEGV - $Self->error("Exec failed with core dump"); - } - exit($? ? 10 : 0); # $?>>8 misses coredumps - } - waitpid($pid, 0); - if ($interactive_debugger) { - # Restore old foreground group - local $SIG{TTOU} = 'IGNORE'; # Ignore SIGTTOU from modyfing terminal settings in bg proccess - POSIX::tcsetpgrp(0, $backup_fg_group); - } - $status = $? || 0; - } - flush STDOUT; - flush STDERR; - - if (!$param{fails} && $status) { - my $firstline = ""; - if (my $fh = IO::File->new("<$param{logfile}")) { - while (defined(my $line = $fh->getline)) { - next if $line =~ /^- /; # Debug message - $firstline = $line; - chomp $firstline; - last; - } - } - $self->error("Exec of $param{cmd}[0] failed: $firstline\n"); - } - if ($param{fails} && $status) { - print "(Exec expected to fail, and did.)\n"; - } - if ($param{fails} && !$status) { - $self->error("Exec of $param{cmd}[0] ok, but expected to fail\n"); - } - return if $self->errors || $self->skips; - - # Read the log file a couple of times to allow for NFS delays - if ($param{check_finished} || $param{expect}) { - for (my $try = $self->tries - 1; $try >= 0; $try--) { - sleep 1 if ($try != $self->tries - 1); - my $moretry = $try != 0; - - my $fh = IO::File->new("<$param{logfile}"); - next if !$fh && $moretry; - local $/; undef $/; - my $wholefile = <$fh>; - $fh->close(); - - # Finished? - if ($param{check_finished} && $wholefile !~ /\*\-\* All Finished \*\-\*/) { - next if $moretry; - $self->error("Missing All Finished\n"); - } - if ($param{expect}) { - # Strip debugging comments - # See also files_identical - $wholefile =~ s/^- [^\n]+\n//mig; - $wholefile =~ s/^- [a-z.0-9]+:\d+:[^\n]+\n//mig; - $wholefile =~ s/^dot [^\n]+\n//mig; - $wholefile =~ s/^==[0-9]+== [^\n]+\n//mig; # valgrind - - # Compare - my $quoted = quotemeta($param{expect}); - my $ok = ($wholefile eq $param{expect} - || _try_regex($wholefile, $param{expect}) == 1 - || $wholefile =~ /$quoted/ms); - if (!$ok) { - #print "**BAD $self->{name} $param{logfile} MT $moretry $try\n"; - next if $moretry; - $self->error("Miscompares in output from $param{cmd}[0]\n"); - $self->error("Might be error in regexp format\n") if $ok < 1; - print "GOT:\n"; - print $wholefile; - print "ENDGOT\n"; - print "EXPECT:\n"; - print $param{expect}; - print "ENDEXPECT\n"; - } - } - last; - } - } - if ($param{expect_filename}) { - files_identical($param{logfile}, $param{expect_filename}, 'logfile'); - } -} - -####################################################################### -# Little utilities - -sub _try_regex { - # Try to eval a regexp - # Returns: - # 1 if $text ~= /$regex/ms - # 0 if no match - # -1 if $regex is invalid, doesn't compile - my $text = shift; - my $regex = shift; - my $result; - { - local $@; - eval { - $result = ($text =~ /$regex/ms); - }; - $result = -1 if $@; - } - return $result; -} - -sub _make_main { - my $self = shift; - my $timing_loop = shift; - - if ($timing_loop && $self->sc) { - $self->error("Cannot use timing loop and SystemC together!\n"); - } - - if ($self->vhdl) { - $self->_read_inputs_vhdl(); - } else { - $self->_read_inputs_v(); - } - - my $filename = $self->{main_filename}; - my $fh = IO::File->new(">$filename") or die "%Error: $! $filename,"; - - print $fh "// Test defines\n"; - print $fh "#define MAIN_TIME_MULTIPLIER " . ($self->{main_time_multiplier} || 1) . "\n"; - - print $fh "#include \n"; - print $fh "#include \n" if $self->{benchmarksim}; - print $fh "#include \n" if $self->{benchmarksim}; - print $fh "#include \n" if $self->{benchmarksim}; - - print $fh "// OS header\n"; - print $fh "#include \"verilatedos.h\"\n"; - - print $fh "// Generated header\n"; - my $vm_prefix = $self->{vm_prefix}; - print $fh "#include \"${vm_prefix}.h\"\n"; - - print $fh "// General headers\n"; - print $fh "#include \"verilated.h\"\n"; - print $fh "#include \"systemc.h\"\n" if $self->sc; - print $fh "#include \"verilated_fst_c.h\"\n" if $self->{trace} && $self->{trace_format} eq 'fst-c'; - print $fh "#include \"verilated_fst_sc.h\"\n" if $self->{trace} && $self->{trace_format} eq 'fst-sc'; - print $fh "#include \"verilated_vcd_c.h\"\n" if $self->{trace} && $self->{trace_format} eq 'vcd-c'; - print $fh "#include \"verilated_vcd_sc.h\"\n" if $self->{trace} && $self->{trace_format} eq 'vcd-sc'; - print $fh "#include \"verilated_save.h\"\n" if $self->{savable}; - - print $fh "std::unique_ptr<${vm_prefix}> topp;\n"; - - if ($self->{savable}) { - $fh->print("\n"); - $fh->print("void save_model(const char* filenamep) {\n"); - $fh->print(" VL_PRINTF(\"Saving model to '%s'\\n\", filenamep);\n"); - $fh->print(" VerilatedSave os;\n"); - $fh->print(" os.open(filenamep);\n"); - $fh->print(" os << *topp;\n"); - $fh->print(" os.close();\n"); - $fh->print("}\n"); - $fh->print("\n"); - $fh->print("void restore_model(const char* filenamep) {\n"); - $fh->print(" VL_PRINTF(\"Restoring model from '%s'\\n\", filenamep);\n"); - $fh->print(" VerilatedRestore os;\n"); - $fh->print(" os.open(filenamep);\n"); - $fh->print(" os >> *topp;\n"); - $fh->print(" os.close();\n"); - $fh->print("}\n"); - } - - #### Main - if ($self->sc) { - print $fh "extern int sc_main(int argc, char** argv);\n"; - print $fh "int sc_main(int argc, char** argv) {\n"; - if ($self->{pins_sc_uint_bool}) { - print $fh " sc_signal> fastclk;\n" if $self->{inputs}{fastclk}; - print $fh " sc_signal> clk;\n" if $self->{inputs}{clk}; - } else { - print $fh " sc_signal fastclk;\n" if $self->{inputs}{fastclk}; - print $fh " sc_signal clk;\n" if $self->{inputs}{clk}; - } - print $fh " sc_set_time_resolution(1, $Self->{sc_time_resolution});\n"; - print $fh " sc_time sim_time($self->{sim_time}, $Self->{sc_time_resolution});\n"; - } else { - print $fh "int main(int argc, char** argv) {\n"; - print $fh " uint64_t sim_time = $self->{sim_time};\n"; - } - - print $fh " const std::unique_ptr contextp{new VerilatedContext};\n"; - print $fh " contextp->threads($self->{context_threads});\n"; - print $fh " contextp->commandArgs(argc, argv);\n"; - print $fh " contextp->debug(" . ($self->{verilated_debug} ? 1 : 0) . ");\n"; - print $fh " srand48(5);\n"; # Ensure determinism - print $fh " contextp->randReset(" . $self->{verilated_randReset} . ");\n" - if defined $self->{verilated_randReset}; - print $fh " topp.reset(new ${vm_prefix}{\"top\"});\n"; - print $fh " contextp->internalsDump()\n;" if $self->{verilated_debug}; - - my $set; - if ($self->sc) { - print $fh " topp->fastclk(fastclk);\n" if $self->{inputs}{fastclk}; - print $fh " topp->clk(clk);\n" if $self->{inputs}{clk}; - $set = ""; - } else { - print $fh " topp->eval();\n"; - $set = "topp->"; - } - - if ($self->{benchmarksim}) { - $fh->print(" std::chrono::time_point starttime;\n"); - $fh->print(" bool warm = false;\n"); - $fh->print(" uint64_t n_evals = 0;\n"); - } - - if ($self->{trace}) { - $fh->print("\n"); - $fh->print("#if VM_TRACE\n"); - $fh->print(" contextp->traceEverOn(true);\n"); - $fh->print(" std::unique_ptr tfp{new VerilatedFstC};\n") if $self->{trace_format} eq 'fst-c'; - $fh->print(" std::unique_ptr tfp{new VerilatedFstSc};\n") if $self->{trace_format} eq 'fst-sc'; - $fh->print(" std::unique_ptr tfp{new VerilatedVcdC};\n") if $self->{trace_format} eq 'vcd-c'; - $fh->print(" std::unique_ptr tfp{new VerilatedVcdSc};\n") if $self->{trace_format} eq 'vcd-sc'; - $fh->print(" sc_core::sc_start(sc_core::SC_ZERO_TIME); // Finish elaboration before trace and open\n") if $self->sc; - $fh->print(" topp->trace(tfp.get(), 99);\n"); - $fh->print(" tfp->open(\"" . $self->trace_filename . "\");\n"); - - if ($self->{trace} && !$self->sc) { - $fh->print(" if (tfp) tfp->dump(contextp->time());\n"); - } - $fh->print("#endif\n"); - } - - if ($self->{savable}) { - $fh->print(" const char* save_time_strp = contextp->commandArgsPlusMatch(\"save_time=\");\n"); - $fh->print(" unsigned int save_time = !save_time_strp[0] ? 0 : std::atoi(save_time_strp + std::strlen(\"+save_time=\"));\n"); - $fh->print(" const char* save_restore_strp = contextp->commandArgsPlusMatch(\"save_restore=\");\n"); - $fh->print(" unsigned int save_restore = !save_restore_strp[0] ? 0 : 1;\n"); - } - - if ($self->{savable}) { - $fh->print(" if (save_restore) {\n"); - $fh->print(" restore_model(\"$self->{obj_dir}/saved.vltsv\");\n"); - $fh->print(" } else {\n"); - } else { - $fh->print(" {\n"); - } - print $fh " ${set}fastclk = false;\n" if $self->{inputs}{fastclk}; - print $fh " ${set}clk = false;\n" if $self->{inputs}{clk}; - if (!$timing_loop) { - _print_advance_time($self, $fh, 10); - } - print $fh " }\n"; - - my $time = $self->sc ? "sc_time_stamp()" : "contextp->time()"; - - print $fh " while ("; - if (!$timing_loop || $self->{inputs}{clk}) { - print $fh "(${time} < sim_time * MAIN_TIME_MULTIPLIER) && "; - } - print $fh "!contextp->gotFinish()) {\n"; - - if ($timing_loop) { - print $fh " topp->eval();\n"; - if ($self->{trace}) { - $fh->print("#if VM_TRACE\n"); - $fh->print(" if (tfp) tfp->dump(contextp->time());\n"); - $fh->print("#endif // VM_TRACE\n"); - } - if ($self->{inputs}{clk}) { - print $fh " uint64_t cycles = contextp->time() / MAIN_TIME_MULTIPLIER;\n"; - print $fh " uint64_t new_time = (cycles + 1) * MAIN_TIME_MULTIPLIER;\n"; - print $fh " if (topp->eventsPending() &&\n"; - print $fh " topp->nextTimeSlot() / MAIN_TIME_MULTIPLIER <= cycles) {\n"; - print $fh " new_time = topp->nextTimeSlot();\n"; - print $fh " } else {\n"; - if ($self->{pins_sc_uint_bool}) { - print $fh " ${set}clk.write(!${set}clk.read());\n"; - } else { - print $fh " ${set}clk = !${set}clk;\n"; - } - print $fh " }\n"; - print $fh " contextp->time(new_time);\n"; - } else { - print $fh " if (!topp->eventsPending()) break;\n"; - print $fh " contextp->time(topp->nextTimeSlot());\n"; - } - } else { - for (my $i = 0; $i < 5; $i++) { - my $action = 0; - if ($self->{inputs}{fastclk}) { - if ($self->{pins_sc_uint_bool}) { - print $fh " ${set}fastclk.write(!${set}fastclk.read());\n"; - } else { - print $fh " ${set}fastclk = !${set}fastclk;\n"; - } - $action = 1; - } - if ($i == 0 && $self->{inputs}{clk}) { - if ($self->{pins_sc_uint_bool}) { - print $fh " ${set}clk.write(!${set}clk.read());\n"; - } else { - print $fh " ${set}clk = !${set}clk;\n"; - } - $action = 1; - } - if ($self->{savable}) { - $fh->print(" if (save_time && ${time} == save_time) {\n"); - $fh->print(" save_model(\"$self->{obj_dir}/saved.vltsv\");\n"); - $fh->print(" printf(\"Exiting after save_model\\n\");\n"); - $fh->print(" topp.reset(nullptr);\n"); - $fh->print(" return 0;\n"); - $fh->print(" }\n"); - } - _print_advance_time($self, $fh, 1, $action); - } - } - if ($self->{benchmarksim}) { - $fh->print(" if (VL_UNLIKELY(!warm)) {\n"); - $fh->print(" starttime = std::chrono::steady_clock::now();\n"); - $fh->print(" warm = true;\n"); - $fh->print(" } else {\n"); - $fh->print(" ++n_evals;\n"); - $fh->print(" }\n"); - } - print $fh " }\n"; - - if ($self->{benchmarksim}) { - $fh->print(" {\n"); - $fh->print(" const std::chrono::duration exec_s = std::chrono::steady_clock::now() - starttime;\n"); - $fh->print(" std::ofstream benchfile(\"" . $self->benchmarksim_filename() . "\", std::ofstream::out | std::ofstream::app);\n"); - $fh->print(" benchfile << std::fixed << std::setprecision(9) << n_evals << \",\" << exec_s.count() << std::endl;\n"); - $fh->print(" benchfile.close();\n"); - $fh->print(" }\n"); - } - - print $fh " if (!contextp->gotFinish()) {\n"; - print $fh ' vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");', "\n"; - print $fh " }\n"; - print $fh " topp->final();\n"; - - if ($self->{coverage}) { - $fh->print("#if VM_COVERAGE\n"); - $fh->print(" contextp->coveragep()->write(\"", $self->{coverage_filename}, "\");\n"); - $fh->print("#endif // VM_COVERAGE\n"); - } - if ($self->{trace}) { - $fh->print("#if VM_TRACE\n"); - $fh->print(" if (tfp) tfp->close();\n"); - $fh->print(" tfp.reset();\n"); - $fh->print("#endif // VM_TRACE\n"); - } - $fh->print("\n"); - - print $fh " topp.reset();\n"; - print $fh " return 0;\n"; - print $fh "}\n"; - $fh->close(); -} - -sub _print_advance_time { - my $self = shift; - my $fh = shift; - my $time = shift; - my $action = shift; - - my $set; - if ($self->sc) { $set = ""; } - else { $set = "topp->"; } - - if ($self->sc) { - print $fh " sc_start(${time} * MAIN_TIME_MULTIPLIER, $Self->{sc_time_resolution});\n"; - } else { - if ($action) { - print $fh " ${set}eval();\n"; - if ($self->{trace} && !$self->sc) { - $fh->print("#if VM_TRACE\n"); - $fh->print(" if (tfp) tfp->dump(contextp->time());\n"); - $fh->print("#endif // VM_TRACE\n"); - } - } - print $fh " contextp->timeInc(${time} * MAIN_TIME_MULTIPLIER);\n"; - } -} - -####################################################################### - -sub _make_top { - my $self = shift; - if ($self->vhdl) { - $self->_make_top_vhdl; - } else { - $self->_make_top_v; - } -} - -sub _make_top_v { - my $self = shift; - - $self->_read_inputs_v(); - - my $fh = IO::File->new(">$self->{top_shell_filename}") - or die "%Error: $! $self->{top_shell_filename},"; - print $fh "module top;\n"; - foreach my $inp (sort (keys %{$self->{inputs}})) { - print $fh " reg ${inp};\n"; - } - # Inst - print $fh " t t (\n"; - my $comma = ""; - foreach my $inp (sort (keys %{$self->{inputs}})) { - print $fh " ${comma}.${inp} (${inp})\n"; - $comma = ","; - } - print $fh " );\n"; - - # Waves - print $fh "\n"; - print $fh "`ifdef WAVES\n"; - print $fh " initial begin\n"; - print $fh " \$display(\"-Tracing Waves to Dumpfile: " . $self->trace_filename . "\");\n"; - print $fh " \$dumpfile(\"" . $self->trace_filename . "\");\n"; - print $fh " \$dumpvars(0, top);\n"; - print $fh " end\n"; - print $fh "`endif\n"; - - # Test - print $fh "\n"; - print $fh " initial begin\n"; - print $fh " fastclk = 0;\n" if $self->{inputs}{fastclk}; - print $fh " clk = 0;\n" if $self->{inputs}{clk}; - print $fh " #10;\n"; - print $fh " fastclk = 1;\n" if $self->{inputs}{fastclk}; - print $fh " clk = 1;\n" if $self->{inputs}{clk}; - print $fh " while (\$time < $self->{sim_time}) begin\n"; - if ($self->{pins_sc_uint_bool}) { - for (my $i = 0; $i < 5; $i++) { - print $fh " #1;\n"; - print $fh " fastclk.write(!fastclk.read());\n" if $self->{inputs}{fastclk}; - print $fh " clk.write(!clk.read());\n" if $i == 4 && $self->{inputs}{clk}; - } - } else { - for (my $i = 0; $i < 5; $i++) { - print $fh " #1;\n"; - print $fh " fastclk = !fastclk;\n" if $self->{inputs}{fastclk}; - print $fh " clk = !clk;\n" if $i == 4 && $self->{inputs}{clk}; - } - } - print $fh " end\n"; - print $fh " end\n"; - - print $fh "endmodule\n"; - $fh->close(); -} - -sub _make_top_vhdl { - my $self = shift; - - $self->_read_inputs_vhdl(); - - my $fh = IO::File->new(">$self->{top_shell_filename}") or die "%Error: $! $self->{top_shell_filename},"; - print $fh "library ieee;\n"; - - my @ports = sort (keys %{$self->{inputs}}); - - print $fh "entity t_ent is\n"; - if ($#ports >= 0) { - print $fh " port(\n"; - my $semi = ""; - foreach my $inp (@ports) { - print $fh " ${semi}${inp} : in std_logic\n"; - $semi = ";"; - } - print $fh " );\n"; - } - print $fh "end;\n"; - - print $fh "entity top is\n"; - print $fh "end;\n"; - - # Inst - print $fh "architecture t_beh of t_ent is\n"; - if ($#ports >= 0) { - foreach my $inp (@ports) { - print $fh " signal ${inp} : std_logic := '0';\n"; - } - } - print $fh " begin\n"; - - print $fh " t : t_ent\n"; - if ($#ports >= 0) { - print $fh " port map(\n"; - my $comma = ""; - foreach my $inp (@ports) { - print $fh "\t${comma}${inp} => ${inp}\n"; - $comma = ","; - } - print $fh " )\n"; - } - print $fh " ;\n"; - - print $fh " end;\n"; - - # Waves TBD - # Test TBD - - print $fh "end;\n"; - $fh->close(); -} - -####################################################################### - -sub _read_inputs_v { - my $self = shift; - my $filename = $self->top_filename; - $filename = "$self->{t_dir}/$filename" if !-r $filename; - my $fh = IO::File->new("<$filename") or die "%Error: $! $filename,"; - my $get_sigs = 1; - my %inputs; - while (defined(my $line = $fh->getline)) { - if ($get_sigs) { - if ($line =~ /^\s*input\s*(\S+)\s*(\/[^\/]+\/|)\s*;/) { - $inputs{$1} = $1; - } - if ($line =~ /^\s*(function|task|endmodule)/) { - $get_sigs = 0; - } - } - if ($line =~ /^\s*module\s+t\b/) { # Ignore any earlier inputs; Module 't' has precedence - %inputs = (); - $get_sigs = 1; - } - } - $self->{inputs}{$_} = $inputs{$_} foreach keys %inputs; - $fh->close(); -} - -####################################################################### - -sub _read_inputs_vhdl { - my $self = shift; - my $filename = $self->top_filename; - $filename = "$self->{t_dir}/$filename" if !-r $filename; - my $fh = IO::File->new("<$filename") or die "%Error: $! $filename,"; - while (defined(my $line = $fh->getline)) { - # Only supports this form right now: - # signal: in ... - # signal: out ... - if ($line =~ /^\s*(\S+)\s*:\s*(in)\b\s*/) { - $self->{inputs}{$1} = $1; - } - if ($line =~ /^\s*(architecture)/) { - last; - } - } - $fh->close(); -} - -####################################################################### -# File utilities - -sub files_identical { - my $self = (ref $_[0] ? shift : $Self); - my $fn1 = shift; - my $fn2 = shift; - my $fn1_is_logfile = shift; - return 1 if $self->errors || $self->skips; - - try: - for (my $try = $self->tries - 1; $try >= 0; $try--) { - sleep 1 if ($try != $self->tries - 1); - my $moretry = $try != 0; - - my $f1 = IO::File->new("<$fn1"); - my $f2 = IO::File->new("<$fn2"); - if (!$f1) { - next try if $moretry; - $self->error("Files_identical file does not exist $fn1\n"); - return 0; - } - if (!$f2 && !$ENV{HARNESS_UPDATE_GOLDEN}) { - next try if $moretry; - $self->error("Files_identical file does not exist $fn2\n"); - return 0; - } - my @l1 = $f1 && $f1->getlines(); - my @l2 = $f2 && $f2->getlines(); - if ($fn1_is_logfile) { - @l1 = grep { - !/^- [^\n]+\n/ - && !/^- [a-z.0-9]+:\d+:[^\n]+\n/ - && !/^-node:/ - && !/^dot [^\n]+\n/ - && !/^In file: .*\/sc_.*:\d+/ - && !/^libgcov.*/ - && !/--- \/tmp\// # t_difftree.pl - && !/\+\+\+ \/tmp\// # t_difftree.pl - && !/^==[0-9]+== ?[^\n]*\n/ # valgrind - } @l1; - @l1 = map { - while (s/(Internal Error: [^\n]+\.(cpp|h)):[0-9]+/$1:#/g) {} - s/^-V\{t[0-9]+,[0-9]+\}/-V{t#,#}/; # --vlt vs --vltmt run differences - $_; - } @l1; - for (my $l = 0; $l <= $#l1; ++$l) { - # Don't put control chars into our source repository - $l1[$l] =~ s/\r/<#013>/mig; - $l1[$l] =~ s/Command Failed[^\n]+/Command Failed/mig; - $l1[$l] =~ s/Version: Verilator[^\n]+/Version: Verilator ###/mig; - $l1[$l] =~ s/CPU Time: +[0-9.]+ seconds[^\n]+/CPU Time: ###/mig; - $l1[$l] =~ s/\?v=[0-9.]+/?v=latest/mig; # warning URL - $l1[$l] =~ s/_h[0-9a-f]{8}_/_h########_/mg; - $l1[$l] =~ s!%Error: /[^: ]+/([^/:])!%Error: .../$1!mg; # avoid absolute paths - $l1[$l] =~ s/ \/[^ ]+\/verilated_std.sv/ verilated_std.sv/mg; - if ($l1[$l] =~ s/Exiting due to.*/Exiting due to/mig) { - splice @l1, $l+1; # Trunc rest - last; - } - } - } - my $nl = $#l1; $nl = $#l2 if ($#l2 > $nl); - for (my $l=0; $l<=$nl; ++$l) { - if (($l1[$l] || "") ne ($l2[$l] || "")) { - next try if $moretry; - $self->error_keep_going("Line " . ($l+1) . " miscompares; $fn1 != $fn2"); - warn("F1: " . ($l1[$l] || "*EOF*\n") - . "F2: " . ($l2[$l] || "*EOF*\n")); - if ($ENV{HARNESS_UPDATE_GOLDEN}) { # Update golden files with current - warn "%Warning: HARNESS_UPDATE_GOLDEN set: cp $fn1 $fn2\n"; - my $fhw = IO::File->new(">$fn2") or $self->error("Files_identical $! $fn2\n"); - $fhw->print(join('', @l1)); - } else { - warn "To update reference: HARNESS_UPDATE_GOLDEN=1 {command} or --golden\n"; - } - return 0; - } - } - return 1; - } -} - -sub files_identical_sorted { - my $self = (ref $_[0] ? shift : $Self); - my $fn1 = shift; - my $fn2 = shift; - my $fn1_is_logfile = shift; - return 1 if $self->errors || $self->skips; - # Set LC_ALL as suggested in the sort manpage to avoid sort order - # changes from the locale. - setenv('LC_ALL', "C"); - my $fn1sort = "$fn1.sort"; - run(cmd => ["sort", "$fn1", "> $fn1sort"]); - return $self->files_identical($fn1sort, $fn2, $fn1_is_logfile); -} - -sub copy_if_golden { - my $self = (ref $_[0] ? shift : $Self); - my $fn1 = shift; - my $fn2 = shift; - if ($ENV{HARNESS_UPDATE_GOLDEN}) { # Update golden files with current - warn "%Warning: HARNESS_UPDATE_GOLDEN set: cp $fn1 $fn2\n"; - eval "use File::Copy;"; - File::Copy::copy($fn1, $fn2); - } -} - -sub vcd_identical { - my $self = (ref $_[0] ? shift : $Self); - my $fn1 = shift; - my $fn2 = shift; - return 0 if $self->errors || $self->skips; - if (!-r $fn1) { $self->error("Vcd_identical file does not exist $fn1\n"); return 0; } - if (!-r $fn2) { $self->error("Vcd_identical file does not exist $fn2\n"); return 0; } - { - # vcddiff to check transitions, if installed - my $cmd = qq{vcddiff --help}; - print "\t$cmd\n" if $::Debug; - my $out = `$cmd`; - if (!$out || $out !~ /Usage:/) { $self->skip("No vcddiff installed\n"); return 1; } - - $cmd = qq{vcddiff "$fn1" "$fn2"}; - print "\t$cmd\n" if $::Debug; - $out = `$cmd`; - if ($? != 0 || $out ne '') { - $cmd = qq{vcddiff "$fn2" "$fn1"}; - print "\t$cmd\n" if $::Debug; - $out = `$cmd`; - if ($? != 0 || $out ne '') { - print $out; - $self->error("VCD miscompares $fn2 $fn1\n"); - $self->copy_if_golden($fn1, $fn2); - return 0; - } - } - } - { - # vcddiff doesn't check module and variable scope, so check that - # Also provides backup if vcddiff not installed - my $h1 = $self->_vcd_read($fn1); - my $h2 = $self->_vcd_read($fn2); - $Data::Dumper::Sortkeys = 1; - my $a = Dumper($h1); - my $b = Dumper($h2); - if ($a ne $b) { - print "$a\n$b\n" if $::Debug; - $self->error("VCD hier miscompares $fn1 $fn2\n"); - $self->copy_if_golden($fn1, $fn2); - return 0; - } - } - return 1; -} - -sub fst2vcd { - my $self = (ref $_[0] ? shift : $Self); - my $fn1 = shift; - my $fn2 = shift; - if (!-r $fn1) { $self->error("File does not exist $fn1\n"); return 0; } - my $cmd = qq{fst2vcd -h}; - print "\t$cmd\n" if $::Debug; - my $out = `$cmd`; - if (!$out || $out !~ /Usage:/) { $self->skip("No fst2vcd installed\n"); return 1; } - - $cmd = qq{fst2vcd -e -f "$fn1" -o "$fn2"}; - print "\t$cmd\n"; # Always print to help debug race cases - $out = `$cmd`; - return 1; -} - -sub fst_identical { - my $self = (ref $_[0] ? shift : $Self); - my $fn1 = shift; - my $fn2 = shift; - return 0 if $self->errors || $self->skips; - my $tmp = $fn1 . ".vcd"; - fst2vcd($fn1, $tmp); - return vcd_identical($tmp, $fn2); -} - -sub _vcd_read { - my $self = (ref $_[0] ? shift : $Self); - my $filename = shift; - my $data = {}; - my $fh = IO::File->new("<$filename"); - if (!$fh) { warn "%Error: $! $filename\n"; return $data; } - my @hier = ($data); - my $lasthier; - while (defined(my $line = $fh->getline)) { - if ($line =~ /\$scope (module|struct|interface)\s+(\S+)/) { - $hier[$#hier]->{$1} ||= {}; - push @hier, $hier[$#hier]->{$1}; - $lasthier = $hier[$#hier]; - } elsif ($line =~ /(\$var \S+\s+\d+\s+)\S+\s+(\S+)/) { - $hier[$#hier]->{$1 . $2} ||= {}; - $lasthier = $hier[$#hier]; - } elsif ($line =~ /(\$attrbegin .* \$end)/) { - if ($lasthier) { $lasthier->{$1} ||= 1; } - } elsif ($line =~ /\$enddefinitions/) { - last; - } - while ($line =~ s/\$upscope//) { - pop @hier; - $lasthier = undef; - } - } - return $data; -} - -our $_Cxx_Version; - -sub cxx_version { - $_Cxx_Version ||= `$ENV{MAKE} -C $ENV{TEST_REGRESS} -f Makefile print-cxx-version`; - return $_Cxx_Version; -} - -our $_Cfg_with_ccache; - -sub cfg_with_ccache { - $_Cfg_with_ccache ||= `grep "OBJCACHE \?= ccache" "$ENV{VERILATOR_ROOT}/include/verilated.mk"` ne ""; - return $_Cfg_with_ccache; -} - -sub tries { - # Number of retries when reading logfiles, generally only need many - # retries when system is busy running a lot of tests - return 2 if !$::Fork->running; - return 7 if (scalar($::Fork->running)) > 1; - return 2; -} - -sub glob_all { - my $self = (ref $_[0] ? shift : $Self); - my $pattern = shift; - - return glob($pattern); -} - -sub glob_one { - my $self = (ref $_[0] ? shift : $Self); - my $pattern = shift; - return if $self->errors || $self->skips; - - my @files = glob($pattern); - my $n = scalar @files; - if ($n == 0) { - $self->error("glob_one: pattern '$pattern' does not match any files\n"); - } elsif ($n != 1) { - my $msg = "glob_one: pattern '$pattern' matches multiple files:\n"; - foreach my $file (@files) { - $msg .= $file . "\n"; - } - $self->error($msg); - } else { - return $files[0]; - } -} - -sub file_grep_not { - my $self = (ref $_[0] ? shift : $Self); - my $filename = shift; - my $regexp = shift; - my $expvalue = shift; - return if $self->errors || $self->skips; - !defined $expvalue or $self->error("file_grep_not: Unexpected 3rd argument: $expvalue"); - - my $contents = $self->file_contents($filename); - return if ($contents eq "_Already_Errored_"); - if ($contents =~ /$regexp/) { - $self->error("File_grep_not: $filename: Regexp found: $regexp\n"); - } -} - -sub file_grep { - my $self = (ref $_[0] ? shift : $Self); - my $filename = shift; - my $regexp = shift; - my $expvalue = shift; - return if $self->errors || $self->skips; - - my $contents = $self->file_contents($filename); - return if ($contents eq "_Already_Errored_"); - if ($contents !~ /$regexp/) { - $self->error("File_grep: $filename: Regexp not found: $regexp\n"); - } elsif (defined($expvalue) && $expvalue ne $1) { - $self->error("File_grep: $filename: Got='$1' Expected='$expvalue' in regexp: $regexp\n"); - } - return @{^CAPTURE}; -} - -sub file_grep_count { - my $self = (ref $_[0] ? shift : $Self); - my $filename = shift; - my $regexp = shift; - my $expcount = shift; - return if $self->errors || $self->skips; - - my $contents = $self->file_contents($filename); - my $count = () = $contents =~ /$regexp/g; - if ($count != $expcount) { - $self->error("file_grep_count: $filename: Got='$count' Expected='$expcount' for regexp: $regexp\n"); - } -} - -sub file_grep_any { - my $self = $Self; - my @filenames = @{$_[0]}; shift; - my $regexp = shift; - my $expvalue = shift; - return if $self->errors || $self->skips; - - foreach my $filename (@filenames) { - my $contents = $self->file_contents($filename); - return if ($contents eq "_Already_Errored_"); - if ($contents =~ /$regexp/) { - if ($expvalue && $expvalue ne $1) { - $self->error("file_grep: $filename: Got='$1' Expected='$expvalue' in regexp: $regexp\n"); - } - return; - } - } - my $msg = "file_grep_any: Regexp '$regexp' not found in any of the following files:\n"; - foreach my $filename (@filenames) { - $msg .= $filename . "\n"; - } - $self->error($msg); -} - -my %_File_Contents_Cache; - -sub file_contents { - my $self = (ref $_[0] ? shift : $Self); - my $filename = shift; - - if (!$_File_Contents_Cache{$filename}) { - my $fh = IO::File->new("<$filename"); - if (!$fh) { - $_File_Contents_Cache{$filename} = "_Already_Errored_"; - $self->error("File_contents file not found: " . $filename . "\n"); - return $_File_Contents_Cache{$filename}; - } - local $/; undef $/; - my $wholefile = <$fh>; - $fh->close(); - $_File_Contents_Cache{$filename} = $wholefile; - } - - return $_File_Contents_Cache{$filename}; -} - -sub write_wholefile { - my $self = (ref $_[0] ? shift : $Self); - my $filename = shift; - my $contents = shift; - my $fh = IO::File->new(">$filename") or die "%Error: $! writing $filename,"; - print $fh $contents; - $fh->close; - delete $_File_Contents_Cache{$filename}; -} - -sub file_sed { - my $self = (ref $_[0] ? shift : $Self); - my $infilename = shift; - my $outfilename = shift; - my $editcb = shift; - my $contents = $self->file_contents($infilename); - { - $_ = $contents; - $editcb->($contents); - $contents = $_; - } - $self->write_wholefile($outfilename, $contents); -} - -sub extract { - my $self = (ref $_[0] ? shift : $Self); - my %param = (#in =>, - #out => - regexp => qr/.*/, - lineno_adjust => -9999, - lines => undef, #'#, #-#', - @_); # All legal arguments shown immediately above - - my $temp_fn = $param{out}; - $temp_fn =~ s!.*/!!g; - $temp_fn = $self->{obj_dir} . "/" . $temp_fn; - - my @out; - my $emph = ""; - my $lineno = 0; - my $lineno_out = 0; - { - my $fh = IO::File->new("<$param{in}") or die "%Error: $! $param{in},"; - while (defined(my $line = $fh->getline)) { - ++$lineno; - if ($line =~ /$param{regexp}/ - && _lineno_match($lineno, $param{lines})) { - if ($line =~ m!t/[A-Za-z0-9_]+.v:(\d+):(\d+):!) { - my $lineno = $1; - my $col = $2; - $lineno += $param{lineno_adjust}; - $lineno = 1 if $lineno < 1; - $line =~ s!t/[A-Za-z0-9_]+.v:(\d+):(\d+):!example.v:${lineno}:${col}!; - } - push @out, " " . $line; - ++$lineno_out; - if ($line =~ /<--/) { - $emph .= "," if $emph; - $emph .= $lineno_out; - } - } - } - } - { - my $fhw = IO::File->new(">$temp_fn") or die "%Error: $! $temp_fn,"; - my $lang = ""; - $lang = " sv" if $param{in} =~ /\.s?vh?$/; - $fhw->print(".. comment: generated by " . $self->{name} . "\n"); - $fhw->print(".. code-block::${lang}\n"); - $fhw->print(" :linenos:\n") if $lang && $#out > 0; - $fhw->print(" :emphasize-lines: ${emph}\n") if $emph; - $fhw->print("\n"); - - foreach my $line (@out) { - $fhw->print($line); - } - } - - $self->files_identical($temp_fn, $param{out}); -} - -sub _lineno_match { - my $lineno = shift; - my $lines = shift; - return 1 if !defined $lines; - foreach my $lc (split /,/, $lines) { - if ($lc =~ /^(\d+)$/) { - return 1 if $1 == $lineno; - } elsif ($lc =~ /^(\d+)-(\d+)$/) { - return 1 if $1 <= $lineno && $2 >= $lineno; - } - } - return 0; -} - -####################################################################### -####################################################################### -####################################################################### -####################################################################### -# Forker class - -package Forker; -use strict; - -# This is a shell that matches Parallel::Forker. -# If that package is not installed, this runs the tests in *series* - -sub new { - my $class = shift; - my $self = {@_}; - bless $self, $class; - return $self; -} - -sub schedule { - my $self = shift; - my %params = (@_); - - $params{run_pre_start}->($self); - if (my $pid = fork()) { # Parent - waitpid($pid, 0); - } else { # Child - $params{run_on_start}->($self); - exit(0); # Don't close anything - } - $params{run_on_finish}->($self); - return $self; -} -sub max_proc { } -sub sig_child { } -sub kill_tree_all { } -sub wait_all { } -sub ready { } -sub running { } -sub is_any_left { return 0; } - -####################################################################### -1; - -package main; -__END__ - -=pod - -=head1 NAME - -driver.pl - Run regression tests - -=head1 SYNOPSIS - - make test # In Verilator directory - ./driver.pl # Or, to run directly - -=head1 DESCRIPTION - -driver.pl invokes Verilator or another simulator on each test file. -See docs/internals.rst in the distribution for more information. - -=head1 DISTRIBUTION - -The latest version is available from L. - -Copyright 2003-2024 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. - -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -=head1 AUTHORS - -Wilson Snyder - -=head1 SEE ALSO - -L - -=cut - -###################################################################### diff --git a/test_regress/driver.py b/test_regress/driver.py new file mode 100755 index 000000000..71d3ed4d0 --- /dev/null +++ b/test_regress/driver.py @@ -0,0 +1,2838 @@ +#!/usr/bin/env python3 +# pylint: disable=C0103,C0114,C0115,C0116,C0209,C0302,R0902,R0903,R0904,R0912,R0913,R0914,R0915,R0916,W0212,W0511,W0603,W1201 +###################################################################### + +import argparse +import collections +import glob +import hashlib +import json +import logging +import multiprocessing +import os +import pickle +import platform +import re +import runpy +import shutil +import signal +import subprocess +import sys +import time + +from functools import lru_cache # Eventually use python 3.9's cache +from pprint import pformat, pprint + +if False: # pylint: disable=using-constant-test + pprint(pformat("Ignored")) # Prevent unused warning + +# Map of all scenarios, with the names used to enable them +All_Scenarios = { + # yapf: disable + 'dist': ['dist'], + 'atsim': ['simulator', 'simulator_st', 'atsim'], + 'ghdl': ['linter', 'simulator', 'simulator_st', 'ghdl'], + 'iv': ['simulator', 'simulator_st', 'iv'], + 'ms': ['linter', 'simulator', 'simulator_st', 'ms'], + 'nc': ['linter', 'simulator', 'simulator_st', 'nc'], + 'vcs': ['linter', 'simulator', 'simulator_st', 'vcs'], + 'xrun': ['linter', 'simulator', 'simulator_st', 'xrun'], + 'xsim': ['linter', 'simulator', 'simulator_st', 'xsim'], + 'vlt': ['linter', 'simulator', 'simulator_st', 'vlt_all', 'vlt'], + 'vltmt': ['simulator', 'vlt_all', 'vltmt'], + # yapf: enable +} + +# Globals +test = None +Arg_Tests = [] +Quitting = False +Vltmt_Threads = 3 + +# So an 'import vltest_bootstrap' inside test files will do nothing +sys.modules['vltest_bootstrap'] = {} + +####################################################################### +####################################################################### +# Decorators + + +class staticproperty(property): + + def __get__(self, owner_self, owner_cls): + return self.fget() + + +####################################################################### +####################################################################### +# VtOs -- OS extensions + + +class VtOs: + + @staticmethod + def delenv(var: str) -> None: + """Delete environment variable, if exists""" + if var in os.environ: + del os.environ[var] + + @staticmethod + def getenv_def(var: str, default=None) -> str: + """Return environment variable, returning default if does not exist""" + if var in os.environ: + return os.environ[var] + return default + + @staticmethod + def mkdir_ok(path: str) -> None: + """Make directory, no error if exists""" + try: + os.mkdir(path) + except FileExistsError: + pass + + @staticmethod + def run_capture(command: str, check=True) -> str: + """Run a command and return results""" + proc = subprocess.run([command], capture_output=True, text=True, shell=True, check=False) + if check and proc.returncode: + sys.exit("%Error: command failed '" + command + "':\n" + proc.stderr + proc.stdout) + return str(proc.stdout) + + @staticmethod + def unlink_ok(filename: str) -> None: + """Unlink a file, no error if fails""" + try: + os.unlink(filename) + except OSError: + pass + + +####################################################################### +####################################################################### +# Capabilities -- What OS/Verilator is built to support + + +class Capabilities: + + # @lru_cache(maxsize=1024) broken with @staticmethod on older pythons we use + _cached_cmake_version = None + _cached_cxx_version = None + _cached_have_coroutines = None + _cached_have_gdb = None + _cached_have_sc = None + _cached_have_solver = None + _cached_make_version = None + + @staticproperty + def cmake_version() -> str: # pylint: disable=no-method-argument + if Capabilities._cached_cmake_version is None: + out = VtOs.run_capture('cmake --version', check=False) + match = re.search(r'cmake version (\d+)\.(\d+)', out, re.IGNORECASE) + if match: + Capabilities._cached_cmake_version = match.group(1) + "." + match.group(2) + else: + Capabilities._cached_cmake_version = 0 + return Capabilities._cached_cmake_version + + @staticproperty + def cxx_version() -> str: # pylint: disable=no-method-argument + if Capabilities._cached_cxx_version is None: + Capabilities._cached_cxx_version = VtOs.run_capture(os.environ['MAKE'] + " -C " + + os.environ['TEST_REGRESS'] + + " -f Makefile print-cxx-version", + check=False) + + return Capabilities._cached_cxx_version + + @staticproperty + def have_coroutines() -> bool: # pylint: disable=no-method-argument + if Capabilities._cached_have_coroutines is None: + Capabilities._cached_have_coroutines = bool( + Capabilities._verilator_get_supported('COROUTINES')) + return Capabilities._cached_have_coroutines + + @staticproperty + def have_gdb() -> bool: # pylint: disable=no-method-argument + if Capabilities._cached_have_gdb is None: + out = VtOs.run_capture('gdb --version 2>/dev/null', check=False) + Capabilities._cached_have_gdb = bool('Copyright' in out) + return Capabilities._cached_have_gdb + + @staticproperty + def have_sc() -> bool: # pylint: disable=no-method-argument + if Capabilities._cached_have_sc is None: + if 'SYSTEMC' in os.environ: + Capabilities._cached_have_sc = True + elif 'SYSTEMC_INCLUDE' in os.environ: + Capabilities._cached_have_sc = True + elif 'CFG_HAVE_SYSTEMC' in os.environ: + Capabilities._cached_have_sc = True + else: + Capabilities._cached_have_sc = bool( + Capabilities._verilator_get_supported('SYSTEMC')) + return Capabilities._cached_have_sc + + @staticproperty + def have_solver() -> bool: # pylint: disable=no-method-argument + if Capabilities._cached_have_solver is None: + out = VtOs.run_capture('(z3 --help || cvc5 --help || cvc4 --help) 2>/dev/null', + check=False) + Capabilities._cached_have_solver = bool('Usage' in out) + return Capabilities._cached_have_solver + + @staticproperty + @lru_cache(maxsize=1024) + def make_version() -> str: # pylint: disable=no-method-argument + if Capabilities._cached_make_version is None: + out = VtOs.run_capture(os.environ['MAKE'] + ' --version', check=False) + match = re.search(r'make ([0-9]+\.[0-9]+)', out, flags=re.IGNORECASE) + if match: + Capabilities._cached_make_version = match.group(1) + else: + Capabilities._cached_make_version = -1 + return Capabilities._cached_make_version + + # Fetch + @staticmethod + def warmup_cache() -> None: + _ignore = Capabilities.have_coroutines + _ignore = Capabilities.have_gdb + _ignore = Capabilities.have_sc + _ignore = Capabilities.have_solver + + # Internals + + @staticmethod + def _verilator_get_supported(feature) -> str: + # Returns if given feature is supported + cmd = "perl " + os.environ['VERILATOR_ROOT'] + "/bin/verilator -get-supported " + feature + out = VtOs.run_capture(cmd, check=False).strip() + if out == '1': + return True + if out in ('', '0'): + return False + sys.exit("%Error: couldn't verilator_get_supported: " + cmd + "\n" + out) + + +####################################################################### +####################################################################### +# Forker class - run multprocess pool of processes +# Similar interface to Perl's Parallel::Forker. + + +class Forker: + + class Job: + + def __init__(self, _id, name, scenario, args, quiet, rerun_skipping, run_pre_start, + run_on_start, run_on_finish): + self.fail_max_skip = False + self.id = _id + self.name = name + self.scenario = scenario + self.args = args + self.quiet = quiet + self.rerun_skipping = rerun_skipping + self.run_pre_start = run_pre_start + self.run_on_start = run_on_start + self.run_on_finish = run_on_finish + self.mprocess = None # Set once call run() + + @property + def pid(self) -> int: + return self.mprocess.pid + + @property + def exitcode(self) -> int: + return self.mprocess.exitcode + + def __init__(self, max_processes): + self._max_processes = max_processes + self._id_next = 0 + self._left = collections.deque() # deque of Job + self._running = {} # key of pid, value of Job + + def is_any_left(self) -> bool: + return self.num_running() > 0 or (len(self._left) > 0 and not Quitting) + + def max_proc(self, n: int) -> None: + self._max_processes = n + + def poll(self) -> bool: + """Run threads, returning if more work to do (if False, sleep)""" + # We don't use SIGCHLD as conflicted with other handler, instead just poll + completed = [] # Need two passes to avoid changing the list we are iterating + nrunning = 0 + more_now = False + for process in self._running.values(): + if process.exitcode is not None: + completed.append(process) + more_now = True + else: + nrunning += 1 + # Start new work now, so running in background while we then collect completions + while len(self._left) and nrunning < self._max_processes and not Quitting: + process = self._left.popleft() + self._run(process) + nrunning += 1 + more_now = True + for process in completed: + self._finished(process) + return more_now + + def running(self) -> list: + return self._running.values() + + def num_running(self) -> int: + return len(self._running) + + def schedule(self, name, scenario, args, quiet, rerun_skipping, run_pre_start, run_on_start, + run_on_finish): + # print("-Forker::schedule: [" + name + "]") + process = Forker.Job(self._id_next, + name=name, + scenario=scenario, + args=args, + quiet=quiet, + rerun_skipping=rerun_skipping, + run_pre_start=run_pre_start, + run_on_start=run_on_start, + run_on_finish=run_on_finish) + self._id_next += 1 + self._left.append(process) + + def kill_tree_all(self) -> None: + # print("-Forker: kill_tree_all") + for process in self._running.values(): + process.mprocess.kill() + + def _run(self, process) -> None: + # print("-Forker: [" + process.name + "] run_pre_start") + process.run_pre_start(process) + + ctx = multiprocessing.get_context('forkserver') + process.mprocess = ctx.Process( # + target=forker.child_start, # pylint: disable=used-before-assignment + args=(process, )) + process.mprocess.start() + + # print("-Forker: [" + process.name + "] RUNNING pid=" + str(process.pid)) + self._running[process.pid] = process + + @staticmethod + def child_start(process) -> None: + # Runs in context of child + # print("-Forker: [" + process.name + "] run_on_start") + process.run_on_start(process) + # print("-Forker: [" + process.name + "] FINISHED run_on_start") + sys.exit(0) + # Don't close anything + + def _finished(self, process) -> None: + del self._running[process.pid] + # print("-Forker: [" + process.name + "] run_on_finish exitcode=" + str(process.exitcode)) + process.run_on_finish(process) + process.mprocess.close() + + +####################################################################### +####################################################################### +# Runner class + + +class Runner: + + def __init__(self, driver_log_filename, quiet, ok_cnt=0, fail1_cnt=0, skip_cnt=0): + self.driver_log_filename = driver_log_filename + self.quiet = quiet + # Counts + self.all_cnt = 0 + self.left_cnt = 0 + self.ok_cnt = ok_cnt + self.fail1_cnt = fail1_cnt + self.fail_cnt = 0 + self.skip_cnt = skip_cnt + self.skip_msgs = [] + self.fail_msgs = [] + self.fail_tests = [] + self._last_proc_finish_time = 0 + self._last_summary_time = 0 + self._last_summary_left = 0 + self._running_ids = {} + self._msg_fail_max_skip = False + Runner.runner = self + + def one_test(self, py_filename: str, scenario: str, rerun_skipping=False) -> None: + self.all_cnt += 1 + self.left_cnt += 1 + forker.schedule(name=py_filename, + scenario=scenario, + args=Args, + quiet=self.quiet, + rerun_skipping=rerun_skipping, + run_pre_start=self._run_pre_start_static, + run_on_start=self._run_on_start_static, + run_on_finish=self._run_on_finish_static) + + @staticmethod + def _run_pre_start_static(process) -> None: + Runner.runner._run_pre_start(process) # pylint: disable=protected-access + + def _run_pre_start(self, process) -> None: + # Running in context of parent, before run_on_start + # Make an identifier that is unique across all current running jobs + i = 1 + while i in self._running_ids: + i += 1 + process.running_id = i + self._running_ids[process.running_id] = 1 + if Args.fail_max and Args.fail_max <= self.fail_cnt: + if not self._msg_fail_max_skip: + self._msg_fail_max_skip = True + print("== Too many test failures; exceeded --fail-max\n", file=sys.stderr) + process.fail_max_skip = 1 + + @staticmethod + def _run_on_start_static(process) -> None: + # Running in context of child, so can't pass data to parent directly + if process.quiet: + sys.stdout = open(os.devnull, 'w') # pylint: disable=R1732,unspecified-encoding + sys.stderr = open(os.devnull, 'w') # pylint: disable=R1732,unspecified-encoding + + print("=" * 70) + global Args + Args = process.args + + global test + test = VlTest(py_filename=process.name, + scenario=process.scenario, + running_id=process.running_id) + test.oprint("=" * 50) + test._prep() + if process.rerun_skipping: + print(" ---------- Earlier logfiles below; test was rerunnable = False\n") + os.system("cat " + test.obj_dir + "/*.log") + print(" ---------- Earlier logfiles above; test was rerunnable = False\n") + elif process.fail_max_skip: + test.skip("Too many test failures; exceeded --fail-max") + else: + VtOs.unlink_ok(test._status_filename) + test._read() + # Don't put anything other than _exit after _read, + # as may call _exit via another path + test._exit() + + @staticmethod + def _run_on_finish_static(process) -> None: + Runner.runner._run_on_finish(process) # pylint: disable=protected-access + + def _run_on_finish(self, process) -> None: + # Running in context of parent + global test + test = VlTest(py_filename=process.name, + scenario=process.scenario, + running_id=process.running_id) + test._quit = Quitting + test._read_status() + if test.ok: + self.ok_cnt += 1 + elif test._quit: + pass + elif test._scenario_off and not test.errors: + pass + elif test._skips and not test.errors and not test.errors_keep_going: + self.skip_msgs.append("\t#" + test.soprint("-Skip: " + test._skips)) + self.skip_cnt += 1 + else: + error_msg = test.errors if test.errors else test.errors_keep_going + test.oprint("FAILED: " + error_msg) + makecmd = VtOs.getenv_def('VERILATOR_MAKE', os.environ['MAKE']) + " &&" + upperdir = 'test_regress/' if re.search(r'test_regress', os.getcwd()) else '' + self.fail_msgs.append("\t#" + test.soprint("%Error: " + error_msg) + "\t\t" + makecmd + + " " + upperdir + test.py_filename + ' ' + + ' '.join(self._manual_args()) + " --" + test.scenario + "\n") + self.fail_tests.append(test) + self.fail_cnt += 1 + self.report(self.driver_log_filename) + other = "" + for proc in forker.running(): + other += " " + proc.name + if other != "" and not Args.quiet: + test.oprint("Simultaneous running tests:" + other) + if Args.stop: + sys.exit("%Error: --stop and errors found\n") + + self.left_cnt -= 1 + self._last_proc_finish_time = time.time() + if process.running_id: + del self._running_ids[process.running_id] + + def wait_and_report(self) -> None: + self.print_summary(force=True) + # Wait for all children to finish + while forker.is_any_left(): + more_now = forker.poll() + if not Args.interactive_debugger: + self.print_summary(force=False) + if not more_now: + time.sleep(0.1) + self.report(None) + self.report(self.driver_log_filename) + + def report(self, filename: str) -> None: + if filename: + with open(filename, "w", encoding="utf8") as fh: + self._report_fh(fh) + else: + self._report_fh(sys.stdout) + + def _report_fh(self, fh) -> None: + fh.write("\n") + fh.write('=' * 70 + "\n") + for f in sorted(self.fail_msgs): + fh.write(f.strip() + "\n") + for f in sorted(self.skip_msgs): + fh.write(f.strip() + "\n") + if self.fail_cnt: + sumtxt = 'FAILED' + elif self.skip_cnt: + sumtxt = 'PASSED w/SKIPS' + else: + sumtxt = 'PASSED' + fh.write("==TESTS DONE, " + sumtxt + ": " + self.sprint_summary() + "\n") + + def print_summary(self, force=False): + change = self._last_summary_left != self.left_cnt + if (force or ((time.time() - self._last_summary_time) >= 15) + or (not self.quiet and change)): + self._last_summary_left = self.left_cnt + self._last_summary_time = time.time() + print("==SUMMARY: " + self.sprint_summary(), file=sys.stderr) + + if (self._last_proc_finish_time != 0 + and ((time.time() - self._last_proc_finish_time) > 15)): + self._last_proc_finish_time = time.time() + other = "" + for proc in forker.running(): + other += " " + proc.name + print("==STILL RUNNING:" + other, file=sys.stderr) + + @staticmethod + def _py_filename_adjust(py_filename: str, + tdir_def: str) -> list: # Return (py_filename, t_dir) + for tdir in Args.test_dirs: # pylint: disable=redefined-outer-name + # t_dir used both absolutely and under obj_dir + try_py_filename = tdir + "/" + os.path.basename(py_filename) + if os.path.exists(try_py_filename): + # Note most tests require error messages of the form t/x.v + # Therefore py_filename must be t/ for local tests + # t_dir must be absolute - used under t or under obj_dir + tdir_abs = os.path.abspath(tdir) + return (try_py_filename, tdir_abs) + return (py_filename, os.path.abspath(tdir_def)) + + def sprint_summary(self) -> str: + delta = time.time() - Start # pylint: disable=used-before-assignment + # Fudge of 120% works out about right so ETA correctly predicts completion time + eta = 1.2 * ((self.all_cnt * (delta / ((self.all_cnt - self.left_cnt) + 0.001))) - delta) + if delta < 10: + eta = 0 + out = "" + if self.left_cnt: + out += "Left " + str(self.left_cnt) + " " + out += "Passed " + str(self.ok_cnt) + # Ordered below most severe to least severe + out += " Failed " + str(self.fail_cnt) + if self.fail1_cnt: + out += " Failed-First " + str(self.fail1_cnt) + if self.skip_cnt: + out += " Skipped " + str(self.skip_cnt) + if forker.num_running(): + out += " Running " + str(forker.num_running()) + if self.left_cnt > 10 and eta > 10: + out += " Eta %d:%02d" % (int(eta / 60), eta % 60) + out += " Time %d:%02d" % (int(delta / 60), delta % 60) + return out + + def _manual_args(self) -> str: + # Return command line with scenarios stripped + out = [] + for oarg in Args.orig_argv_sw: + showarg = True + for val in All_Scenarios.values(): + for allscarg in val: + if oarg == "--" + allscarg: + showarg = False + # Also strip certain flags that per-test debugging won't want + if showarg and oarg != '--rerun' and oarg != '--quiet': + out.append(oarg) + return out + + +####################################################################### +####################################################################### +# Test exceptions + + +class VtSkipException(Exception): + pass + + +class VtErrorException(Exception): + pass + + +####################################################################### +####################################################################### +# Test class + + +class VlTest: + + _file_contents_cache = {} + + # @lru_cache(maxsize=1024) broken with @staticmethod on older pythons we use + _cached_aslr_off = None + _cached_cfg_with_ccache = None + + def __init__(self, py_filename, scenario, running_id): + self.py_filename = py_filename # Name of .py file to get setup from + self.running_id = running_id + self.scenario = scenario + + self._have_solver_called = False + self._inputs = {} + self._ok = False + self._quit = False + self._scenario_off = False # scenarios() didn't match running scenario + self._skips = None + + match = re.match(r'^(.*/)?([^/]*)\.py', self.py_filename) + self.name = match.group(2) # Name of this test + + self.benchmark = Args.benchmark + self.benchmarksim = False + self.clean_command = None + self.context_threads = 0 # Number of threads to allocate in the context + self.errors = None + self.errors_keep_going = None + self.main_time_multiplier = 1 + self.make_main = 1 # Make __main.cpp + self.make_pli = 0 # need to compile pli + self.make_top_shell = 1 # Make a default __top.v file + self.rerunnable = True # Rerun if fails + self.sc_time_resolution = "SC_PS" # Keep - PS is SystemC default + self.sim_time = 1100 # simulation time units for main wrapper + self.threads = -1 # --threads (negative means auto based on scenario) + self.verbose = Args.verbose + self.verilated_randReset = "" + self.vm_prefix = "V" + self.name + + # Make e.g. self.vlt, self.vltmt etc + self.vlt = False # Set below also + self.vltmt = False # Set below also + self.xsim = False # Set below also + for ascenario in All_Scenarios: + self.__dict__[ascenario] = False + self.__dict__[scenario] = True + self.vlt_all = self.vlt or self.vltmt # Any Verilator scenario + + (self.py_filename, self.t_dir) = Runner._py_filename_adjust(self.py_filename, ".") + for tdir in Args.test_dirs: # pylint: disable=redefined-outer-name + # t_dir used both absolutely and under obj_dir + self.t_dir = None + if os.path.exists(tdir + "/" + self.name + ".py"): + # Note most tests require error messages of the form t/x.v + # Therefore py_filename must be t/ for local tests + self.py_filename = os.path.relpath(tdir + "/" + self.name + ".py") + # t_dir must be absolute - used under t or under obj_dir + self.t_dir = os.path.abspath(tdir) + break + + if not self.t_dir: + sys.exit("%Error: Can't locate dir for " + self.name) + + scen_dir = os.path.relpath(self.t_dir + "/../obj_" + self.scenario) + # Simplify filenames on local runs + scen_dir = re.sub(r'^t/\.\./', '', scen_dir) + # Not mkpath so error if try to build somewhere odd + VtOs.mkdir_ok(scen_dir) + self.obj_dir = scen_dir + "/" + self.name + + define_opt = self._define_opt_calc() + + # All compilers + self.v_flags = [] + if self.xsim: + self.v_flags += ["-f input.xsim.vc"] + elif os.path.exists('input.vc'): + self.v_flags += ["-f input.vc"] + if not re.search(r'/test_regress', self.t_dir): # Don't include standard dir, only site's + self.v_flags += ["+incdir+" + self.t_dir + " -y " + self.t_dir] + self.v_flags += [define_opt + "TEST_OBJ_DIR=" + self.obj_dir] + if Args.verbose: + self.v_flags += [define_opt + "TEST_VERBOSE=1"] + if Args.benchmark: + self.v_flags += [define_opt + "TEST_BENCHMARK=Args.benchmark"] + if Args.trace: + self.v_flags += [define_opt + "WAVES=1"] + + self.v_flags2 = [] # Overridden in some sim files + self.v_other_filenames = [] + self.all_run_flags = [] + + self.pli_flags = [ + "-I" + os.environ['VERILATOR_ROOT'] + "/include/vltstd", "-fPIC", "-shared" + ] + if platform.system() == 'Darwin': + self.pli_flags += ["-Wl,-undefined,dynamic_lookup"] + else: + self.pli_flags += ["-rdynamic"] + if Args.verbose: + self.pli_flags += ["-DTEST_VERBOSE=1"] + self.pli_flags += ["-o", self.obj_dir + "/libvpi.so"] + + self.tool_c_flags = [] + # ATSIM + self.atsim_define = 'ATSIM' + self.atsim_flags = [ + "-c", "+sv", "+define+ATSIM", ("+sv_dir+" + self.obj_dir + "/.athdl_compile") + ] + self.atsim_flags2 = [] # Overridden in some sim files + self.atsim_run_flags = [] + # GHDL + self.ghdl_define = 'GHDL' + self.ghdl_work_dir = self.obj_dir + "/ghdl_compile" + self.ghdl_flags = [("-v" if Args.debug else ""), + ("--workdir=" + self.obj_dir + "/ghdl_compile")] + self.ghdl_flags2 = [] # Overridden in some sim files + self.ghdl_run_flags = [] + # IV + self.iv_define = 'IVERILOG' + self.iv_flags = ["+define+IVERILOG", "-g2012", ("-o" + self.obj_dir + "/simiv")] + self.iv_flags2 = [] # Overridden in some sim files + self.iv_run_flags = [] + # VCS + self.vcs_define = 'VCS' + self.vcs_flags = [ + "+vcs+lic+wait", "+cli", "-debug_access", "+define+VCS+1", "-q", "-sverilog", + "-CFLAGS", "'-DVCS'" + ] + self.vcs_flags2 = [] # Overridden in some sim files + self.vcs_run_flags = ["+vcs+lic_wait"] + # NC + self.nc_define = 'NC' + self.nc_flags = [ + "+licqueue", "+nowarn+LIBNOU", "+define+NC=1", "-q", "+assert", "+sv", "-c", + ("+access+r" if Args.trace else "") + ] + self.nc_flags2 = [] # Overridden in some sim files + self.nc_run_flags = ["+licqueue", "-q", "+assert", "+sv", "-R"] + # ModelSim + self.ms_define = 'MS' + self.ms_flags = [ + "-sv", "-work", (self.obj_dir + "/work"), "+define+MS=1", "-ccflags", '\"-DMS=1\"' + ] + self.ms_flags2 = [] # Overridden in some sim files + self.ms_run_flags = ["-lib", self.obj_dir + "/work", "-c", "-do", "'run -all;quit'"] + # XSim + self.xsim_define = 'XSIM' + self.xsim_flags = [ + "--nolog", "--sv", "--define", "XSIM", "--work", + (self.name + "=" + self.obj_dir + "/xsim") + ] + self.xsim_flags2 = [] # Overridden in some sim files + self.xsim_run_flags = [ + "--nolog", "--runall", "--lib", (self.name + "=" + self.obj_dir + "/xsim"), + (" --debug all" if Args.trace else "") + ] + self.xsim_run_flags2 = [] # Overridden in some sim files + # Xcelium (xrun) + self.xrun = 0 + self.xrun_define = 'XRUN' + self.xrun_flags = [] # Doesn't really have a compile step + self.xrun_flags2 = [] # Overridden in some sim files + self.xrun_run_flags = [ + "-64", "-access", "+rwc", "-newsv", "-sv", "-xmlibdirname", self.obj_dir + "/work", + "-l", self.obj_dir + "/history", "-quiet", "-plinowarn" + ] + # Verilator + self.verilator_define = 'VERILATOR' + self.verilator_flags = [ + "-cc", + "-Mdir", + self.obj_dir, + "--fdedup", # As currently disabled unless -O3 + "--debug-check", + "--comp-limit-members", + "10" + ] + self.verilator_flags2 = [] + self.verilator_flags3 = ["--clk clk"] + self.verilator_make_gmake = True + self.verilator_make_cmake = False + self.verilated_debug = Args.verilated_debug + + self._status_filename = self.obj_dir + "/V" + self.name + ".status" + self.coverage_filename = self.obj_dir + "/coverage.dat" + self.golden_filename = re.sub(r'\.py$', '.out', self.py_filename) + self.main_filename = self.obj_dir + "/" + self.vm_prefix + "__main.cpp" + self.compile_log_filename = self.obj_dir + "/vlt_compile.log" + self.run_log_filename = self.obj_dir + "/vlt_sim.log" + self.stats = self.obj_dir + "/V" + self.name + "__stats.txt" + self.top_filename = re.sub(r'\.py$', '', self.py_filename) + '.' + self.v_suffix + self.pli_filename = re.sub(r'\.py$', '', self.py_filename) + '.cpp' + self.top_shell_filename = self.obj_dir + "/" + self.vm_prefix + "__top.v" + + def _define_opt_calc(self) -> str: + return "--define " if self.xsim else "+define+" + + def init_benchmarksim(self) -> None: + # Simulations with benchmarksim enabled append to the same file between runs. + # Test files must ensure a clean benchmark data file before executing tests. + filename = self.benchmarksim_filename + with open(filename, 'w', encoding="utf8") as fh: + fh.write("# Verilator simulation benchmark data\n") + fh.write("# Test name: " + self.name + "\n") + fh.write("# Top file: " + self.top_filename + "\n") + fh.write("evals, time[s]\n") + + def soprint(self, message: str) -> str: + message = message.rstrip() + "\n" + message = self.scenario + "/" + self.name + ": " + message + return message + + def oprint(self, message: str) -> None: + message = message.rstrip() + "\n" + print(self.soprint(message), end="") + + def error(self, message: str) -> None: + """Called from tests as: error("Reason message") + Newline is optional. Only first line is passed to summaries + Throws a VtErrorException, so rest of testing is not executed""" + message = message.rstrip() + "\n" + print("%Warning: " + self.scenario + "/" + self.name + ": " + message, + file=sys.stderr, + end="") + if not self.errors: + message = re.sub(r'\n.*', '\n', message) + self.errors = message + raise VtErrorException + + def error_keep_going(self, message: str) -> None: + """Called from tests as: error_keep_going("Reason message") + Newline is optional. Only first line is passed to summaries""" + if self._quit: + return + message = message.rstrip() + "\n" + print("%Warning: " + self.scenario + "/" + self.name + ": " + message, + file=sys.stderr, + end="") + if not self.errors_keep_going: + message = re.sub(r'\n.*', '\n', message) + self.errors_keep_going = message + + def skip(self, message: str) -> None: + """Called from tests as: skip("Reason message"[, ...]) + Newline is optional. Only first line is passed to summaries. + Throws a VtSkipException, so rest of testing is not executed""" + message = message.rstrip() + "\n" + print("-Skip: " + self.scenario + "/" + self.name + ": " + message, + file=sys.stderr, + end="") + if not self._skips: + message = re.sub(r'\n.*', '\n', message) + self._skips = message + raise VtSkipException + + def scenarios(self, *scenario_list) -> None: + """Called from tests as: scenarios() to + specify which scenarios this test runs under. Where ... is + one cases listed in All_Scenarios. + All scenarios must be on one line; this is parsed outside Python.""" + enabled_scenarios = {} + for param in scenario_list: + hit = False + for allsc, allscs in All_Scenarios.items(): + for allscarg in allscs: + if param == allscarg: + hit = True + enabled_scenarios[allsc] = True + if not hit: + self.error("scenarios(...) has unknown scenario '" + param + "'") + + if not enabled_scenarios.get(self.scenario, None): + self._scenario_off = True + self.skip("scenario '" + self.scenario + "' not enabled for test") + # self._exit() implied by skip's exception + + @staticmethod + def _prefilter_scenario(py_filename: str, scenario: str) -> bool: + """Read a python file to see if scenarios require it to be run. + Much faster than parsing the file for a runtime check.""" + (py_filename, _) = Runner._py_filename_adjust(py_filename, ".") + with open(py_filename, 'r', encoding="utf-8") as fh: + for line in fh: + m = re.search(r'^\s*test.scenarios\((.*?)\)', line) + if m: + for param in re.findall(r"""["']([^,]*)["']""", m.group(1)): + for allscarg in All_Scenarios[scenario]: + if param == allscarg: + return True + return False + + def _prep(self) -> None: + VtOs.mkdir_ok(self.obj_dir) # Ok if already exists + + def _read(self) -> None: + if not os.path.exists(self.py_filename): + self.error("Can't open " + self.py_filename) + return + global test + test = self + sys.path.append(self.t_dir) # To find vltest_bootstrap.py + # print("_read/exec py_filename=" + self.py_filename) + # print("_read/exec dir=", ' '.join(dir())) + # print("_read/exec vars=", ' '.join(vars().keys())) + # print("_read/exec globals=", ' '.join(globals().keys())) + # print("_read/exec locals=", ' '.join(locals().keys())) + try: + runpy.run_path(self.py_filename, globals()) + except (VtErrorException, VtSkipException): + pass + + def _exit(self): + if self.ok: + self.oprint("Self PASSED") + elif self._skips and not self.errors: + self.oprint("-Skip: " + self._skips) + else: + # If no worse errors, promote errors_keep_going to normal errors + if not self.errors and self.errors_keep_going: + self.errors = self.errors_keep_going + if not self.errors: + self.error("Missing ok") + self.oprint("%Error: " + self.errors) + self._write_status() + sys.exit(0) + + def _write_status(self) -> None: + with open(self._status_filename, "wb") as fh: + pass_to_driver = { + '_ok': self._ok, + '_scenario_off': self._scenario_off, + '_skips': self._skips, + 'errors': self.errors, + } + pickle.dump(pass_to_driver, fh) + + def _read_status(self) -> None: + filename = self._status_filename + if not os.path.isfile(filename): + self.error_keep_going("Child test did not return status (test has Python error?): " + + self.py_filename) + return + with open(filename, "rb") as fh: + dic = pickle.load(fh) + for k in dic.keys(): + # print("_read_status " + filename + ".test['" + k + "]=" + pformat(dic[k])) + setattr(self, k, dic[k]) + + #---------------------------------------------------------------------- + # Methods invoked by tests + + def clean(self) -> None: + """Called on a rerun to cleanup files.""" + if self.clean_command: + os.system(self.clean_command) + # Prevents false-failures when switching compilers + # Remove old results to force hard rebuild + os.system('/bin/rm -rf ' + self.obj_dir + '__fail1') + os.system('/bin/mv ' + self.obj_dir + ' ' + self.obj_dir + '__fail1') + + def clean_objs(self) -> None: + os.system("/bin/rm -rf " + ' '.join(glob.glob(self.obj_dir + "/*"))) + + def _checkflags(self, param): + checkflags = ( + ' ' + ' '.join(param['v_flags']) + # + ' ' + ' '.join(param['v_flags2']) + # + ' ' + ' '.join(param['verilator_flags']) + # + ' ' + ' '.join(param['verilator_flags2']) + # + ' ' + ' '.join(param['verilator_flags3']) + ' ') + return checkflags + + def compile_vlt_cmd(self, **kwargs) -> list: + """Return default command list to run verilator""" + param = {'stdout_filename': None} + param.update(vars(self)) + param.update(kwargs) + vlt_cmd = [ + "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + *self._compile_vlt_flags(**param), param['top_filename'], *param['v_other_filenames'] + ] + if param['stdout_filename']: + vlt_cmd += ["> " + param['stdout_filename']] + return vlt_cmd + + def _compile_vlt_flags(self, **param) -> list: + checkflags = self._checkflags(param) + d_verilator_flags = ' ' + ' '.join(self.driver_verilator_flags) + ' ' + + self.pins_sc_uint_bool = ( # pylint: disable=attribute-defined-outside-init + bool( + re.search(r'-pins-sc-uint-bool\b', checkflags) + or re.search(r'-pins-sc-uint-bool\b', d_verilator_flags))) + self.savable = ( # pylint: disable=attribute-defined-outside-init + bool(re.search(r'-savable\b', checkflags))) + self.coverage = ( # pylint: disable=attribute-defined-outside-init + bool(re.search(r'-coverage\b', checkflags))) + self.sanitize = param.get('sanitize', None) # pylint: disable=attribute-defined-outside-init + self.sc = ( # pylint: disable=attribute-defined-outside-init + bool(re.search(r'-sc\b', checkflags))) + self.timing = ( # pylint: disable=attribute-defined-outside-init + bool(re.search(r'( -?-timing\b| -?-binary\b)', checkflags))) + self.trace = ( # pylint: disable=attribute-defined-outside-init + bool(Args.trace or re.search(r'-trace\b|-trace-fst\b', checkflags))) + + if re.search(r'-trace-fst', checkflags): + if self.sc: + self.trace_format = 'fst-sc' # pylint: disable=attribute-defined-outside-init + else: + self.trace_format = 'fst-c' # pylint: disable=attribute-defined-outside-init + elif self.sc: + self.trace_format = 'vcd-sc' # pylint: disable=attribute-defined-outside-init + else: + self.trace_format = 'vcd-c' # pylint: disable=attribute-defined-outside-init + + if param.get('benchmarksim', None): + self.benchmarksim = True # pylint: disable=attribute-defined-outside-init + + verilator_flags = [*param.get('verilator_flags', "")] + if Args.gdb: + verilator_flags += ["--gdb"] + if Args.gdbbt: + verilator_flags += ["--gdbbt"] + if Args.rr: + verilator_flags += ["--rr"] + if Args.trace: + verilator_flags += ["--trace"] + if Args.gdbsim or Args.rrsim: + verilator_flags += ["-CFLAGS -ggdb -LDFLAGS -ggdb"] + verilator_flags += ["--x-assign unique"] # More likely to be buggy + + if param['vltmt']: + verilator_flags += ["--debug-partition"] + if param['threads'] >= 0: + verilator_flags += ["--threads", str(param['threads'])] + if param['vltmt'] and re.search(r'-trace-fst ', checkflags): + verilator_flags += ["--trace-threads 2"] + if self.sanitize: + verilator_flags += [ + "-CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined" + ] + if param['verilator_make_cmake']: + verilator_flags += ["--make cmake"] + if param['verilator_make_gmake']: + verilator_flags += ["--make gmake"] + if param['make_main'] and param['verilator_make_gmake']: + verilator_flags += ["--exe"] + if param['make_main'] and param['verilator_make_gmake']: + verilator_flags += ["../" + self.main_filename] + + cmdargs = [ + "--prefix", + param['vm_prefix'], + *verilator_flags, + *param['verilator_flags2'], + *param['verilator_flags3'], + *param['v_flags'], + *param['v_flags2'], + # Flags from driver cmdline override default flags and + # flags from the test itself + *self.driver_verilator_flags, + ] + return cmdargs + + def lint(self, **kwargs) -> None: + """Run a linter. Arguments similar to run(); default arguments are from self""" + param = {} + param.update(vars(self)) + param.update({ # Lint-specific default overrides + 'make_main': False, + 'make_top_shell': False, + 'verilator_flags2': ["--lint-only"], + 'verilator_make_gmake': False + }) + param.update(kwargs) + self.compile(**param) + + def compile(self, **kwargs) -> None: + """Run simulation compiler. Arguments similar to run(); default arguments are from self""" + param = { + 'expect_filename': None, + 'fails': False, + 'make_flags': [], + 'tee': True, + 'timing_loop': False, + } + param.update(vars(self)) + param.update(kwargs) + + if self.verbose: + self.oprint("Compile") + + if param['vlt'] and param['threads'] > 1: + self.error("'threads =' argument must be <= 1 for vlt scenario") + # Compute automatic parameter values + checkflags = self._checkflags(param) + if re.search(r'(^|\s)-?-threads\s', checkflags): + self.error("Specify threads via 'threads=' argument, not as a command line option") + + if param['threads'] < 0 and param['vltmt']: + param['threads'] = calc_threads(Vltmt_Threads) + if not param['context_threads']: + param['context_threads'] = param['threads'] if (param['threads'] >= 1) else 1 + if re.search(r'( -?-main\b| -?-binary\b)', checkflags): + param['make_main'] = False + if re.search(r'( -?-build\b| -?-binary\b)', checkflags): + param['verilator_make_cmake'] = False + param['verilator_make_gmake'] = False + self.threads = param['threads'] + self.context_threads = param['context_threads'] + + self.compile_vlt_cmd(**param) + + if not re.search(r'TEST_DUMPFILE', ' '.join(self.v_flags)): + self.v_flags += [self._define_opt_calc() + "TEST_DUMPFILE=" + self.trace_filename] + + if not param['make_top_shell']: + self.top_shell_filename = "" + else: + self.top_shell_filename = self.obj_dir + "/" + self.vm_prefix + "__top." + self.v_suffix + param['top_shell_filename'] = self.top_shell_filename + + if param['atsim']: + tool_define = param['atsim_define'] + self._make_top(param['make_top_shell']) + self.run(logfile=self.obj_dir + "/atsim_compile.log", + fails=param['fails'], + cmd=[ + VtOs.getenv_def('VERILATOR_ATSIM', "atsim"), + ' '.join(param['atsim_flags']), + ' '.join(param['atsim_flags2']), + ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), + param['top_filename'], + param['top_shell_filename'], + ' '.join(param['v_other_filenames']), + ]) + elif param['ghdl']: + tool_define = param['ghdl_define'] + VtOs.mkdir_ok(self.ghdl_work_dir) + self._make_top(param['make_top_shell']) + tool_exe = VtOs.getenv_def('VERILATOR_GHDL', "ghdl") + self.run( + logfile=self.obj_dir + "/ghdl_compile.log", + fails=param['fails'], + cmd=[ + tool_exe, + # Add -c here, as having -c twice freaks it out + ("" if re.search(r' -c\b', tool_exe) else "-c"), + ' '.join(param['ghdl_flags']), + ' '.join(param['ghdl_flags2']), + #' '.join(param['v_flags']), # Not supported + #' '.join(param['v_flags2']), # Not supported + param['top_filename'], + param['top_shell_filename'], + ' '.join(param['v_other_filenames']), + "-e t", + ]) + elif param['vcs']: + tool_define = param['vcs_define'] + self._make_top(param['make_top_shell']) + self.run(logfile=self.obj_dir + "/vcs_compile.log", + fails=param['fails'], + cmd=[ + VtOs.getenv_def('VERILATOR_VCS', "vcs"), + ' '.join(param['vcs_flags']), + ' '.join(param['vcs_flags2']), + ("-CFLAGS -DTEST_VERBOSE=1" if Args.verbose else ""), + ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), + param['top_filename'], + param['top_shell_filename'], + ' '.join(param['v_other_filenames']), + ]) + elif param['nc']: + tool_define = param['nc_define'] + self._make_top(param['make_top_shell']) + self.run(logfile=self.obj_dir + "/nc_compile.log", + fails=param['fails'], + cmd=[ + VtOs.getenv_def('VERILATOR_NCVERILOG', "ncverilog"), + ' '.join(param['nc_flags']), + ' '.join(param['nc_flags2']), + ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), + param['top_filename'], + param['top_shell_filename'], + ' '.join(param['v_other_filenames']), + ]) + elif param['ms']: + tool_define = param['ms_define'] + self._make_top(param['make_top_shell']) + self.run(logfile=self.obj_dir + "/ms_compile.log", + fails=param['fails'], + cmd=[ + ("vlib " + self.obj_dir + "/work && "), + VtOs.getenv_def('VERILATOR_MODELSIM', "vlog"), + ' '.join(param['ms_flags']), + ' '.join(param['ms_flags2']), + ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), + param['top_filename'], + param['top_shell_filename'], + ]) + elif param['iv']: + tool_define = param['iv_define'] + self._make_top(param['make_top_shell']) + cmd = (VtOs.getenv_def('VERILATOR_IVERILOG', "iverilog"), ' '.join(param['iv_flags']), + ' '.join(param['iv_flags2']), ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), param['top_filename'], param['top_shell_filename'], + ' '.join(param['v_other_filenames'])) + cmd = list(map(lambda str: re.sub(r'\+define\+', '-D ', str), cmd)) + self.run(logfile=self.obj_dir + "/iv_compile.log", fails=param['fails'], cmd=cmd) + elif param['xrun']: + tool_define = param['xrun_define'] + self._make_top(param['make_top_shell']) + elif param['xsim']: + tool_define = param['xsim_define'] + self._make_top(param['make_top_shell']) + self.run(logfile=self.obj_dir + "/xsim_compile.log", + fails=param['fails'], + cmd=[ + VtOs.getenv_def('VERILATOR_XVLOG', "xvlog"), + ' '.join(param['xsim_flags']), + ' '.join(param['xsim_flags2']), + ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), + param['top_filename'], + param['top_shell_filename'], + ]) + elif param['vlt_all']: + tool_define = param['verilator_define'] + + if self.sc and not self.have_sc: + self.skip("Test requires SystemC; ignore error since not installed\n") + return + + if self.timing and not self.have_coroutines: + self.skip("Test requires Coroutines; ignore error since not available\n") + return + + if param['verilator_make_cmake'] and not self.have_cmake: + self.skip( + "Test requires CMake; ignore error since not available or version too old\n") + return + + if not param['fails'] and param['make_main']: + self._make_main(param['timing_loop']) + + if (param['verilator_make_gmake'] + or (not param['verilator_make_gmake'] and not param['verilator_make_cmake'])): + vlt_cmd = self.compile_vlt_cmd(**param) + if self.verbose: + self.oprint("Running Verilator (gmake)") + if Args.verilation: + self.run(logfile=self.obj_dir + "/vlt_compile.log", + fails=param['fails'], + tee=param['tee'], + expect_filename=param['expect_filename'], + verilator_run=True, + cmd=vlt_cmd) + + if param['verilator_make_cmake']: + vlt_args = self._compile_vlt_flags(**param) + if self.verbose: + self.oprint("Running cmake") + VtOs.mkdir_ok(self.obj_dir) + csources = [] + if param['make_main']: + csources.append(self.main_filename) + self.run( + logfile=self.obj_dir + "/vlt_cmake.log", + fails=param['fails'], + tee=param['tee'], + expect_filename=param['expect_filename'], + verilator_run=True, + cmd=[ + "cd \"" + self.obj_dir + "\" && cmake", + "\"" + self.t_dir + "/..\"", + "-DTEST_VERILATOR_ROOT=" + os.environ['VERILATOR_ROOT'], + "-DTEST_NAME=" + self.name, + "-DTEST_CSOURCES=\"" + ' '.join(csources) + "\"", + "-DTEST_VERILATOR_ARGS=\"" + ' '.join(vlt_args) + "\"", + "-DTEST_VERILATOR_SOURCES=\"" + param['top_filename'] + ' ' + + ' '.join(param['v_other_filenames']) + "\"", + "-DTEST_VERBOSE=\"" + ("1" if self.verbose else "0") + "\"", + "-DTEST_SYSTEMC=\"" + ("1" if self.sc else "0") + "\"", + "-DCMAKE_PREFIX_PATH=\"" + + (VtOs.getenv_def('SYSTEMC_INCLUDE', VtOs.getenv_def('SYSTEMC', '')) + + "/..\""), + "-DTEST_OPT_FAST=\"" + ("-Os" if param['benchmark'] else "-O0") + "\"", + "-DTEST_OPT_GLOBAL=\"" + ("-Os" if param['benchmark'] else "-O0") + "\"", + "-DTEST_VERILATION=\"" + ("1" if Args.verilation else "0") + "\"", + ]) + + if not param['fails'] and param['verilator_make_gmake']: + if self.verbose: + self.oprint("Running make (gmake)") + self.run( + logfile=self.obj_dir + "/vlt_gcc.log", + entering=self.obj_dir, + cmd=[ + os.environ['MAKE'], + "-C " + self.obj_dir, + "-f " + os.path.abspath(os.path.dirname(__file__)) + "/Makefile_obj", + ("" if self.verbose else "--no-print-directory"), + "VM_PREFIX=" + self.vm_prefix, + "TEST_OBJ_DIR=" + self.obj_dir, + "CPPFLAGS_DRIVER=-D" + self.name.upper(), + ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if self.verbose else ""), + ("" if param['benchmark'] else "OPT_FAST=-O0"), + ("" if param['benchmark'] else "OPT_GLOBAL=-O0"), + self.vm_prefix, # bypass default rule, as we don't need archive + *param['make_flags'], + ]) + + if not param['fails'] and param['verilator_make_cmake']: + if self.verbose: + self.oprint("Running cmake --build") + self.run(logfile=self.obj_dir + "/vlt_cmake_build.log", + cmd=[ + "cmake", + "--build", + self.obj_dir, + ("--verbose" if self.verbose else ""), + ]) + else: + self.error("No compile step defined for '%s' scenario" % self.scenario()) + + if param['make_pli']: + if self.verbose: + self.oprint("Compile vpi") + cmd = [ + os.environ['CXX'], *param['pli_flags'], "-D" + tool_define, "-DIS_VPI", + VtOs.getenv_def('CFLAGS', ''), self.pli_filename + ] + self.run(logfile=self.obj_dir + "/pli_compile.log", fails=param['fails'], cmd=cmd) + + def execute(self, **kwargs) -> None: + """Run simulation executable. + Arguments similar to run(); default arguments are from self""" + # Default arguments are from self + # params may be expect or {tool}_expect + param = { + 'aslr_off': False, + 'entering': False, + 'check_finished': False, + 'executable': None, + 'expect_filename': None, + 'fails': False, + 'run_env': '', + 'tee': True, + 'use_libvpi': False + } + param.update(vars(self)) + param.update(kwargs) + + if self.verbose: + self.oprint("Run") + + if not self.verbose: + os.environ['SYSTEMC_DISABLE_COPYRIGHT_MESSAGE'] = 'DISABLE' + else: + VtOs.delenv('SYSTEMC_DISABLE_COPYRIGHT_MESSAGE') + + if not self._have_solver_called: + os.environ['VERILATOR_SOLVER'] = "test.py-file-needs-have_solver()-call" + + if param['check_finished'] is None and not param['fails']: + param['check_finished'] = 1 + + run_env = param['run_env'] + if run_env: + run_env = run_env + ' ' + + if param['atsim']: + cmd = [ + "echo q | " + run_env + self.obj_dir + "/athdl_sv", + ' '.join(param['atsim_run_flags']), ' '.join(param['all_run_flags']) + ] + self.run(cmd=cmd, + check_finished=param['check_finished'], + entering=param['entering'], + expect_filename=param.get('atsim_run_expect_filename', None), + fails=param['fails'], + logfile=param.get('logfile', self.obj_dir + "/atsim_sim.log"), + tee=param['tee']) + elif param['ghdl']: + cmd = [ + run_env + self.obj_dir + "/simghdl", ' '.join(param['ghdl_run_flags']), + ' '.join(param['all_run_flags']) + ] + self.run(cmd=cmd, + check_finished=param['check_finished'], + entering=param['entering'], + expect_filename=param.get('ghdl_run_expect_filename', None), + fails=param['fails'], + logfile=param.get('logfile', self.obj_dir + "/ghdl_sim.log"), + tee=param['tee']) + elif param['iv']: + cmd = [ + run_env + self.obj_dir + "/simiv", ' '.join(param['iv_run_flags']), + ' '.join(param['all_run_flags']) + ] + if param['use_libvpi']: + # Don't enter command line on $stop, include vpi + cmd += ["vvp -n -m " + self.obj_dir + "/libvpi.so"] + self.run(cmd=cmd, + check_finished=param['check_finished'], + entering=param['entering'], + expect_filename=param.get('iv_run_expect_filename', None), + fails=param['fails'], + logfile=param.get('logfile', self.obj_dir + "/vlt_sim.log"), + tee=param['tee']) + elif param['ms']: + pli_opt = "" + if param['use_libvpi']: + pli_opt = "-pli " + self.obj_dir + "/libvpi.so" + cmd = [ + "echo q | " + run_env + VtOs.getenv_def('VERILATOR_MODELSIM', "vsim"), + ' '.join(param['ms_run_flags']), ' '.join(param['all_run_flags']), pli_opt, + (" top") + ] + self.run(cmd=cmd, + check_finished=param['check_finished'], + entering=param['entering'], + expect_filename=param.get('ms_run_expect_filename', None), + fails=param['fails'], + logfile=param.get('logfile', self.obj_dir + "/ms_sim.log"), + tee=param['tee']) + elif param['nc']: + cmd = [ + "echo q | " + run_env + VtOs.getenv_def('VERILATOR_NCVERILOG', "ncverilog"), + ' '.join(param['nc_run_flags']), ' '.join(param['all_run_flags']) + ] + self.run(cmd=cmd, + check_finished=param['check_finished'], + entering=param['entering'], + expect_filename=param.get('nc_run_expect_filename', None), + fails=param['fails'], + logfile=param.get('logfile', self.obj_dir + "/nc_sim.log"), + tee=param['tee']) + elif param['vcs']: + # my $fh = IO::File->new(">simv.key") or die "%Error: $! simv.key," + # fh.print("quit\n"); fh.close() + cmd = [ + "echo q | " + run_env + "./simv", ' '.join(param['vcs_run_flags']), + ' '.join(param['all_run_flags']) + ] + self.run(cmd=cmd, + check_finished=param['check_finished'], + entering=param['entering'], + expect_filename=param.get('vcs_run_expect_filename', None), + fails=param['fails'], + logfile=param.get('logfile', self.obj_dir + "/vcs_sim.log"), + tee=param['tee']) + elif param['xrun']: + pli_opt = "" + if param['use_libvpi']: + pli_opt = "-loadvpi " + self.obj_dir + "/libvpi.so:vpi_compat_bootstrap" + cmd = [ + "echo q | " + run_env + VtOs.getenv_def('VERILATOR_XRUN', "xrun"), + ' '.join(param['xrun_run_flags']), + ' '.join(param['xrun_flags2']), + ' '.join(param['all_run_flags']), + pli_opt, + param['top_filename'], + ] + self.run(cmd=cmd, + check_finished=param['check_finished'], + entering=param['entering'], + expect_filename=param.get('xrun_run_expect_filename', None), + fails=param['fails'], + logfile=param.get('logfile', self.obj_dir + "/xrun_sim.log"), + tee=param['tee']) + elif param['xsim']: + cmd = [ + run_env + VtOs.getenv_def('VERILATOR_XELAB', "xelab"), + ' '.join(param['xsim_run_flags']), ' '.join(param['xsim_run_flags2']), + ' '.join(param['all_run_flags']), (" " + self.name + ".top") + ] + self.run(cmd=cmd, + check_finished=param['check_finished'], + entering=param['entering'], + expect_filename=param.get('xsim_run_expect_filename', None), + fails=param['fails'], + logfile=param.get('logfile', self.obj_dir + "/xsim_sim.log"), + tee=param['tee']) + elif param['vlt_all']: + if not param['executable']: + param['executable'] = self.obj_dir + "/" + param['vm_prefix'] + debugger = "" + if Args.gdbsim: + debugger = VtOs.getenv_def('VERILATOR_GDB', "gdb") + " " + elif Args.rrsim: + debugger = "rr record " + cmd = [ + (run_env + debugger + param['executable'] + (" -ex 'run " if Args.gdbsim else "")), + *param['all_run_flags'], + ("'" if Args.gdbsim else ""), + ] + self.run( + cmd=cmd, + aslr_off=param['aslr_off'], # Disable address space layour randomization + check_finished=param['check_finished'], # Check for All Finished + entering=param['entering'], # Print entering directory information + expect_filename=param['expect_filename'], + fails=param['fails'], + logfile=param.get('logfile', self.obj_dir + "/vlt_sim.log"), + tee=param['tee'], + verilator_run=True, + ) + else: + self.error("No execute step for this simulator") + + #--------------------------------------------------------------- + # Accessors + + @property + def aslr_off(self) -> str: + if VlTest._cached_aslr_off is None: + out = VtOs.run_capture('setarch --addr-no-randomize echo OK 2>/dev/null', check=False) + if re.search(r'OK', out): + VlTest._cached_aslr_off = "setarch --addr-no-randomize " + else: + VlTest._cached_aslr_off = "" + return VlTest._cached_aslr_off + + @property + def benchmarksim_filename(self) -> str: + return self.obj_dir + "/" + self.name + "_benchmarksim.csv" + + @property + def driver_verilator_flags(self) -> list: + return Args.passdown_verilator_flags + + @property + def get_default_vltmt_threads(self) -> int: + return Vltmt_Threads + + @property + def ok(self) -> bool: + if self.errors or self.errors_keep_going or self._skips: + self._ok = False + return self._ok + + def passes(self, is_ok=True): + if not self.errors: + self._ok = is_ok + + @property + def too_few_cores(self) -> bool: + return calc_threads(Vltmt_Threads) < Vltmt_Threads + + @property + def trace_filename(self) -> str: + if re.match(r'^fst', self.trace_format): + return self.obj_dir + "/simx.fst" + return self.obj_dir + "/simx.vcd" + + def skip_if_too_few_cores(self) -> None: + if self.too_few_cores: + self.skip("Skipping due to too few cores") + + @property + def v_suffix(self) -> str: + return "v" + + @property + def wno_unopthreads_for_few_cores(self) -> str: + if self.too_few_cores: + print("Too few cores, using -Wno-UNOPTTHREADS") + return "-Wno-UNOPTTHREADS" + return "" + + #--------------------------------------------------------------- + # Capabilities + + @property + def cmake_version(self) -> str: + return Capabilities.cmake_version + + @property + def cxx_version(self) -> str: + return Capabilities.cxx_version + + @property + def have_cmake(self) -> bool: + ver = Capabilities.cmake_version + if not ver: + return False + m = re.match(r'^(\d+)\.(\d+)$', ver) + if not m: + return False + return int(m.group(1)) > 3 or int(m.group(2)) >= 8 # >= 3.8 + + @property + def have_coroutines(self) -> bool: + return Capabilities.have_coroutines + + @property + def have_gdb(self) -> bool: + return Capabilities.have_gdb + + @property + def have_sc(self) -> bool: + return Capabilities.have_sc + + @property + def have_solver(self) -> bool: + self._have_solver_called = True + return Capabilities.have_solver + + @property + def make_version(self) -> str: + return Capabilities.make_version + + #--------------------------------------------------------------- + # OS functions + + def getenv_def(self, var: str, default=None) -> str: + """Return environment variable, returning default if does not exist""" + return VtOs.getenv_def(var, default) + + def mkdir_ok(self, filename) -> None: + """Make directory, no error if exists""" + if test.verbose: + print("\tmkdir " + filename) + VtOs.mkdir_ok(filename) + + def run_capture(self, cmd: str, check=True) -> str: + """Run a command and return results""" + if test.verbose: + print("\t" + cmd) + return VtOs.run_capture(cmd, check=check) + + def setenv(self, var: str, val: str) -> None: + """Set enviornment variable""" + print("\texport %s='%s'" % (var, val)) + os.environ[var] = val + + def unlink_ok(self, filename) -> None: + """Unlink a file, no error if fails""" + if test.verbose: + print("\trm " + filename) + VtOs.unlink_ok(filename) + + #---------------------------------------------------------------------- + + def run( + self, # + cmd: list, + aslr_off=False, # Disable address space layour randomization + check_finished=False, # Check for All Finished + entering=None, # Print entering directory information + expect_filename=None, # Filename that should match logfile + fails=False, # Command should fail + logfile=None, # Filename to write putput to + tee=True, + verilator_run=False) -> str: # Move gcov data to parallel area + + try: + command = ' '.join(cmd) + except TypeError: + print('run(cmd=' + pformat(cmd)) + command = ' '.join(cmd) + + if aslr_off and aslr_off != "": + prefix = self.aslr_off + if prefix: + command = prefix + " " + command + + if Args.benchmark and re.match(r'^cd ', command): + command = "time " + command + + if verilator_run: + # Gcov fails when parallel jobs write same data file, + # so we make sure .gcda output dir is unique across all running jobs. + # We can't just put each one in an unique obj_dir as it uses too much disk. + # Must use absolute path as some execute()s have different PWD + self.setenv('GCOV_PREFIX_STRIP', '99') + self.setenv('GCOV_PREFIX', + os.path.abspath(__file__ + "/../obj_dist/gcov_" + str(self.running_id))) + os.makedirs(os.environ['GCOV_PREFIX'], exist_ok=True) + else: + VtOs.delenv('GCOV_PREFIX_STRIP') + VtOs.delenv('GCOV_PREFIX') + + print("\t" + command + ((" > " + logfile) if logfile else "")) + + if entering: + print("driver: Entering directory '" + os.path.abspath(entering) + "'") + + # Execute command redirecting output, keeping order between stderr and stdout. + # Must do low-level IO so GCC interaction works (can't be line-based) + status = None + if True: # process_caller_block # pylint: disable=using-constant-test + + logfh = None + if logfile: + logfh = open(logfile, 'wb') # pylint: disable=consider-using-with + + with subprocess.Popen(command, + shell=True, + bufsize=0, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT) as proc: + + rawbuf = bytearray(2048) + + while True: + finished = proc.poll() + # Need to check readinto once, even after poll "completes" + got = proc.stdout.readinto(rawbuf) + if got: + data = rawbuf[0:got] + if tee: + sys.stdout.write(data.decode('latin-1')) + if Args.interactive_debugger: + sys.stdout.flush() + if logfh: + logfh.write(data) + elif finished is not None: + break + + if logfh: + logfh.close() + + rc = proc.returncode # Negative if killed by signal + if (rc in ( + -4, # SIGILL + -8, # SIGFPA + -11)): # SIGSEGV + self.error("Exec failed with core dump") + status = 10 + elif rc: + status = 10 + else: + status = 0 + + sys.stdout.flush() + sys.stderr.flush() + + if entering: + print("driver: Leaving directory '" + os.path.abspath(entering) + "'") + + if not fails and status: + firstline = "" + if logfile: + with open(logfile, 'r', encoding="utf8") as fh: + for line in fh: + line = line.rstrip() + if re.match(r'^- ', line): # Debug message + continue + firstline = line + break + self.error("Exec of " + cmd[0] + " failed: " + firstline) + if fails and status: + print("(Exec expected to fail, and did.)") + if fails and not status: + self.error("Exec of " + cmd[0] + " ok, but expected to fail") + if self.errors or self._skips: + return False + + # Read the log file a couple of times to allow for NFS delays + if check_finished: + delay = 0.25 + for tryn in range(Args.log_retries - 1, -1, -1): + if tryn != Args.log_retries - 1: + time.sleep(delay) + delay = min(1, delay * 2) + moretry = tryn != 0 + if not self._run_log_try(logfile, check_finished, moretry): + break + if expect_filename: + self.files_identical(logfile, expect_filename, is_logfile=True) + return False + + return True + + def _run_log_try(self, logfile: str, check_finished: bool, moretry: bool) -> bool: + # If moretry, then return true to try again + with open(logfile, 'r', encoding='latin-1', newline='\n') as fh: + if not fh and moretry: + return True + wholefile = str(fh.read()) + + # Finished? + if check_finished and not re.search(r'\*\-\* All Finished \*\-\*', wholefile): + if moretry: + return True + self.error("Missing '*-* All Finished *-*'") + + return False + + ####################################################################### + # Little utilities + + @staticmethod + def _try_regex(text: str, regex) -> None: + # Try to eval a regexp + # Returns: + # 1 if $text ~= /$regex/ms + # 0 if no match + # -1 if $regex is invalid, doesn't compile + try: + m = re.search(regex, text) + return 1 if m else 0 + except re.error: + return -1 + + def _make_main(self, timing_loop: bool) -> None: + if timing_loop and self.sc: + self.error("Cannot use timing loop and SystemC together!") + + self._read_inputs_v() + + filename = self.main_filename + with open(filename, "w", encoding="utf8") as fh: + + fh.write("// Test defines\n") + fh.write("#define MAIN_TIME_MULTIPLIER " + + str(int(round(self.main_time_multiplier, 0))) + "\n") + + fh.write("#include \n") + if self.benchmarksim: + fh.write("#include \n") + fh.write("#include \n") + fh.write("#include \n") + + fh.write("// OS header\n") + fh.write('#include "verilatedos.h"' + "\n") + + fh.write("// Generated header\n") + fh.write('#include "' + self.vm_prefix + '.h"' + "\n") + + fh.write("// General headers\n") + fh.write('#include "verilated.h"' + "\n") + if self.sc: + fh.write('#include "systemc.h"' + "\n") + if self.trace and self.trace_format == 'fst-c': + fh.write("#include \"verilated_fst_c.h\"\n") + if self.trace and self.trace_format == 'fst-sc': + fh.write("#include \"verilated_fst_sc.h\"\n") + if self.trace and self.trace_format == 'vcd-c': + fh.write("#include \"verilated_vcd_c.h\"\n") + if self.trace and self.trace_format == 'vcd-sc': + fh.write("#include \"verilated_vcd_sc.h\"\n") + if self.savable: + fh.write("#include \"verilated_save.h\"\n") + + fh.write("std::unique_ptr<" + self.vm_prefix + "> topp;\n") + + if self.savable: + fh.write("\n") + fh.write("void save_model(const char* filenamep) {\n") + fh.write(" VL_PRINTF(\"Saving model to '%s'\\n\", filenamep);\n") + fh.write(" VerilatedSave os;\n") + fh.write(" os.open(filenamep);\n") + fh.write(" os << *topp;\n") + fh.write(" os.close();\n") + fh.write("}\n") + fh.write("\n") + fh.write("void restore_model(const char* filenamep) {\n") + fh.write(" VL_PRINTF(\"Restoring model from '%s'\\n\", filenamep);\n") + fh.write(" VerilatedRestore os;\n") + fh.write(" os.open(filenamep);\n") + fh.write(" os >> *topp;\n") + fh.write(" os.close();\n") + fh.write("}\n") + + #### Main + if self.sc: + fh.write("extern int sc_main(int argc, char** argv);\n") + fh.write("int sc_main(int argc, char** argv) {\n") + if 'fastclk' in self._inputs: + if self.pins_sc_uint_bool: + fh.write(" sc_signal> fastclk;\n") + else: + fh.write(" sc_signal fastclk;\n") + if 'clk' in self._inputs: + if self.pins_sc_uint_bool: + fh.write(" sc_signal> clk;\n") + else: + fh.write(" sc_signal clk;\n") + fh.write(" sc_set_time_resolution(1, " + self.sc_time_resolution + ");\n") + fh.write(" sc_time sim_time(" + str(self.sim_time) + ", " + + self.sc_time_resolution + ");\n") + else: + fh.write("int main(int argc, char** argv) {\n") + fh.write(" uint64_t sim_time = " + str(self.sim_time) + ";\n") + + fh.write( + " const std::unique_ptr contextp{new VerilatedContext};\n") + fh.write(" contextp->threads(" + str(self.context_threads) + ");\n") + fh.write(" contextp->commandArgs(argc, argv);\n") + fh.write(" contextp->debug(" + ('1' if self.verilated_debug else '0') + ");\n") + fh.write(" srand48(5);\n") # Ensure determinism + if self.verilated_randReset is not None and self.verilated_randReset != "": + fh.write(" contextp->randReset(" + str(self.verilated_randReset) + ");\n") + fh.write(" topp.reset(new " + self.vm_prefix + "{\"top\"});\n") + if self.verilated_debug: + fh.write(" contextp->internalsDump()\n;") + + if self.sc: + if 'fastclk' in self._inputs: + fh.write(" topp->fastclk(fastclk);\n") + if 'clk' in self._inputs: + fh.write(" topp->clk(clk);\n") + setp = "" + else: + fh.write(" topp->eval();\n") + setp = "topp->" + + if self.benchmarksim: + fh.write(" std::chrono::time_point starttime;\n") + fh.write(" bool warm = false;\n") + fh.write(" uint64_t n_evals = 0;\n") + + if self.trace: + fh.write("\n") + fh.write("#if VM_TRACE\n") + fh.write(" contextp->traceEverOn(true);\n") + if self.trace_format == 'fst-c': + fh.write(" std::unique_ptr tfp{new VerilatedFstC};\n") + if self.trace_format == 'fst-sc': + fh.write(" std::unique_ptr tfp{new VerilatedFstSc};\n") + if self.trace_format == 'vcd-c': + fh.write(" std::unique_ptr tfp{new VerilatedVcdC};\n") + if self.trace_format == 'vcd-sc': + fh.write(" std::unique_ptr tfp{new VerilatedVcdSc};\n") + if self.sc: + fh.write(" sc_core::sc_start(sc_core::SC_ZERO_TIME);" + + " // Finish elaboration before trace and open\n") + fh.write(" topp->trace(tfp.get(), 99);\n") + fh.write(" tfp->open(\"" + self.trace_filename + "\");\n") + + if self.trace and not self.sc: + fh.write(" if (tfp) tfp->dump(contextp->time());\n") + fh.write("#endif\n") + + if self.savable: + fh.write(" const char* save_time_strp" + " = contextp->commandArgsPlusMatch(\"save_time=\");\n") + fh.write(" unsigned int save_time = !save_time_strp[0]" + " ? 0 : std::atoi(save_time_strp + std::strlen(\"+save_time=\"));\n") + fh.write(" const char* save_restore_strp" + " = contextp->commandArgsPlusMatch(\"save_restore=\");\n") + fh.write(" unsigned int save_restore = !save_restore_strp[0] ? 0 : 1;\n") + + if self.savable: + fh.write(" if (save_restore) {\n") + fh.write(" restore_model(\"" + self.obj_dir + "/saved.vltsv\");\n") + fh.write(" } else {\n") + else: + fh.write(" {\n") + + if 'fastclk' in self._inputs: + fh.write(" " + setp + "fastclk = false;\n") + if 'clk' in self._inputs: + fh.write(" " + setp + "clk = false;\n") + if not timing_loop: + self._print_advance_time(fh, 10, None) + fh.write(" }\n") + + timestamp = "sc_time_stamp()" if self.sc else "contextp->time()" + + fh.write(" while (") + if not timing_loop or 'clk' in self._inputs: + fh.write("(" + timestamp + " < sim_time * MAIN_TIME_MULTIPLIER) && ") + fh.write("!contextp->gotFinish()) {\n") + + if timing_loop: + fh.write(" topp->eval();\n") + if self.trace: + fh.write("#if VM_TRACE\n") + fh.write(" if (tfp) tfp->dump(contextp->time());\n") + fh.write("#endif // VM_TRACE\n") + if 'clk' in self._inputs: + fh.write(" const uint64_t cycles" + " = contextp->time() / MAIN_TIME_MULTIPLIER;\n") + fh.write(" uint64_t new_time = (cycles + 1) * MAIN_TIME_MULTIPLIER;\n") + fh.write(" if (topp->eventsPending() &&\n") + fh.write(" topp->nextTimeSlot()" + " / MAIN_TIME_MULTIPLIER <= cycles) {\n") + fh.write(" new_time = topp->nextTimeSlot();\n") + fh.write(" } else {\n") + if self.pins_sc_uint_bool: + fh.write(" " + setp + "clk.write(!" + setp + "clk.read());\n") + else: + fh.write(" " + setp + "clk = !" + setp + "clk;\n") + fh.write(" }\n") + fh.write(" contextp->time(new_time);\n") + else: + fh.write(" if (!topp->eventsPending()) break;\n") + fh.write(" contextp->time(topp->nextTimeSlot());\n") + else: + for i in range(5): + action = False + if 'fastclk' in self._inputs: + if self.pins_sc_uint_bool: + fh.write(" " + setp + "fastclk.write(!" + setp + + "fastclk.read());\n") + else: + fh.write(" " + setp + "fastclk = !" + setp + "fastclk;\n") + action = True + if i == 0 and 'clk' in self._inputs: + if self.pins_sc_uint_bool: + fh.write(" " + setp + "clk.write(!" + setp + "clk.read());\n") + else: + fh.write(" " + setp + "clk = !" + setp + "clk;\n") + action = True + if self.savable: + fh.write(" if (save_time && " + timestamp + " == save_time) {\n") + fh.write(" save_model(\"" + self.obj_dir + "/saved.vltsv\");\n") + fh.write(" printf(\"Exiting after save_model\\n\");\n") + fh.write(" topp.reset(nullptr);\n") + fh.write(" return 0;\n") + fh.write(" }\n") + self._print_advance_time(fh, 1, action) + if self.benchmarksim: + fh.write(" if (VL_UNLIKELY(!warm)) {\n") + fh.write(" starttime = std::chrono::steady_clock::now();\n") + fh.write(" warm = true;\n") + fh.write(" } else {\n") + fh.write(" ++n_evals;\n") + fh.write(" }\n") + + fh.write(" }\n") + + if self.benchmarksim: + fh.write(" {\n") + fh.write(" const std::chrono::duration exec_s" + " = std::chrono::steady_clock::now() - starttime;\n") + fh.write(" std::ofstream benchfile(\"" + self.benchmarksim_filename + + "\", std::ofstream::out | std::ofstream::app);\n") + fh.write(" benchfile << std::fixed << std::setprecision(9)" + " << n_evals << \",\" << exec_s.count() << std::endl;\n") + fh.write(" benchfile.close();\n") + fh.write(" }\n") + + fh.write(" if (!contextp->gotFinish()) {\n") + fh.write(' vl_fatal(__FILE__, __LINE__, "main",' + + ' "%Error: Timeout; never got a $finish");' + "\n") + fh.write(" }\n") + fh.write(" topp->final();\n") + fh.write("\n") + + if self.coverage: + fh.write("#if VM_COVERAGE\n") + fh.write(" contextp->coveragep()->write(\"" + self.coverage_filename + "\");\n") + fh.write("#endif // VM_COVERAGE\n") + + if self.trace: + fh.write("#if VM_TRACE\n") + fh.write(" if (tfp) tfp->close();\n") + fh.write(" tfp.reset();\n") + fh.write("#endif // VM_TRACE\n") + + fh.write(" topp.reset();\n") + fh.write(" return 0;\n") + fh.write("}\n") + + def _print_advance_time(self, fh, timeinc: str, action: bool) -> None: + setp = "" if self.sc else "topp->" + if self.sc: + fh.write(" sc_start(" + str(timeinc) + " * MAIN_TIME_MULTIPLIER, " + + self.sc_time_resolution + ");\n") + else: + if action: + fh.write(" " + setp + "eval();\n") + if self.trace and not self.sc: + fh.write("#if VM_TRACE\n") + fh.write(" if (tfp) tfp->dump(contextp->time());\n") + fh.write("#endif // VM_TRACE\n") + fh.write(" contextp->timeInc(" + str(timeinc) + " * MAIN_TIME_MULTIPLIER);\n") + + ####################################################################### + + def _make_top(self, needed=True) -> None: + if not needed: + return + self._make_top_v() + + def _make_top_v(self) -> None: + self._read_inputs_v() + + with open(self.top_shell_filename, 'w', encoding="utf8") as fh: + fh.write("module top;\n") + for inp in sorted(self._inputs.keys()): + fh.write(" reg " + inp + ";\n") + # Inst + fh.write(" t t (\n") + comma = "" + for inp in sorted(self._inputs.keys()): + fh.write(" " + comma + "." + inp + " (" + inp + ")\n") + comma = "," + fh.write(" );\n") + + # Waves + fh.write("\n") + fh.write("`ifdef WAVES\n") + fh.write(" initial begin\n") + fh.write(" $display(\"-Tracing Waves to Dumpfile: " + self.trace_filename + + "\");\n") + fh.write(" $dumpfile(\"" + self.trace_filename + "\");\n") + fh.write(" $dumpvars(0, top);\n") + fh.write(" end\n") + fh.write("`endif\n") + + # Test + fh.write("\n") + fh.write(" initial begin\n") + if 'fastclk' in self._inputs: + fh.write(" fastclk = 0;\n") + if 'clk' in self._inputs: + fh.write(" clk = 0;\n") + fh.write(" #10;\n") + if 'fastclk' in self._inputs: + fh.write(" fastclk = 1;\n") + if 'clk' in self._inputs: + fh.write(" clk = 1;\n") + fh.write(" while ($time < " + str(self.sim_time) + ") begin\n") + for i in range(6): + fh.write(" #1;\n") + if 'fastclk' in self._inputs: + fh.write(" fastclk = !fastclk;\n") + if i == 4 and 'clk' in self._inputs: + fh.write(" clk = !clk;\n") + fh.write(" end\n") + fh.write(" end\n") + + fh.write("endmodule\n") + + ####################################################################### + + def _read_inputs_v(self) -> None: + filename = self.top_filename + if not os.path.exists(filename): + filename = self.t_dir + '/' + filename + with open(filename, 'r', encoding="utf8") as fh: + get_sigs = True + inputs = {} + for line in fh: + if get_sigs: + m = re.match(r'^\s*input\s*(\S+)\s*(\/[^\/]+\/|)\s*;', line) + if m: + inputs[m.group(1)] = m.group(1) + if re.match(r'^\s*(function|task|endmodule)', line): + get_sigs = False + # Ignore any earlier inputs; Module 't' has precedence + if re.match(r'^\s*module\s+t\b', line): + inputs = {} + get_sigs = True + for sig, val in inputs.items(): + self._inputs[sig] = val + + ####################################################################### + # File utilities + + def files_identical(self, fn1: str, fn2: str, is_logfile=False) -> None: + """Test if two files have identical contents""" + delay = 0.25 + for tryn in range(Args.log_retries, -1, -1): + if tryn != Args.log_retries - 1: + time.sleep(delay) + delay = min(1, delay * 2) + moretry = tryn != 0 + if not self._files_identical_try( + fn1=fn1, fn2=fn2, is_logfile=is_logfile, moretry=moretry): + break + + def _files_identical_try(self, fn1: str, fn2: str, is_logfile: bool, moretry: bool) -> bool: + # If moretry, then return true to try again + try: + f1 = open( # pylint: disable=consider-using-with + fn1, 'r', encoding='latin-1', newline='\n') + except FileNotFoundError: + f1 = None + if not moretry: + self.error("Files_identical file does not exist: " + fn1) + return True # Retry + try: + f2 = open( # pylint: disable=consider-using-with + fn2, 'r', encoding='latin-1', newline='\n') + except FileNotFoundError: + f2 = None + if not moretry: + self.copy_if_golden(fn1, fn2) + self.error("Files_identical file does not exist: " + fn2) + return True # Retry + again = self._files_identical_reader(f1, + f2, + fn1=fn1, + fn2=fn2, + is_logfile=is_logfile, + moretry=moretry) + if f1: + f1.close() + if f2: + f2.close() + return again + + def _files_identical_reader(self, f1, f2, fn1: str, fn2: str, is_logfile: bool, + moretry: bool) -> None: + # If moretry, then return true to try again + l1s = f1.readlines() + l2s = f2.readlines() if f2 else [] + # print(" rawGOT="+pformat(l1s)+"\n rawEXP="+pformat(l2s)) + if is_logfile: + l1o = [] + for line in l1s: + if (re.match(r'^- [^\n]+\n', line) # + or re.match(r'^- [a-z.0-9]+:\d+:[^\n]+\n', line) + or re.match(r'^-node:', line) # + or re.match(r'^dot [^\n]+\n', line) # + or re.match(r'^Aborted', line) # + or re.match(r'^In file: .*\/sc_.*:\d+', line) # + or re.match(r'^libgcov.*', line) # + or re.match(r'--- \/tmp\/', line) # t_difftree.py + or re.match(r'\+\+\+ \/tmp\/', line) # t_difftree.py + or re.match(r'^==[0-9]+== ?[^\n]*\n', line)): # valgrind + continue + # Don't put control chars or unstable lines into source repository + while True: + (line, didn) = re.subn(r'(Internal Error: [^\n]+?\.(cpp|h)):[0-9]+', r'\1:#', + line) + if not didn: + break + # --vlt vs --vltmt run differences + line = re.sub(r'^-V\{t[0-9]+,[0-9]+\}', '-V{t#,#}', line) + line = re.sub(r'\r', '<#013>', line) + line = re.sub(r'Command Failed[^\n]+', 'Command Failed', line) + line = re.sub(r'Version: Verilator[^\n]+', 'Version: Verilator ###', line) + line = re.sub(r'CPU Time: +[0-9.]+ seconds[^\n]+', 'CPU Time: ###', line) + line = re.sub(r'\?v=[0-9.]+', '?v=latest', line) # warning URL + line = re.sub(r'_h[0-9a-f]{8}_', '_h########_', line) + line = re.sub(r'%Error: /[^: ]+/([^/:])', r'%Error: .../\1', + line) # Avoid absolute paths + line = re.sub(r' \/[^ ]+\/verilated_std.sv', ' verilated_std.sv', line) + # + (line, n) = re.subn(r'Exiting due to.*', r"Exiting due to", line) + if n: + l1o.append(line) + break # Trunc rest + l1o.append(line) + # + l1s = l1o + + for lineno_m1 in range(0, max(len(l1s), len(l2s))): + l1 = l1s[lineno_m1] if lineno_m1 < len(l1s) else "*EOF*\n" + l2 = l2s[lineno_m1] if lineno_m1 < len(l2s) else "*EOF*\n" + if l1 != l2: + # print(" clnGOT="+pformat(l1s)+"\n clnEXP="+pformat(l2s)) + if moretry: + return True # Retry + self.error_keep_going("Line " + str(lineno_m1) + " miscompares; " + fn1 + " != " + + fn2) + for c in range(min(len(l1), len(l2))): + if ord(l1[c]) != ord(l2[c]): + print("Miscompare starts at column " + str(c) + + (" w/ F1(got)=0x%02x F2(exp)=0x%02x" % (ord(l1[c]), ord(l2[c]))), + file=sys.stderr) + break + print("F1(got): " + l1 + "F2(exp): " + l2, file=sys.stderr) + if 'HARNESS_UPDATE_GOLDEN' in os.environ: # Update golden files with current + print("%Warning: HARNESS_UPDATE_GOLDEN set: cp " + fn1 + " " + fn2, + file=sys.stderr) + with open(fn2, 'w', encoding="utf8") as fhw: + fhw.write(''.join(l1s)) + else: + print("To update reference: HARNESS_UPDATE_GOLDEN=1 {command} or --golden", + file=sys.stderr) + return False # No retry - bad + + return False # No retry - good + + def files_identical_sorted(self, fn1: str, fn2: str, is_logfile=False) -> None: + """Test if two files, after sorting both, have identical contents""" + # Set LC_ALL as suggested in the sort manpage to avoid sort order + # changes from the locale. + os.environ['LC_ALL'] = 'C' + fn1sort = fn1 + '.sort' + self.run(cmd=['sort', fn1, "> " + fn1sort]) + self.files_identical(fn1sort, fn2, is_logfile) + + def copy_if_golden(self, fn1: str, fn2: str) -> None: + """Copy a file if updating golden .out files""" + if 'HARNESS_UPDATE_GOLDEN' in os.environ: # Update golden files with current + print("%Warning: HARNESS_UPDATE_GOLDEN set: cp " + fn1 + " " + fn2, file=sys.stderr) + shutil.copy(fn1, fn2) + + def vcd_identical(self, fn1: str, fn2: str) -> None: + """Test if two VCD files have logically-identical contents""" + # vcddiff to check transitions, if installed + cmd = "vcddiff --help" + out = test.run_capture(cmd, check=True) + cmd = 'vcddiff ' + fn1 + ' ' + fn2 + out = test.run_capture(cmd, check=True) + if out != "": + cmd = 'vcddiff ' + fn2 + " " + fn1 # Reversed arguments + out = VtOs.run_capture(cmd, check=False) + if out != "": + print(out) + self.copy_if_golden(fn1, fn2) + self.error("VCD miscompares " + fn2 + " " + fn1) + + # vcddiff doesn't check module and variable scope, so check that + # Also provides backup if vcddiff not installed + h1 = self._vcd_read(fn1) + h2 = self._vcd_read(fn2) + a = json.dumps(h1, sort_keys=True, indent=1) + b = json.dumps(h2, sort_keys=True, indent=1) + if a != b: + self.copy_if_golden(fn1, fn2) + self.error("VCD hier miscompares " + fn1 + " " + fn2 + "\nGOT=" + a + "\nEXP=" + b + + "\n") + + def fst2vcd(self, fn1: str, fn2: str) -> None: + cmd = "fst2vcd -h" + out = VtOs.run_capture(cmd, check=False) + if out == "" or not re.search(r'Usage:', out): + self.skip("No fst2vcd installed") + return + + cmd = 'fst2vcd -e -f "' + fn1 + '" -o "' + fn2 + '"' + print("\t " + cmd + "\n") # Always print to help debug race cases + out = VtOs.run_capture(cmd, check=False) + print(out) + + def fst_identical(self, fn1: str, fn2: str) -> None: + """Test if two FST files have logically-identical contents""" + tmp = fn1 + ".vcd" + self.fst2vcd(fn1, tmp) + self.vcd_identical(tmp, fn2) + + def _vcd_read(self, filename: str) -> str: + data = {} + with open(filename, 'r', encoding='latin-1') as fh: + hier_stack = ["TOP"] + var = [] + for line in fh: + match1 = re.search(r'\$scope (module|struct|interface)\s+(\S+)', line) + match2 = re.search(r'(\$var (\S+)\s+\d+\s+)\S+\s+(\S+)', line) + match3 = re.search(r'(\$attrbegin .* \$end)', line) + line = line.rstrip() + # print("VR"+ ' '*len(hier_stack) +" L " + line) + if match1: # $scope + name = match1.group(2) + # print("VR"+ ' '*len(hier_stack) +" scope " + line) + hier_stack += [name] + scope = '.'.join(hier_stack) + data[scope] = match1.group(1) + " " + name + elif match2: # $var + # print("VR"+ ' '*len(hier_stack) +" var " + line) + scope = '.'.join(hier_stack) + var = match2.group(2) + data[scope + "." + var] = match2.group(1) + match2.group(3) + elif match3: # $attrbegin + # print("VR"+ ' '*len(hier_stack) +" attr " + line) + if var: + scope = '.'.join(hier_stack) + data[scope + "." + var + "#"] = match3.group(1) + elif re.search(r'\$enddefinitions', line): + break + n = len(re.findall(r'\$upscope', line)) + if n: + for i in range(0, n): # pylint: disable=unused-variable + # print("VR"+ ' '*len(hier_stack) +" upscope " + line) + hier_stack.pop() + return data + + def inline_checks(self) -> None: + covfn = self.coverage_filename + contents = self.file_contents(covfn) + + if self.verbose: + self.oprint("Extract checks") + with open(self.top_filename, 'r', encoding="utf8") as fh: + flineno = 0 + for line in fh: + flineno += 1 + if re.search(r'CHECK', line): + match1 = re.search( + r'CHECK_COVER *\( *((-|[0-9])+) *,' + r'*"([^"]+)" *, *("([^"]+)" *,|) *(\d+) *\)', line) + match2 = re.search(r'CHECK_COVER_MISSING *\( *((-|[0-9])+) *\)', line) + if match1: + lineno = flineno + int(match1.group(1)) + hier = match1.group(3) + comment = match1.group(5) + count = match1.group(6) + regexp = "\001l\002" + str(lineno) + if comment: + regexp += ".*\001o\002" + re.escape(comment) + if hier: + regexp += ".*\001h\002" + re.escape(hier) + regexp += ".*' " + str(count) + if not re.search(regexp, contents): + self.error("CHECK_COVER: " + covfn + ":" + str(flineno) + + ": Regexp not found: " + regexp + "\n" + "From " + + self.top_filename + ": " + line) + elif match2: + lineno = flineno + int(match2.group(1)) + regexp = "\001l\002" + str(lineno) + if re.search(regexp, contents): + self.error("CHECK_COVER_MISSING: " + covfn + ":" + str(flineno) + + ": Regexp found: " + regexp + "\n" + "From " + + self.top_filename + ": " + line) + else: + self.error(self.top_filename + ":" + str(flineno) + + ": Unknown CHECK request: " + line) + + @staticproperty + def cfg_with_ccache() -> bool: # pylint: disable=no-method-argument + if VlTest._cached_cfg_with_ccache is None: + mkf = VlTest._file_contents_static(os.environ['VERILATOR_ROOT'] + + "/include/verilated.mk") + VlTest._cached_cfg_with_ccache = bool(re.match(r'OBJCACHE \?= ccache', mkf)) + return VlTest._cached_cfg_with_ccache + + def glob_some(self, pattern: str) -> list: + """Return list of filenames matching a glob, with at least one match required.""" + files = glob.glob(pattern) + # print("glob_some('" + pattern + "') files =\n " + pformat(files)) + if not files: + self.error("glob_one: pattern '" + pattern + "' does not match any files") + return ['No_file_found'] + return sorted(files) + + def glob_one(self, pattern: str) -> str: + """Return a filename matching a glob, with exactly one match required.""" + files = self.glob_some(pattern) + if files and len(files) > 1: + msg = "glob_one: pattern '" + pattern + "' matches multiple files:\n" + for file in files: + msg += file + "\n" + self.error(msg) + return 'Multiple_files_found' + return files[0] + + def file_grep_not(self, filename: str, regexp) -> None: + contents = self.file_contents(filename) + if contents == "_Already_Errored_": + return + if re.search(regexp, contents, re.MULTILINE): + self.error("File_grep_not: " + filename + ": Regexp found: '" + regexp + "'") + + def file_grep(self, filename: str, regexp, expvalue=None) -> list: + contents = self.file_contents(filename) + if contents == "_Already_Errored_": + return None + match = re.search(regexp, contents, re.MULTILINE) + if not match: + self.error("File_grep: " + filename + ": Regexp not found: " + regexp) + return None + if expvalue and str(expvalue) != match.group(1): + self.error("File_grep: " + filename + ": Got='" + match.group(1) + "' Expected='" + + str(expvalue) + "' in regexp: '" + regexp + "'") + return None + return [match.groups()] + + def file_grep_count(self, filename: str, regexp, expcount: int) -> None: + contents = self.file_contents(filename) + if contents == "_Already_Errored_": + return + count = len(re.findall(regexp, contents)) + if expcount != count: + self.error("File_grep_count: " + filename + ": Got='" + str(count) + "' Expected='" + + str(expcount) + "' in regexp: '" + regexp + "'") + + def file_grep_any(self, filenames: list, regexp, expvalue=None) -> None: + for filename in filenames: + contents = self.file_contents(filename) + if contents == "_Already_Errored_": + return + match = re.search(regexp, contents) + if match: + if expvalue and str(expvalue) != match.group(1): + self.error("file_grep: " + filename + ": Got='" + match.group(1) + + "' Expected='" + str(expvalue) + "' in regexp: " + regexp) + return + msg = "file_grep_any: Regexp '" + regexp + "' not found in any of the following files:\n" + for filename in filenames: + msg += filename + "\n" + self.error(msg) + + def file_contents(self, filename: str) -> str: + if filename not in self._file_contents_cache: + if not os.path.exists(filename): + self._file_contents_cache[filename] = "_Already_Errored_" + self.error("File_contents file not found: " + filename) + else: + with open(filename, 'r', encoding='latin-1') as fh: + self._file_contents_cache[filename] = str(fh.read()) + return self._file_contents_cache[filename] + + @staticmethod + def _file_contents_static(filename: str) -> str: + if filename not in VlTest._file_contents_cache: + if not os.path.exists(filename): + VlTest._file_contents_cache[filename] = "_Already_Errored_" + sys.exit("_file_contents_static file not found: " + filename) + else: + with open(filename, 'r', encoding='latin-1') as fh: + VlTest._file_contents_cache[filename] = str(fh.read()) + return VlTest._file_contents_cache[filename] + + def write_wholefile(self, filename: str, contents: str) -> None: + with open(filename, 'wb') as fh: + fh.write(contents.encode('latin-1')) + if filename in self._file_contents_cache: + del self._file_contents_cache[filename] + + def file_sed(self, in_filename: str, out_filename, edit_lambda) -> None: + contents = self.file_contents(in_filename) + contents = edit_lambda(contents) + self.write_wholefile(out_filename, contents) + + def extract( + self, + in_filename: str, + out_filename: str, + regexp=r'.*', + lineno_adjust=-9999, # + lines=None) -> None: #'#, #-#' + temp_fn = out_filename + temp_fn = re.sub(r'.*/', '', temp_fn) + temp_fn = self.obj_dir + "/" + temp_fn + + out = [] + emph = "" + lineno = 0 + lineno_out = 0 + with open(in_filename, 'r', encoding="latin-1") as fh: + for line in fh: + lineno += 1 + if re.search(regexp, line) and self._lineno_match(lineno, lines): + match = re.search(r't/[A-Za-z0-9_]+.v:(\d+):(\d+):', line) + if match: + mlineno = int(match.group(1)) + lineno_adjust + col = int(match.group(2)) + mlineno = max(1, mlineno) + line = re.sub(r't/[A-Za-z0-9_]+.v:(\d+):(\d+):', + 'example.v:' + str(mlineno) + ':' + str(col), line) + out.append(" " + line) + lineno_out += 1 + if '<--' in line: + if emph: + emph += "," + emph += str(lineno_out) + + with open(temp_fn, 'w', encoding="latin-1") as fhw: + lang = " sv" if re.search(r'\.s?vh?$', in_filename) else "" + fhw.write(".. comment: generated by " + self.name + "\n") + fhw.write(".. code-block::" + lang + "\n") + if lang != "" and len(out) > 1: + fhw.write(" :linenos:\n") + if emph: + fhw.write(" :emphasize-lines: " + emph + "\n") + fhw.write("\n") + for line in out: + fhw.write(line) + + self.files_identical(temp_fn, out_filename) + + @staticmethod + def _lineno_match(lineno: int, lines: str) -> bool: + if not lines: + return True + for lc in lines.split(','): + match1 = re.match(r'^(\d+)$', lc) + match2 = re.match(r'^(\d+)-(\d+)$', lc) + if match1 and int(match1.group(1)) == lineno: + return True + if match2 and int(match2.group(1)) <= lineno <= int(match2.group(2)): + return True + return False + + +###################################################################### +###################################################################### +# Global Functions + + +def calc_jobs() -> int: + ok_threads = max_procs() + print("driver.py: Found %d cores, using -j %d" % (ok_threads, ok_threads)) + return ok_threads + + +def calc_threads(default_threads) -> int: + ok_threads = max_procs() + return ok_threads if (ok_threads < default_threads) else default_threads + + +def _calc_hashset() -> list: + match = re.match(r'^(\d+)/(\d+)$', Args.hashset) + if not match: + sys.exit("%Error: Need number/number format for --hashset: " + Args.hashset) + setn = int(match.group(1)) + nsets = int(match.group(2)) + new = [] + global Arg_Tests + for t in Arg_Tests: + checksum = int(hashlib.sha256(t.encode("utf-8")).hexdigest()[0:4], 16) + if (setn % nsets) == (checksum % nsets): + new.append(t) + Arg_Tests = new + + +####################################################################### +####################################################################### +# Verilator utilities + + +@lru_cache(maxsize=1) +def max_procs() -> int: + procs = multiprocessing.cpu_count() + if procs < 2: + print("driver.py: Python didn't find at least two CPUs") + return procs + + +def _parameter(param: str) -> None: + global _Parameter_Next_Level + if _Parameter_Next_Level: + if not re.match(r'^(\d+)$', param): + sys.exit("%Error: Expected number following " + _Parameter_Next_Level + ": " + param) + Args.passdown_verilator_flags.append(param) + _Parameter_Next_Level = None + elif re.search(r'\.py', param): + Arg_Tests.append(param) + elif re.match(r'^-?(-debugi|-dumpi)', param): + Args.passdown_verilator_flags.append(param) + _Parameter_Next_Level = param + elif re.match(r'^-?(-W||-debug-check)', param): + Args.passdown_verilator_flags.append(param) + else: + sys.exit("%Error: Unknown parameter: " + param) + + +def run_them() -> None: + VtOs.mkdir_ok("obj_dist") + timestart = time.strftime("%Y%m%d_%H%M%S") + + runner = Runner(driver_log_filename="obj_dist/driver_" + timestart + ".log", quiet=Args.quiet) + for test_py in Arg_Tests: + for scenario in sorted(set(Args.scenarios)): + if VlTest._prefilter_scenario(test_py, scenario): + runner.one_test(py_filename=test_py, scenario=scenario) + runner.wait_and_report() + + if Args.rerun and runner.fail_cnt and not Quitting: + print('=' * 70) + print('=' * 70) + print("RERUN ==\n") + + # Avoid parallel run to ensure that isn't causing problems + # If > 10 failures something more wrong and get results quickly + if runner.fail_cnt < 10: + forker.max_proc(1) + + orig_runner = runner + runner = Runner(driver_log_filename="obj_dist/driver_" + timestart + "_rerun.log", + quiet=False, + fail1_cnt=orig_runner.fail_cnt, + ok_cnt=orig_runner.ok_cnt, + skip_cnt=orig_runner.skip_cnt) + for ftest in orig_runner.fail_tests: + # Reschedule test + if ftest.rerunnable: + ftest.clean() + runner.one_test(py_filename=ftest.py_filename, + scenario=ftest.scenario, + rerun_skipping=not ftest.rerunnable) + + runner.wait_and_report() + + if runner.fail_cnt: + sys.exit(10) + + +###################################################################### +###################################################################### +# Main + +if __name__ == '__main__': + os.environ['PYTHONUNBUFFERED'] = "1" + + if ('VERILATOR_ROOT' not in os.environ) and os.path.isfile('../bin/verilator'): + os.environ['VERILATOR_ROOT'] = os.getcwd() + "/.." + if 'MAKE' not in os.environ: + os.environ['MAKE'] = "make" + if 'CXX' not in os.environ: + os.environ['CXX'] = "c++" + if 'TEST_REGRESS' in os.environ: + sys.exit("%Error: TEST_REGRESS environment variable is already set") + os.environ['TEST_REGRESS'] = os.getcwd() + + forker = None + Start = time.time() + _Parameter_Next_Level = None + + def sig_int(signum, env) -> None: # pylint: disable=unused-argument + global Quitting + if Quitting: + sys.exit("\nQuitting (immediately)...") + print("\nQuitting... (send another interrupt signal for immediate quit)") + Quitting = True + if forker: + forker.kill_tree_all() + + signal.signal(signal.SIGINT, sig_int) + + #--------------------------------------------------------------------- + + parser = argparse.ArgumentParser( + allow_abbrev=False, + formatter_class=argparse.RawDescriptionHelpFormatter, + description="""Run Verilator regression tests""", + epilog="""driver.py invokes Verilator or another simulator on each test file. + See docs/internals.rst in the distribution for more information. + + Copyright 2024-2024 by Wilson Snyder. This program is free software; you + can redistribute it and/or modify it under the terms of either the GNU + Lesser General Public License Version 3 or the Perl Artistic License + Version 2.0. + + SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") + + parser.add_argument('--benchmark', action='store', help='enable benchmarking') + parser.add_argument('--debug', action='store_const', const=9, help='enable debug') + # --debugi: see _parameter() + parser.add_argument('--fail-max', + action='store', + default=None, + help='run Verilator executable with gdb') + parser.add_argument('--gdb', action='store_true', help='run Verilator executable with gdb') + parser.add_argument('--gdbbt', + action='store_true', + help='run Verilated executable with gdb and backtrace') + parser.add_argument('--gdbsim', action='store_true', help='run Verilated executable with gdb') + parser.add_argument('--golden', '--gold', action='store_true', help='update golden .out files') + parser.add_argument('--hashset', action='store', help='split tests based on /') + parser.add_argument('--jobs', + '-j', + action='store', + default=0, + type=int, + help='parallel job count (0=cpu count)') + parser.add_argument('--quiet', + action='store_true', + help='suppress output except failures and progress') + parser.add_argument('--rerun', action='store_true', help='rerun all tests that fail') + parser.add_argument('--rr', action='store_true', help='run Verilator executable with rr') + parser.add_argument('--rrsim', action='store_true', help='run Verilated executable with rr') + parser.add_argument('--sanitize', action='store_true', help='run address sanitizer') + parser.add_argument('--site', + action='store_true', + help='include VERILATOR_TEST_SITE test list') + parser.add_argument('--stop', action='store_true', help='stop on the first error') + parser.add_argument('--trace', action='store_true', help='enable simulator waveform tracing') + parser.add_argument('--verbose', + action='store_true', + help='compile and run test in verbose mode') + parser.add_argument( + '--verilation', # -no-verilation undocumented debugging + action='store_true', + default=True, + help="don't run verilator compile() phase") + parser.add_argument('--verilated-debug', + action='store_true', + help='enable Verilated executable debug') + ## Scenarios + for scen, v in All_Scenarios.items(): + parser.add_argument('--' + scen, + dest='scenarios', + action='append_const', + const=scen, + help='scenario-enable ' + scen) + + (Args, rest) = parser.parse_known_intermixed_args() + Args.passdown_verilator_flags = [] + + for arg in rest: + _parameter(arg) + + if Args.debug: + Args.passdown_verilator_flags.append("--debug --no-skip-identical") + logging.basicConfig(level=logging.DEBUG) + logging.info("In driver.py, ARGV=" + ' '.join(sys.argv)) + + # Use Args for some global information, so gets passed to forked process + Args.interactive_debugger = Args.gdb or Args.gdbsim or Args.rr or Args.rrsim + if Args.jobs > 1 and Args.interactive_debugger: + sys.exit("%Error: Unable to use -j > 1 with --gdb* and --rr* options") + + if Args.golden: + os.environ['HARNESS_UPDATE_GOLDEN'] = '1' + if Args.jobs == 0: + Args.jobs = 1 if Args.interactive_debugger else calc_jobs() + if not Args.scenarios: + Args.scenarios = [] + Args.scenarios.append('dist') + Args.scenarios.append('vlt') + + Args.orig_argv_sw = [] + for arg in sys.argv: + if re.match(r'^-', arg) and not re.match(r'^-j$', arg): + Args.orig_argv_sw.append(arg) + + Args.test_dirs = ["t"] + if 'VERILATOR_TESTS_SITE' in os.environ: + if Args.site or len(Arg_Tests) >= 1: + for tdir in os.environ['VERILATOR_TESTS_SITE'].split(':'): + Args.test_dirs.append(tdir) + + if not Arg_Tests: # Run everything + uniq = {} + for tdir in Args.test_dirs: + # Uniquify by inode, so different paths to same place get combined + stats = os.stat(tdir) + if stats.st_ino not in uniq: + uniq[stats.st_ino] = 1 + Arg_Tests += sorted(glob.glob(tdir + "/t_*.py")) + if Args.hashset: + _calc_hashset() + + # Number of retries when reading logfiles, generally only need many + # retries when system is busy running a lot of tests + Args.log_retries = 10 if (len(Arg_Tests) > 3) else 2 + + forker = Forker(Args.jobs) + + if len(Arg_Tests) >= 2 and Args.jobs >= 2: + # Read supported into master process, so don't call every subprocess + Capabilities.warmup_cache() + # Without this tests such as t_debug_sigsegv_bt_bad.py will occasionally + # block on input and cause a SIGSTOP, then a "fg" was needed to resume testing. + print("== Many jobs; redirecting STDIN", file=sys.stderr) + # + sys.stdin = open("/dev/null", 'r', encoding="utf8") # pylint: disable=consider-using-with + + run_them() diff --git a/test_regress/t/TestVpiMain.cpp b/test_regress/t/TestVpiMain.cpp index cbd09fa85..ab368cb24 100644 --- a/test_regress/t/TestVpiMain.cpp +++ b/test_regress/t/TestVpiMain.cpp @@ -107,32 +107,22 @@ int main(int argc, char** argv) { #endif while (!contextp->gotFinish()) { - // Call registered timed callbacks (e.g. clock timer) - // These are called at the beginning of the time step - // before the iterative regions (IEEE 1800-2012 4.4.1) - VerilatedVpi::callTimedCbs(); + do { + // We must evaluate whole design until we process all 'events' for + // this time step + do { + top->eval_step(); + VerilatedVpi::clearEvalNeeded(); + VerilatedVpi::doInertialPuts(); + settle_value_callbacks(); + } while (VerilatedVpi::evalNeeded()); - // Call Value Change callbacks triggered by Timer callbacks - // These can modify signal values - settle_value_callbacks(); + // Run ReadWrite callback as we are done processing this eval step + VerilatedVpi::callCbs(cbReadWriteSynch); + VerilatedVpi::doInertialPuts(); + settle_value_callbacks(); + } while (VerilatedVpi::evalNeeded() || VerilatedVpi::hasCbs(cbReadWriteSynch)); - // We must evaluate whole design until we process all 'events' - bool again = true; - while (again) { - // Evaluate design - top->eval_step(); - - // Call Value Change callbacks triggered by eval() - // These can modify signal values - again = settle_value_callbacks(); - - // Call registered ReadWrite callbacks - again |= VerilatedVpi::callCbs(cbReadWriteSynch); - - // Call Value Change callbacks triggered by ReadWrite callbacks - // These can modify signal values - again |= settle_value_callbacks(); - } top->eval_end_step(); // Call ReadOnly callbacks @@ -161,9 +151,12 @@ int main(int argc, char** argv) { // It should be called in simulation cycle before everything else // but not on first cycle VerilatedVpi::callCbs(cbNextSimTime); + settle_value_callbacks(); - // Call Value Change callbacks triggered by NextTimeStep callbacks - // These can modify signal values + // Call registered timed callbacks (e.g. clock timer) + // These are called at the beginning of the time step + // before the iterative regions (IEEE 1800-2012 4.4.1) + VerilatedVpi::callTimedCbs(); settle_value_callbacks(); } diff --git a/test_regress/t/bootstrap.pl b/test_regress/t/bootstrap.pl deleted file mode 100755 index 564203d1e..000000000 --- a/test_regress/t/bootstrap.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -# DESCRIPTION: Verilator: Verilog Test driver bootstrapper -# -# Copyright 2008-2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# This is exec'ed by every test that is run standalone (called from the -# shell as ./t_test_name.pl) - -use FindBin; -use Cwd qw(chdir); - -my @args = @ARGV; -chdir("$FindBin::Bin/.."); -$ENV{PWD} = Cwd::getcwd(); # Else chdir leaves the .. which confuses later commands - -@args = map { s!.*test_regress/!!; $_; } @args; - -exec("./driver.pl", @args); -die "$!, in exec"; diff --git a/test_regress/t/t_EXAMPLE.pl b/test_regress/t/t_EXAMPLE.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_EXAMPLE.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_EXAMPLE.py b/test_regress/t/t_EXAMPLE.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_EXAMPLE.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v index 9693c0bee..75a416220 100644 --- a/test_regress/t/t_EXAMPLE.v +++ b/test_regress/t/t_EXAMPLE.v @@ -45,7 +45,7 @@ module t(/*AUTOARG*/ wire [63:0] result = {32'h0, out}; // Test loop - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif diff --git a/test_regress/t/t_a1_first_cc.pl b/test_regress/t/t_a1_first_cc.pl deleted file mode 100755 index e2da95eb4..000000000 --- a/test_regress/t/t_a1_first_cc.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# show-config: This test runs the very first time we've executed Verilator -# after building so we make sure to run with --gdbbt, so if it dumps we'll -# get a trace. - -scenarios(simulator => 1); - -$DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree"; - -run(cmd => ["perl", "$ENV{VERILATOR_ROOT}/bin/verilator", $DEBUG_QUIET, "-V"], - verilator_run => 1, - ); - -compile( - verilator_flags2 => [$DEBUG_QUIET, "--trace"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_a1_first_cc.py b/test_regress/t/t_a1_first_cc.py new file mode 100755 index 000000000..fd253303d --- /dev/null +++ b/test_regress/t/t_a1_first_cc.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# show-config: This test runs the very first time we've executed Verilator +# after building so we make sure to run with --gdbbt, so if it dumps we'll +# get a trace. + +import vltest_bootstrap + +test.scenarios('vlt') + +DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree" + +test.run( + cmd=[ + "perl", + os.environ["VERILATOR_ROOT"] + "/bin/verilator", # + DEBUG_QUIET, + "-V" + ], + verilator_run=True) + +test.compile(verilator_flags2=[DEBUG_QUIET, "--trace"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_a2_first_sc.pl b/test_regress/t/t_a2_first_sc.pl deleted file mode 100755 index 5a2abf87c..000000000 --- a/test_regress/t/t_a2_first_sc.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# This test runs the very first time we've executed Verilator --sc -# after building so we make sure to run with --gdbbt, so if it dumps we'll -# get a trace. - -scenarios(simulator => 1); - -top_filename("t/t_a1_first_cc.v"); - -$DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree"; - -compile( - verilator_flags2 => [$DEBUG_QUIET, "-sc --trace"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_a2_first_sc.py b/test_regress/t/t_a2_first_sc.py new file mode 100755 index 000000000..f8123f6db --- /dev/null +++ b/test_regress/t/t_a2_first_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# This test runs the very first time we've executed Verilator --sc +# after building so we make sure to run with --gdbbt, so if it dumps we'll +# get a trace. + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_a1_first_cc.v" + +DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree" + +test.compile(verilator_flags2=[DEBUG_QUIET, "-sc --trace"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_a3_selftest.pl b/test_regress/t/t_a3_selftest.pl deleted file mode 100755 index a0a71531c..000000000 --- a/test_regress/t/t_a3_selftest.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_EXAMPLE.v"); - -compile( - verilator_flags2 => ['--debug-self-test'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_a3_selftest.py b/test_regress/t/t_a3_selftest.py new file mode 100755 index 000000000..dc4bcb78f --- /dev/null +++ b/test_regress/t/t_a3_selftest.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_EXAMPLE.v" + +test.compile(verilator_flags2=['--debug-self-test'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.passes() diff --git a/test_regress/t/t_a3_selftest_thread.pl b/test_regress/t/t_a3_selftest_thread.pl deleted file mode 100755 index a47da043c..000000000 --- a/test_regress/t/t_a3_selftest_thread.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_EXAMPLE.v"); - -lint( - v_flags => ["--lint-only --verilate-jobs 2 --debug-self-test"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_a3_selftest_thread.py b/test_regress/t/t_a3_selftest_thread.py new file mode 100755 index 000000000..6f8a00043 --- /dev/null +++ b/test_regress/t/t_a3_selftest_thread.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_EXAMPLE.v" + +test.lint(v_flags=["--lint-only --verilate-jobs 2 --debug-self-test"]) + +test.passes() diff --git a/test_regress/t/t_a5_attributes_include.pl b/test_regress/t/t_a5_attributes_include.pl deleted file mode 100755 index 3ae096f50..000000000 --- a/test_regress/t/t_a5_attributes_include.pl +++ /dev/null @@ -1,49 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); -rerunnable(0); - -my $root = ".."; - -if ($ENV{VERILATOR_TEST_NO_ATTRIBUTES}) { - skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES"); -} elsif (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - check(); -} -sub check { - my $root = ".."; - # some of the files are only used in Verilation - # and are only in "include" folder - my @srcfiles = glob("$root/include/*.cpp"); - my $srcfiles_str = join(" ", @srcfiles); - my $clang_args = "-I$root/include/ -I$root/include/vltstd/ -fcoroutines-ts"; - - sub run_clang_check { - { - my $cmd = qq{python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";}; - print "\t$cmd\n" if $::Debug; - my $out = `$cmd`; - if (!$out || $out !~ /Clang imported/) { skip("No libclang installed\n"); return 1; } - } - run(logfile => $Self->{run_log_filename}, - tee => 1, - cmd => ["python3", "$root/nodist/clang_check_attributes --verilator-root=$root --cxxflags='$clang_args' $srcfiles_str"]); - - file_grep($Self->{run_log_filename}, "Number of functions reported unsafe: 0"); - } - - run_clang_check(); -} - -ok(1); -1; diff --git a/test_regress/t/t_a5_attributes_include.py b/test_regress/t/t_a5_attributes_include.py new file mode 100755 index 000000000..730a6d447 --- /dev/null +++ b/test_regress/t/t_a5_attributes_include.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') +test.rerunnable = False + +root = ".." + + +def have_clang_check(): + cmd = 'python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";' + if test.verbose: + print("\t" + cmd) + nout = test.run_capture(cmd, check=False) + if not nout or not re.search(r'Clang imported', nout): + return False + return True + + +if 'VERILATOR_TEST_NO_ATTRIBUTES' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES") +if not os.path.exists(root + "/src/obj_dbg/compile_commands.json"): + test.skip("compile_commands.json not found. Please install 'bear > 3.0' and rebuild Verilator") +if not have_clang_check(): + test.skip("No libclang installed\n") + +# some of the files are only used in Verilation +# and are only in "include" folder +srcfiles = test.glob_some(root + "/include/*.cpp") +srcfiles_str = " ".join(srcfiles) +clang_args = "-I" + root + "/include/ -I" + root + "/include/vltstd/ -fcoroutines-ts" + +test.run(logfile=test.run_log_filename, + tee=True, + cmd=["python3", root + "/nodist/clang_check_attributes", + "--verilator-root=" + root, + "--cxxflags='" + clang_args + "'", + srcfiles_str]) # yapf:disable + +test.file_grep(test.run_log_filename, r'Number of functions reported unsafe: +(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_a5_attributes_src.pl b/test_regress/t/t_a5_attributes_src.pl deleted file mode 100755 index df7f4d841..000000000 --- a/test_regress/t/t_a5_attributes_src.pl +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); -rerunnable(0); -my $root = ".."; -if ($ENV{VERILATOR_TEST_NO_ATTRIBUTES}) { - skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES"); -} elsif (! -e "$root/src/obj_dbg/compile_commands.json") { - skip("compile_commands.json not found. Please install 'bear > 3.0' and rebuild Verilator."); -} else { - check(); -} -sub check { - # some of the files are only used in Verilation - # and are only in "include" folder - my @srcfiles = grep { !/\/(V3Const|Vlc\w*|\w*_test|\w*_sc|\w*.yy).cpp$/ } - glob("$root/src/*.cpp $root/src/obj_dbg/V3Const__gen.cpp"); - my $srcfiles_str = join(" ", @srcfiles); - - sub run_clang_check { - { - my $cmd = qq{python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";}; - print "\t$cmd\n" if $::Debug; - my $out = `$cmd`; - if (!$out || $out !~ /Clang imported/) { skip("No libclang installed\n"); return 1; } - } - run(logfile => $Self->{run_log_filename}, - tee => 1, - cmd => ["python3", - "$root/nodist/clang_check_attributes", - "--verilator-root=$root", - "--compilation-root=$root/src/obj_dbg", - "--compile-commands-dir=$root/src/obj_dbg", - "$srcfiles_str"]); - - file_grep($Self->{run_log_filename}, "Number of functions reported unsafe: 0"); - } - - run_clang_check(); -} - -ok(1); -1; diff --git a/test_regress/t/t_a5_attributes_src.py b/test_regress/t/t_a5_attributes_src.py new file mode 100755 index 000000000..3c55ea4e2 --- /dev/null +++ b/test_regress/t/t_a5_attributes_src.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') +test.rerunnable = False + +root = ".." + + +def have_clang_check(): + cmd = 'python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";' + if test.verbose: + print("\t" + cmd) + nout = test.run_capture(cmd, check=False) + if not nout or not re.search(r'Clang imported', nout): + return False + return True + + +if 'VERILATOR_TEST_NO_ATTRIBUTES' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES") +if not os.path.exists(root + "/src/obj_dbg/compile_commands.json"): + test.skip("compile_commands.json not found. Please install 'bear > 3.0' and rebuild Verilator") +if not have_clang_check(): + test.skip("No libclang installed\n") + +# some of the files are only used in Verilation +# and are only in "include" folder +srcfiles = test.glob_some(root + "/src/*.cpp") + test.glob_some(root + + "/src/obj_dbg/V3Const__gen.cpp") +srcfiles = [f for f in srcfiles if re.search(r'\/(V3Const|Vlc\w*|\w*_test|\w*_sc|\w*.yy).cpp$', f)] +srcfiles_str = " ".join(srcfiles) + +test.run(logfile=test.run_log_filename, + tee=True, + cmd=["python3", root + "/nodist/clang_check_attributes", + "--verilator-root=" + root, + "--compilation-root=" + root + "/src/obj_dbg", + "--compile-commands-dir=" + root + "/src/obj_dbg", + srcfiles_str]) # yapf:disable + +test.file_grep(test.run_log_filename, r'Number of functions reported unsafe: +(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_a6_examples.pl b/test_regress/t/t_a6_examples.pl deleted file mode 100755 index c2b374144..000000000 --- a/test_regress/t/t_a6_examples.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -$Self->{clean_command} = 'rm -rf ../examples/*/build ../examples/*/obj*'; - -my @examples = sort(glob("../examples/*")); -for my $example (@examples) { - run(cmd => ["$ENV{MAKE} -C $example"]); -} - -ok(1); -1; diff --git a/test_regress/t/t_a6_examples.py b/test_regress/t/t_a6_examples.py new file mode 100755 index 000000000..8d2bb7005 --- /dev/null +++ b/test_regress/t/t_a6_examples.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.clean_command = '/bin/rm -rf ../examples/*/build ../examples/*/obj*' + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +examples = sorted(test.glob_some(root + "/examples/*")) +for example in examples: + test.run(cmd=[os.environ["MAKE"], "-C", example]) + +test.passes() diff --git a/test_regress/t/t_a7_hier_block_cmake.py b/test_regress/t/t_a7_hier_block_cmake.py new file mode 100755 index 000000000..508e8b999 --- /dev/null +++ b/test_regress/t/t_a7_hier_block_cmake.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import multiprocessing + +# If a test fails, broken .cmake may disturb the next run +test.clean_objs() + +test.scenarios('simulator') +test.top_filename = "t/t_hier_block.v" + +threads = ('-DTEST_THREADS=6' if test.vltmt else '-DTEST_THREADS=1') + +if not test.have_cmake: + test.skip("Test requires CMake; ignore error since not available or version too old") + +test.run(logfile=test.obj_dir + "/cmake.log", + cmd=[ + 'cd "' + test.obj_dir + '" && cmake ' + test.t_dir + '/t_hier_block_cmake', + "-DCMAKE_PREFIX_PATH=" + os.environ["VERILATOR_ROOT"], threads + ]) + +test.run(logfile=test.obj_dir + "/build.log", + cmd=[ + 'cd "' + test.obj_dir + '" && cmake --build', '.', ('-v' if test.verbose else ''), + '-j ' + str(multiprocessing.cpu_count()), '--', "CXX_FLAGS=" + str(threads) + ]) + +test.run(logfile=test.obj_dir + "/run.log", + cmd=['cd "' + test.obj_dir + '" && ./t_hier_block_cmake', '.']) + +target_dir = test.obj_dir + '/CMakeFiles/t_hier_block_cmake.dir/Vt_hier_block.dir/' +test.file_grep(target_dir + 'Vsub0/sub0.sv', r'^module\s+(\S+)\s+', "sub0") +test.file_grep(target_dir + 'Vsub1/sub1.sv', r'^module\s+(\S+)\s+', "sub1") +test.file_grep(target_dir + 'Vsub2/sub2.sv', r'^module\s+(\S+)\s+', "sub2") +test.file_grep(target_dir + 'Vt_hier_block__stats.txt', + r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.obj_dir + '/run.log', r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_alias2_unsup.pl b/test_regress/t/t_alias2_unsup.pl deleted file mode 100755 index 06b988a99..000000000 --- a/test_regress/t/t_alias2_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alias2_unsup.py b/test_regress/t/t_alias2_unsup.py new file mode 100755 index 000000000..272fc1280 --- /dev/null +++ b/test_regress/t/t_alias2_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_alias_unsup.pl b/test_regress/t/t_alias_unsup.pl deleted file mode 100755 index 06b988a99..000000000 --- a/test_regress/t/t_alias_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alias_unsup.py b/test_regress/t/t_alias_unsup.py new file mode 100755 index 000000000..272fc1280 --- /dev/null +++ b/test_regress/t/t_alias_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_abs.pl b/test_regress/t/t_altera_lpm_abs.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_abs.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_abs.py b/test_regress/t/t_altera_lpm_abs.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_abs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_add_sub.pl b/test_regress/t/t_altera_lpm_add_sub.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_add_sub.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_add_sub.py b/test_regress/t/t_altera_lpm_add_sub.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_add_sub.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_and.pl b/test_regress/t/t_altera_lpm_and.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_and.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_and.py b/test_regress/t/t_altera_lpm_and.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_and.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_bustri.pl b/test_regress/t/t_altera_lpm_bustri.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_bustri.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_bustri.py b/test_regress/t/t_altera_lpm_bustri.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_bustri.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_clshift.pl b/test_regress/t/t_altera_lpm_clshift.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_clshift.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_clshift.py b/test_regress/t/t_altera_lpm_clshift.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_clshift.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_compare.pl b/test_regress/t/t_altera_lpm_compare.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_compare.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_compare.py b/test_regress/t/t_altera_lpm_compare.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_constant.pl b/test_regress/t/t_altera_lpm_constant.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_constant.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_constant.py b/test_regress/t/t_altera_lpm_constant.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_constant.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_counter.pl b/test_regress/t/t_altera_lpm_counter.pl deleted file mode 100755 index 3f4aa0eed..000000000 --- a/test_regress/t/t_altera_lpm_counter.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}", "--binary --no-timing"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_counter.py b/test_regress/t/t_altera_lpm_counter.py new file mode 100755 index 000000000..8863b8607 --- /dev/null +++ b/test_regress/t/t_altera_lpm_counter.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module, "--binary --no-timing"]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_decode.pl b/test_regress/t/t_altera_lpm_decode.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_decode.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_decode.py b/test_regress/t/t_altera_lpm_decode.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_decode.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_divide.pl b/test_regress/t/t_altera_lpm_divide.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_divide.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_divide.py b/test_regress/t/t_altera_lpm_divide.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_divide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_ff.pl b/test_regress/t/t_altera_lpm_ff.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_ff.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_ff.py b/test_regress/t/t_altera_lpm_ff.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_ff.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_fifo.pl b/test_regress/t/t_altera_lpm_fifo.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_fifo.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_fifo.py b/test_regress/t/t_altera_lpm_fifo.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_fifo.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_fifo_dc.pl b/test_regress/t/t_altera_lpm_fifo_dc.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_fifo_dc.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_fifo_dc.py b/test_regress/t/t_altera_lpm_fifo_dc.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_fifo_dc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_inv.pl b/test_regress/t/t_altera_lpm_inv.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_inv.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_inv.py b/test_regress/t/t_altera_lpm_inv.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_inv.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_latch.pl b/test_regress/t/t_altera_lpm_latch.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_latch.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_latch.py b/test_regress/t/t_altera_lpm_latch.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_latch.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_mult.pl b/test_regress/t/t_altera_lpm_mult.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_mult.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_mult.py b/test_regress/t/t_altera_lpm_mult.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_mult.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_mult_noinl.pl b/test_regress/t/t_altera_lpm_mult_noinl.pl deleted file mode 100755 index 63f8aa315..000000000 --- a/test_regress/t/t_altera_lpm_mult_noinl.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; -$module =~ s/_noinl//; - -compile( - verilator_flags2 => ["--top-module ${module}", "-fno-inline"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_mult_noinl.py b/test_regress/t/t_altera_lpm_mult_noinl.py new file mode 100755 index 000000000..82c1fef6a --- /dev/null +++ b/test_regress/t/t_altera_lpm_mult_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) +module = re.sub(r'_noinl', '', module) + +test.compile(verilator_flags2=["--top-module", module, "-fno-inline"]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_mux.pl b/test_regress/t/t_altera_lpm_mux.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_mux.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_mux.py b/test_regress/t/t_altera_lpm_mux.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_mux.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_or.pl b/test_regress/t/t_altera_lpm_or.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_or.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_or.py b/test_regress/t/t_altera_lpm_or.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_or.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_ram_dp.pl b/test_regress/t/t_altera_lpm_ram_dp.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_ram_dp.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_ram_dp.py b/test_regress/t/t_altera_lpm_ram_dp.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_ram_dp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_ram_dq.pl b/test_regress/t/t_altera_lpm_ram_dq.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_ram_dq.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_ram_dq.py b/test_regress/t/t_altera_lpm_ram_dq.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_ram_dq.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_ram_io.pl b/test_regress/t/t_altera_lpm_ram_io.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_ram_io.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_ram_io.py b/test_regress/t/t_altera_lpm_ram_io.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_ram_io.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_rom.pl b/test_regress/t/t_altera_lpm_rom.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_rom.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_rom.py b/test_regress/t/t_altera_lpm_rom.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_rom.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_shiftreg.pl b/test_regress/t/t_altera_lpm_shiftreg.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_shiftreg.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_shiftreg.py b/test_regress/t/t_altera_lpm_shiftreg.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_shiftreg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_xor.pl b/test_regress/t/t_altera_lpm_xor.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_xor.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_xor.py b/test_regress/t/t_altera_lpm_xor.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_xor.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_alw_combdly.pl b/test_regress/t/t_alw_combdly.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_alw_combdly.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_combdly.py b/test_regress/t/t_alw_combdly.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_alw_combdly.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_dly.pl b/test_regress/t/t_alw_dly.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_alw_dly.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_dly.py b/test_regress/t/t_alw_dly.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_alw_dly.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_noreorder.pl b/test_regress/t/t_alw_noreorder.pl deleted file mode 100755 index c30d624bd..000000000 --- a/test_regress/t/t_alw_noreorder.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_alw_reorder.v"); -compile( - verilator_flags2 => ["--stats -fno-reorder"], - ); - -file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); -# Here we should see some dly vars since reorder is disabled. -# (Whereas our twin test, t_alw_reorder, should see no dly vars -# since it enables the reorder step.) -my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root*.cpp"); -file_grep_any(\@files, qr/dly__t__DOT__v1/i); -file_grep_any(\@files, qr/dly__t__DOT__v2/i); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_noreorder.py b/test_regress/t/t_alw_noreorder.py new file mode 100755 index 000000000..a64bbc380 --- /dev/null +++ b/test_regress/t/t_alw_noreorder.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_alw_reorder.v" +test.compile(verilator_flags2=["--stats -fno-reorder"]) + +test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 0) +# Here we should see some dly vars since reorder is disabled. +# (Whereas our twin test, t_alw_reorder, should see no dly vars +# since it enables the reorder step.) +files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root*.cpp") +test.file_grep_any(files, r'dly__t__DOT__v1') +test.file_grep_any(files, r'dly__t__DOT__v2') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_nosplit.pl b/test_regress/t/t_alw_nosplit.pl deleted file mode 100755 index a1d66aaad..000000000 --- a/test_regress/t/t_alw_nosplit.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_nosplit.py b/test_regress/t/t_alw_nosplit.py new file mode 100755 index 000000000..e719df544 --- /dev/null +++ b/test_regress/t/t_alw_nosplit.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 0) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_reorder.pl b/test_regress/t/t_alw_reorder.pl deleted file mode 100755 index 0c855076f..000000000 --- a/test_regress/t/t_alw_reorder.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); -# Important: if reorder succeeded, we should see no dly vars. -# Equally important: twin test t_alw_noreorder should see dly vars, -# is identical to this test except for disabling the reorder step. -foreach my $file ( - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.h"), - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp") - ) { - file_grep_not($file, qr/dly__t__DOT__v1/i); - file_grep_not($file, qr/dly__t__DOT__v2/i); - file_grep_not($file, qr/dly__t__DOT__v3/i); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_reorder.py b/test_regress/t/t_alw_reorder.py new file mode 100755 index 000000000..d61a33150 --- /dev/null +++ b/test_regress/t/t_alw_reorder.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats"]) + +test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 0) + +# Important: if reorder succeeded, we should see no dly vars. +# Equally important: twin test t_alw_noreorder should see dly vars, +# is identical to this test except for disabling the reorder step. +for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): + test.file_grep_not(filename, r'dly__t__DOT__v1') + test.file_grep_not(filename, r'dly__t__DOT__v2') + test.file_grep_not(filename, r'dly__t__DOT__v3') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_split.pl b/test_regress/t/t_alw_split.pl deleted file mode 100755 index 7b60fb6fc..000000000 --- a/test_regress/t/t_alw_split.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 4); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_split.py b/test_regress/t/t_alw_split.py new file mode 100755 index 000000000..08fff24cc --- /dev/null +++ b/test_regress/t/t_alw_split.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 4) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_split_cond.pl b/test_regress/t/t_alw_split_cond.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_alw_split_cond.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_split_cond.py b/test_regress/t/t_alw_split_cond.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_alw_split_cond.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_alw_split_rst.pl b/test_regress/t/t_alw_split_rst.pl deleted file mode 100755 index fe393b88e..000000000 --- a/test_regress/t/t_alw_split_rst.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats", - $Self->wno_unopthreads_for_few_cores()] - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 12); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_split_rst.py b/test_regress/t/t_alw_split_rst.py new file mode 100755 index 000000000..f801e0883 --- /dev/null +++ b/test_regress/t/t_alw_split_rst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats", test.wno_unopthreads_for_few_cores]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 12) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_splitord.pl b/test_regress/t/t_alw_splitord.pl deleted file mode 100755 index 972bb3672..000000000 --- a/test_regress/t/t_alw_splitord.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 5); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_splitord.py b/test_regress/t/t_alw_splitord.py new file mode 100755 index 000000000..0324c5dd2 --- /dev/null +++ b/test_regress/t/t_alw_splitord.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 5) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_backw_index_bad.pl b/test_regress/t/t_array_backw_index_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_array_backw_index_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_backw_index_bad.py b/test_regress/t/t_array_backw_index_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_array_backw_index_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_compare.pl b/test_regress/t/t_array_compare.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_array_compare.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_compare.py b/test_regress/t/t_array_compare.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_compare.v b/test_regress/t/t_array_compare.v index 116bbf1d1..6ed1468d1 100644 --- a/test_regress/t/t_array_compare.v +++ b/test_regress/t/t_array_compare.v @@ -6,11 +6,7 @@ // bug1071 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); reg [3:0] array_1 [2:0]; reg [3:0] array_2 [2:0]; diff --git a/test_regress/t/t_array_in_struct.pl b/test_regress/t/t_array_in_struct.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_array_in_struct.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_in_struct.py b/test_regress/t/t_array_in_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_in_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_index_increment.pl b/test_regress/t/t_array_index_increment.pl deleted file mode 100755 index beaa2ca59..000000000 --- a/test_regress/t/t_array_index_increment.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_index_increment.py b/test_regress/t/t_array_index_increment.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_index_increment.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_index_increment.v b/test_regress/t/t_array_index_increment.v index 8d89223fa..89adc33a2 100644 --- a/test_regress/t/t_array_index_increment.v +++ b/test_regress/t/t_array_index_increment.v @@ -4,11 +4,7 @@ // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); string test_string = "abcd"; diff --git a/test_regress/t/t_array_list_bad.pl b/test_regress/t/t_array_list_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_array_list_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_list_bad.py b/test_regress/t/t_array_list_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_array_list_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_mda.pl b/test_regress/t/t_array_mda.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_array_mda.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_mda.py b/test_regress/t/t_array_mda.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_mda.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_method.pl b/test_regress/t/t_array_method.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_array_method.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_method.py b/test_regress/t/t_array_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_method_bad.pl b/test_regress/t/t_array_method_bad.pl deleted file mode 100755 index c65314f7b..000000000 --- a/test_regress/t/t_array_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_method_bad.py b/test_regress/t/t_array_method_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_array_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_method_map.pl b/test_regress/t/t_array_method_map.pl deleted file mode 100755 index bd07fc421..000000000 --- a/test_regress/t/t_array_method_map.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_array_method_map.py b/test_regress/t/t_array_method_map.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_array_method_map.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_array_method_unsup.pl b/test_regress/t/t_array_method_unsup.pl deleted file mode 100755 index bd07fc421..000000000 --- a/test_regress/t/t_array_method_unsup.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_array_method_unsup.py b/test_regress/t/t_array_method_unsup.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_array_method_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_array_packed_endian.pl b/test_regress/t/t_array_packed_endian.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_array_packed_endian.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_packed_endian.py b/test_regress/t/t_array_packed_endian.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_packed_endian.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_packed_sysfunct.pl b/test_regress/t/t_array_packed_sysfunct.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_array_packed_sysfunct.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_packed_sysfunct.py b/test_regress/t/t_array_packed_sysfunct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_packed_sysfunct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_packed_write_read.pl b/test_regress/t/t_array_packed_write_read.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_array_packed_write_read.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_packed_write_read.py b/test_regress/t/t_array_packed_write_read.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_packed_write_read.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_pattern_2d.pl b/test_regress/t/t_array_pattern_2d.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_array_pattern_2d.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_2d.py b/test_regress/t/t_array_pattern_2d.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_pattern_2d.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_pattern_bad.pl b/test_regress/t/t_array_pattern_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_array_pattern_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_bad.py b/test_regress/t/t_array_pattern_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_array_pattern_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_pattern_bad2.pl b/test_regress/t/t_array_pattern_bad2.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_array_pattern_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_bad2.py b/test_regress/t/t_array_pattern_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_array_pattern_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_pattern_bad3.pl b/test_regress/t/t_array_pattern_bad3.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_array_pattern_bad3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_bad3.py b/test_regress/t/t_array_pattern_bad3.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_array_pattern_bad3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_pattern_enum.py b/test_regress/t/t_array_pattern_enum.py new file mode 100755 index 000000000..4ac3b843d --- /dev/null +++ b/test_regress/t/t_array_pattern_enum.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.skip('Needs clang fix') + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_pattern_enum.v b/test_regress/t/t_array_pattern_enum.v new file mode 100644 index 000000000..8581a1cee --- /dev/null +++ b/test_regress/t/t_array_pattern_enum.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +package Pkg; + typedef enum { + RED=0, + GREEN=1, + BLUE=2 + } color_t; + + typedef struct { + color_t pixels[32]; + } line_t; + + typedef struct { + line_t line[32]; + } screen_t; +endpackage + +module t; + Pkg::screen_t screen; + + initial begin + screen = '{ default: '0, Pkg::color_t: Pkg::RED}; + $display("%p", screen); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_array_pattern_packed.pl b/test_regress/t/t_array_pattern_packed.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_array_pattern_packed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_packed.py b/test_regress/t/t_array_pattern_packed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_pattern_packed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_pattern_unpacked.pl b/test_regress/t/t_array_pattern_unpacked.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_array_pattern_unpacked.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_unpacked.py b/test_regress/t/t_array_pattern_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_pattern_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_query.pl b/test_regress/t/t_array_query.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_array_query.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_query.py b/test_regress/t/t_array_query.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_query.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_query_with.pl b/test_regress/t/t_array_query_with.pl deleted file mode 100755 index a86f4c404..000000000 --- a/test_regress/t/t_array_query_with.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_query_with.py b/test_regress/t/t_array_query_with.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_array_query_with.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_rev.pl b/test_regress/t/t_array_rev.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_array_rev.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_rev.py b/test_regress/t/t_array_rev.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_rev.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_type_methods.pl b/test_regress/t/t_array_type_methods.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_array_type_methods.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_type_methods.py b/test_regress/t/t_array_type_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_type_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_type_methods.v b/test_regress/t/t_array_type_methods.v index 80875aaf0..f6dd39d8b 100644 --- a/test_regress/t/t_array_type_methods.v +++ b/test_regress/t/t_array_type_methods.v @@ -6,13 +6,9 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); logic [3:0] foo [1:0]; logic [3:0] fooe [1:0]; diff --git a/test_regress/t/t_array_unpacked_public.pl b/test_regress/t/t_array_unpacked_public.pl deleted file mode 100755 index a45993904..000000000 --- a/test_regress/t/t_array_unpacked_public.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--public-flat-rw"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_unpacked_public.py b/test_regress/t/t_array_unpacked_public.py new file mode 100755 index 000000000..31843bd7b --- /dev/null +++ b/test_regress/t/t_array_unpacked_public.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--public-flat-rw"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_arraysel_wide.pl b/test_regress/t/t_arraysel_wide.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_arraysel_wide.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_arraysel_wide.py b/test_regress/t/t_arraysel_wide.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_arraysel_wide.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_assert_basic.pl b/test_regress/t/t_assert_basic.pl deleted file mode 100755 index 59aeed76c..000000000 --- a/test_regress/t/t_assert_basic.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_basic.py b/test_regress/t/t_assert_basic.py new file mode 100755 index 000000000..d97aaff01 --- /dev/null +++ b/test_regress/t/t_assert_basic.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_basic_cover.pl b/test_regress/t/t_assert_basic_cover.pl deleted file mode 100755 index 245e17e68..000000000 --- a/test_regress/t/t_assert_basic_cover.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_basic.v"); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user'], - ); - -execute( - check_finished => 1, - ); - -#Needs work -print "-Info: NOT checking for coverage\n"; -#file_grep($Self->{coverage_filename}, qr/t=>'psl_cover',o=>'cover',c=>2\);/); -#file_grep($Self->{coverage_filename}, qr/DefaultClock.*,c=>1\);/); -#file_grep($Self->{coverage_filename}, qr/ToggleLogIf.*,c=>9\);/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_basic_cover.py b/test_regress/t/t_assert_basic_cover.py new file mode 100755 index 000000000..045f31a9c --- /dev/null +++ b/test_regress/t/t_assert_basic_cover.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_basic.v" + +test.compile(verilator_flags2=['--assert --cc --coverage-user']) + +test.execute() + +#Needs work +print("-Info: NOT checking for coverage") +#test.file_grep(test.coverage_filename, r't=>'psl_cover',o=>'cover',c=>2\);') +#test.file_grep(test.coverage_filename, r'DefaultClock.*,c=>1\);') +#test.file_grep(test.coverage_filename, r'ToggleLogIf.*,c=>9\);') + +test.passes() diff --git a/test_regress/t/t_assert_basic_fail.pl b/test_regress/t/t_assert_basic_fail.pl deleted file mode 100755 index 6e51b415d..000000000 --- a/test_regress/t/t_assert_basic_fail.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_basic.v"); - -compile( - v_flags2 => ['+define+FAILING_ASSERTIONS', - ($Self->{vlt_all} ? '--assert' - : ($Self->{nc} ? '+assert' : ''))], - fails => $Self->{nc}, - ); - -execute( - fails => $Self->{vlt_all}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_basic_fail.py b/test_regress/t/t_assert_basic_fail.py new file mode 100755 index 000000000..08961e17e --- /dev/null +++ b/test_regress/t/t_assert_basic_fail.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_basic.v" + +test.compile(v_flags2=[ + '+define+FAILING_ASSERTIONS', ('--assert' if test.vlt_all else ('+assert' if test.nc else '')) +], + fails=test.nc) + +test.execute(fails=test.vlt_all) + +test.passes() diff --git a/test_regress/t/t_assert_basic_off.pl b/test_regress/t/t_assert_basic_off.pl deleted file mode 100755 index 15cc14b28..000000000 --- a/test_regress/t/t_assert_basic_off.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_basic.v"); - -compile( - v_flags2 => [], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_basic_off.py b/test_regress/t/t_assert_basic_off.py new file mode 100755 index 000000000..cd9e8e0c5 --- /dev/null +++ b/test_regress/t/t_assert_basic_off.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_basic.v" + +test.compile(v_flags2=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_casez.pl b/test_regress/t/t_assert_casez.pl deleted file mode 100755 index b3a7f940f..000000000 --- a/test_regress/t/t_assert_casez.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_casez.py b/test_regress/t/t_assert_casez.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_casez.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_clock_event_unsup.pl b/test_regress/t/t_assert_clock_event_unsup.pl deleted file mode 100755 index 1e3627720..000000000 --- a/test_regress/t/t_assert_clock_event_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_clock_event_unsup.py b/test_regress/t/t_assert_clock_event_unsup.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_clock_event_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_comp.pl b/test_regress/t/t_assert_comp.pl deleted file mode 100755 index 59aeed76c..000000000 --- a/test_regress/t/t_assert_comp.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_comp.py b/test_regress/t/t_assert_comp.py new file mode 100755 index 000000000..d97aaff01 --- /dev/null +++ b/test_regress/t/t_assert_comp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_comp_bad.pl b/test_regress/t/t_assert_comp_bad.pl deleted file mode 100755 index 3bc6896ac..000000000 --- a/test_regress/t/t_assert_comp_bad.pl +++ /dev/null @@ -1,68 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - vcs_flags2 => ['-assert svaext'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_USERWARN_faulty.rst", - regexp => qr/\$warn.*User/); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_USERERROR_faulty.rst", - regexp => qr/\$error.*User/); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_USERINFO_faulty.rst", - regexp => qr/\$info.*User/); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_USERFATAL_faulty.rst", - regexp => qr/\$fatal.*User/); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_USERWARN_msg.rst", - regexp => qr/USERWARN:.* User/); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_USERERROR_msg.rst", - regexp => qr/USERERROR:.* User/); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_USERINFO_msg.rst", - regexp => qr/-Info:.* User/); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_USERFATAL_msg.rst", - regexp => qr/USERFATAL:.* User/); -} - -ok(1); -1; diff --git a/test_regress/t/t_assert_comp_bad.py b/test_regress/t/t_assert_comp_bad.py new file mode 100755 index 000000000..12cec4f93 --- /dev/null +++ b/test_regress/t/t_assert_comp_bad.py @@ -0,0 +1,57 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.compile(verilator_flags2=['--assert'], + nc_flags2=['+assert'], + vcs_flags2=['-assert svaext'], + fails=True, + expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_USERWARN_faulty.rst", + regexp=r'\$warn.*User') + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_USERERROR_faulty.rst", + regexp=r'\$error.*User') + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_USERINFO_faulty.rst", + regexp=r'\$info.*User') + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_USERFATAL_faulty.rst", + regexp=r'\$fatal.*User') + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_USERWARN_msg.rst", + regexp=r'USERWARN:.* User') + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_USERERROR_msg.rst", + regexp=r'USERERROR:.* User') + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_USERINFO_msg.rst", + regexp=r'-Info:.* User') + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_USERFATAL_msg.rst", + regexp=r'USERFATAL:.* User') + +test.passes() diff --git a/test_regress/t/t_assert_cover.pl b/test_regress/t/t_assert_cover.pl deleted file mode 100755 index 0ea346fe6..000000000 --- a/test_regress/t/t_assert_cover.pl +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_cover.v"); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user'], - nc_flags2 => ["+nccovoverwrite +nccoverage+all +nccovtest+$Self->{name}"] - ); - -execute( - check_finished => 1, - ); - -if ($Self->{nc}) { - my $name = $Self->{name}; - my $cf = "$Self->{obj_dir}/${name}__nccover.cf"; - { - my $fh = IO::File->new(">$cf") or die "%Error: $! writing $cf,"; - $fh->printf("report_summary -module *\n"); - $fh->printf("report_detail -both -instance *\n"); - $fh->printf("report_html -both -instance * > $Self->{obj_dir}/${name}__nccover.html\n"); - $fh->close; - } - run(logfile => "$Self->{obj_dir}/${name}__nccover.log", - tee => 0, - cmd => [($ENV{VERILATOR_ICCR} || 'iccr'), - "-test ${name} ${cf}"]); -} - -file_grep($Self->{run_log_filename}, qr/COVER: Cyc==4/); -file_grep($Self->{run_log_filename}, qr/COVER: Cyc==5/); -file_grep($Self->{run_log_filename}, qr/COVER: Cyc==6/); - -# Allow old SystemC::Coverage format dump, or new binary dump -file_grep($Self->{coverage_filename}, qr/(cyc_eq_5.*,c=>[^0]|cyc_eq_5.* [1-9][0-9]*\n)/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_cover.py b/test_regress/t/t_assert_cover.py new file mode 100755 index 000000000..4c62fcc22 --- /dev/null +++ b/test_regress/t/t_assert_cover.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_cover.v" + +test.compile(verilator_flags2=['--assert --cc --coverage-user'], + nc_flags2=["+nccovoverwrite +nccoverage+all +nccovtest+" + test.name]) + +test.execute() + +if test.nc: + cf = test.obj_dir + "/" + test.name + "__nccover.cf" + + with open(cf, 'w', encoding="utf8") as fh: + fh.write("report_summary -module *\n") + fh.write("report_detail -both -instance *\n") + fh.write("report_html -both -instance * > " + test.obj_dir + "/" + test.name + + "__nccover.html\n") + + test.run(logfile=test.obj_dir + "/" + test.name + "__nccover.log", + tee=False, + cmd=[test.getenv_def("VERILATOR_ICCR", 'iccr'), "-test", test.name, cf]) + +test.file_grep(test.run_log_filename, r'COVER: Cyc==4') +test.file_grep(test.run_log_filename, r'COVER: Cyc==5') +test.file_grep(test.run_log_filename, r'COVER: Cyc==6') + +# Allow old SystemC::Coverage format dump, or new binary dump +test.file_grep(test.coverage_filename, r'(cyc_eq_5.*,c=>[^0]|cyc_eq_5.* [1-9][0-9]*\n)') + +test.passes() diff --git a/test_regress/t/t_assert_cover_off.pl b/test_regress/t/t_assert_cover_off.pl deleted file mode 100755 index 3f40bb5e8..000000000 --- a/test_regress/t/t_assert_cover_off.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_cover.v"); - -compile( - v_flags2 => [], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_cover_off.py b/test_regress/t/t_assert_cover_off.py new file mode 100755 index 000000000..356558121 --- /dev/null +++ b/test_regress/t/t_assert_cover_off.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_cover.v" + +test.compile(v_flags2=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_ctl_arg.out b/test_regress/t/t_assert_ctl_arg.out index ea70da0f3..61360e55d 100644 --- a/test_regress/t/t_assert_ctl_arg.out +++ b/test_regress/t/t_assert_ctl_arg.out @@ -2,12 +2,12 @@ Running all asserts at: t/t_assert_ctl_arg.v:49 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:49 -[0] %Error: t_assert_ctl_arg.v:135: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. --Info: t/t_assert_ctl_arg.v:135: Verilog $stop, ignored due to +verilator+error+limit +[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +-Info: t/t_assert_ctl_arg.v:137: Verilog $stop, ignored due to +verilator+error+limit Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:49 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:49 -[0] %Error: t_assert_ctl_arg.v:141: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:49 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:49 @@ -30,11 +30,11 @@ Running all asserts at: t/t_assert_ctl_arg.v:56 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:56 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:56 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:56 -[0] %Error: t_assert_ctl_arg.v:149: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:56 -[0] %Error: t_assert_ctl_arg.v:155: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:56 @@ -57,11 +57,11 @@ Testing assume_simple_immediate at t/t_assert_ctl_arg.v:63 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:63 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:63 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:63 -[0] %Error: t_assert_ctl_arg.v:163: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:63 -[0] %Error: t_assert_ctl_arg.v:169: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63 Passed 'top.t.cover_final_deferred_immediate_stmt_63' at t/t_assert_ctl_arg.v:63 @@ -87,27 +87,27 @@ Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:69 Running all asserts at: t/t_assert_ctl_arg.v:71 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:135: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:141: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:149: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:155: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:163: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:169: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Passed 'top.t.cover_simple_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 @@ -126,19 +126,19 @@ Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:73 Running all asserts at: t/t_assert_ctl_arg.v:76 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:135: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:141: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:149: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:155: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:76 @@ -149,27 +149,27 @@ Passed 'top.t.cover_observed_deferred_immediate_stmt_76' at t/t_assert_ctl_arg.v Running all asserts at: t/t_assert_ctl_arg.v:78 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:135: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:141: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:149: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:155: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:163: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:169: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Passed 'top.t.cover_simple_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 @@ -179,11 +179,11 @@ Passed 'top.t.cover_final_deferred_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 Running all asserts at: t/t_assert_ctl_arg.v:80 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:80 -[0] %Error: t_assert_ctl_arg.v:135: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:80 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:80 -[0] %Error: t_assert_ctl_arg.v:141: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:80 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:80 @@ -195,11 +195,11 @@ Passed 'top.t.cover_simple_immediate_stmt_80' at t/t_assert_ctl_arg.v:80 Running all asserts at: t/t_assert_ctl_arg.v:82 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:82 -[0] %Error: t_assert_ctl_arg.v:135: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:82 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:82 -[0] %Error: t_assert_ctl_arg.v:141: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:82 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:82 @@ -220,11 +220,11 @@ Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:84 Running all asserts at: t/t_assert_ctl_arg.v:86 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:86 -[0] %Error: t_assert_ctl_arg.v:135: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:86 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:86 -[0] %Error: t_assert_ctl_arg.v:141: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:86 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:86 @@ -245,27 +245,27 @@ Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:88 Running all asserts at: t/t_assert_ctl_arg.v:90 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:135: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:141: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:149: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:155: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:163: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:169: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Passed 'top.t.cover_simple_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 @@ -284,17 +284,17 @@ Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:92 Running all asserts at: t/t_assert_ctl_arg.v:97 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:97 -[0] %Error: t_assert_ctl_arg.v:135: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:97 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:97 -[0] %Error: t_assert_ctl_arg.v:149: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:97 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:97 -[0] %Error: t_assert_ctl_arg.v:163: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:97 @@ -315,34 +315,34 @@ Running all asserts at: t/t_assert_ctl_arg.v:103 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:103 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:103 -[0] %Error: t_assert_ctl_arg.v:141: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:103 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:103 -[0] %Error: t_assert_ctl_arg.v:155: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:103 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:103 -[0] %Error: t_assert_ctl_arg.v:169: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 ========== Running all asserts at: t/t_assert_ctl_arg.v:106 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:106 -[0] %Error: t_assert_ctl_arg.v:135: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:106 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:106 -[0] %Error: t_assert_ctl_arg.v:149: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:106 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:106 -[0] %Error: t_assert_ctl_arg.v:163: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:106 @@ -353,27 +353,27 @@ Passed 'top.t.cover_final_deferred_immediate_stmt_106' at t/t_assert_ctl_arg.v:1 Running all asserts at: t/t_assert_ctl_arg.v:108 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:135: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:141: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:149: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:155: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:163: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:169: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Passed 'top.t.cover_simple_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 @@ -393,23 +393,24 @@ Running all asserts at: t/t_assert_ctl_arg.v:112 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:112 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:112 -[0] %Error: t_assert_ctl_arg.v:141: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:112 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:112 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:112 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:112 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:112 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:112 -[0] %Error: t_assert_ctl_arg.v:169: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:112 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:112 Passed 'top.t.cover_simple_immediate_stmt_112' at t/t_assert_ctl_arg.v:112 Passed 'top.t.cover_final_deferred_immediate_stmt_112' at t/t_assert_ctl_arg.v:112 Disabling concurrent asserts, time: 10 Enabling concurrent asserts, time: 20 -[20] %Error: t_assert_ctl_arg.v:180: Assertion failed in top.t.concurrent.assert_concurrent: 'assert' failed. -Failed 'top.t.concurrent.assert_concurrent_else' at t/t_assert_ctl_arg.v:181 -Failed 'top.t.concurrent.assert_concurrent_stmt_else' at t/t_assert_ctl_arg.v:183 -[20] %Error: t_assert_ctl_arg.v:185: Assertion failed in top.t.concurrent.assume_concurrent: 'assert' failed. -Failed 'top.t.concurrent.assume_concurrent_else' at t/t_assert_ctl_arg.v:186 -Failed 'top.t.concurrent.assume_concurrent_stmt_else' at t/t_assert_ctl_arg.v:188 +*-* All Finished *-* +[20] %Error: t_assert_ctl_arg.v:182: Assertion failed in top.t.concurrent.assert_concurrent: 'assert' failed. +Failed 'top.t.concurrent.assert_concurrent_else' at t/t_assert_ctl_arg.v:183 +Failed 'top.t.concurrent.assert_concurrent_stmt_else' at t/t_assert_ctl_arg.v:185 +[20] %Error: t_assert_ctl_arg.v:187: Assertion failed in top.t.concurrent.assume_concurrent: 'assert' failed. +Failed 'top.t.concurrent.assume_concurrent_else' at t/t_assert_ctl_arg.v:188 +Failed 'top.t.concurrent.assume_concurrent_stmt_else' at t/t_assert_ctl_arg.v:190 diff --git a/test_regress/t/t_assert_ctl_arg.pl b/test_regress/t/t_assert_ctl_arg.pl deleted file mode 100755 index c669fed5e..000000000 --- a/test_regress/t/t_assert_ctl_arg.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--assert", "--timing", "--coverage-user", "--exe $Self->{t_dir}/$Self->{name}.cpp"], - nc_flags2 => ["+nccovoverwrite", "+nccoverage+all", "+nccovtest+$Self->{name}"], - ); - -execute( - all_run_flags => ["+verilator+error+limit+100"], - expect_filename => $Self->{golden_filename}, - ); - -files_identical($Self->{coverage_filename}, "$Self->{t_dir}/t_assert_ctl_arg_coverage.out"); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_arg.py b/test_regress/t/t_assert_ctl_arg.py new file mode 100755 index 000000000..812f7c3a0 --- /dev/null +++ b/test_regress/t/t_assert_ctl_arg.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_top_shell=False, + make_main=False, + verilator_flags2=["--assert", "--timing", "--coverage-user", "--exe", test.pli_filename], + nc_flags2=["+nccovoverwrite", "+nccoverage+all", "+nccovtest+" + test.name]) + +test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.golden_filename) + +test.files_identical(test.coverage_filename, test.t_dir + "/t_assert_ctl_arg_coverage.out") + +test.passes() diff --git a/test_regress/t/t_assert_ctl_arg.v b/test_regress/t/t_assert_ctl_arg.v index 04f88ca05..c3961213e 100644 --- a/test_regress/t/t_assert_ctl_arg.v +++ b/test_regress/t/t_assert_ctl_arg.v @@ -120,6 +120,8 @@ module t (/*AUTOARG*/ #10; $display("Enabling concurrent asserts, time: %g", $time); $assertcontrol(ON, CONCURRENT); + + $write("*-* All Finished *-*\n"); $finish; end endmodule diff --git a/test_regress/t/t_assert_ctl_arg_coverage.out b/test_regress/t/t_assert_ctl_arg_coverage.out index 792a95c95..90e951eb6 100644 --- a/test_regress/t/t_assert_ctl_arg_coverage.out +++ b/test_regress/t/t_assert_ctl_arg_coverage.out @@ -35,8 +35,8 @@ C 'ft/t_assert_ctl_arg.vl112n40pagev_user/tocover_final_deferred_immed C 'ft/t_assert_ctl_arg.vl112n43pagev_user/tocover_observed_deferred_immediate_112htop.t.cover_observed_deferred_immediate_112' 0 C 'ft/t_assert_ctl_arg.vl112n45pagev_user/tocover_final_deferred_immediate_stmt_112htop.t.cover_final_deferred_immediate_stmt_112' 1 C 'ft/t_assert_ctl_arg.vl112n48pagev_user/tocover_observed_deferred_immediate_stmt_112htop.t.cover_observed_deferred_immediate_stmt_112' 0 -C 'ft/t_assert_ctl_arg.vl190n22pagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0 -C 'ft/t_assert_ctl_arg.vl191n27pagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0 +C 'ft/t_assert_ctl_arg.vl192n22pagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0 +C 'ft/t_assert_ctl_arg.vl193n27pagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0 C 'ft/t_assert_ctl_arg.vl49n31pagev_user/tocover_simple_immediate_49htop.t.cover_simple_immediate_49' 1 C 'ft/t_assert_ctl_arg.vl49n36pagev_user/tocover_simple_immediate_stmt_49htop.t.cover_simple_immediate_stmt_49' 1 C 'ft/t_assert_ctl_arg.vl49n39pagev_user/tocover_final_deferred_immediate_49htop.t.cover_final_deferred_immediate_49' 0 diff --git a/test_regress/t/t_assert_ctl_arg_noinl.pl b/test_regress/t/t_assert_ctl_arg_noinl.pl deleted file mode 100755 index 32cb9b25f..000000000 --- a/test_regress/t/t_assert_ctl_arg_noinl.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t_assert_ctl_arg.v"); -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - "--assert", "--timing", "--coverage-user", "--exe $Self->{t_dir}/t_assert_ctl_arg.cpp", "-fno-inline" - ], - nc_flags2 => ["+nccovoverwrite", "+nccoverage+all", "+nccovtest+$Self->{name}"], - ); - -execute( - all_run_flags => ["+verilator+error+limit+100"], - expect_filename => "$Self->{t_dir}/t_assert_ctl_arg.out", - ); - -files_identical($Self->{coverage_filename}, "$Self->{t_dir}/t_assert_ctl_arg_coverage.out"); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_arg_noinl.py b/test_regress/t/t_assert_ctl_arg_noinl.py new file mode 100755 index 000000000..b36df045f --- /dev/null +++ b/test_regress/t/t_assert_ctl_arg_noinl.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_assert_ctl_arg.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + "--assert", "--timing", "--coverage-user", "--exe", + test.t_dir + "/t_assert_ctl_arg.cpp", "-fno-inline" + ], + nc_flags2=["+nccovoverwrite", "+nccoverage+all", "+nccovtest+" + test.name]) + +test.execute(all_run_flags=["+verilator+error+limit+100"], + expect_filename=test.t_dir + "/t_assert_ctl_arg.out") + +test.files_identical(test.coverage_filename, test.t_dir + "/t_assert_ctl_arg_coverage.out") + +test.passes() diff --git a/test_regress/t/t_assert_ctl_arg_unsup.pl b/test_regress/t/t_assert_ctl_arg_unsup.pl deleted file mode 100755 index 147dcdcd9..000000000 --- a/test_regress/t/t_assert_ctl_arg_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_arg_unsup.py b/test_regress/t/t_assert_ctl_arg_unsup.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_assert_ctl_arg_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_ctl_concurrent.pl b/test_regress/t/t_assert_ctl_concurrent.pl deleted file mode 100755 index c82d5093e..000000000 --- a/test_regress/t/t_assert_ctl_concurrent.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing --assert"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_concurrent.py b/test_regress/t/t_assert_ctl_concurrent.py new file mode 100755 index 000000000..bf8998d5c --- /dev/null +++ b/test_regress/t/t_assert_ctl_concurrent.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing --assert"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_ctl_concurrent_noinl.pl b/test_regress/t/t_assert_ctl_concurrent_noinl.pl deleted file mode 100755 index 2339bbf25..000000000 --- a/test_regress/t/t_assert_ctl_concurrent_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t_assert_ctl_concurrent.v"); -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing --assert --fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_concurrent_noinl.py b/test_regress/t/t_assert_ctl_concurrent_noinl.py new file mode 100755 index 000000000..d96a4a589 --- /dev/null +++ b/test_regress/t/t_assert_ctl_concurrent_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_assert_ctl_concurrent.v" + +test.compile(verilator_flags2=["--exe --main --timing --assert --fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_ctl_immediate.pl b/test_regress/t/t_assert_ctl_immediate.pl deleted file mode 100755 index 55081d509..000000000 --- a/test_regress/t/t_assert_ctl_immediate.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--assert', '--timing'], - ); - -execute( - all_run_flags => ["+verilator+error+limit+100"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_immediate.py b/test_regress/t/t_assert_ctl_immediate.py new file mode 100755 index 000000000..cbd7dd9cc --- /dev/null +++ b/test_regress/t/t_assert_ctl_immediate.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--assert', '--timing']) + +test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_ctl_immediate_noinl.pl b/test_regress/t/t_assert_ctl_immediate_noinl.pl deleted file mode 100755 index 925795a67..000000000 --- a/test_regress/t/t_assert_ctl_immediate_noinl.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t_assert_ctl_immediate.v"); -golden_filename("t/t_assert_ctl_immediate.out"); -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--assert --timing --fno-inline'], - ); - -execute( - all_run_flags => ["+verilator+error+limit+100"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_immediate_noinl.py b/test_regress/t/t_assert_ctl_immediate_noinl.py new file mode 100755 index 000000000..be07788c3 --- /dev/null +++ b/test_regress/t/t_assert_ctl_immediate_noinl.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_assert_ctl_immediate.v" +test.golden_filename = "t/t_assert_ctl_immediate.out" + +test.compile(verilator_flags2=['--assert --timing --fno-inline']) + +test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_ctl_unsup.pl b/test_regress/t/t_assert_ctl_unsup.pl deleted file mode 100755 index b3b9ca877..000000000 --- a/test_regress/t/t_assert_ctl_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--assert'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_unsup.py b/test_regress/t/t_assert_ctl_unsup.py new file mode 100755 index 000000000..0275f2df9 --- /dev/null +++ b/test_regress/t/t_assert_ctl_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_disable_bad.pl b/test_regress/t/t_assert_disable_bad.pl deleted file mode 100755 index 1f68597d8..000000000 --- a/test_regress/t/t_assert_disable_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_disable_bad.py b/test_regress/t/t_assert_disable_bad.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_disable_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_disable_iff.pl b/test_regress/t/t_assert_disable_iff.pl deleted file mode 100755 index 63d2a42a6..000000000 --- a/test_regress/t/t_assert_disable_iff.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_disable_iff.py b/test_regress/t/t_assert_disable_iff.py new file mode 100755 index 000000000..b17623e03 --- /dev/null +++ b/test_regress/t/t_assert_disable_iff.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert --cc --coverage-user']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_disabled.pl b/test_regress/t/t_assert_disabled.pl deleted file mode 100755 index 812f91229..000000000 --- a/test_regress/t/t_assert_disabled.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_on.v"); - -compile(); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_disabled.py b/test_regress/t/t_assert_disabled.py new file mode 100755 index 000000000..b45b81326 --- /dev/null +++ b/test_regress/t/t_assert_disabled.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_on.v" + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_dup_bad.pl b/test_regress/t/t_assert_dup_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_assert_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_dup_bad.py b/test_regress/t/t_assert_dup_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_assert_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_elab.pl b/test_regress/t/t_assert_elab.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_assert_elab.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_elab.py b/test_regress/t/t_assert_elab.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assert_elab.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_elab_bad.pl b/test_regress/t/t_assert_elab_bad.pl deleted file mode 100755 index 586badd6b..000000000 --- a/test_regress/t/t_assert_elab_bad.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_elab.v"); -unlink("$Self->{obj_dir}/t_assert_elab_bad.log"); - - -compile( - v_flags2 => ['+define+FAILING_ASSERTIONS', - $Self->{vlt_all} ? '--assert' : ($Self->{nc} ? '+assert':'')], - fails => 1, -); - -execute( - fails => $Self->{vlt_all}, -); - -file_grep("$Self->{obj_dir}/vlt_compile.log", -qr/%Warning-USERFATAL: "Parameter 5 is invalid...string and constant both work"/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_elab_bad.py b/test_regress/t/t_assert_elab_bad.py new file mode 100755 index 000000000..12c2d4b32 --- /dev/null +++ b/test_regress/t/t_assert_elab_bad.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_elab.v" + +test.unlink_ok(test.obj_dir + "/t_assert_elab_bad.log") + +test.compile(v_flags2=[ + '+define+FAILING_ASSERTIONS', ('--assert' if test.vlt_all else ('+assert' if test.nc else '')) +], + fails=True) + +test.execute(fails=test.vlt_all) + +test.file_grep(test.compile_log_filename, + r'%Warning-USERFATAL: "Parameter 5 is invalid...string and constant both work"') + +test.passes() diff --git a/test_regress/t/t_assert_enabled_bad.pl b/test_regress/t/t_assert_enabled_bad.pl deleted file mode 100755 index 689a3b7e2..000000000 --- a/test_regress/t/t_assert_enabled_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_on.v"); - -compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_enabled_bad.py b/test_regress/t/t_assert_enabled_bad.py new file mode 100755 index 000000000..aa290b7d0 --- /dev/null +++ b/test_regress/t/t_assert_enabled_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_on.v" + +test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) + +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_enabled_off.pl b/test_regress/t/t_assert_enabled_off.pl deleted file mode 100755 index 13894bf05..000000000 --- a/test_regress/t/t_assert_enabled_off.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_assert_on.v"); - -compile( - verilator_flags2 => ["--assert"], - ); - -execute( - all_run_flags => ["+verilator+noassert"], -); - -ok(1); -1; diff --git a/test_regress/t/t_assert_enabled_off.py b/test_regress/t/t_assert_enabled_off.py new file mode 100755 index 000000000..f2cce0678 --- /dev/null +++ b/test_regress/t/t_assert_enabled_off.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_assert_on.v" + +test.compile(verilator_flags2=["--assert"]) + +test.execute(all_run_flags=["+verilator+noassert"]) + +test.passes() diff --git a/test_regress/t/t_assert_enabled_on_bad.pl b/test_regress/t/t_assert_enabled_on_bad.pl deleted file mode 100755 index 6e1aa5190..000000000 --- a/test_regress/t/t_assert_enabled_on_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_assert_on.v"); - -compile( - verilator_flags2 => ["--assert"], - ); - -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_enabled_on_bad.py b/test_regress/t/t_assert_enabled_on_bad.py new file mode 100755 index 000000000..5789d18b7 --- /dev/null +++ b/test_regress/t/t_assert_enabled_on_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_assert_on.v" + +test.compile(verilator_flags2=["--assert"]) + +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_iff.pl b/test_regress/t/t_assert_iff.pl deleted file mode 100755 index 63d2a42a6..000000000 --- a/test_regress/t/t_assert_iff.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_iff.py b/test_regress/t/t_assert_iff.py new file mode 100755 index 000000000..b17623e03 --- /dev/null +++ b/test_regress/t/t_assert_iff.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert --cc --coverage-user']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_iff_bad1.pl b/test_regress/t/t_assert_iff_bad1.pl deleted file mode 100755 index 3959b8306..000000000 --- a/test_regress/t/t_assert_iff_bad1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename('t_assert_iff.v'); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user -DFAIL1'], - ); - -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_iff_bad1.py b/test_regress/t/t_assert_iff_bad1.py new file mode 100755 index 000000000..0855ac24f --- /dev/null +++ b/test_regress/t/t_assert_iff_bad1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = 't_assert_iff.v' + +test.compile(verilator_flags2=['--assert --cc --coverage-user -DFAIL1']) + +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_iff_bad2.pl b/test_regress/t/t_assert_iff_bad2.pl deleted file mode 100755 index f71edd058..000000000 --- a/test_regress/t/t_assert_iff_bad2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename('t_assert_iff.v'); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user -DFAIL2'], - ); - -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_iff_bad2.py b/test_regress/t/t_assert_iff_bad2.py new file mode 100755 index 000000000..6d25b802f --- /dev/null +++ b/test_regress/t/t_assert_iff_bad2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = 't_assert_iff.v' + +test.compile(verilator_flags2=['--assert --cc --coverage-user -DFAIL2']) + +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_iff_clk_unsup.pl b/test_regress/t/t_assert_iff_clk_unsup.pl deleted file mode 100755 index 1e3627720..000000000 --- a/test_regress/t/t_assert_iff_clk_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_iff_clk_unsup.py b/test_regress/t/t_assert_iff_clk_unsup.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_iff_clk_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_imm_nz_bad.pl b/test_regress/t/t_assert_imm_nz_bad.pl deleted file mode 100755 index 9841a8c0f..000000000 --- a/test_regress/t/t_assert_imm_nz_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_imm_nz_bad.py b/test_regress/t/t_assert_imm_nz_bad.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_imm_nz_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_implication.pl b/test_regress/t/t_assert_implication.pl deleted file mode 100755 index 1564fe383..000000000 --- a/test_regress/t/t_assert_implication.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert --cc'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_implication.py b/test_regress/t/t_assert_implication.py new file mode 100755 index 000000000..724621ce6 --- /dev/null +++ b/test_regress/t/t_assert_implication.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert --cc']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_implication_bad.pl b/test_regress/t/t_assert_implication_bad.pl deleted file mode 100755 index 9b934c0ec..000000000 --- a/test_regress/t/t_assert_implication_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_implication.v"); - -compile( - v_flags2 => ['+define+FAIL_ASSERT_1'], - verilator_flags2 => ['--assert --cc'], - ); - -execute( - ); - -# We expect to get a message when this assert fires: -file_grep($Self->{run_log_filename}, qr/wrong implication/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_implication_bad.py b/test_regress/t/t_assert_implication_bad.py new file mode 100755 index 000000000..873345737 --- /dev/null +++ b/test_regress/t/t_assert_implication_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_implication.v" + +test.compile(v_flags2=['+define+FAIL_ASSERT_1'], verilator_flags2=['--assert --cc']) + +test.execute() + +# We expect to get a message when this assert fires: +test.file_grep(test.run_log_filename, r'wrong implication') + +test.passes() diff --git a/test_regress/t/t_assert_inside_cond.pl b/test_regress/t/t_assert_inside_cond.pl deleted file mode 100755 index 1b42241ea..000000000 --- a/test_regress/t/t_assert_inside_cond.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_inside_cond.py b/test_regress/t/t_assert_inside_cond.py new file mode 100755 index 000000000..1a2dfabae --- /dev/null +++ b/test_regress/t/t_assert_inside_cond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_inside_cond_bad.pl b/test_regress/t/t_assert_inside_cond_bad.pl deleted file mode 100755 index 59d4ea08c..000000000 --- a/test_regress/t/t_assert_inside_cond_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_assert_inside_cond.v"); - -compile( - verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_inside_cond_bad.py b/test_regress/t/t_assert_inside_cond_bad.py new file mode 100755 index 000000000..8f955b403 --- /dev/null +++ b/test_regress/t/t_assert_inside_cond_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_assert_inside_cond.v" + +test.compile(verilator_flags2=["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_named_property.pl b/test_regress/t/t_assert_named_property.pl deleted file mode 100755 index a86f4c404..000000000 --- a/test_regress/t/t_assert_named_property.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_named_property.py b/test_regress/t/t_assert_named_property.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_named_property.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_past.pl b/test_regress/t/t_assert_past.pl deleted file mode 100755 index a86f4c404..000000000 --- a/test_regress/t/t_assert_past.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_past.py b/test_regress/t/t_assert_past.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_past.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_procedural_clk_bad.pl b/test_regress/t/t_assert_procedural_clk_bad.pl deleted file mode 100755 index 1e3627720..000000000 --- a/test_regress/t/t_assert_procedural_clk_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_procedural_clk_bad.py b/test_regress/t/t_assert_procedural_clk_bad.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_procedural_clk_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_property.pl b/test_regress/t/t_assert_property.pl deleted file mode 100755 index 1564fe383..000000000 --- a/test_regress/t/t_assert_property.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert --cc'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property.py b/test_regress/t/t_assert_property.py new file mode 100755 index 000000000..724621ce6 --- /dev/null +++ b/test_regress/t/t_assert_property.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert --cc']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_property_fail_1.pl b/test_regress/t/t_assert_property_fail_1.pl deleted file mode 100755 index e3ba3d21e..000000000 --- a/test_regress/t/t_assert_property_fail_1.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_property.v"); - -compile( - v_flags2 => ['+define+FAIL_ASSERT_1'], - verilator_flags2 => ['--assert --cc'], - ); - -execute( - ); - -# We expect to get a message when this assert fires: -file_grep($Self->{run_log_filename}, qr/cyc != 3/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_fail_1.py b/test_regress/t/t_assert_property_fail_1.py new file mode 100755 index 000000000..64539f556 --- /dev/null +++ b/test_regress/t/t_assert_property_fail_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_property.v" + +test.compile(v_flags2=['+define+FAIL_ASSERT_1'], verilator_flags2=['--assert --cc']) + +test.execute() + +# We expect to get a message when this assert fires: +test.file_grep(test.run_log_filename, r'cyc != 3') + +test.passes() diff --git a/test_regress/t/t_assert_property_fail_2_bad.pl b/test_regress/t/t_assert_property_fail_2_bad.pl deleted file mode 100755 index f12587b25..000000000 --- a/test_regress/t/t_assert_property_fail_2_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_property.v"); - -compile( - v_flags2 => ['+define+FAIL_ASSERT_2'], - verilator_flags2 => ['--assert --cc'], - ); - -execute( - fails => 1 - ); - -file_grep($Self->{run_log_filename}, qr/'assert' failed/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_fail_2_bad.py b/test_regress/t/t_assert_property_fail_2_bad.py new file mode 100755 index 000000000..f89198139 --- /dev/null +++ b/test_regress/t/t_assert_property_fail_2_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_property.v" + +test.compile(v_flags2=['+define+FAIL_ASSERT_2'], verilator_flags2=['--assert --cc']) + +test.execute(fails=True) + +test.file_grep(test.run_log_filename, r"'assert' failed") + +test.passes() diff --git a/test_regress/t/t_assert_property_pexpr_unsup.pl b/test_regress/t/t_assert_property_pexpr_unsup.pl deleted file mode 100755 index fa4fb8b52..000000000 --- a/test_regress/t/t_assert_property_pexpr_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert --error-limit 1000'], - fails => $Self->{vlt_all}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_pexpr_unsup.py b/test_regress/t/t_assert_property_pexpr_unsup.py new file mode 100755 index 000000000..7b40cd490 --- /dev/null +++ b/test_regress/t/t_assert_property_pexpr_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(expect_filename=test.golden_filename, + verilator_flags2=['--assert --error-limit 1000'], + fails=test.vlt_all) + +test.passes() diff --git a/test_regress/t/t_assert_property_untyped.pl b/test_regress/t/t_assert_property_untyped.pl deleted file mode 100755 index a86f4c404..000000000 --- a/test_regress/t/t_assert_property_untyped.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_untyped.py b/test_regress/t/t_assert_property_untyped.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_property_untyped.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_property_untyped_unsup.pl b/test_regress/t/t_assert_property_untyped_unsup.pl deleted file mode 100755 index 1e3627720..000000000 --- a/test_regress/t/t_assert_property_untyped_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_untyped_unsup.py b/test_regress/t/t_assert_property_untyped_unsup.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_property_untyped_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_property_var_unsup.pl b/test_regress/t/t_assert_property_var_unsup.pl deleted file mode 100755 index 7284ec30e..000000000 --- a/test_regress/t/t_assert_property_var_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert --error-limit 1000'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_var_unsup.py b/test_regress/t/t_assert_property_var_unsup.py new file mode 100755 index 000000000..25f9960b8 --- /dev/null +++ b/test_regress/t/t_assert_property_var_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, + verilator_flags2=['--assert --error-limit 1000'], + fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_question.pl b/test_regress/t/t_assert_question.pl deleted file mode 100755 index b3a7f940f..000000000 --- a/test_regress/t/t_assert_question.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_question.py b/test_regress/t/t_assert_question.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_question.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_recursive_property_unsup.pl b/test_regress/t/t_assert_recursive_property_unsup.pl deleted file mode 100755 index 8e28a9204..000000000 --- a/test_regress/t/t_assert_recursive_property_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename=>$Self->{golden_filename}, - verilator_flags2=> ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_recursive_property_unsup.py b/test_regress/t/t_assert_recursive_property_unsup.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_recursive_property_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_sampled.pl b/test_regress/t/t_assert_sampled.pl deleted file mode 100755 index a86f4c404..000000000 --- a/test_regress/t/t_assert_sampled.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_sampled.py b/test_regress/t/t_assert_sampled.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_sampled.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_synth.pl b/test_regress/t/t_assert_synth.pl deleted file mode 100755 index 59aeed76c..000000000 --- a/test_regress/t/t_assert_synth.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth.py b/test_regress/t/t_assert_synth.py new file mode 100755 index 000000000..d97aaff01 --- /dev/null +++ b/test_regress/t/t_assert_synth.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_synth_full.pl b/test_regress/t/t_assert_synth_full.pl deleted file mode 100755 index be8b7d192..000000000 --- a/test_regress/t/t_assert_synth_full.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_synth.v"); - -compile( - v_flags2 => ['+define+FAILING_FULL +define+ATTRIBUTES'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 0, - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth_full.py b/test_regress/t/t_assert_synth_full.py new file mode 100755 index 000000000..5d213121c --- /dev/null +++ b/test_regress/t/t_assert_synth_full.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_synth.v" + +test.compile(v_flags2=['+define+FAILING_FULL +define+ATTRIBUTES'], + verilator_flags2=['--assert'], + nc_flags2=['+assert']) + +test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_synth_full_vlt.pl b/test_regress/t/t_assert_synth_full_vlt.pl deleted file mode 100755 index 14827a677..000000000 --- a/test_regress/t/t_assert_synth_full_vlt.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_synth.v"); - -compile( - v_flags2 => ['+define+FAILING_FULL', "t/t_assert_synth_full.vlt"], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 0, - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth_full_vlt.py b/test_regress/t/t_assert_synth_full_vlt.py new file mode 100755 index 000000000..39ceee722 --- /dev/null +++ b/test_regress/t/t_assert_synth_full_vlt.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_synth.v" + +test.compile(v_flags2=['+define+FAILING_FULL', "t/t_assert_synth_full.vlt"], + verilator_flags2=['--assert'], + nc_flags2=['+assert']) + +test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_synth_off.pl b/test_regress/t/t_assert_synth_off.pl deleted file mode 100755 index 5d352ebe2..000000000 --- a/test_regress/t/t_assert_synth_off.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_synth.v"); - -compile( - v_flags2 => ['+define+FAILING_FULL', - '+define+FAILING_PARALLEL', - '+define+FAILING_OH', - '+define+FAILING_OC', - ], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth_off.py b/test_regress/t/t_assert_synth_off.py new file mode 100755 index 000000000..ce86721c2 --- /dev/null +++ b/test_regress/t/t_assert_synth_off.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_synth.v" + +test.compile(v_flags2=[ + '+define+FAILING_FULL', '+define+FAILING_PARALLEL', '+define+FAILING_OH', '+define+FAILING_OC' +]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_synth_parallel.pl b/test_regress/t/t_assert_synth_parallel.pl deleted file mode 100755 index 40cb662f1..000000000 --- a/test_regress/t/t_assert_synth_parallel.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_synth.v"); - -compile( - v_flags2 => ['+define+FAILING_PARALLEL', '+define+ATTRIBUTES'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 0, - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth_parallel.py b/test_regress/t/t_assert_synth_parallel.py new file mode 100755 index 000000000..1218cfb79 --- /dev/null +++ b/test_regress/t/t_assert_synth_parallel.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_synth.v" + +test.compile(v_flags2=['+define+FAILING_PARALLEL', '+define+ATTRIBUTES'], + verilator_flags2=['--assert'], + nc_flags2=['+assert']) + +test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_synth_parallel_vlt.pl b/test_regress/t/t_assert_synth_parallel_vlt.pl deleted file mode 100755 index 782d98d15..000000000 --- a/test_regress/t/t_assert_synth_parallel_vlt.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_synth.v"); - -compile( - v_flags2 => ['+define+FAILING_PARALLEL', "t/t_assert_synth_parallel.vlt"], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 0, - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth_parallel_vlt.py b/test_regress/t/t_assert_synth_parallel_vlt.py new file mode 100755 index 000000000..72f8e67fc --- /dev/null +++ b/test_regress/t/t_assert_synth_parallel_vlt.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_synth.v" + +test.compile(v_flags2=['+define+FAILING_PARALLEL', "t/t_assert_synth_parallel.vlt"], + verilator_flags2=['--assert'], + nc_flags2=['+assert']) + +test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_unique_case.pl b/test_regress/t/t_assert_unique_case.pl deleted file mode 100755 index ad2c2c8fc..000000000 --- a/test_regress/t/t_assert_unique_case.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_assert_unique_case_bad.v"); - -compile( - verilator_flags2 => ["-x-assign 0 --assert-case --no-stop-fail +define+NO_STOP_FAIL"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_unique_case.py b/test_regress/t/t_assert_unique_case.py new file mode 100755 index 000000000..a76d4eb50 --- /dev/null +++ b/test_regress/t/t_assert_unique_case.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_unique_case_bad.v" + +test.compile(verilator_flags2=["-x-assign 0 --assert-case --no-stop-fail +define+NO_STOP_FAIL"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_unique_case_bad.pl b/test_regress/t/t_assert_unique_case_bad.pl deleted file mode 100755 index 70f34a0e1..000000000 --- a/test_regress/t/t_assert_unique_case_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-x-assign 0 --assert"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_unique_case_bad.py b/test_regress/t/t_assert_unique_case_bad.py new file mode 100755 index 000000000..3924fa02d --- /dev/null +++ b/test_regress/t/t_assert_unique_case_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-x-assign 0 --assert"]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assign_expr.pl b/test_regress/t/t_assign_expr.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_assign_expr.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assign_expr.py b/test_regress/t/t_assign_expr.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assign_expr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assign_inline.pl b/test_regress/t/t_assign_inline.pl deleted file mode 100755 index 1683d1777..000000000 --- a/test_regress/t/t_assign_inline.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-O0 -fgate"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assign_inline.py b/test_regress/t/t_assign_inline.py new file mode 100755 index 000000000..6a30330fc --- /dev/null +++ b/test_regress/t/t_assign_inline.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-O0 -fgate"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.out b/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.out index d4fd4ace8..e4937d2bd 100644 --- a/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.out +++ b/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.out @@ -4,8 +4,8 @@ t/t_assign_on_rhs_of_nonblocking_unsup.v:24:18: ... Location of blocking assignment 24 | y <= (x = 2); | ^ - t/t_assign_on_rhs_of_nonblocking_unsup.v:21:10: ... Location of nonblocking assignment + t/t_assign_on_rhs_of_nonblocking_unsup.v:21:12: ... Location of nonblocking assignment 21 | x <= 1; - | ^ + | ^~ ... For error description see https://verilator.org/warn/BLKANDNBLK?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.pl b/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.py b/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assign_slice_overflow.pl b/test_regress/t/t_assign_slice_overflow.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_assign_slice_overflow.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assign_slice_overflow.py b/test_regress/t/t_assign_slice_overflow.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assign_slice_overflow.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assign_slice_overflow_ox.pl b/test_regress/t/t_assign_slice_overflow_ox.pl deleted file mode 100755 index 8702b94fe..000000000 --- a/test_regress/t/t_assign_slice_overflow_ox.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t_assign_slice_overflow.v"); - -compile( - verilator_flags2 => ["-fno-expand"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assign_slice_overflow_ox.py b/test_regress/t/t_assign_slice_overflow_ox.py new file mode 100755 index 000000000..b1371a321 --- /dev/null +++ b/test_regress/t/t_assign_slice_overflow_ox.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t_assign_slice_overflow.v" + +test.compile(verilator_flags2=["-fno-expand"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assigndly_dynamic.pl b/test_regress/t/t_assigndly_dynamic.pl deleted file mode 100755 index 270c8b710..000000000 --- a/test_regress/t/t_assigndly_dynamic.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -compile( - verilator_flags2 => ["--exe --main --timing +define+WITH_DELAY"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assigndly_dynamic.py b/test_regress/t/t_assigndly_dynamic.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_assigndly_dynamic.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assigndly_dynamic_delay.py b/test_regress/t/t_assigndly_dynamic_delay.py new file mode 100755 index 000000000..6fc5a819d --- /dev/null +++ b/test_regress/t/t_assigndly_dynamic_delay.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assigndly_dynamic" + +test.compile(verilator_flags2=["--exe --main --timing +define+WITH_DELAY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assigndly_dynamic_nofork.pl b/test_regress/t/t_assigndly_dynamic_nofork.pl deleted file mode 100755 index b4872e54c..000000000 --- a/test_regress/t/t_assigndly_dynamic_nofork.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assigndly_task.v"); - -compile( - verilator_flags2 => ["--timing"], - ); - -foreach my $file ( - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.h"), - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp") - ) { - file_grep_not($file, qr/__Vfork_/i); -} - -ok(1); -1; diff --git a/test_regress/t/t_assigndly_dynamic_nofork.py b/test_regress/t/t_assigndly_dynamic_nofork.py new file mode 100755 index 000000000..999869c5c --- /dev/null +++ b/test_regress/t/t_assigndly_dynamic_nofork.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assigndly_task.v" + +test.compile(verilator_flags2=["--timing"]) + +for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): + test.file_grep_not(filename, r'__Vfork_') + +test.passes() diff --git a/test_regress/t/t_assigndly_dynamic_notiming_bad.pl b/test_regress/t/t_assigndly_dynamic_notiming_bad.pl deleted file mode 100755 index bf0b971e2..000000000 --- a/test_regress/t/t_assigndly_dynamic_notiming_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--no-timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assigndly_dynamic_notiming_bad.py b/test_regress/t/t_assigndly_dynamic_notiming_bad.py new file mode 100755 index 000000000..6f71603b5 --- /dev/null +++ b/test_regress/t/t_assigndly_dynamic_notiming_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assigndly_task.pl b/test_regress/t/t_assigndly_task.pl deleted file mode 100755 index da2e37bda..000000000 --- a/test_regress/t/t_assigndly_task.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assigndly_task.py b/test_regress/t/t_assigndly_task.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_assigndly_task.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_assoc.pl b/test_regress/t/t_assoc.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_assoc.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc.py b/test_regress/t/t_assoc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc.v b/test_regress/t/t_assoc.v index f3e89620e..d1e6c12b5 100644 --- a/test_regress/t/t_assoc.v +++ b/test_regress/t/t_assoc.v @@ -6,8 +6,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t (/*AUTOARG*/ @@ -121,6 +120,29 @@ module t (/*AUTOARG*/ `checkh(sum, 1 + 2); end + begin // Issue #5435 + int a; + int ok; + int dict [int]; + + dict[3] = 'h13; + dict[4] = 'h14; + dict[5] = 'h15; + + a = 4; + ok = dict.first(a); + if (a != 3) $stop; + if (ok != 1) $stop; + a = 4; + ok = dict.next(a); + if (a != 5) $stop; + if (ok != 1) $stop; + a = 4; + ok = dict.last(a); + if (a != 5) $stop; + if (ok != 1) $stop; + end + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_assoc2.pl b/test_regress/t/t_assoc2.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_assoc2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc2.py b/test_regress/t/t_assoc2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc2.v b/test_regress/t/t_assoc2.v index 07a6dc6db..f3d03dcc2 100644 --- a/test_regress/t/t_assoc2.v +++ b/test_regress/t/t_assoc2.v @@ -6,8 +6,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_assoc_compare.pl b/test_regress/t/t_assoc_compare.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_assoc_compare.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_compare.py b/test_regress/t/t_assoc_compare.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc_method.pl b/test_regress/t/t_assoc_method.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_assoc_method.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_method.py b/test_regress/t/t_assoc_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc_method.v b/test_regress/t/t_assoc_method.v index 76edc7dd6..0cc6c5d2b 100644 --- a/test_regress/t/t_assoc_method.v +++ b/test_regress/t/t_assoc_method.v @@ -1,15 +1,21 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); + module t (/*AUTOARG*/); typedef struct { int x, y; } point; + + function automatic int vec_len_squared(point p); + return p.x * p.x + p.y * p.y; + endfunction + initial begin int q[int]; int qe[int]; // Empty @@ -18,6 +24,7 @@ module t (/*AUTOARG*/); point points_q[int]; point points_qv[$]; int i; + bit b; q = '{10:1, 11:2, 12:2, 13:4, 14:3}; `checkp(q, "'{'ha:'h1, 'hb:'h2, 'hc:'h2, 'hd:'h4, 'he:'h3} "); @@ -116,8 +123,12 @@ module t (/*AUTOARG*/); i = qe.sum; `checkh(i, 32'h0); + i = qe.sum with (item + 1); + `checkh(i, 32'h0); i = qe.product; `checkh(i, 32'h0); + i = qe.product with (item + 1); + `checkh(i, 32'h0); q = '{10:32'b1100, 11:32'b1010}; i = q.and; @@ -135,10 +146,16 @@ module t (/*AUTOARG*/); i = qe.and; `checkh(i, 32'b0); + i = qe.and with (item + 1); + `checkh(i, 32'h0); i = qe.or; `checkh(i, 32'b0); + i = qe.or with (item + 1); + `checkh(i, 32'b0); i = qe.xor; `checkh(i, 32'b0); + i = qe.xor with (item + 1); + `checkh(i, 32'b0); i = q.and(); `checkh(i, 32'b1000); @@ -165,6 +182,19 @@ module t (/*AUTOARG*/); `checkh(q == qe, 1'b1); `checkh(q != qe, 1'b0); + i = points_q.sum with (vec_len_squared(item)); + `checkh(i, 32'h2a); + i = points_q.product with (vec_len_squared(item)); + `checkh(i, 32'h6a4); + b = points_q.sum with (vec_len_squared(item) == 5); + `checkh(b, 1'b1); + b = points_q.sum with (vec_len_squared(item) == 0); + `checkh(b, 1'b0); + b = points_q.product with (vec_len_squared(item) inside {5, 17}); + `checkh(b, 1'b0); + b = points_q.sum with (vec_len_squared(item) inside {5, 17, 20}); + `checkh(b, 1'b1); + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_assoc_method_bad.out b/test_regress/t/t_assoc_method_bad.out index 794685136..52cb6da31 100644 --- a/test_regress/t/t_assoc_method_bad.out +++ b/test_regress/t/t_assoc_method_bad.out @@ -18,6 +18,11 @@ : ... note: In instance 't' 18 | v = a.first(); | ^~~~~ +%Error-UNSUPPORTED: t/t_assoc_method_bad.v:18:13: Unsupported: Non-variable on LHS of built-in method 'first' + : ... note: In instance 't' + 18 | v = a.first(); + | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_assoc_method_bad.v:19:13: The 2 arguments passed to .next method does not match its requiring 1 arguments : ... note: In instance 't' 19 | v = a.next(k, "bad2"); @@ -26,6 +31,10 @@ : ... note: In instance 't' 20 | v = a.last(); | ^~~~ +%Error-UNSUPPORTED: t/t_assoc_method_bad.v:20:13: Unsupported: Non-variable on LHS of built-in method 'last' + : ... note: In instance 't' + 20 | v = a.last(); + | ^~~~ %Error: t/t_assoc_method_bad.v:21:13: The 2 arguments passed to .prev method does not match its requiring 1 arguments : ... note: In instance 't' 21 | v = a.prev(k, "bad2"); diff --git a/test_regress/t/t_assoc_method_bad.pl b/test_regress/t/t_assoc_method_bad.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_assoc_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_method_bad.py b/test_regress/t/t_assoc_method_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_assoc_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assoc_method_map.pl b/test_regress/t/t_assoc_method_map.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_assoc_method_map.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_method_map.py b/test_regress/t/t_assoc_method_map.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_assoc_method_map.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assoc_nokey_bad.pl b/test_regress/t/t_assoc_nokey_bad.pl deleted file mode 100755 index c42f6c90d..000000000 --- a/test_regress/t/t_assoc_nokey_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_nokey_bad.py b/test_regress/t/t_assoc_nokey_bad.py new file mode 100755 index 000000000..dece38f4e --- /dev/null +++ b/test_regress/t/t_assoc_nokey_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assoc_ref_type.pl b/test_regress/t/t_assoc_ref_type.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_assoc_ref_type.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_ref_type.py b/test_regress/t/t_assoc_ref_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc_ref_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc_wildcard.pl b/test_regress/t/t_assoc_wildcard.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_assoc_wildcard.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_wildcard.py b/test_regress/t/t_assoc_wildcard.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc_wildcard.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc_wildcard.v b/test_regress/t/t_assoc_wildcard.v index 8e67d841f..9469243b3 100644 --- a/test_regress/t/t_assoc_wildcard.v +++ b/test_regress/t/t_assoc_wildcard.v @@ -6,8 +6,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_assoc_wildcard_bad.pl b/test_regress/t/t_assoc_wildcard_bad.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_assoc_wildcard_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_wildcard_bad.py b/test_regress/t/t_assoc_wildcard_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_assoc_wildcard_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assoc_wildcard_map.pl b/test_regress/t/t_assoc_wildcard_map.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_assoc_wildcard_map.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_wildcard_map.py b/test_regress/t/t_assoc_wildcard_map.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_assoc_wildcard_map.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assoc_wildcard_method.pl b/test_regress/t/t_assoc_wildcard_method.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_assoc_wildcard_method.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_wildcard_method.py b/test_regress/t/t_assoc_wildcard_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc_wildcard_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc_wildcard_method.v b/test_regress/t/t_assoc_wildcard_method.v index 85ff6606d..5fdaadcc9 100644 --- a/test_regress/t/t_assoc_wildcard_method.v +++ b/test_regress/t/t_assoc_wildcard_method.v @@ -9,12 +9,20 @@ `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t (/*AUTOARG*/); + typedef struct { int x, y; } point; + + function automatic int vec_len_squared(point p); + return p.x * p.x + p.y * p.y; + endfunction + initial begin int q[*]; int qe [ * ]; // Empty - Note spaces around [*] for parsing coverage + point points_q[*] = '{"a": point'{1, 2}, "b": point'{2, 4}, "c": point'{1, 4}}; int qv[$]; // Value returns int qi[$]; // Index returns int i; + bit b; string v; q = '{"a":1, "b":2, "c":2, "d":4, "e":3}; @@ -95,11 +103,17 @@ module t (/*AUTOARG*/); `checkh(i, 32'b0110); i = qe.and; - `checkh(i, 32'b0); + `checkh(i, 32'h0); + i = qe.and with (item + 1); + `checkh(i, 32'h0); i = qe.or; `checkh(i, 32'b0); + i = qe.or with (item + 1); + `checkh(i, 32'b0); i = qe.xor; `checkh(i, 32'b0); + i = qe.xor with (item + 1); + `checkh(i, 32'b0); i = q.and(); `checkh(i, 32'b1000); @@ -121,6 +135,19 @@ module t (/*AUTOARG*/); i = qe.xor(); `checkh(i, 32'b0); + i = points_q.sum with (vec_len_squared(item)); + `checkh(i, 32'h2a); + i = points_q.product with (vec_len_squared(item)); + `checkh(i, 32'h6a4); + b = points_q.sum with (vec_len_squared(item) == 5); + `checkh(b, 1'b1); + b = points_q.sum with (vec_len_squared(item) == 0); + `checkh(b, 1'b0); + b = points_q.product with (vec_len_squared(item) inside {5, 17}); + `checkh(b, 1'b0); + b = points_q.sum with (vec_len_squared(item) inside {5, 17, 20}); + `checkh(b, 1'b1); + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_attr_parenstar.pl b/test_regress/t/t_attr_parenstar.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_attr_parenstar.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_attr_parenstar.py b/test_regress/t/t_attr_parenstar.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_attr_parenstar.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bench_mux4k.pl b/test_regress/t/t_bench_mux4k.pl deleted file mode 100755 index cc9340de4..000000000 --- a/test_regress/t/t_bench_mux4k.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--stats", - $Self->wno_unopthreads_for_few_cores()] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bench_mux4k.py b/test_regress/t/t_bench_mux4k.py new file mode 100755 index 000000000..1141bf9d2 --- /dev/null +++ b/test_regress/t/t_bench_mux4k.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--stats", test.wno_unopthreads_for_few_cores]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bench_mux4k_onecpu.pl b/test_regress/t/t_bench_mux4k_onecpu.pl deleted file mode 100755 index 4aa4cada7..000000000 --- a/test_regress/t/t_bench_mux4k_onecpu.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_bench_mux4k.v"); - -compile( - v_flags2 => ["--stats", - $Self->wno_unopthreads_for_few_cores()] - ); - -# WSL2 gives a warning and we must skip the test: -# "physcpubind: 0 1 2 3 ...\n No NUMA support available on this system." -my $nout = `numactl --show`; -if ($nout !~ /cpu/ || $nout =~ /No NUMA support available/i) { - skip("No numactl available"); -} else { - execute( - run_env => 'numactl -m 0 -C 0,0,0,0,0,0,0,0', - check_finished => 1, - ); - ok(1); -} - -1; diff --git a/test_regress/t/t_bench_mux4k_onecpu.py b/test_regress/t/t_bench_mux4k_onecpu.py new file mode 100755 index 000000000..d71cf4d42 --- /dev/null +++ b/test_regress/t/t_bench_mux4k_onecpu.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_bench_mux4k.v" + +test.compile(v_flags2=["--stats", test.wno_unopthreads_for_few_cores]) + +# WSL2 gives a warning and we must skip the test: +# "physcpubind: 0 1 2 3 ...\n No NUMA support available on this system." +nout = test.run_capture("numactl --show", check=False) + +if not nout or not re.search(r'cpu', nout) or re.search(r'No NUMA support available', nout, + re.IGNORECASE): + test.skip("No numactl available") + +test.execute(run_env='numactl -m 0 -C 0,0,0,0,0,0,0,0') + +test.passes() diff --git a/test_regress/t/t_benchmarksim.pl b/test_regress/t/t_benchmarksim.pl deleted file mode 100755 index 59fed2993..000000000 --- a/test_regress/t/t_benchmarksim.pl +++ /dev/null @@ -1,53 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# Use any top file -top_filename("t/t_gen_alw.v"); - -init_benchmarksim(); - -# As an example, compile and simulate the top file with varying optimization level -my @l_opt = (1, 2, 3); - -foreach my $l_opt (@l_opt) { - compile( - benchmarksim => 1, - v_flags2 => ["-O$l_opt"] - ); - - execute( - check_finished => 1, - ); -} - -my $fh = IO::File->new("<" . benchmarksim_filename()) or error("Benchmark data file not found"); -my $lines = 0; -while (defined(my $line = $fh->getline)) { - if ($line =~ /^#/) { next; } - if ($lines == 0) { - error("Expected header but found $line") if $line ne "evals, time[s]\n"; - } else { - my @data = grep {$_ != ""} ($line =~ /(\d*\.?\d*)/g); - error("Expected 2 tokens on line " . $lines . " but got " . scalar(@data)) if scalar(@data) != 2; - my $cycles = $data[0]; - my $time = $data[1]; - error("Invalid data on line " . $lines) if $cycles <= 0.0 || $time <= 0.0; - } - $lines += 1; -} -my $n_lines_expected = scalar(@l_opt) + 1; - -error("Expected " . $n_lines_expected . " lines but found " . $lines) - if int($lines) != int($n_lines_expected); - -1; -ok(1); diff --git a/test_regress/t/t_benchmarksim.py b/test_regress/t/t_benchmarksim.py new file mode 100755 index 000000000..966eea90c --- /dev/null +++ b/test_regress/t/t_benchmarksim.py @@ -0,0 +1,54 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_gen_alw.v" # Use any top file + +test.init_benchmarksim() + +# As an example, compile and simulate the top file with varying optimization level +l_opts = [1, 2, 3] + +for l_opt in l_opts: + test.compile(benchmarksim=1, v_flags2=["-O" + str(l_opt)]) + + test.execute() + +filename = test.benchmarksim_filename +gotn = 0 +with open(filename, 'r', encoding="utf8") as fh: + lineno = 0 + headered = False + for line in fh: + lineno += 1 + if re.match(r'^#', line): + continue + if not headered: + headered = True + if not re.search(r'evals, ', line): + test.error(filename + ":" + str(lineno) + ": Expected header but found: " + line) + else: + m = re.search(r'(\d+\.?\d*),(\d+\.?\d*)', line) + if not m: + test.error(filename + ":" + str(lineno) + ": Expected 2 tokens on line: " + line) + continue + cycles = float(m.group(1)) + time = float(m.group(2)) + if cycles <= 0.0 or time <= 0.0: + test.error(filename + ":" + str(lineno) + ": Invalid data on line: " + line) + continue + gotn += 1 + +n_lines_expected = len(l_opts) +if gotn != int(n_lines_expected): + test.error("Expected " + str(n_lines_expected) + " lines but found " + str(gotn)) + +test.passes() diff --git a/test_regress/t/t_bigmem_bad.pl b/test_regress/t/t_bigmem_bad.pl deleted file mode 100755 index 66a4e492d..000000000 --- a/test_regress/t/t_bigmem_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bigmem_bad.py b/test_regress/t/t_bigmem_bad.py new file mode 100755 index 000000000..dece38f4e --- /dev/null +++ b/test_regress/t/t_bigmem_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_bind.pl b/test_regress/t/t_bind.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_bind.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bind.py b/test_regress/t/t_bind.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bind.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bind2.pl b/test_regress/t/t_bind2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_bind2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bind2.py b/test_regress/t/t_bind2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bind2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bind_nfound.pl b/test_regress/t/t_bind_nfound.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_bind_nfound.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_bind_nfound.py b/test_regress/t/t_bind_nfound.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_bind_nfound.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_bitsel_concat.pl b/test_regress/t/t_bitsel_concat.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_bitsel_concat.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_concat.py b/test_regress/t/t_bitsel_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_concat.v b/test_regress/t/t_bitsel_concat.v index c18aa2c2e..34c05f8ed 100644 --- a/test_regress/t/t_bitsel_concat.v +++ b/test_regress/t/t_bitsel_concat.v @@ -34,6 +34,13 @@ module t(/*AUTOARG*/); return 16'hf0ed; endfunction + int i; + typedef int arr_t[1:0][3:0]; + + function arr_t valarr(); + return '{'{1,2,3,4}, '{5,6,7,8}}; + endfunction + initial begin aa = 8'haa; bb = 8'hbb; @@ -84,6 +91,9 @@ module t(/*AUTOARG*/); s8 = q.sum()[11-:8]; `checkh(s8, 8'h0e); + i = valarr()[1][2]; + $display(i); + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_bitsel_const_bad.out b/test_regress/t/t_bitsel_const_bad.out index 549399517..c3ad070be 100644 --- a/test_regress/t/t_bitsel_const_bad.out +++ b/test_regress/t/t_bitsel_const_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_bitsel_const_bad.v:21:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' +%Error: t/t_bitsel_const_bad.v:16:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' - 21 | assign a = b[0]; + 16 | assign a = b[0]; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_bitsel_const_bad.pl b/test_regress/t/t_bitsel_const_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_bitsel_const_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_const_bad.py b/test_regress/t/t_bitsel_const_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_bitsel_const_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_bitsel_const_bad.v b/test_regress/t/t_bitsel_const_bad.v index 26eed4d95..501a30793 100644 --- a/test_regress/t/t_bitsel_const_bad.v +++ b/test_regress/t/t_bitsel_const_bad.v @@ -6,12 +6,7 @@ // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); // Note that if we declare "wire [0:0] b", this works just fine. wire a; diff --git a/test_regress/t/t_bitsel_enum.pl b/test_regress/t/t_bitsel_enum.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_bitsel_enum.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_enum.py b/test_regress/t/t_bitsel_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_slice.pl b/test_regress/t/t_bitsel_slice.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_bitsel_slice.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_slice.py b/test_regress/t/t_bitsel_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_struct.pl b/test_regress/t/t_bitsel_struct.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_bitsel_struct.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_struct.py b/test_regress/t/t_bitsel_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_struct.v b/test_regress/t/t_bitsel_struct.v index 80fb3f837..ebaac9431 100644 --- a/test_regress/t/t_bitsel_struct.v +++ b/test_regress/t/t_bitsel_struct.v @@ -9,12 +9,8 @@ // without warranty, 2012 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t(/*AUTOARG*/); - input clk; typedef struct packed { logic [1:0][15:0] channel; logic others; diff --git a/test_regress/t/t_bitsel_struct2.pl b/test_regress/t/t_bitsel_struct2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_bitsel_struct2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_struct2.py b/test_regress/t/t_bitsel_struct2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_struct2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_struct3.pl b/test_regress/t/t_bitsel_struct3.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_bitsel_struct3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_struct3.py b/test_regress/t/t_bitsel_struct3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_struct3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_struct3.v b/test_regress/t/t_bitsel_struct3.v index ee92dfd0f..59eb30b0c 100644 --- a/test_regress/t/t_bitsel_struct3.v +++ b/test_regress/t/t_bitsel_struct3.v @@ -12,12 +12,8 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t(/*AUTOARG*/); - input clk; typedef struct packed { logic [15:0] channel; logic [15:0] others; diff --git a/test_regress/t/t_bitsel_wire_array_bad.out b/test_regress/t/t_bitsel_wire_array_bad.out index 43ba6671a..24c6ffdcb 100644 --- a/test_regress/t/t_bitsel_wire_array_bad.out +++ b/test_regress/t/t_bitsel_wire_array_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_bitsel_wire_array_bad.v:21:16: Illegal assignment of constant to unpacked array +%Error: t/t_bitsel_wire_array_bad.v:16:16: Illegal assignment of constant to unpacked array : ... note: In instance 't' - 21 | assign b = a[0]; + 16 | assign b = a[0]; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_bitsel_wire_array_bad.pl b/test_regress/t/t_bitsel_wire_array_bad.pl deleted file mode 100755 index af94708c0..000000000 --- a/test_regress/t/t_bitsel_wire_array_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -# Compile time only test - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_wire_array_bad.py b/test_regress/t/t_bitsel_wire_array_bad.py new file mode 100755 index 000000000..d0fba6a98 --- /dev/null +++ b/test_regress/t/t_bitsel_wire_array_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +# Compile time only test + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_bitsel_wire_array_bad.v b/test_regress/t/t_bitsel_wire_array_bad.v index fba95f691..d29828c7e 100644 --- a/test_regress/t/t_bitsel_wire_array_bad.v +++ b/test_regress/t/t_bitsel_wire_array_bad.v @@ -6,12 +6,7 @@ // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); // a and b are arrays of length 1. wire a[0:0]; // Array of nets diff --git a/test_regress/t/t_blocking.pl b/test_regress/t/t_blocking.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_blocking.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_blocking.py b/test_regress/t/t_blocking.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_blocking.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bug3180.pl b/test_regress/t/t_bug3180.pl deleted file mode 100755 index 79556a789..000000000 --- a/test_regress/t/t_bug3180.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wall -Wno-DECLFILENAME --coverage-line'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_bug3180.py b/test_regress/t/t_bug3180.py new file mode 100755 index 000000000..eb6589504 --- /dev/null +++ b/test_regress/t/t_bug3180.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wall -Wno-DECLFILENAME --coverage-line']) + +test.passes() diff --git a/test_regress/t/t_c_this.pl b/test_regress/t/t_c_this.pl deleted file mode 100755 index 7fa144221..000000000 --- a/test_regress/t/t_c_this.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -if ($Self->{vlt_all}) { - # The word 'this' (but only the whole word 'this' should have been replaced - # in the contents. - my $has_this = 0; - my $has_xthis = 0; - my $has_thisx = 0; - my $has_xthisx = 0; - for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root__DepSet_*__0.cpp")) { - my $text = file_contents($file); - $has_this = 1 if ($text =~ m/\bthis->clk\b/); - $has_xthis = 1 if ($text =~ m/\bxthis\b/); - $has_thisx = 1 if ($text =~ m/\bthisx\b/); - $has_xthisx = 1 if ($text =~ m/\bxthisx\b/); - } - error("Some file has 'this->clk'") if $has_this; - error("No file has 'xthis'") if !$has_xthis; - error("No file has 'thisx'") if !$has_thisx; - error("No file has 'xthisx'") if !$has_xthisx; -} - -ok(1); -1; diff --git a/test_regress/t/t_c_this.py b/test_regress/t/t_c_this.py new file mode 100755 index 000000000..bdbed8811 --- /dev/null +++ b/test_regress/t/t_c_this.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +if test.vlt_all: + # The word 'this' (but only the whole word 'this' should have been replaced + # in the contents. + has_this = False + has_xthis = False + has_thisx = False + has_xthisx = False + for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + + "___024root__DepSet_*__0.cpp"): + text = test.file_contents(filename) + if re.search(r'\bthis->clk\b', text): + has_this = True + if re.search(r'\bxthis\b', text): + has_xthis = True + if re.search(r'\bthisx\b', text): + has_thisx = True + if re.search(r'\bxthisx\b', text): + has_xthisx = True + + if has_this: + test.error("Some file has 'this->clk'") + if not has_xthis: + test.error("No file has 'xthis'") + if not has_thisx: + test.error("No file has 'thisx'") + if not has_xthisx: + test.error("No file has 'xthisx'") + +test.passes() diff --git a/test_regress/t/t_case_66bits.pl b/test_regress/t/t_case_66bits.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_66bits.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_66bits.py b/test_regress/t/t_case_66bits.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_66bits.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_66bits_noexpand.pl b/test_regress/t/t_case_66bits_noexpand.pl deleted file mode 100755 index 738da6174..000000000 --- a/test_regress/t/t_case_66bits_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_case_66bits.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_66bits_noexpand.py b/test_regress/t/t_case_66bits_noexpand.py new file mode 100755 index 000000000..2316143be --- /dev/null +++ b/test_regress/t/t_case_66bits_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_case_66bits.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_auto1.pl b/test_regress/t/t_case_auto1.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_auto1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_auto1.py b/test_regress/t/t_case_auto1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_auto1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_deep.pl b/test_regress/t/t_case_deep.pl deleted file mode 100755 index 7d49cd2cd..000000000 --- a/test_regress/t/t_case_deep.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_deep.py b/test_regress/t/t_case_deep.py new file mode 100755 index 000000000..95c3e8bca --- /dev/null +++ b/test_regress/t/t_case_deep.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_default_bad.pl b/test_regress/t/t_case_default_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_case_default_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_default_bad.py b/test_regress/t/t_case_default_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_default_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_dupitems.pl b/test_regress/t/t_case_dupitems.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_dupitems.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_dupitems.py b/test_regress/t/t_case_dupitems.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_dupitems.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_duplicated_if.pl b/test_regress/t/t_case_duplicated_if.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_duplicated_if.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_duplicated_if.py b/test_regress/t/t_case_duplicated_if.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_duplicated_if.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_enum_complete.pl b/test_regress/t/t_case_enum_complete.pl deleted file mode 100755 index 59837c4db..000000000 --- a/test_regress/t/t_case_enum_complete.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-CASEINCOMPLETE"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_enum_complete.py b/test_regress/t/t_case_enum_complete.py new file mode 100755 index 000000000..03bb69a41 --- /dev/null +++ b/test_regress/t/t_case_enum_complete.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-CASEINCOMPLETE"]) + +test.passes() diff --git a/test_regress/t/t_case_enum_complete_wildcard.pl b/test_regress/t/t_case_enum_complete_wildcard.pl deleted file mode 100755 index 59837c4db..000000000 --- a/test_regress/t/t_case_enum_complete_wildcard.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-CASEINCOMPLETE"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_enum_complete_wildcard.py b/test_regress/t/t_case_enum_complete_wildcard.py new file mode 100755 index 000000000..03bb69a41 --- /dev/null +++ b/test_regress/t/t_case_enum_complete_wildcard.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-CASEINCOMPLETE"]) + +test.passes() diff --git a/test_regress/t/t_case_enum_emptyish.pl b/test_regress/t/t_case_enum_emptyish.pl deleted file mode 100755 index 7d49cd2cd..000000000 --- a/test_regress/t/t_case_enum_emptyish.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_enum_emptyish.py b/test_regress/t/t_case_enum_emptyish.py new file mode 100755 index 000000000..539f320b1 --- /dev/null +++ b/test_regress/t/t_case_enum_emptyish.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test) + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_enum_incomplete_bad.pl b/test_regress/t/t_case_enum_incomplete_bad.pl deleted file mode 100755 index 1d5773686..000000000 --- a/test_regress/t/t_case_enum_incomplete_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--assert'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_enum_incomplete_bad.py b/test_regress/t/t_case_enum_incomplete_bad.py new file mode 100755 index 000000000..0275f2df9 --- /dev/null +++ b/test_regress/t/t_case_enum_incomplete_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_enum_incomplete_wildcard_bad.pl b/test_regress/t/t_case_enum_incomplete_wildcard_bad.pl deleted file mode 100755 index 1d5773686..000000000 --- a/test_regress/t/t_case_enum_incomplete_wildcard_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--assert'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_enum_incomplete_wildcard_bad.py b/test_regress/t/t_case_enum_incomplete_wildcard_bad.py new file mode 100755 index 000000000..0275f2df9 --- /dev/null +++ b/test_regress/t/t_case_enum_incomplete_wildcard_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_genx_bad.pl b/test_regress/t/t_case_genx_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_case_genx_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_genx_bad.py b/test_regress/t/t_case_genx_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_genx_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_group.pl b/test_regress/t/t_case_group.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_group.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_group.py b/test_regress/t/t_case_group.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_group.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_huge.pl b/test_regress/t/t_case_huge.pl deleted file mode 100755 index c8266ccbc..000000000 --- a/test_regress/t/t_case_huge.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10); - file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 8); -} elsif ($Self->{vltmt}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10); - file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 9); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_huge.py b/test_regress/t/t_case_huge.py new file mode 100755 index 000000000..7b6f76fea --- /dev/null +++ b/test_regress/t/t_case_huge.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 10) + test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', 8) +elif test.vltmt: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 10) + test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', 9) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_huge_sub.v b/test_regress/t/t_case_huge_sub.v index b593c05fa..b0d8e72c5 100644 --- a/test_regress/t/t_case_huge_sub.v +++ b/test_regress/t/t_case_huge_sub.v @@ -25,8 +25,11 @@ module t_case_huge_sub (/*AUTOARG*/ // End of automatics // ============================= - // Created from perl - // for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); }; + // Created from Python3: + // for i in range(1024): + // print(" 10'h%03x: begin outa = 10'h%03x; outb = 2'b%d%d; outc = 1'b%d; end" + // % (i, random.randint(0,1024), random.randint(0,1), + // random.randint(0,1), random.randint(0,1))) always @(/*AS*/index) begin case (index) diff --git a/test_regress/t/t_case_huge_sub2.v b/test_regress/t/t_case_huge_sub2.v index 20d8422ca..c03c39889 100644 --- a/test_regress/t/t_case_huge_sub2.v +++ b/test_regress/t/t_case_huge_sub2.v @@ -21,8 +21,11 @@ module t_case_huge_sub2 (/*AUTOARG*/ // End of automatics // ============================= - // Created from perl - // for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); }; + // Created from Python3: + // for i in range(1024): + // print(" 10'h%03x: begin outa = 10'h%03x; outb = 2'b%d%d; outc = 1'b%d; end" + // % (i, random.randint(0,1024), random.randint(0,1), + // random.randint(0,1), random.randint(0,1))) always @(/*AS*/index) begin case (index[7:0]) diff --git a/test_regress/t/t_case_huge_sub3.v b/test_regress/t/t_case_huge_sub3.v index 82f100177..aba38bf15 100644 --- a/test_regress/t/t_case_huge_sub3.v +++ b/test_regress/t/t_case_huge_sub3.v @@ -22,9 +22,10 @@ module t_case_huge_sub3 (/*AUTOARG*/ // End of automatics // ============================= - // Created from perl - //for $i (0..255) { $r=rand(4); printf "\t8'h%02x: begin outr <= outr^index[8:5]^4'h%01x; end\n", $i, - //rand(256); }; + // Created from Pthon3: + // for i in range(256): + // print(" 8'h%02x: begin outr <= outr^index[8:5]^4'h%01x; end" + // % (i, random.randint(0,15))) // Reset cheating initial outr = 4'b0; diff --git a/test_regress/t/t_case_incrdecr.pl b/test_regress/t/t_case_incrdecr.pl deleted file mode 100755 index 729c0cc8a..000000000 --- a/test_regress/t/t_case_incrdecr.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--trace --fno-split -x-assign 0"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_incrdecr.py b/test_regress/t/t_case_incrdecr.py new file mode 100755 index 000000000..30ddf27c9 --- /dev/null +++ b/test_regress/t/t_case_incrdecr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--trace --fno-split -x-assign 0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_inside.pl b/test_regress/t/t_case_inside.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_inside.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_inside.py b/test_regress/t/t_case_inside.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_inside.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_inside_bad.pl b/test_regress/t/t_case_inside_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_case_inside_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_inside_bad.py b/test_regress/t/t_case_inside_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_inside_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_itemwidth.pl b/test_regress/t/t_case_itemwidth.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_itemwidth.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_itemwidth.py b/test_regress/t/t_case_itemwidth.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_itemwidth.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_nest.pl b/test_regress/t/t_case_nest.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_nest.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_nest.py b/test_regress/t/t_case_nest.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_nest.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_onehot.pl b/test_regress/t/t_case_onehot.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_onehot.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_onehot.py b/test_regress/t/t_case_onehot.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_onehot.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_orig.pl b/test_regress/t/t_case_orig.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_orig.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_orig.py b/test_regress/t/t_case_orig.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_orig.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_overlap_bad.pl b/test_regress/t/t_case_overlap_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_case_overlap_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_overlap_bad.py b/test_regress/t/t_case_overlap_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_overlap_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_reducer.pl b/test_regress/t/t_case_reducer.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_reducer.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_reducer.py b/test_regress/t/t_case_reducer.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_reducer.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_string.pl b/test_regress/t/t_case_string.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_string.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_string.py b/test_regress/t/t_case_string.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_string2.pl b/test_regress/t/t_case_string2.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_case_string2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_string2.py b/test_regress/t/t_case_string2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_string2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_unique_many.pl b/test_regress/t/t_case_unique_many.pl deleted file mode 100755 index df24ee6be..000000000 --- a/test_regress/t/t_case_unique_many.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--assert"], - sanitize => 0, # GCC 11.4.0 hang bug - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_unique_many.py b/test_regress/t/t_case_unique_many.py new file mode 100755 index 000000000..15e80d521 --- /dev/null +++ b/test_regress/t/t_case_unique_many.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--assert"], sanitize=False) # GCC 11.4.0 hang bug + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_wild.pl b/test_regress/t/t_case_wild.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_case_wild.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_wild.py b/test_regress/t/t_case_wild.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_wild.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_wild.v b/test_regress/t/t_case_wild.v index ac8db4014..ef2002a14 100644 --- a/test_regress/t/t_case_wild.v +++ b/test_regress/t/t_case_wild.v @@ -60,9 +60,6 @@ module sub (/*AUTOARG*/ output reg [4:0] out2; always @* begin - // Test empty cases - casez (in[0]) - endcase casez (in) 24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00}; 24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00}; diff --git a/test_regress/t/t_case_write1.pl b/test_regress/t/t_case_write1.pl deleted file mode 100755 index 33e2bb517..000000000 --- a/test_regress/t/t_case_write1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats -O3 -x-assign fast"], - ); - -execute( - check_finished => 1, - ); - -files_identical("$Self->{obj_dir}/$Self->{name}_logger.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_case_write1.py b/test_regress/t/t_case_write1.py new file mode 100755 index 000000000..37d0f7a42 --- /dev/null +++ b/test_regress/t/t_case_write1.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats -O3 -x-assign fast"]) + +test.execute() + +test.files_identical(test.obj_dir + "/" + test.name + "_logger.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_write1_noexpand.pl b/test_regress/t/t_case_write1_noexpand.pl deleted file mode 100755 index 48c57c39a..000000000 --- a/test_regress/t/t_case_write1_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_case_write1.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_write1_noexpand.py b/test_regress/t/t_case_write1_noexpand.py new file mode 100755 index 000000000..3ed6fde1c --- /dev/null +++ b/test_regress/t/t_case_write1_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_case_write1.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_write2.pl b/test_regress/t/t_case_write2.pl deleted file mode 100755 index 33e2bb517..000000000 --- a/test_regress/t/t_case_write2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats -O3 -x-assign fast"], - ); - -execute( - check_finished => 1, - ); - -files_identical("$Self->{obj_dir}/$Self->{name}_logger.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_case_write2.py b/test_regress/t/t_case_write2.py new file mode 100755 index 000000000..37d0f7a42 --- /dev/null +++ b/test_regress/t/t_case_write2.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats -O3 -x-assign fast"]) + +test.execute() + +test.files_identical(test.obj_dir + "/" + test.name + "_logger.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_x.pl b/test_regress/t/t_case_x.pl deleted file mode 100755 index 005873da6..000000000 --- a/test_regress/t/t_case_x.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--x-assign 0"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_x.py b/test_regress/t/t_case_x.py new file mode 100755 index 000000000..8aee590f3 --- /dev/null +++ b/test_regress/t/t_case_x.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-assign 0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_x_bad.pl b/test_regress/t/t_case_x_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_case_x_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_x_bad.py b/test_regress/t/t_case_x_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_x_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_zx_bad.pl b/test_regress/t/t_case_zx_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_case_zx_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_zx_bad.py b/test_regress/t/t_case_zx_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_zx_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cast.pl b/test_regress/t/t_cast.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_cast.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast.py b/test_regress/t/t_cast.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_cast.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_cast_class.pl b/test_regress/t/t_cast_class.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_cast_class.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_class.py b/test_regress/t/t_cast_class.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_cast_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_cast_class_incompat_bad.pl b/test_regress/t/t_cast_class_incompat_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_cast_class_incompat_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_class_incompat_bad.py b/test_regress/t/t_cast_class_incompat_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_cast_class_incompat_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cast_param_logic.pl b/test_regress/t/t_cast_param_logic.pl deleted file mode 100755 index 09b2ce4eb..000000000 --- a/test_regress/t/t_cast_param_logic.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_param_logic.py b/test_regress/t/t_cast_param_logic.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_cast_param_logic.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_cast_param_type.pl b/test_regress/t/t_cast_param_type.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_cast_param_type.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_param_type.py b/test_regress/t/t_cast_param_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_cast_param_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_cast_size_bad.pl b/test_regress/t/t_cast_size_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_cast_size_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_size_bad.py b/test_regress/t/t_cast_size_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_cast_size_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cast_types.pl b/test_regress/t/t_cast_types.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_cast_types.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_types.py b/test_regress/t/t_cast_types.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_cast_types.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_castdyn.pl b/test_regress/t/t_castdyn.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_castdyn.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn.py b/test_regress/t/t_castdyn.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_castdyn.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_castdyn_bbox.pl b/test_regress/t/t_castdyn_bbox.pl deleted file mode 100755 index 3c7a5909b..000000000 --- a/test_regress/t/t_castdyn_bbox.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_castdyn.v"); - -lint( - verilator_flags2 => ['-bbox-unsup'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn_bbox.py b/test_regress/t/t_castdyn_bbox.py new file mode 100755 index 000000000..3bc0aac7a --- /dev/null +++ b/test_regress/t/t_castdyn_bbox.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_castdyn.v" + +test.lint(verilator_flags2=['-bbox-unsup']) + +test.passes() diff --git a/test_regress/t/t_castdyn_castconst_bad.pl b/test_regress/t/t_castdyn_castconst_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_castdyn_castconst_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn_castconst_bad.py b/test_regress/t/t_castdyn_castconst_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_castdyn_castconst_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_castdyn_enum.pl b/test_regress/t/t_castdyn_enum.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_castdyn_enum.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn_enum.py b/test_regress/t/t_castdyn_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_castdyn_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_castdyn_run_bad.pl b/test_regress/t/t_castdyn_run_bad.pl deleted file mode 100755 index 8b1946a7b..000000000 --- a/test_regress/t/t_castdyn_run_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn_run_bad.py b/test_regress/t/t_castdyn_run_bad.py new file mode 100755 index 000000000..2fdd6e92d --- /dev/null +++ b/test_regress/t/t_castdyn_run_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_castdyn_unsup_bad.pl b/test_regress/t/t_castdyn_unsup_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_castdyn_unsup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn_unsup_bad.py b/test_regress/t/t_castdyn_unsup_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_castdyn_unsup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_ccache_report.pl b/test_regress/t/t_ccache_report.pl deleted file mode 100755 index 90c5004a2..000000000 --- a/test_regress/t/t_ccache_report.pl +++ /dev/null @@ -1,49 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->cfg_with_ccache) { - skip("Requires configuring with ccache"); -} -else { - top_filename("t_a1_first_cc.v"); - - # This test requires rebuilding the object files to check the ccache log - foreach my $filename (glob("$Self->{obj_dir}/*.o")) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; - } - - compile( - verilator_flags2 => ['--trace'], - make_flags => "ccache-report" - ); - - my $report = "$Self->{obj_dir}/$Self->{vm_prefix}__ccache_report.txt"; - - # We do not actually want to make this test depend on whether the file was - # cached or not, so trim the report to ignore actual caching behaviour - run(cmd => ["sed", "-i", "-e", "'s/ : .*/ : IGNORED/; /|/s/.*/IGNORED/;'", $report]); - files_identical($report, "t/$Self->{name}__ccache_report_initial.out"); - - # Now rebuild again (should be all up to date) - run( - logfile => "$Self->{obj_dir}/rebuild.log", - cmd => ["make", "-C", $Self->{obj_dir}, - "-f", "$Self->{vm_prefix}.mk", - $Self->{vm_prefix}, "ccache-report"] - ); - - files_identical($report, "t/$Self->{name}__ccache_report_rebuild.out"); -} - -ok(1); -1; diff --git a/test_regress/t/t_ccache_report.py b/test_regress/t/t_ccache_report.py new file mode 100755 index 000000000..56d6a44af --- /dev/null +++ b/test_regress/t/t_ccache_report.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_a1_first_cc.v" + +if not test.cfg_with_ccache: + test.skip("Requires configuring with ccache") + +# This test requires rebuilding the object files to check the ccache log +for filename in glob.glob(test.obj_dir + "/*.o"): + test.unlink_ok(filename) + +test.compile(verilator_flags2=['--trace'], make_flags=["ccache-report"]) + +report = test.obj_dir + "/" + test.vm_prefix + "__ccache_report.txt" + +# We do not actually want to make this test depend on whether the file was +# cached or not, so trim the report to ignore actual caching behaviour +test.run(cmd=["sed", "-i", "-e", "'s/ : .*/ : IGNORED/; /|/s/.*/IGNORED/;'", report]) +test.files_identical(report, "t/" + test.name + "__ccache_report_initial.out") + +# Now rebuild again (should be all up to date) +test.run(logfile=test.obj_dir + "/rebuild.log", + cmd=[ + "make", "-C " + test.obj_dir, "-f " + test.vm_prefix + ".mk", test.vm_prefix, + "ccache-report" + ]) + +test.files_identical(report, "t/" + test.name + "__ccache_report_rebuild.out") + +test.passes() diff --git a/test_regress/t/t_cellarray.pl b/test_regress/t/t_cellarray.pl deleted file mode 100755 index fa5c2725e..000000000 --- a/test_regress/t/t_cellarray.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--stats -fno-dfg"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Gate assign merged\s+(\d+)/i, 28); -} - -ok(1); -1; diff --git a/test_regress/t/t_cellarray.py b/test_regress/t/t_cellarray.py new file mode 100755 index 000000000..402425622 --- /dev/null +++ b/test_regress/t/t_cellarray.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--stats -fno-dfg"]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Gate assign merged\s+(\d+)', 28) + +test.passes() diff --git a/test_regress/t/t_checker.pl b/test_regress/t/t_checker.pl deleted file mode 100755 index 657040447..000000000 --- a/test_regress/t/t_checker.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--assert'], - expect_filename => $Self->{golden_filename}, - fails => $Self->{vlt_all}, - ); - -#execute( -# check_finished => 1, -# ); - -ok(1); -1; diff --git a/test_regress/t/t_checker.py b/test_regress/t/t_checker.py new file mode 100755 index 000000000..c735f5265 --- /dev/null +++ b/test_regress/t/t_checker.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--assert'], + expect_filename=test.golden_filename, + fails=test.vlt_all) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_chg_first.pl b/test_regress/t/t_chg_first.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_chg_first.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_chg_first.py b/test_regress/t/t_chg_first.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_chg_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class1.pl b/test_regress/t/t_class1.pl deleted file mode 100755 index 6247bd126..000000000 --- a/test_regress/t/t_class1.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class1.py b/test_regress/t/t_class1.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_class1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class2.pl b/test_regress/t/t_class2.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class2.py b/test_regress/t/t_class2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_assign_bad.pl b/test_regress/t/t_class_assign_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_class_assign_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_assign_bad.py b/test_regress/t/t_class_assign_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_class_assign_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_assign_cond.pl b/test_regress/t/t_class_assign_cond.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_assign_cond.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_assign_cond.py b/test_regress/t/t_class_assign_cond.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_assign_cond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_assign_cond_bad.pl b/test_regress/t/t_class_assign_cond_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_class_assign_cond_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_assign_cond_bad.py b/test_regress/t/t_class_assign_cond_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_class_assign_cond_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_builtin_bad.pl b/test_regress/t/t_class_builtin_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_builtin_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_builtin_bad.py b/test_regress/t/t_class_builtin_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_builtin_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_capitalization.pl b/test_regress/t/t_class_capitalization.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_class_capitalization.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_capitalization.py b/test_regress/t/t_class_capitalization.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_capitalization.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_class.pl b/test_regress/t/t_class_class.pl deleted file mode 100755 index 6ad7137de..000000000 --- a/test_regress/t/t_class_class.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_class.py b/test_regress/t/t_class_class.py new file mode 100755 index 000000000..710a094ab --- /dev/null +++ b/test_regress/t/t_class_class.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_compare.pl b/test_regress/t/t_class_compare.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_class_compare.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_compare.py b/test_regress/t/t_class_compare.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_const.pl b/test_regress/t/t_class_const.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_const.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_const.py b/test_regress/t/t_class_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_copy.pl b/test_regress/t/t_class_copy.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_copy.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_copy.py b/test_regress/t/t_class_copy.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_copy.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_copy2.pl b/test_regress/t/t_class_copy2.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_copy2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_copy2.py b/test_regress/t/t_class_copy2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_copy2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_copy_bad.pl b/test_regress/t/t_class_copy_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_copy_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_copy_bad.py b/test_regress/t/t_class_copy_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_copy_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_diamond.pl b/test_regress/t/t_class_diamond.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_class_diamond.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_diamond.py b/test_regress/t/t_class_diamond.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_diamond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_dict.pl b/test_regress/t/t_class_dict.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_dict.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_dict.py b/test_regress/t/t_class_dict.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_dict.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_enum.pl b/test_regress/t/t_class_enum.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_enum.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_enum.py b/test_regress/t/t_class_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends.pl b/test_regress/t/t_class_extends.pl deleted file mode 100755 index 696e24d17..000000000 --- a/test_regress/t/t_class_extends.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_flags => 'VM_PARALLEL_BUILDS=1', # bug2775 - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends.py b/test_regress/t/t_class_extends.py new file mode 100755 index 000000000..952d410ef --- /dev/null +++ b/test_regress/t/t_class_extends.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_flags=['VM_PARALLEL_BUILDS=1']) # bug2775) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends1.pl b/test_regress/t/t_class_extends1.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_extends1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends1.py b/test_regress/t/t_class_extends1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extends1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends2.pl b/test_regress/t/t_class_extends2.pl deleted file mode 100755 index 696e24d17..000000000 --- a/test_regress/t/t_class_extends2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_flags => 'VM_PARALLEL_BUILDS=1', # bug2775 - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends2.py b/test_regress/t/t_class_extends2.py new file mode 100755 index 000000000..952d410ef --- /dev/null +++ b/test_regress/t/t_class_extends2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_flags=['VM_PARALLEL_BUILDS=1']) # bug2775) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_alias_unsup.pl b/test_regress/t/t_class_extends_alias_unsup.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_class_extends_alias_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_alias_unsup.py b/test_regress/t/t_class_extends_alias_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_alias_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_aliased_real_bad.pl b/test_regress/t/t_class_extends_aliased_real_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_class_extends_aliased_real_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_aliased_real_bad.py b/test_regress/t/t_class_extends_aliased_real_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_aliased_real_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_bad.pl b/test_regress/t/t_class_extends_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_extends_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_bad.py b/test_regress/t/t_class_extends_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_colon.pl b/test_regress/t/t_class_extends_colon.pl deleted file mode 100755 index 696e24d17..000000000 --- a/test_regress/t/t_class_extends_colon.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_flags => 'VM_PARALLEL_BUILDS=1', # bug2775 - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_colon.py b/test_regress/t/t_class_extends_colon.py new file mode 100755 index 000000000..952d410ef --- /dev/null +++ b/test_regress/t/t_class_extends_colon.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_flags=['VM_PARALLEL_BUILDS=1']) # bug2775) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_int_param_bad.pl b/test_regress/t/t_class_extends_int_param_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_class_extends_int_param_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_int_param_bad.py b/test_regress/t/t_class_extends_int_param_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_int_param_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_nf_bad.pl b/test_regress/t/t_class_extends_nf_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_extends_nf_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_nf_bad.py b/test_regress/t/t_class_extends_nf_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_nf_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_param.pl b/test_regress/t/t_class_extends_param.pl deleted file mode 100755 index e191e87f4..000000000 --- a/test_regress/t/t_class_extends_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_param.py b/test_regress/t/t_class_extends_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extends_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_param_unused.pl b/test_regress/t/t_class_extends_param_unused.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_extends_param_unused.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_param_unused.py b/test_regress/t/t_class_extends_param_unused.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extends_param_unused.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_protect_ids.pl b/test_regress/t/t_class_extends_protect_ids.pl deleted file mode 100755 index 883b58df0..000000000 --- a/test_regress/t/t_class_extends_protect_ids.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d" )) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -top_filename("t/t_class_extends.v"); - -compile( - make_flags => 'VM_PARALLEL_BUILDS=1', # bug2775 - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_protect_ids.py b/test_regress/t/t_class_extends_protect_ids.py new file mode 100755 index 000000000..f6fa53979 --- /dev/null +++ b/test_regress/t/t_class_extends_protect_ids.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_class_extends.v" + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile( + make_flags=['VM_PARALLEL_BUILDS=1'], # bug2775 + verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_rec_bad.pl b/test_regress/t/t_class_extends_rec_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_extends_rec_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_rec_bad.py b/test_regress/t/t_class_extends_rec_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_rec_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_this.pl b/test_regress/t/t_class_extends_this.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_extends_this.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_this.py b/test_regress/t/t_class_extends_this.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extends_this.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_this3.pl b/test_regress/t/t_class_extends_this3.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_extends_this3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_this3.py b/test_regress/t/t_class_extends_this3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extends_this3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_this_protect_ids.pl b/test_regress/t/t_class_extends_this_protect_ids.pl deleted file mode 100755 index 6e7e4d2b2..000000000 --- a/test_regress/t/t_class_extends_this_protect_ids.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d" )) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -top_filename("t/t_class_extends_this.v"); - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_this_protect_ids.py b/test_regress/t/t_class_extends_this_protect_ids.py new file mode 100755 index 000000000..8ed657472 --- /dev/null +++ b/test_regress/t/t_class_extends_this_protect_ids.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_class_extends_this.v" + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_vsyment.pl b/test_regress/t/t_class_extends_vsyment.pl deleted file mode 100755 index 8eeb2a6f6..000000000 --- a/test_regress/t/t_class_extends_vsyment.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_vsyment.py b/test_regress/t/t_class_extends_vsyment.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_class_extends_vsyment.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_class_extern.pl b/test_regress/t/t_class_extern.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_extern.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extern.py b/test_regress/t/t_class_extern.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extern.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extern_bad.pl b/test_regress/t/t_class_extern_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_extern_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extern_bad.py b/test_regress/t/t_class_extern_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extern_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_field_name.pl b/test_regress/t/t_class_field_name.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_field_name.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_field_name.py b/test_regress/t/t_class_field_name.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_field_name.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_format.pl b/test_regress/t/t_class_format.pl deleted file mode 100755 index 03b63c1a0..000000000 --- a/test_regress/t/t_class_format.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_format.py b/test_regress/t/t_class_format.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_class_format.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_forward.pl b/test_regress/t/t_class_forward.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_forward.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_forward.py b/test_regress/t/t_class_forward.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_forward.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_func_arg_unused.pl b/test_regress/t/t_class_func_arg_unused.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_class_func_arg_unused.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_func_arg_unused.py b/test_regress/t/t_class_func_arg_unused.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_func_arg_unused.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_func_dot.pl b/test_regress/t/t_class_func_dot.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_func_dot.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_func_dot.py b/test_regress/t/t_class_func_dot.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_func_dot.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_fwd_cc.pl b/test_regress/t/t_class_fwd_cc.pl deleted file mode 100755 index aca1cb3c1..000000000 --- a/test_regress/t/t_class_fwd_cc.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_fwd_cc.py b/test_regress/t/t_class_fwd_cc.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_class_fwd_cc.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_class_if_assign.pl b/test_regress/t/t_class_if_assign.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_if_assign.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_if_assign.py b/test_regress/t/t_class_if_assign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_if_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_imp2.pl b/test_regress/t/t_class_imp2.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_class_imp2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_imp2.py b/test_regress/t/t_class_imp2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_imp2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_inc.pl b/test_regress/t/t_class_inc.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_class_inc.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_inc.py b/test_regress/t/t_class_inc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_inc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_local.pl b/test_regress/t/t_class_local.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_local.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_local.py b/test_regress/t/t_class_local.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_local_bad.pl b/test_regress/t/t_class_local_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_local_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_local_bad.py b/test_regress/t/t_class_local_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_local_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_local_protect_ids.pl b/test_regress/t/t_class_local_protect_ids.pl deleted file mode 100755 index 724eb9525..000000000 --- a/test_regress/t/t_class_local_protect_ids.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d")) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -top_filename("t/t_class_local.v"); - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_local_protect_ids.py b/test_regress/t/t_class_local_protect_ids.py new file mode 100755 index 000000000..81b18d6cc --- /dev/null +++ b/test_regress/t/t_class_local_protect_ids.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_class_local.v" + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_local_typedef_bad.out b/test_regress/t/t_class_local_typedef_bad.out new file mode 100644 index 000000000..26653bffe --- /dev/null +++ b/test_regress/t/t_class_local_typedef_bad.out @@ -0,0 +1,14 @@ +%Error-ENCAPSULATED: t/t_class_local_typedef_bad.v:13:8: 't1' is hidden as 'local' within this context (IEEE 1800-2023 8.18) + 13 | Cls::t1 var1; + | ^~ + t/t_class_local_typedef_bad.v:13:8: ... Location of definition + 9 | local typedef bit t1; + | ^~ + ... For error description see https://verilator.org/warn/ENCAPSULATED?v=latest +%Error-ENCAPSULATED: t/t_class_local_typedef_bad.v:14:8: 't2' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) + 14 | Cls::t2 var2; + | ^~ + t/t_class_local_typedef_bad.v:14:8: ... Location of definition + 10 | protected typedef bit t2; + | ^~ +%Error: Exiting due to diff --git a/test_regress/t/t_class_local_typedef_bad.py b/test_regress/t/t_class_local_typedef_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_local_typedef_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_local_typedef_bad.v b/test_regress/t/t_class_local_typedef_bad.v new file mode 100755 index 000000000..1688e7266 --- /dev/null +++ b/test_regress/t/t_class_local_typedef_bad.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + class Cls; + local typedef bit t1; + protected typedef bit t2; + endclass + + Cls::t1 var1; // BAD: access error expected + Cls::t2 var2; // BAD: access error expected + +endmodule diff --git a/test_regress/t/t_class_member_bad.pl b/test_regress/t/t_class_member_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_member_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_member_bad.py b/test_regress/t/t_class_member_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_member_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_member_bad2.pl b/test_regress/t/t_class_member_bad2.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_member_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_member_bad2.py b/test_regress/t/t_class_member_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_member_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_member_sens.pl b/test_regress/t/t_class_member_sens.pl deleted file mode 100755 index 3aa893e2f..000000000 --- a/test_regress/t/t_class_member_sens.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - sanitize => 1, - ); - -execute( - check_finished => 1, - aslr_off => 1, # Some GCC versions hit an address-sanitizer bug otherwise - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_member_sens.py b/test_regress/t/t_class_member_sens.py new file mode 100755 index 000000000..de7e2e82d --- /dev/null +++ b/test_regress/t/t_class_member_sens.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(sanitize=True) + +test.execute(aslr_off=True) # Some GCC versions hit an address-sanitizer bug otherwise) + +test.passes() diff --git a/test_regress/t/t_class_member_var_virt_bad.pl b/test_regress/t/t_class_member_var_virt_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_class_member_var_virt_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_member_var_virt_bad.py b/test_regress/t/t_class_member_var_virt_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_member_var_virt_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_membersel_int.pl b/test_regress/t/t_class_membersel_int.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_class_membersel_int.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_membersel_int.py b/test_regress/t/t_class_membersel_int.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_membersel_int.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_membersel_int.v b/test_regress/t/t_class_membersel_int.v index a0367f11d..68e70f22b 100644 --- a/test_regress/t/t_class_membersel_int.v +++ b/test_regress/t/t_class_membersel_int.v @@ -20,5 +20,5 @@ module Sub; endmodule module t; - Sub foo; + Sub foo(); endmodule diff --git a/test_regress/t/t_class_method.pl b/test_regress/t/t_class_method.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_method.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_method.py b/test_regress/t/t_class_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_method_bad.pl b/test_regress/t/t_class_method_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_method_bad.py b/test_regress/t/t_class_method_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_method_str_literal.pl b/test_regress/t/t_class_method_str_literal.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_class_method_str_literal.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_method_str_literal.py b/test_regress/t/t_class_method_str_literal.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_method_str_literal.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_method_struct.pl b/test_regress/t/t_class_method_struct.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_method_struct.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_method_struct.py b/test_regress/t/t_class_method_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_method_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_mispure_bad.pl b/test_regress/t/t_class_mispure_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_class_mispure_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_mispure_bad.py b/test_regress/t/t_class_mispure_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_mispure_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_misstatic_bad.pl b/test_regress/t/t_class_misstatic_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_class_misstatic_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_misstatic_bad.py b/test_regress/t/t_class_misstatic_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_misstatic_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_mod_bad.pl b/test_regress/t/t_class_mod_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_mod_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_mod_bad.py b/test_regress/t/t_class_mod_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_mod_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_module.pl b/test_regress/t/t_class_module.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_module.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_module.py b/test_regress/t/t_class_module.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_module.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_name.pl b/test_regress/t/t_class_name.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_name.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_name.py b/test_regress/t/t_class_name.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_name.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_nested_link.pl b/test_regress/t/t_class_nested_link.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_nested_link.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_nested_link.py b/test_regress/t/t_class_nested_link.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_nested_link.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_new.pl b/test_regress/t/t_class_new.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_new.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new.py b/test_regress/t/t_class_new.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_new.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_new_bad.pl b/test_regress/t/t_class_new_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_new_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_bad.py b/test_regress/t/t_class_new_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_new_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_new_default.pl b/test_regress/t/t_class_new_default.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_class_new_default.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_default.py b/test_regress/t/t_class_new_default.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_new_default.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_new_noparen.pl b/test_regress/t/t_class_new_noparen.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_class_new_noparen.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_noparen.py b/test_regress/t/t_class_new_noparen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_new_noparen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_new_ref_bad.pl b/test_regress/t/t_class_new_ref_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_class_new_ref_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_ref_bad.py b/test_regress/t/t_class_new_ref_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_new_ref_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_new_return.pl b/test_regress/t/t_class_new_return.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_new_return.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_return.py b/test_regress/t/t_class_new_return.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_new_return.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_new_this.pl b/test_regress/t/t_class_new_this.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_class_new_this.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_this.py b/test_regress/t/t_class_new_this.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_new_this.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_null_bad.pl b/test_regress/t/t_class_null_bad.pl deleted file mode 100755 index 8b1946a7b..000000000 --- a/test_regress/t/t_class_null_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_null_bad.py b/test_regress/t/t_class_null_bad.py new file mode 100755 index 000000000..2fdd6e92d --- /dev/null +++ b/test_regress/t/t_class_null_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_null_struct.pl b/test_regress/t/t_class_null_struct.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_null_struct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_null_struct.py b/test_regress/t/t_class_null_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_null_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_override.pl b/test_regress/t/t_class_override.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_override.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_override.py b/test_regress/t/t_class_override.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_override.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_override_bad.pl b/test_regress/t/t_class_override_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_override_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_override_bad.py b/test_regress/t/t_class_override_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_override_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_package.pl b/test_regress/t/t_class_package.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_package.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_package.py b/test_regress/t/t_class_package.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_package.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_packed.pl b/test_regress/t/t_class_packed.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_class_packed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_packed.py b/test_regress/t/t_class_packed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_packed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_packed.v b/test_regress/t/t_class_packed.v index 676557e43..daef3ec55 100644 --- a/test_regress/t/t_class_packed.v +++ b/test_regress/t/t_class_packed.v @@ -10,11 +10,11 @@ module t (/*AUTOARG*/ ); input clk; - //TODO sub #(.WIDTH(1)) w1; - //TODO sub #(.WIDTH(2)) w2; - //TODO sub #(.WIDTH(3)) w3; - //TODO sub #(.WIDTH(4)) w4; - sub #(.WIDTH(5)) w5; + //TODO sub #(.WIDTH(1)) w1(); + //TODO sub #(.WIDTH(2)) w2(); + //TODO sub #(.WIDTH(3)) w3(); + //TODO sub #(.WIDTH(4)) w4(); + sub #(.WIDTH(5)) w5(); always @ (posedge clk) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_class_param.pl b/test_regress/t/t_class_param.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param.py b/test_regress/t/t_class_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_bad1.pl b/test_regress/t/t_class_param_bad1.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_param_bad1.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_bad1.py b/test_regress/t/t_class_param_bad1.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_bad1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_bad2.pl b/test_regress/t/t_class_param_bad2.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_class_param_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_bad2.py b/test_regress/t/t_class_param_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_bad_paren.pl b/test_regress/t/t_class_param_bad_paren.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_class_param_bad_paren.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_bad_paren.py b/test_regress/t/t_class_param_bad_paren.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_bad_paren.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_circ_bad.pl b/test_regress/t/t_class_param_circ_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_class_param_circ_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_circ_bad.py b/test_regress/t/t_class_param_circ_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_class_param_circ_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_comma_bad.pl b/test_regress/t/t_class_param_comma_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_param_comma_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_comma_bad.py b/test_regress/t/t_class_param_comma_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_comma_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_enum.pl b/test_regress/t/t_class_param_enum.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_param_enum.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_enum.py b/test_regress/t/t_class_param_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_enum_bad.pl b/test_regress/t/t_class_param_enum_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_class_param_enum_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_enum_bad.py b/test_regress/t/t_class_param_enum_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_class_param_enum_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_extends.pl b/test_regress/t/t_class_param_extends.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_param_extends.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_extends.py b/test_regress/t/t_class_param_extends.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_extends.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_extends2.pl b/test_regress/t/t_class_param_extends2.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_param_extends2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_extends2.py b/test_regress/t/t_class_param_extends2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_extends2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_extends3.pl b/test_regress/t/t_class_param_extends3.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_class_param_extends3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_extends3.py b/test_regress/t/t_class_param_extends3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_extends3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_extra_bad.out b/test_regress/t/t_class_param_extra_bad.out new file mode 100644 index 000000000..65b1d443e --- /dev/null +++ b/test_regress/t/t_class_param_extra_bad.out @@ -0,0 +1,11 @@ +%Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:21: Parameter not found: '__paramNumber1' + 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; + | ^~~ + ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest +%Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:26: Parameter not found: '__paramNumber2' + 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; + | ^~~~~~~ +%Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:35: Parameter not found: '__paramNumber3' + 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; + | ^~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_class_param_extra_bad.py b/test_regress/t/t_class_param_extra_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_extra_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_extra_bad.v b/test_regress/t/t_class_param_extra_bad.v new file mode 100644 index 000000000..378c39ebe --- /dev/null +++ b/test_regress/t/t_class_param_extra_bad.v @@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + class Cls1; + typedef bit bool_t; + endclass + + localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; + +endmodule diff --git a/test_regress/t/t_class_param_func_return.pl b/test_regress/t/t_class_param_func_return.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_param_func_return.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_func_return.py b/test_regress/t/t_class_param_func_return.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_func_return.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_lvalue.pl b/test_regress/t/t_class_param_lvalue.pl deleted file mode 100755 index 13587bf85..000000000 --- a/test_regress/t/t_class_param_lvalue.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_lvalue.py b/test_regress/t/t_class_param_lvalue.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_class_param_lvalue.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_class_param_mod.pl b/test_regress/t/t_class_param_mod.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_param_mod.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_mod.py b/test_regress/t/t_class_param_mod.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_mod.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_nconst_bad.pl b/test_regress/t/t_class_param_nconst_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_param_nconst_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_nconst_bad.py b/test_regress/t/t_class_param_nconst_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_nconst_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_nested_bad.pl b/test_regress/t/t_class_param_nested_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_class_param_nested_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_nested_bad.py b/test_regress/t/t_class_param_nested_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_class_param_nested_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_noinit.pl b/test_regress/t/t_class_param_noinit.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_class_param_noinit.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_noinit.py b/test_regress/t/t_class_param_noinit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_noinit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_noinit_bad.pl b/test_regress/t/t_class_param_noinit_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_class_param_noinit_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_noinit_bad.py b/test_regress/t/t_class_param_noinit_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_noinit_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_override_local_bad.pl b/test_regress/t/t_class_param_override_local_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_class_param_override_local_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_override_local_bad.py b/test_regress/t/t_class_param_override_local_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_param_override_local_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_pkg.pl b/test_regress/t/t_class_param_pkg.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_param_pkg.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_pkg.py b/test_regress/t/t_class_param_pkg.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_pkg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_rewrite.py b/test_regress/t/t_class_param_rewrite.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_rewrite.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_rewrite.v b/test_regress/t/t_class_param_rewrite.v new file mode 100644 index 000000000..17664ec71 --- /dev/null +++ b/test_regress/t/t_class_param_rewrite.v @@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module test; + typedef enum { FOO_0 } foo_e; + typedef enum { BAR_0 } bar_e; + + class baz #(parameter type E = foo_e); + static function void print(); + E enum_item; + if (enum_item.first().name() != "BAR_0") + $stop; + endfunction + endclass + + initial begin + baz#(bar_e)::print(); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_class_param_subtype_bad_paren.pl b/test_regress/t/t_class_param_subtype_bad_paren.pl deleted file mode 100755 index 13944a9e5..000000000 --- a/test_regress/t/t_class_param_subtype_bad_paren.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_class_param_subtype.v"); - -lint( - fails => 1, - v_flags2 => ['+define+BAD_PAREN'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_subtype_bad_paren.py b/test_regress/t/t_class_param_subtype_bad_paren.py new file mode 100755 index 000000000..6b8a1cf07 --- /dev/null +++ b/test_regress/t/t_class_param_subtype_bad_paren.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_class_param_subtype.v" + +test.lint(fails=True, v_flags2=['+define+BAD_PAREN'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_subtype_constsim.pl b/test_regress/t/t_class_param_subtype_constsim.pl deleted file mode 100755 index 2336fb402..000000000 --- a/test_regress/t/t_class_param_subtype_constsim.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_class_param_subtype.v"); - -compile( - v_flags2 => ['+define+CONSTSIM'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_subtype_constsim.py b/test_regress/t/t_class_param_subtype_constsim.py new file mode 100755 index 000000000..cc356de23 --- /dev/null +++ b/test_regress/t/t_class_param_subtype_constsim.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_class_param_subtype.v" + +test.compile(v_flags2=['+define+CONSTSIM']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_type.pl b/test_regress/t/t_class_param_type.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_param_type.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_type.py b/test_regress/t/t_class_param_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_typedef.pl b/test_regress/t/t_class_param_typedef.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_param_typedef.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_typedef.py b/test_regress/t/t_class_param_typedef.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_typedef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_typedef2.pl b/test_regress/t/t_class_param_typedef2.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_param_typedef2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_typedef2.py b/test_regress/t/t_class_param_typedef2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_typedef2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_unused_default.pl b/test_regress/t/t_class_param_unused_default.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_param_unused_default.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_unused_default.py b/test_regress/t/t_class_param_unused_default.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_unused_default.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_virtual_bad.pl b/test_regress/t/t_class_param_virtual_bad.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_class_param_virtual_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_virtual_bad.py b/test_regress/t/t_class_param_virtual_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_param_virtual_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_ref_as_arg_cast.pl b/test_regress/t/t_class_ref_as_arg_cast.pl deleted file mode 100755 index 8c2ca139b..000000000 --- a/test_regress/t/t_class_ref_as_arg_cast.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_ref_as_arg_cast.py b/test_regress/t/t_class_ref_as_arg_cast.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_class_ref_as_arg_cast.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_class_ref_bad.out b/test_regress/t/t_class_ref_bad.out new file mode 100644 index 000000000..d11276ec2 --- /dev/null +++ b/test_regress/t/t_class_ref_bad.out @@ -0,0 +1,4 @@ +%Error: Internal Error: t/t_class_ref_bad.v:15:11: ../V3LinkDot.cpp:#: Bad package link + 15 | s = ClsRigh::m_s; + | ^~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_class_ref_bad.py b/test_regress/t/t_class_ref_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_ref_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_ref_bad.v b/test_regress/t/t_class_ref_bad.v new file mode 100644 index 000000000..5f28f6967 --- /dev/null +++ b/test_regress/t/t_class_ref_bad.v @@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class ClsRight; + string m_s; +endclass + +module t (/*AUTOARG*/); + string s; + initial begin + // verilator lint_off PKGNODECL + s = ClsRigh::m_s; // Bad typo, issue #5475 + end +endmodule diff --git a/test_regress/t/t_class_ref_ref.py b/test_regress/t/t_class_ref_ref.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_class_ref_ref.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_class_ref_ref.v b/test_regress/t/t_class_ref_ref.v new file mode 100644 index 000000000..92cee9e8e --- /dev/null +++ b/test_regress/t/t_class_ref_ref.v @@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class Cls#(type T = bit); +endclass + +module t(/*AUTOARG*/); + + Cls#(bit) cb; + + Cls#(Cls#(bit)) ccb; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_class_short_circuit.pl b/test_regress/t/t_class_short_circuit.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_short_circuit.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_short_circuit.py b/test_regress/t/t_class_short_circuit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_short_circuit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_split.pl b/test_regress/t/t_class_split.pl deleted file mode 100755 index 2dd83547c..000000000 --- a/test_regress/t/t_class_split.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--output-split 10'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_split.py b/test_regress/t/t_class_split.py new file mode 100755 index 000000000..628bb8901 --- /dev/null +++ b/test_regress/t/t_class_split.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--output-split 10']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static.pl b/test_regress/t/t_class_static.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_class_static.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static.py b/test_regress/t/t_class_static.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static.v b/test_regress/t/t_class_static.v index f1df96ea5..f92c9a68b 100644 --- a/test_regress/t/t_class_static.v +++ b/test_regress/t/t_class_static.v @@ -30,12 +30,7 @@ class Cls; endfunction endclass -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); Cls a = new; Cls b = new; diff --git a/test_regress/t/t_class_static_default_arg.py b/test_regress/t/t_class_static_default_arg.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static_default_arg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_default_arg.v b/test_regress/t/t_class_static_default_arg.v new file mode 100644 index 000000000..19ebe5082 --- /dev/null +++ b/test_regress/t/t_class_static_default_arg.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +class Foo; + static function bit get_first(bit q[$] = {1'b1}); + return q[0]; + endfunction +endclass + +module t (/*AUTOARG*/); + + initial begin + bit first; + bit arg[$] = {1'b0, 1'b1}; + first = Foo::get_first(); + if (first != 1) $stop; + first = Foo::get_first(arg); + if (first != 0) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_class_static_member.pl b/test_regress/t/t_class_static_member.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_class_static_member.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_member.py b/test_regress/t/t_class_static_member.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static_member.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_member.v b/test_regress/t/t_class_static_member.v index fa4b417ad..1867b73b0 100644 --- a/test_regress/t/t_class_static_member.v +++ b/test_regress/t/t_class_static_member.v @@ -25,12 +25,7 @@ class Cls; endclass -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); Cls a = new; Cls b = new; diff --git a/test_regress/t/t_class_static_member_pkg.pl b/test_regress/t/t_class_static_member_pkg.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_class_static_member_pkg.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_member_pkg.py b/test_regress/t/t_class_static_member_pkg.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static_member_pkg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_member_pkg.v b/test_regress/t/t_class_static_member_pkg.v index 02770cd79..49d320198 100644 --- a/test_regress/t/t_class_static_member_pkg.v +++ b/test_regress/t/t_class_static_member_pkg.v @@ -27,12 +27,7 @@ class Cls; endclass endpackage -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); Pkg::Cls a = new; Pkg::Cls b = new; diff --git a/test_regress/t/t_class_static_member_sel.pl b/test_regress/t/t_class_static_member_sel.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_class_static_member_sel.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_member_sel.py b/test_regress/t/t_class_static_member_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static_member_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_method.pl b/test_regress/t/t_class_static_method.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_static_method.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_method.py b/test_regress/t/t_class_static_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_method_protect_ids.pl b/test_regress/t/t_class_static_method_protect_ids.pl deleted file mode 100755 index 208380b3b..000000000 --- a/test_regress/t/t_class_static_method_protect_ids.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d")) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -top_filename("t/t_class_static_method.v"); - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_method_protect_ids.py b/test_regress/t/t_class_static_method_protect_ids.py new file mode 100755 index 000000000..955f1a347 --- /dev/null +++ b/test_regress/t/t_class_static_method_protect_ids.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_class_static_method.v" + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_order.pl b/test_regress/t/t_class_static_order.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_static_order.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_order.py b/test_regress/t/t_class_static_order.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static_order.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_super_bad.out b/test_regress/t/t_class_super_bad.out index 088fbf489..3800174f6 100644 --- a/test_regress/t/t_class_super_bad.out +++ b/test_regress/t/t_class_super_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_class_super_bad.v:15:12: 'super' used outside class (IEEE 1800-2023 8.15) - 15 | super.addr = 2; +%Error: t/t_class_super_bad.v:12:12: 'super' used outside class (IEEE 1800-2023 8.15) + 12 | super.addr = 2; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_super_bad.pl b/test_regress/t/t_class_super_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_super_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_super_bad.py b/test_regress/t/t_class_super_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_super_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_super_bad.v b/test_regress/t/t_class_super_bad.v index 20a229969..8a9e7c675 100644 --- a/test_regress/t/t_class_super_bad.v +++ b/test_regress/t/t_class_super_bad.v @@ -5,11 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 // -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t(/*AUTOARG*/); + bit [3:0] addr; initial begin super.addr = 2; diff --git a/test_regress/t/t_class_super_bad2.pl b/test_regress/t/t_class_super_bad2.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_super_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_super_bad2.py b/test_regress/t/t_class_super_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_super_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_super_new.pl b/test_regress/t/t_class_super_new.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_super_new.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_super_new.py b/test_regress/t/t_class_super_new.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_super_new.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_super_new2.pl b/test_regress/t/t_class_super_new2.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_class_super_new2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_super_new2.py b/test_regress/t/t_class_super_new2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_super_new2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_super_new_bad_nfirst.pl b/test_regress/t/t_class_super_new_bad_nfirst.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_class_super_new_bad_nfirst.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_super_new_bad_nfirst.py b/test_regress/t/t_class_super_new_bad_nfirst.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_super_new_bad_nfirst.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_this_constructor.pl b/test_regress/t/t_class_this_constructor.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_this_constructor.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_this_constructor.py b/test_regress/t/t_class_this_constructor.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_this_constructor.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_typedef.pl b/test_regress/t/t_class_typedef.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_typedef.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_typedef.py b/test_regress/t/t_class_typedef.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_typedef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_unsup_bad.out b/test_regress/t/t_class_unsup_bad.out index a3f592e5c..6f5f72792 100644 --- a/test_regress/t/t_class_unsup_bad.out +++ b/test_regress/t/t_class_unsup_bad.out @@ -1,4 +1,10 @@ -%Error: t/t_class_unsup_bad.v:28:24: Syntax error: 'const'/'rand'/'randc' not allowed before function/task declaration - 28 | const function void func_const; endfunction +%Error: t/t_class_unsup_bad.v:24:21: Syntax error: 'static'/'virtual'/'rand'/'randc' not allowed before typedef declaration + 24 | rand typedef int irand_t; + | ^~~~~~~ +%Error: t/t_class_unsup_bad.v:25:22: Syntax error: 'static'/'virtual'/'rand'/'randc' not allowed before typedef declaration + 25 | randc typedef int icrand_t; + | ^~~~~~~~ +%Error: t/t_class_unsup_bad.v:31:24: Syntax error: 'const'/'rand'/'randc' not allowed before function/task declaration + 31 | const function void func_const; endfunction | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_unsup_bad.pl b/test_regress/t/t_class_unsup_bad.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_class_unsup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_unsup_bad.py b/test_regress/t/t_class_unsup_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_unsup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_unsup_bad.v b/test_regress/t/t_class_unsup_bad.v index dd5fd639b..ade12a18e 100644 --- a/test_regress/t/t_class_unsup_bad.v +++ b/test_regress/t/t_class_unsup_bad.v @@ -21,6 +21,9 @@ class C #(parameter P=1); rand int irand; randc int icrand; + rand typedef int irand_t; + randc typedef int icrand_t; + task classtask; endtask function int classfunc; endfunction virtual function void func_virtual; endfunction diff --git a/test_regress/t/t_class_uses_this.pl b/test_regress/t/t_class_uses_this.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_uses_this.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_uses_this.py b/test_regress/t/t_class_uses_this.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_uses_this.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_uses_this.v b/test_regress/t/t_class_uses_this.v index 862296e6a..ac8ac11f1 100644 --- a/test_regress/t/t_class_uses_this.v +++ b/test_regress/t/t_class_uses_this.v @@ -41,11 +41,8 @@ class wrapped_int; endfunction endclass -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t(/*AUTOARG*/); + Cls bar; Cls baz; wrapped_int i1, i2; diff --git a/test_regress/t/t_class_uses_this_bad.out b/test_regress/t/t_class_uses_this_bad.out index d0a3d6aa8..c9ee4ca37 100644 --- a/test_regress/t/t_class_uses_this_bad.out +++ b/test_regress/t/t_class_uses_this_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_class_uses_this_bad.v:15:12: 'this' used outside class (IEEE 1800-2023 8.11) - 15 | this.addr = 2; +%Error: t/t_class_uses_this_bad.v:11:12: 'this' used outside class (IEEE 1800-2023 8.11) + 11 | this.addr = 2; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_uses_this_bad.pl b/test_regress/t/t_class_uses_this_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_uses_this_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_uses_this_bad.py b/test_regress/t/t_class_uses_this_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_uses_this_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_uses_this_bad.v b/test_regress/t/t_class_uses_this_bad.v index 1db9fade6..4abd84682 100644 --- a/test_regress/t/t_class_uses_this_bad.v +++ b/test_regress/t/t_class_uses_this_bad.v @@ -5,11 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 // -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t(/*AUTOARG*/); bit [3:0] addr; initial begin this.addr = 2; diff --git a/test_regress/t/t_class_virtual.pl b/test_regress/t/t_class_virtual.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_virtual.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual.py b/test_regress/t/t_class_virtual.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_virtual.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_virtual_bad.pl b/test_regress/t/t_class_virtual_bad.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_class_virtual_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual_bad.py b/test_regress/t/t_class_virtual_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_virtual_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_virtual_chain_ctor.pl b/test_regress/t/t_class_virtual_chain_ctor.pl deleted file mode 100755 index 5b8136393..000000000 --- a/test_regress/t/t_class_virtual_chain_ctor.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual_chain_ctor.py b/test_regress/t/t_class_virtual_chain_ctor.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_class_virtual_chain_ctor.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_class_virtual_protect_ids.pl b/test_regress/t/t_class_virtual_protect_ids.pl deleted file mode 100755 index 940170b06..000000000 --- a/test_regress/t/t_class_virtual_protect_ids.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d")) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -top_filename("t/t_class_virtual.v"); - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual_protect_ids.py b/test_regress/t/t_class_virtual_protect_ids.py new file mode 100755 index 000000000..b42e1e842 --- /dev/null +++ b/test_regress/t/t_class_virtual_protect_ids.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_class_virtual.v" + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_virtual_pure.pl b/test_regress/t/t_class_virtual_pure.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_class_virtual_pure.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual_pure.py b/test_regress/t/t_class_virtual_pure.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_virtual_pure.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_virtual_pure_bad.pl b/test_regress/t/t_class_virtual_pure_bad.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_class_virtual_pure_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual_pure_bad.py b/test_regress/t/t_class_virtual_pure_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_virtual_pure_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_vparam.pl b/test_regress/t/t_class_vparam.pl deleted file mode 100755 index c81275cdf..000000000 --- a/test_regress/t/t_class_vparam.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_vparam.py b/test_regress/t/t_class_vparam.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_vparam.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_vparam.v b/test_regress/t/t_class_vparam.v index 6d927d6ac..38d88c7a7 100644 --- a/test_regress/t/t_class_vparam.v +++ b/test_regress/t/t_class_vparam.v @@ -22,11 +22,7 @@ class arg_class_t; int ifield; endclass -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); vclass vir; paramed_class_t#(arg_class_t) argu; diff --git a/test_regress/t/t_class_wide.pl b/test_regress/t/t_class_wide.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_class_wide.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_wide.py b/test_regress/t/t_class_wide.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_wide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_2in.pl b/test_regress/t/t_clk_2in.pl deleted file mode 100755 index 9f3664937..000000000 --- a/test_regress/t/t_clk_2in.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - vcs_flags2 => ['-assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_2in.py b/test_regress/t/t_clk_2in.py new file mode 100755 index 000000000..69b0d367c --- /dev/null +++ b/test_regress/t/t_clk_2in.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename], + vcs_flags2=['-assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_2in_vec.pl b/test_regress/t/t_clk_2in_vec.pl deleted file mode 100755 index 5950dcac8..000000000 --- a/test_regress/t/t_clk_2in_vec.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_2in.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["+define+T_CLK_2IN_VEC=1"], - verilator_flags2 => ["--exe $Self->{t_dir}/t_clk_2in.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_2in_vec.py b/test_regress/t/t_clk_2in_vec.py new file mode 100755 index 000000000..5939f11bf --- /dev/null +++ b/test_regress/t/t_clk_2in_vec.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_clk_2in.cpp" +test.top_filename = "t/t_clk_2in.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["+define+T_CLK_2IN_VEC=1"], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat.pl b/test_regress/t/t_clk_concat.pl deleted file mode 100755 index 9547871f6..000000000 --- a/test_regress/t/t_clk_concat.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["+define+ATTRIBUTES --no-json-edit-nums"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"clk0",.*"loc":"e,74:[^"]*",.*"origName":"clk0",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"clk1",.*"loc":"e,75:[^"]*",.*"origName":"clk1",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"clk2",.*"loc":"e,76:[^"]*",.*"origName":"clk2",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat.py b/test_regress/t/t_clk_concat.py new file mode 100755 index 000000000..66ab4b571 --- /dev/null +++ b/test_regress/t/t_clk_concat.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=["+define+ATTRIBUTES --no-json-edit-nums"]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk0",.*"loc":"e,74:[^"]*",.*"origName":"clk0",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk1",.*"loc":"e,75:[^"]*",.*"origName":"clk1",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk2",.*"loc":"e,76:[^"]*",.*"origName":"clk2",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat2.pl b/test_regress/t/t_clk_concat2.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_clk_concat2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat2.py b/test_regress/t/t_clk_concat2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_concat2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat3.pl b/test_regress/t/t_clk_concat3.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_clk_concat3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat3.py b/test_regress/t/t_clk_concat3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_concat3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat4.pl b/test_regress/t/t_clk_concat4.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_clk_concat4.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat4.py b/test_regress/t/t_clk_concat4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_concat4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat5.pl b/test_regress/t/t_clk_concat5.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_clk_concat5.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat5.py b/test_regress/t/t_clk_concat5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_concat5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat6.pl b/test_regress/t/t_clk_concat6.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_clk_concat6.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat6.py b/test_regress/t/t_clk_concat6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_concat6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat_vlt.pl b/test_regress/t/t_clk_concat_vlt.pl deleted file mode 100755 index 15b22b63c..000000000 --- a/test_regress/t/t_clk_concat_vlt.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_concat.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["--no-json-edit-nums", "t/t_clk_concat.vlt"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"clk0",.*"loc":"f,78:[^"]*",.*"origName":"clk0",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"clk1",.*"loc":"f,79:[^"]*",.*"origName":"clk1",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"clk2",.*"loc":"f,80:[^"]*",.*"origName":"clk2",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"data_in",.*"loc":"f,82:[^"]*",.*"origName":"data_in",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"non_clker",.*"varType":"PORT",.*"dtypeName":"logic"/); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat_vlt.py b/test_regress/t/t_clk_concat_vlt.py new file mode 100755 index 000000000..b634813cc --- /dev/null +++ b/test_regress/t/t_clk_concat_vlt.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clk_concat.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=["--no-json-edit-nums", "t/t_clk_concat.vlt"]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk0",.*"loc":"f,78:[^"]*",.*"origName":"clk0",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk1",.*"loc":"f,79:[^"]*",.*"origName":"clk1",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk2",.*"loc":"f,80:[^"]*",.*"origName":"clk2",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"data_in",.*"loc":"f,82:[^"]*",.*"origName":"data_in",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"non_clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_condflop.pl b/test_regress/t/t_clk_condflop.pl deleted file mode 100755 index ce1f8586f..000000000 --- a/test_regress/t/t_clk_condflop.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_condflop.py b/test_regress/t/t_clk_condflop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_condflop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_dpulse.pl b/test_regress/t/t_clk_dpulse.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_clk_dpulse.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_dpulse.py b/test_regress/t/t_clk_dpulse.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_dpulse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_dsp.pl b/test_regress/t/t_clk_dsp.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_clk_dsp.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_dsp.py b/test_regress/t/t_clk_dsp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_dsp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_first.pl b/test_regress/t/t_clk_first.pl deleted file mode 100755 index 3a3c0f2d0..000000000 --- a/test_regress/t/t_clk_first.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["+define+ATTRIBUTES=1"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_first.py b/test_regress/t/t_clk_first.py new file mode 100755 index 000000000..88dfd68d3 --- /dev/null +++ b/test_regress/t/t_clk_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["+define+ATTRIBUTES=1"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_first_bad.pl b/test_regress/t/t_clk_first_bad.pl deleted file mode 100755 index 7061aebc4..000000000 --- a/test_regress/t/t_clk_first_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_clk_first_deprecated.v"); - -lint( - verilator_flags2 => ["--lint-only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_first_bad.py b/test_regress/t/t_clk_first_bad.py new file mode 100755 index 000000000..d6fa215bd --- /dev/null +++ b/test_regress/t/t_clk_first_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_clk_first_deprecated.v" + +test.lint(verilator_flags2=["--lint-only"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clk_first_deprecated.pl b/test_regress/t/t_clk_first_deprecated.pl deleted file mode 100755 index 600551635..000000000 --- a/test_regress/t/t_clk_first_deprecated.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only", "-Wno-DEPRECATED"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_first_deprecated.py b/test_regress/t/t_clk_first_deprecated.py new file mode 100755 index 000000000..c6aee9ea5 --- /dev/null +++ b/test_regress/t/t_clk_first_deprecated.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only", "-Wno-DEPRECATED"]) + +test.passes() diff --git a/test_regress/t/t_clk_gate_ext.pl b/test_regress/t/t_clk_gate_ext.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_clk_gate_ext.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_gate_ext.py b/test_regress/t/t_clk_gate_ext.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_gate_ext.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_gater.pl b/test_regress/t/t_clk_gater.pl deleted file mode 100755 index 80eb32da7..000000000 --- a/test_regress/t/t_clk_gater.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats", - $Self->wno_unopthreads_for_few_cores()] - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - #Optimization is disabled - #file_grep ($Self->{stats}, qr/Optimizations, Gaters inserted\s+(\d+)/i, 3); -} - -ok(1); -1; diff --git a/test_regress/t/t_clk_gater.py b/test_regress/t/t_clk_gater.py new file mode 100755 index 000000000..507391524 --- /dev/null +++ b/test_regress/t/t_clk_gater.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats", test.wno_unopthreads_for_few_cores]) + +test.execute() + +#Optimization is disabled +#test.file_grep(test.stats, r'Optimizations, Gaters inserted\s+(\d+)'i, 3) + +test.passes() diff --git a/test_regress/t/t_clk_gen.pl b/test_regress/t/t_clk_gen.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_clk_gen.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_gen.py b/test_regress/t/t_clk_gen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_gen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_inp_init.pl b/test_regress/t/t_clk_inp_init.pl deleted file mode 100755 index 7a546294f..000000000 --- a/test_regress/t/t_clk_inp_init.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2018 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the -# GNU Lesser General Public License Version 3 or the Perl Artistic -# License Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"]); - -execute(check_finished => 1); - -ok(1); -1; diff --git a/test_regress/t/t_clk_inp_init.py b/test_regress/t/t_clk_inp_init.py new file mode 100755 index 000000000..f840b04dc --- /dev/null +++ b/test_regress/t/t_clk_inp_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the +# GNU Lesser General Public License Version 3 or the Perl Artistic +# License Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_latch.pl b/test_regress/t/t_clk_latch.pl deleted file mode 100755 index ce1f8586f..000000000 --- a/test_regress/t/t_clk_latch.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_latch.py b/test_regress/t/t_clk_latch.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_latch.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_latch_edgestyle.pl b/test_regress/t/t_clk_latch_edgestyle.pl deleted file mode 100755 index 52730f4f4..000000000 --- a/test_regress/t/t_clk_latch_edgestyle.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_latch.v"); - - -compile( - v_flags2 => ['+define+EDGE_DETECT_STYLE'], - ); - -execute( - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_latch_edgestyle.py b/test_regress/t/t_clk_latch_edgestyle.py new file mode 100755 index 000000000..395d09419 --- /dev/null +++ b/test_regress/t/t_clk_latch_edgestyle.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clk_latch.v" + +test.compile(v_flags2=['+define+EDGE_DETECT_STYLE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_latchgate.pl b/test_regress/t/t_clk_latchgate.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_clk_latchgate.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_latchgate.py b/test_regress/t/t_clk_latchgate.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_latchgate.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_powerdn.pl b/test_regress/t/t_clk_powerdn.pl deleted file mode 100755 index ce1f8586f..000000000 --- a/test_regress/t/t_clk_powerdn.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_powerdn.py b/test_regress/t/t_clk_powerdn.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_powerdn.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_scope_bad.pl b/test_regress/t/t_clk_scope_bad.pl deleted file mode 100755 index cc34dc85f..000000000 --- a/test_regress/t/t_clk_scope_bad.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_clk_scope_bad.py b/test_regress/t/t_clk_scope_bad.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_clk_scope_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_clk_vecgen1.pl b/test_regress/t/t_clk_vecgen1.pl deleted file mode 100755 index 35ae37fc6..000000000 --- a/test_regress/t/t_clk_vecgen1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_vecgen1.v"); - -compile( - v_flags2 => ['+define+T_TEST1',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_vecgen1.py b/test_regress/t/t_clk_vecgen1.py new file mode 100755 index 000000000..12a6cc2e5 --- /dev/null +++ b/test_regress/t/t_clk_vecgen1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clk_vecgen1.v" + +test.compile(v_flags2=['+define+T_TEST1']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_vecgen2.pl b/test_regress/t/t_clk_vecgen2.pl deleted file mode 100755 index a6c215d47..000000000 --- a/test_regress/t/t_clk_vecgen2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_vecgen1.v"); - -compile( - v_flags2 => ['+define+T_TEST2',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_vecgen2.py b/test_regress/t/t_clk_vecgen2.py new file mode 100755 index 000000000..6c46e2c7c --- /dev/null +++ b/test_regress/t/t_clk_vecgen2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clk_vecgen1.v" + +test.compile(v_flags2=['+define+T_TEST2']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_vecgen3.pl b/test_regress/t/t_clk_vecgen3.pl deleted file mode 100755 index 2ffc58208..000000000 --- a/test_regress/t/t_clk_vecgen3.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_vecgen1.v"); - -compile( - v_flags2 => ['+define+T_TEST3',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_vecgen3.py b/test_regress/t/t_clk_vecgen3.py new file mode 100755 index 000000000..7e8939ce1 --- /dev/null +++ b/test_regress/t/t_clk_vecgen3.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clk_vecgen1.v" + +test.compile(v_flags2=['+define+T_TEST3']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocked_release_combo.pl b/test_regress/t/t_clocked_release_combo.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_clocked_release_combo.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocked_release_combo.py b/test_regress/t/t_clocked_release_combo.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clocked_release_combo.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocker.pl b/test_regress/t/t_clocker.pl deleted file mode 100755 index 1af79252d..000000000 --- a/test_regress/t/t_clocker.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--trace"] - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_clocker.py b/test_regress/t/t_clocker.py new file mode 100755 index 000000000..b03987abd --- /dev/null +++ b/test_regress/t/t_clocker.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--trace"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_bad1.pl b/test_regress/t/t_clocking_bad1.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_bad1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_bad1.py b/test_regress/t/t_clocking_bad1.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_bad1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_bad2.pl b/test_regress/t/t_clocking_bad2.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_bad2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_bad2.py b/test_regress/t/t_clocking_bad2.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_bad3.pl b/test_regress/t/t_clocking_bad3.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_bad3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_bad3.py b/test_regress/t/t_clocking_bad3.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_bad3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_bad4.pl b/test_regress/t/t_clocking_bad4.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_bad4.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_bad4.py b/test_regress/t/t_clocking_bad4.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_bad4.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_bad5.pl b/test_regress/t/t_clocking_bad5.pl deleted file mode 100755 index 7fdfc93e0..000000000 --- a/test_regress/t/t_clocking_bad5.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_bad5.py b/test_regress/t/t_clocking_bad5.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_bad5.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_concat.pl b/test_regress/t/t_clocking_concat.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_clocking_concat.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_concat.py b/test_regress/t/t_clocking_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clocking_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_empty_block.pl b/test_regress/t/t_clocking_empty_block.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_clocking_empty_block.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_empty_block.py b/test_regress/t/t_clocking_empty_block.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_clocking_empty_block.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_inout.pl b/test_regress/t/t_clocking_inout.pl deleted file mode 100755 index b8493bd06..000000000 --- a/test_regress/t/t_clocking_inout.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - make_main => 0, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_inout.py b/test_regress/t/t_clocking_inout.py new file mode 100755 index 000000000..d05629d98 --- /dev/null +++ b/test_regress/t/t_clocking_inout.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"], make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_notiming.pl b/test_regress/t/t_clocking_notiming.pl deleted file mode 100755 index bf475c910..000000000 --- a/test_regress/t/t_clocking_notiming.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--no-timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_notiming.py b/test_regress/t/t_clocking_notiming.py new file mode 100755 index 000000000..6f71603b5 --- /dev/null +++ b/test_regress/t/t_clocking_notiming.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_out_on_change.pl b/test_regress/t/t_clocking_out_on_change.pl deleted file mode 100755 index bc08e4a19..000000000 --- a/test_regress/t/t_clocking_out_on_change.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_out_on_change.py b/test_regress/t/t_clocking_out_on_change.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_clocking_out_on_change.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_react.py b/test_regress/t/t_clocking_react.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_clocking_react.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_react.v b/test_regress/t/t_clocking_react.v new file mode 100644 index 000000000..2f8a111d9 --- /dev/null +++ b/test_regress/t/t_clocking_react.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +interface axi_if; + logic clk; + wire rlast; + wire rvalid; + clocking cb @(posedge clk); + inout rlast, rvalid; + endclocking +endinterface + +module t; + axi_if axi_vi(); + initial begin + axi_vi.clk = 1'b0; + #1 axi_vi.clk = 1'b1; // triggers line 26 + #1 axi_vi.clk = 1'b0; // triggers line 29 (shouldn't happen) + #1 axi_vi.clk = 1'b1; // triggers line 18 (shouldn't happen) + end + initial begin + @(negedge axi_vi.rvalid); + $display("[%0t] rvalid==%b", $time, axi_vi.rvalid); + $display("[%0t] rlast is 1: ", $time, axi_vi.rlast === 1); + if (axi_vi.rlast === 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + initial begin + $display("[%0t] rvalid <= 1", $time); + axi_vi.cb.rvalid <= 1'b1; // assigned on first clk posedge (line 13) + @(posedge axi_vi.rvalid); + $display("[%0t] rvalid <= 0", $time); + axi_vi.cb.rvalid <= 1'b0; // assigned on second clk posedge (line 15), but should be on first + @(negedge axi_vi.clk); + $display("[%0t] rlast <= 1", $time); + axi_vi.cb.rlast <= 1'b1; // assigned on second clk posedge (line 15), shouldn't happen + end +endmodule diff --git a/test_regress/t/t_clocking_sched.pl b/test_regress/t/t_clocking_sched.pl deleted file mode 100755 index f071267de..000000000 --- a/test_regress/t/t_clocking_sched.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_sched.py b/test_regress/t/t_clocking_sched.py new file mode 100755 index 000000000..97abb660e --- /dev/null +++ b/test_regress/t/t_clocking_sched.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_sched_timing.pl b/test_regress/t/t_clocking_sched_timing.pl deleted file mode 100755 index 1d537460a..000000000 --- a/test_regress/t/t_clocking_sched_timing.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_clocking_sched.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_sched_timing.py b/test_regress/t/t_clocking_sched_timing.py new file mode 100755 index 000000000..5737cc7a9 --- /dev/null +++ b/test_regress/t/t_clocking_sched_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_clocking_sched.v" + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_sched_timing_forkproc.pl b/test_regress/t/t_clocking_sched_timing_forkproc.pl deleted file mode 100755 index 7c1c36bef..000000000 --- a/test_regress/t/t_clocking_sched_timing_forkproc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -scenarios(vlt => 1); - -top_filename("t/t_clocking_sched.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_sched_timing_forkproc.py b/test_regress/t/t_clocking_sched_timing_forkproc.py new file mode 100755 index 000000000..25f9bb0ff --- /dev/null +++ b/test_regress/t/t_clocking_sched_timing_forkproc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_clocking_sched.v" + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_timing1.pl b/test_regress/t/t_clocking_timing1.pl deleted file mode 100755 index fbcaf794f..000000000 --- a/test_regress/t/t_clocking_timing1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clocking_timing.v"); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_timing1.py b/test_regress/t/t_clocking_timing1.py new file mode 100755 index 000000000..01e5d2048 --- /dev/null +++ b/test_regress/t/t_clocking_timing1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clocking_timing.v" + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_timing2.pl b/test_regress/t/t_clocking_timing2.pl deleted file mode 100755 index d5e2d9864..000000000 --- a/test_regress/t/t_clocking_timing2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clocking_timing.v"); - -compile( - verilator_flags2 => ["--exe --main --timing -DTEST_INPUT_SKEW=12 -DTEST_OUTPUT_SKEW=16"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_timing2.py b/test_regress/t/t_clocking_timing2.py new file mode 100755 index 000000000..702df2678 --- /dev/null +++ b/test_regress/t/t_clocking_timing2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clocking_timing.v" + +test.compile(verilator_flags2=["--exe --main --timing -DTEST_INPUT_SKEW=12 -DTEST_OUTPUT_SKEW=16"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_unsup1.pl b/test_regress/t/t_clocking_unsup1.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_unsup1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_unsup1.py b/test_regress/t/t_clocking_unsup1.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_unsup1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_unsup2.pl b/test_regress/t/t_clocking_unsup2.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_unsup2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_unsup2.py b/test_regress/t/t_clocking_unsup2.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_unsup2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_virtual.pl b/test_regress/t/t_clocking_virtual.pl deleted file mode 100755 index 9d615c1c3..000000000 --- a/test_regress/t/t_clocking_virtual.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_virtual.py b/test_regress/t/t_clocking_virtual.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_clocking_virtual.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_xref.pl b/test_regress/t/t_clocking_xref.pl deleted file mode 100755 index 9d615c1c3..000000000 --- a/test_regress/t/t_clocking_xref.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_xref.py b/test_regress/t/t_clocking_xref.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_clocking_xref.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_comb_input_0.pl b/test_regress/t/t_comb_input_0.pl deleted file mode 100755 index 0bb6b8592..000000000 --- a/test_regress/t/t_comb_input_0.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - #make_top_shell => 0, - make_main => 0, - v_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_comb_input_0.py b/test_regress/t/t_comb_input_0.py new file mode 100755 index 000000000..74e183dab --- /dev/null +++ b/test_regress/t/t_comb_input_0.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile( + #make_top_shell = False, + make_main=False, + v_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_comb_input_1.pl b/test_regress/t/t_comb_input_1.pl deleted file mode 100755 index 0bb6b8592..000000000 --- a/test_regress/t/t_comb_input_1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - #make_top_shell => 0, - make_main => 0, - v_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_comb_input_1.py b/test_regress/t/t_comb_input_1.py new file mode 100755 index 000000000..74e183dab --- /dev/null +++ b/test_regress/t/t_comb_input_1.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile( + #make_top_shell = False, + make_main=False, + v_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_comb_input_2.pl b/test_regress/t/t_comb_input_2.pl deleted file mode 100755 index 0bb6b8592..000000000 --- a/test_regress/t/t_comb_input_2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - #make_top_shell => 0, - make_main => 0, - v_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_comb_input_2.py b/test_regress/t/t_comb_input_2.py new file mode 100755 index 000000000..74e183dab --- /dev/null +++ b/test_regress/t/t_comb_input_2.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile( + #make_top_shell = False, + make_main=False, + v_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_comb_loop_through_unpacked_array.pl b/test_regress/t/t_comb_loop_through_unpacked_array.pl deleted file mode 100755 index c7f63144c..000000000 --- a/test_regress/t/t_comb_loop_through_unpacked_array.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_comb_loop_through_unpacked_array.py b/test_regress/t/t_comb_loop_through_unpacked_array.py new file mode 100755 index 000000000..41b8d5138 --- /dev/null +++ b/test_regress/t/t_comb_loop_through_unpacked_array.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.passes() diff --git a/test_regress/t/t_compiler_include.pl b/test_regress/t/t_compiler_include.pl deleted file mode 100755 index e03b9971f..000000000 --- a/test_regress/t/t_compiler_include.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp", "--compiler-include $Self->{t_dir}/t_compiler_include.h", "--output-split 0"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_compiler_include.py b/test_regress/t/t_compiler_include.py new file mode 100755 index 000000000..f2d4a6302 --- /dev/null +++ b/test_regress/t/t_compiler_include.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + "--exe", test.pli_filename, "--compiler-include", + test.t_dir + "/t_compiler_include.h", "--output-split 0" + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_compiler_include_dpi.pl b/test_regress/t/t_compiler_include_dpi.pl deleted file mode 100755 index 048b6fdea..000000000 --- a/test_regress/t/t_compiler_include_dpi.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_compiler_include_dpi.v"); - -compile( - v_flags2 => ["t/t_compiler_include_dpi.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --compiler-include $Self->{t_dir}/t_compiler_include_dpi.h --output-split 0"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_compiler_include_dpi.py b/test_regress/t/t_compiler_include_dpi.py new file mode 100755 index 000000000..b1b215937 --- /dev/null +++ b/test_regress/t/t_compiler_include_dpi.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_compiler_include_dpi.v" + +test.compile(v_flags2=["t/t_compiler_include_dpi.cpp"], + verilator_flags2=[ + "-Wall -Wno-DECLFILENAME --compiler-include", + test.t_dir + "/t_compiler_include_dpi.h --output-split 0" + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_compiler_include_dpi_split.pl b/test_regress/t/t_compiler_include_dpi_split.pl deleted file mode 100755 index 35ac0a040..000000000 --- a/test_regress/t/t_compiler_include_dpi_split.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_compiler_include_dpi.v"); - -compile( - v_flags2 => ["t/t_compiler_include_dpi.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --compiler-include $Self->{t_dir}/t_compiler_include_dpi.h --output-split 1"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_compiler_include_dpi_split.py b/test_regress/t/t_compiler_include_dpi_split.py new file mode 100755 index 000000000..97b694be1 --- /dev/null +++ b/test_regress/t/t_compiler_include_dpi_split.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_compiler_include_dpi.v" + +test.compile(v_flags2=["t/t_compiler_include_dpi.cpp"], + verilator_flags2=[ + "-Wall -Wno-DECLFILENAME --compiler-include", + test.t_dir + "/t_compiler_include_dpi.h --output-split 1" + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_compiler_include_split.pl b/test_regress/t/t_compiler_include_split.pl deleted file mode 100755 index cd4f8377b..000000000 --- a/test_regress/t/t_compiler_include_split.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_compiler_include.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/t_compiler_include.cpp", "--compiler-include $Self->{t_dir}/t_compiler_include.h", "--output-split 1"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_compiler_include_split.py b/test_regress/t/t_compiler_include_split.py new file mode 100755 index 000000000..daae2e49f --- /dev/null +++ b/test_regress/t/t_compiler_include_split.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_compiler_include.cpp" +test.top_filename = "t/t_compiler_include.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + "--exe", test.pli_filename, "--compiler-include", + test.t_dir + "/t_compiler_include.h", "--output-split 1" + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_large.pl b/test_regress/t/t_concat_large.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_concat_large.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_large.py b/test_regress/t/t_concat_large.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_concat_large.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_large_bad.pl b/test_regress/t/t_concat_large_bad.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_concat_large_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_large_bad.py b/test_regress/t/t_concat_large_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_concat_large_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_concat_link_bad.out b/test_regress/t/t_concat_link_bad.out index ad22af64a..25e935028 100644 --- a/test_regress/t/t_concat_link_bad.out +++ b/test_regress/t/t_concat_link_bad.out @@ -1,12 +1,21 @@ %Error: t/t_concat_link_bad.v:13:20: Syntax error: Not expecting REPLICATE under a DOT in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ + t/t_concat_link_bad.v:13:34: ... Resolving this reference + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ %Error: t/t_concat_link_bad.v:13:26: Syntax error: Not expecting CONCAT under a REPLICATE in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ + t/t_concat_link_bad.v:13:34: ... Resolving this reference + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ %Error: t/t_concat_link_bad.v:13:20: Syntax error: Not expecting CONST under a REPLICATE in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ + t/t_concat_link_bad.v:13:34: ... Resolving this reference + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ %Warning-IMPLICIT: t/t_concat_link_bad.v:13:12: Signal definition not found, creating implicitly: 'bar_s' 13 | assign bar_s = {foo_s, foo_s}.f1; | ^~~~~ diff --git a/test_regress/t/t_concat_link_bad.pl b/test_regress/t/t_concat_link_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_concat_link_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_link_bad.py b/test_regress/t/t_concat_link_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_concat_link_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_concat_opt.pl b/test_regress/t/t_concat_opt.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_concat_opt.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_opt.py b/test_regress/t/t_concat_opt.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_concat_opt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_or.pl b/test_regress/t/t_concat_or.pl deleted file mode 100755 index 4409f8046..000000000 --- a/test_regress/t/t_concat_or.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_or.py b/test_regress/t/t_concat_or.py new file mode 100755 index 000000000..f92eef979 --- /dev/null +++ b/test_regress/t/t_concat_or.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only"]) + +test.passes() diff --git a/test_regress/t/t_concat_sel.pl b/test_regress/t/t_concat_sel.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_concat_sel.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_sel.py b/test_regress/t/t_concat_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_concat_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_string.pl b/test_regress/t/t_concat_string.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_concat_string.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_string.py b/test_regress/t/t_concat_string.py new file mode 100755 index 000000000..2b17673d7 --- /dev/null +++ b/test_regress/t/t_concat_string.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import signal +import vltest_bootstrap + +test.scenarios('simulator') + +signal.alarm(5) # 5s timeout + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_string.v b/test_regress/t/t_concat_string.v index 680dc8caa..b0538c185 100644 --- a/test_regress/t/t_concat_string.v +++ b/test_regress/t/t_concat_string.v @@ -18,6 +18,13 @@ module t (/*AUTOARG*/); s = {"abcd", e.name(), "ijkl"}; if (s != "abcdefghijkl") $stop; + // hang V3Width if complexity grows exponential (2**52 should suffice) + s = {"a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", + "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z", + "a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", + "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z"}; + if (s != "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz") $stop; + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_concat_unpack.pl b/test_regress/t/t_concat_unpack.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_concat_unpack.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_unpack.py b/test_regress/t/t_concat_unpack.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_concat_unpack.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const.pl b/test_regress/t/t_const.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_const.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const.py b/test_regress/t/t_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_bad.pl b/test_regress/t/t_const_bad.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_const_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_bad.py b/test_regress/t/t_const_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_const_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_const_bitoptree_bug3096.pl b/test_regress/t/t_const_bitoptree_bug3096.pl deleted file mode 100755 index 6a43c15a1..000000000 --- a/test_regress/t/t_const_bitoptree_bug3096.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2015 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_bitoptree_bug3096.py b/test_regress/t/t_const_bitoptree_bug3096.py new file mode 100755 index 000000000..1b17842fa --- /dev/null +++ b/test_regress/t/t_const_bitoptree_bug3096.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--exe", test.pli_filename]) + +test.execute(check_finished=False) + +test.passes() diff --git a/test_regress/t/t_const_dec_mixed_bad.pl b/test_regress/t/t_const_dec_mixed_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_const_dec_mixed_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_dec_mixed_bad.py b/test_regress/t/t_const_dec_mixed_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_const_dec_mixed_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_const_hi.pl b/test_regress/t/t_const_hi.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_const_hi.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_hi.py b/test_regress/t/t_const_hi.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_const_hi.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_no_opt.pl b/test_regress/t/t_const_no_opt.pl deleted file mode 100755 index db1a41047..000000000 --- a/test_regress/t/t_const_no_opt.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_const_opt.v"); - -# Run the same design as t_const_opt.pl without bitopt tree optimization to make sure that the result is same. -compile( - verilator_flags2 => [ - "-Wno-UNOPTTHREADS", - "--stats", - "-fno-const-bit-op-tree", - "$Self->{t_dir}/t_const_opt.cpp", - "-CFLAGS", - "-Wno-tautological-compare" - ], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_no_opt.py b/test_regress/t/t_const_no_opt.py new file mode 100755 index 000000000..6633ac18d --- /dev/null +++ b/test_regress/t/t_const_no_opt.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_opt_const.v" + +# Run the same design as t_opt_const.py without bitopt tree optimization to make sure that the result is same. +test.compile(verilator_flags2=[ + "-Wno-UNOPTTHREADS", "--stats", "-fno-const-bit-op-tree", test.t_dir + + "/t_opt_const.cpp", "-CFLAGS", "-Wno-tautological-compare" +]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_number_bad.out b/test_regress/t/t_const_number_bad.out new file mode 100644 index 000000000..64979a485 --- /dev/null +++ b/test_regress/t/t_const_number_bad.out @@ -0,0 +1,25 @@ +%Error: t/t_const_number_bad.v:9:29: Number is missing value digits: 32'd + 9 | parameter integer FOO2 = 32'd-6; + | ^~~~ +%Error: t/t_const_number_bad.v:10:29: Number is missing value digits: 32'd + 10 | parameter integer FOO3 = 32'd; + | ^~~~ +%Error: t/t_const_number_bad.v:11:29: Number is missing value digits: 32'h + 11 | parameter integer FOO4 = 32'h; + | ^~~~ +%Error: t/t_const_number_bad.v:13:29: Illegal character in binary constant: 2 + 13 | parameter integer FOO5 = 32'b2; + | ^~~~~ +%Error: t/t_const_number_bad.v:14:29: Illegal character in octal constant + 14 | parameter integer FOO6 = 32'o8; + | ^~~~~ +%Error: t/t_const_number_bad.v:17:33: Illegal character in binary constant: 4 + 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; + | ^~~~~~ +%Error: t/t_const_number_bad.v:17:33: Too many digits for 1 bit number: '1'b1?4' + 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; + | ^~~~~~ +%Error: t/t_const_number_bad.v:17:39: syntax error, unexpected INTEGER NUMBER, expecting ';' + 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; + | ^~~ +%Error: Exiting due to diff --git a/test_regress/t/t_const_number_bad.py b/test_regress/t/t_const_number_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_const_number_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_number_bad.v b/test_regress/t/t_const_number_bad.v similarity index 100% rename from test_regress/t/t_number_bad.v rename to test_regress/t/t_const_number_bad.v diff --git a/test_regress/t/t_const_number_unsized.py b/test_regress/t/t_const_number_unsized.py new file mode 100755 index 000000000..dbdaf4551 --- /dev/null +++ b/test_regress/t/t_const_number_unsized.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_number_unsized.v b/test_regress/t/t_const_number_unsized.v new file mode 100644 index 000000000..2f9a54b63 --- /dev/null +++ b/test_regress/t/t_const_number_unsized.v @@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); + +module t; + int s; + logic [255:0] n; + + initial begin + s = $bits('d123); + `checkd(s, 32); + s = $bits('h123); + `checkd(s, 32); + s = $bits('o123); + `checkd(s, 32); + s = $bits('b101); + `checkd(s, 32); + + // verilator lint_off WIDTHEXPAND + + // Used to warn "Too many digits for 32 bit number" + // ... As that number was unsized ('...) it is limited to 32 bits + // But other simulators don't warn, and language of (IEEE 1800-2023 5.7.1) + // has been updated to accepting this legal + n = 'd123456789123456789123456789; + s = $bits('d123456789123456789123456789); + `checkh(n, 256'h661efdf2e3b19f7c045f15); + `checkd(s, 87); + + n = 'h123456789123456789123456789; + s = $bits('h123456789123456789123456789); + `checkh(n, 256'h123456789123456789123456789); + `checkd(s, 108); + + //FIX octal digits in master test, if don't merge this + n = 'o123456777123456777123456777; + s = $bits('o123456777123456777123456777); + `checkh(n, 256'h53977fca72eff94e5dff); + `checkd(s, 81); + + n = 'b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010; + s = $bits('b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010); + `checkh(n, 256'haaaaaaaaaaaaaaaaaaaaaaa); + `checkd(s, 92); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_const_number_v_bad.out b/test_regress/t/t_const_number_v_bad.out new file mode 100644 index 000000000..b222a145f --- /dev/null +++ b/test_regress/t/t_const_number_v_bad.out @@ -0,0 +1,21 @@ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:11:25: Unbased unsized literals require IEEE 1800-2005 or later. + 11 | wire [127:0] FOO1 = '0; + | ^~ + ... For warning description see https://verilator.org/warn/NEWERSTD?v=latest + ... Use "/* verilator lint_off NEWERSTD */" and lint_on around source to disable this message. +%Warning-NEWERSTD: t/t_const_number_v_bad.v:12:25: Unbased unsized literals require IEEE 1800-2005 or later. + 12 | wire [127:0] FOO2 = '1; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:13:25: Unbased unsized literals require IEEE 1800-2005 or later. + 13 | wire [127:0] FOO3 = 'x; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:14:25: Unbased unsized literals require IEEE 1800-2005 or later. + 14 | wire [127:0] FOO4 = 'X; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:15:25: Unbased unsized literals require IEEE 1800-2005 or later. + 15 | wire [127:0] FOO5 = 'z; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:16:25: Unbased unsized literals require IEEE 1800-2005 or later. + 16 | wire [127:0] FOO6 = 'Z; + | ^~ +%Error: Exiting due to diff --git a/test_regress/t/t_const_number_v_bad.py b/test_regress/t/t_const_number_v_bad.py new file mode 100755 index 000000000..93c8b0951 --- /dev/null +++ b/test_regress/t/t_const_number_v_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--language 1364-2005"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_number_v_bad.v b/test_regress/t/t_const_number_v_bad.v similarity index 100% rename from test_regress/t/t_number_v_bad.v rename to test_regress/t/t_const_number_v_bad.v diff --git a/test_regress/t/t_const_op_red_scope.pl b/test_regress/t/t_const_op_red_scope.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_const_op_red_scope.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_op_red_scope.py b/test_regress/t/t_const_op_red_scope.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_const_op_red_scope.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_opt.pl b/test_regress/t/t_const_opt.pl deleted file mode 100755 index f97a44629..000000000 --- a/test_regress/t/t_const_opt.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTTHREADS", "-fno-dfg", - "--stats", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 45); -} -ok(1); -1; diff --git a/test_regress/t/t_const_opt_cov.pl b/test_regress/t/t_const_opt_cov.pl deleted file mode 100755 index 211e1d79a..000000000 --- a/test_regress/t/t_const_opt_cov.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTTHREADS", "--stats", "--coverage", "--trace"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 144); -} - -ok(1); -1; diff --git a/test_regress/t/t_const_opt_dfg.pl b/test_regress/t/t_const_opt_dfg.pl deleted file mode 100755 index 3af0d6cd8..000000000 --- a/test_regress/t/t_const_opt_dfg.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_const_opt.v"); - -compile( - verilator_flags2 => ["-Wno-UNOPTTHREADS", - "--stats", "$Self->{t_dir}/t_const_opt.cpp"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 40); -} -ok(1); -1; diff --git a/test_regress/t/t_const_opt_no_expand.pl b/test_regress/t/t_const_opt_no_expand.pl deleted file mode 100755 index d4701df03..000000000 --- a/test_regress/t/t_const_opt_no_expand.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_const_opt.v"); - -compile( - verilator_flags2 => ["-Wno-UNOPTTHREADS", "-fno-dfg", "-fno-expand", - "--stats", "$Self->{t_dir}/t_const_opt.cpp"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 1); -} -ok(1); -1; diff --git a/test_regress/t/t_const_opt_or.pl b/test_regress/t/t_const_opt_or.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_const_opt_or.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_opt_red.pl b/test_regress/t/t_const_opt_red.pl deleted file mode 100755 index a9e16fbf5..000000000 --- a/test_regress/t/t_const_opt_red.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTTHREADS", "--stats"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 158); -} - -ok(1); -1; diff --git a/test_regress/t/t_const_opt_shortcut.pl b/test_regress/t/t_const_opt_shortcut.pl deleted file mode 100755 index beae879d6..000000000 --- a/test_regress/t/t_const_opt_shortcut.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - verilator_flags2 => ["-Wno-UNOPTTHREADS", "--stats"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_overflow_bad.out b/test_regress/t/t_const_overflow_bad.out index 641cd071d..092232847 100644 --- a/test_regress/t/t_const_overflow_bad.out +++ b/test_regress/t/t_const_overflow_bad.out @@ -1,16 +1,16 @@ -%Error: t/t_const_overflow_bad.v:9:34: Too many digits for 94 bit number: 94'd123456789012345678901234567890 +%Error: t/t_const_overflow_bad.v:9:34: Too many digits for 94 bit number: '94'd123456789012345678901234567890' 9 | parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -%Error: t/t_const_overflow_bad.v:11:31: Too many digits for 8 bit number: 8'habc +%Error: t/t_const_overflow_bad.v:11:31: Too many digits for 8 bit number: '8'habc' 11 | parameter [200:0] SMALLH = 8'habc; | ^~~~~~ -%Error: t/t_const_overflow_bad.v:12:31: Too many digits for 6 bit number: 6'o1234 +%Error: t/t_const_overflow_bad.v:12:31: Too many digits for 6 bit number: '6'o1234' 12 | parameter [200:0] SMALLO = 6'o1234; | ^~~~~~~ -%Error: t/t_const_overflow_bad.v:13:31: Too many digits for 3 bit number: 3'b1111 +%Error: t/t_const_overflow_bad.v:13:31: Too many digits for 3 bit number: '3'b1111' 13 | parameter [200:0] SMALLB = 3'b1111; | ^~~~~~~ -%Error: t/t_const_overflow_bad.v:19:35: Too many digits for 129 bit number: 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d +%Error: t/t_const_overflow_bad.v:19:35: Too many digits for 129 bit number: '129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d' 19 | parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_overflow_bad.pl b/test_regress/t/t_const_overflow_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_const_overflow_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_overflow_bad.py b/test_regress/t/t_const_overflow_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_const_overflow_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_const_sel_sel_extend.pl b/test_regress/t/t_const_sel_sel_extend.pl deleted file mode 100755 index 84ae125be..000000000 --- a/test_regress/t/t_const_sel_sel_extend.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_const_sel_sel_extend.py b/test_regress/t/t_const_sel_sel_extend.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_const_sel_sel_extend.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_const_slicesel.pl b/test_regress/t/t_const_slicesel.pl deleted file mode 100755 index becd8a5aa..000000000 --- a/test_regress/t/t_const_slicesel.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl - -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(linter => 1); - -lint( -); - -ok(1); -1; diff --git a/test_regress/t/t_const_slicesel.py b/test_regress/t/t_const_slicesel.py new file mode 100755 index 000000000..290deb6cd --- /dev/null +++ b/test_regress/t/t_const_slicesel.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 + +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_const_slicesel_bad.pl b/test_regress/t/t_const_slicesel_bad.pl deleted file mode 100755 index 5d84a06aa..000000000 --- a/test_regress/t/t_const_slicesel_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl - -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(linter => 1); - -lint( - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_slicesel_bad.py b/test_regress/t/t_const_slicesel_bad.py new file mode 100755 index 000000000..415956256 --- /dev/null +++ b/test_regress/t/t_const_slicesel_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 + +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True) + +test.passes() diff --git a/test_regress/t/t_const_string_func.pl b/test_regress/t/t_const_string_func.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_const_string_func.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_string_func.py b/test_regress/t/t_const_string_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_const_string_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint.pl b/test_regress/t/t_constraint.pl deleted file mode 100755 index e90393bab..000000000 --- a/test_regress/t/t_constraint.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - verilator_flags2 => ['-Wno-CONSTRAINTIGN'], - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint.py b/test_regress/t/t_constraint.py new file mode 100755 index 000000000..dbae8a1dc --- /dev/null +++ b/test_regress/t/t_constraint.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile(verilator_flags2=['-Wno-CONSTRAINTIGN']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_dist.py b/test_regress/t/t_constraint_dist.py new file mode 100755 index 000000000..dbae8a1dc --- /dev/null +++ b/test_regress/t/t_constraint_dist.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile(verilator_flags2=['-Wno-CONSTRAINTIGN']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_dist.v b/test_regress/t/t_constraint_dist.v new file mode 100644 index 000000000..343a7aad5 --- /dev/null +++ b/test_regress/t/t_constraint_dist.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +`define check_rand(cl, field, cond) \ +begin \ + longint prev_result; \ + int ok = 0; \ + if (!bit'(cl.randomize())) $stop; \ + prev_result = longint'(field); \ + if (!(cond)) $stop; \ + repeat(9) begin \ + longint result; \ + if (!bit'(cl.randomize())) $stop; \ + result = longint'(field); \ + if (!(cond)) $stop; \ + if (result != prev_result) ok = 1; \ + prev_result = result; \ + end \ + if (ok != 1) $stop; \ +end + +class C; + rand int x, y, z, w; + int que[$] = '{3, 4, 5}; + int arr[3] = '{5, 6, 7}; + constraint distrib { + x dist { [1:3] := 0, [5:6], [9:15] :/ 0 }; + y dist { [1:3] := 0, 5, 6 := 8, [9:15] :/ 0 }; + x < 20; + }; + constraint distinside { + z dist {que}; + w dist {arr}; + }; +endclass + +module t; + initial begin + C c = new; + `check_rand(c, c.x, 5 <= c.x && c.x <= 6); + `check_rand(c, c.y, 5 <= c.y && c.y <= 6); + `check_rand(c, c.z, 3 <= c.z && c.z <= 5); + `check_rand(c, c.w, 5 <= c.w && c.w <= 7); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_foreach.pl b/test_regress/t/t_constraint_foreach.pl deleted file mode 100755 index 7b520d284..000000000 --- a/test_regress/t/t_constraint_foreach.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_foreach.py b/test_regress/t/t_constraint_foreach.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_foreach.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_foreach.v b/test_regress/t/t_constraint_foreach.v index 6bd36c704..a2c7f9f93 100644 --- a/test_regress/t/t_constraint_foreach.v +++ b/test_regress/t/t_constraint_foreach.v @@ -8,12 +8,15 @@ begin \ longint prev_result; \ int ok = 0; \ - for (int i = 0; i < 10; i++) begin \ + if (!bit'(cl.randomize())) $stop; \ + prev_result = longint'(field); \ + if (!(cond)) $stop; \ + repeat(9) begin \ longint result; \ if (!bit'(cl.randomize())) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ - if (i > 0 && result != prev_result) ok = 1; \ + if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ @@ -26,14 +29,24 @@ class C; x < 7; foreach(q[i]) x > i; + foreach(q[i]) // loop again with the same index name + x > i; }; endclass class D; rand bit posit; rand int x; + int o[$]; // empty + int p[$] = {1}; int q[$] = {0, 0, 0, 0, 0}; constraint fore { + if (posit == 1) { + foreach(o[i]) o[i] > 0; + } + if (posit == 1) { + foreach(p[i]) p[i] > 0; + } if (posit == 1) { x < 7; foreach(q[i]) diff --git a/test_regress/t/t_constraint_inheritance.pl b/test_regress/t/t_constraint_inheritance.pl deleted file mode 100755 index 7b520d284..000000000 --- a/test_regress/t/t_constraint_inheritance.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_inheritance.py b/test_regress/t/t_constraint_inheritance.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_inheritance.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_inheritance.v b/test_regress/t/t_constraint_inheritance.v index e37040c4d..081d1cb0a 100644 --- a/test_regress/t/t_constraint_inheritance.v +++ b/test_regress/t/t_constraint_inheritance.v @@ -8,12 +8,15 @@ begin \ longint prev_result; \ int ok = 0; \ - for (int i = 0; i < 10; i++) begin \ + if (!bit'(cl.randomize())) $stop; \ + prev_result = longint'(field); \ + if (!(cond)) $stop; \ + repeat(9) begin \ longint result; \ if (!bit'(cl.randomize())) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ - if (i > 0 && result != prev_result) ok = 1; \ + if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ diff --git a/test_regress/t/t_constraint_inheritance_with.pl b/test_regress/t/t_constraint_inheritance_with.pl deleted file mode 100755 index 7b520d284..000000000 --- a/test_regress/t/t_constraint_inheritance_with.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_inheritance_with.py b/test_regress/t/t_constraint_inheritance_with.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_inheritance_with.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_inheritance_with.v b/test_regress/t/t_constraint_inheritance_with.v index 2a1e4a020..b5e949dd6 100644 --- a/test_regress/t/t_constraint_inheritance_with.v +++ b/test_regress/t/t_constraint_inheritance_with.v @@ -8,12 +8,15 @@ begin \ longint prev_result; \ int ok = 0; \ - for (int i = 0; i < 10; i++) begin \ + if (!bit'(cl.randomize() with { constr; })) $stop; \ + prev_result = longint'(field); \ + if (!(cond)) $stop; \ + repeat(9) begin \ longint result; \ if (!bit'(cl.randomize() with { constr; })) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ - if (i > 0 && result != prev_result) ok = 1; \ + if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ diff --git a/test_regress/t/t_constraint_json_only.pl b/test_regress/t/t_constraint_json_only.pl deleted file mode 100755 index 89cef23e6..000000000 --- a/test_regress/t/t_constraint_json_only.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums', '-Wno-CONSTRAINTIGN'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical($out_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_constraint_json_only.py b/test_regress/t/t_constraint_json_only.py new file mode 100755 index 000000000..66928c7bf --- /dev/null +++ b/test_regress/t/t_constraint_json_only.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile( + verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '-Wno-CONSTRAINTIGN'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_method_bad.pl b/test_regress/t/t_constraint_method_bad.pl deleted file mode 100755 index 66fa61649..000000000 --- a/test_regress/t/t_constraint_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_constraint_method_bad.py b/test_regress/t/t_constraint_method_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_constraint_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_mode.pl b/test_regress/t/t_constraint_mode.pl deleted file mode 100755 index c4618c2fd..000000000 --- a/test_regress/t/t_constraint_mode.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_mode.py b/test_regress/t/t_constraint_mode.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_mode.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_mode_bad.pl b/test_regress/t/t_constraint_mode_bad.pl deleted file mode 100755 index 147dcdcd9..000000000 --- a/test_regress/t/t_constraint_mode_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_constraint_mode_bad.py b/test_regress/t/t_constraint_mode_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_constraint_mode_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_mode_unsup.pl b/test_regress/t/t_constraint_mode_unsup.pl deleted file mode 100755 index 45e5bcdde..000000000 --- a/test_regress/t/t_constraint_mode_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_constraint_mode_unsup.py b/test_regress/t/t_constraint_mode_unsup.py new file mode 100755 index 000000000..6585af685 --- /dev/null +++ b/test_regress/t/t_constraint_mode_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_nosolver_bad.out b/test_regress/t/t_constraint_nosolver_bad.out index fbc57de11..9b379f091 100644 --- a/test_regress/t/t_constraint_nosolver_bad.out +++ b/test_regress/t/t_constraint_nosolver_bad.out @@ -5,4 +5,3 @@ Process::open: execvp(someimaginarysolver): No such file or directory %Error: t/t_constraint.v:23: Verilog $stop Aborting... -Aborted (core dumped) diff --git a/test_regress/t/t_constraint_nosolver_bad.pl b/test_regress/t/t_constraint_nosolver_bad.pl deleted file mode 100755 index 5f489c0d1..000000000 --- a/test_regress/t/t_constraint_nosolver_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_constraint.v"); - -compile( - ); - -execute( - run_env => 'VERILATOR_SOLVER=someimaginarysolver', - fails => 1, - check_finished => 0, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_constraint_nosolver_bad.py b/test_regress/t/t_constraint_nosolver_bad.py new file mode 100755 index 000000000..118aafe1b --- /dev/null +++ b/test_regress/t/t_constraint_nosolver_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_constraint.v" + +test.compile() + +test.execute(run_env='VERILATOR_SOLVER=someimaginarysolver', + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_operators.pl b/test_regress/t/t_constraint_operators.pl deleted file mode 100755 index c4618c2fd..000000000 --- a/test_regress/t/t_constraint_operators.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_operators.py b/test_regress/t/t_constraint_operators.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_operators.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_operators.v b/test_regress/t/t_constraint_operators.v index 4dce0d367..c4faac203 100644 --- a/test_regress/t/t_constraint_operators.v +++ b/test_regress/t/t_constraint_operators.v @@ -34,9 +34,9 @@ class Packet; constraint one_c { one == 1; } constraint sel { d[15:8] == 8'h55; } constraint ifelse { - if (one == 1) out0 == 'h333; + if (one) out0 == 'h333; - if (one == 0) tiny != tiny; + if (!one) tiny != tiny; else out1 == 'h333; if (one == 1) out2 == 'h333; else tiny != tiny; @@ -58,6 +58,11 @@ class Packet; else if (one == 1) tiny != tiny; else { tiny != tiny; } + + if (one && zero) tiny != tiny; + if (~one && zero) tiny != tiny; + if (zero || (one & zero)) tiny != tiny; + if (zero && (one | zero)) tiny != tiny; } endclass diff --git a/test_regress/t/t_constraint_state.pl b/test_regress/t/t_constraint_state.pl deleted file mode 100755 index c4618c2fd..000000000 --- a/test_regress/t/t_constraint_state.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_state.py b/test_regress/t/t_constraint_state.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_state.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_xml.pl b/test_regress/t/t_constraint_xml.pl deleted file mode 100755 index 4cb7c4c79..000000000 --- a/test_regress/t/t_constraint_xml.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only', '-Wno-CONSTRAINTIGN'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical($out_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_constraint_xml.py b/test_regress/t/t_constraint_xml.py new file mode 100755 index 000000000..118386ead --- /dev/null +++ b/test_regress/t/t_constraint_xml.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only', '-Wno-CONSTRAINTIGN'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_continue_do_while_bad.pl b/test_regress/t/t_continue_do_while_bad.pl deleted file mode 100755 index 8e28a9204..000000000 --- a/test_regress/t/t_continue_do_while_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename=>$Self->{golden_filename}, - verilator_flags2=> ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_continue_do_while_bad.py b/test_regress/t/t_continue_do_while_bad.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_continue_do_while_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_convert2string.pl b/test_regress/t/t_convert2string.pl deleted file mode 100755 index beaa2ca59..000000000 --- a/test_regress/t/t_convert2string.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_convert2string.py b/test_regress/t/t_convert2string.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_convert2string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_cover_assert.pl b/test_regress/t/t_cover_assert.pl deleted file mode 100755 index d76b12847..000000000 --- a/test_regress/t/t_cover_assert.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --coverage"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cover_assert.py b/test_regress/t/t_cover_assert.py new file mode 100755 index 000000000..5ca9ccb5c --- /dev/null +++ b/test_regress/t/t_cover_assert.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --coverage"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cover_const_compare.pl b/test_regress/t/t_cover_const_compare.pl deleted file mode 100755 index 205218f81..000000000 --- a/test_regress/t/t_cover_const_compare.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--coverage-line'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cover_const_compare.py b/test_regress/t/t_cover_const_compare.py new file mode 100755 index 000000000..313bee7b5 --- /dev/null +++ b/test_regress/t/t_cover_const_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--coverage-line']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_cover_lib.pl b/test_regress/t/t_cover_lib.pl deleted file mode 100755 index 986f0e572..000000000 --- a/test_regress/t/t_cover_lib.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--coverage t/t_cover_lib_c.cpp"], - verilator_flags2 => ["--exe -Wall -Wno-DECLFILENAME"], - make_flags => 'CPPFLAGS_ADD=-DTEST_OBJ_DIR="' . $Self->{obj_dir} . '"', - make_top_shell => 0, - make_main => 0, - ); - -execute( - check_finished => 1, - ); - -files_identical_sorted("$Self->{obj_dir}/coverage1.dat", "t/t_cover_lib_1.out"); -files_identical_sorted("$Self->{obj_dir}/coverage2.dat", "t/t_cover_lib_2.out"); -files_identical_sorted("$Self->{obj_dir}/coverage3.dat", "t/t_cover_lib_3.out"); -files_identical_sorted("$Self->{obj_dir}/coverage4.dat", "t/t_cover_lib_4.out"); -files_identical_sorted("$Self->{obj_dir}/coverage1_per_instance.dat", "t/t_cover_lib_1_per_instance.out"); - -ok(1); -1; diff --git a/test_regress/t/t_cover_lib.py b/test_regress/t/t_cover_lib.py new file mode 100755 index 000000000..e9df3352d --- /dev/null +++ b/test_regress/t/t_cover_lib.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--coverage t/t_cover_lib_c.cpp"], + verilator_flags2=["--exe -Wall -Wno-DECLFILENAME"], + make_flags=['CPPFLAGS_ADD=-DTEST_OBJ_DIR="' + test.obj_dir + '"'], + make_top_shell=False, + make_main=False) + +test.execute() +test.files_identical_sorted(test.obj_dir + "/coverage1.dat", "t/t_cover_lib_1.out") +test.files_identical_sorted(test.obj_dir + "/coverage2.dat", "t/t_cover_lib_2.out") +test.files_identical_sorted(test.obj_dir + "/coverage3.dat", "t/t_cover_lib_3.out") +test.files_identical_sorted(test.obj_dir + "/coverage4.dat", "t/t_cover_lib_4.out") +test.files_identical_sorted(test.obj_dir + "/coverage1_per_instance.dat", + "t/t_cover_lib_1_per_instance.out") + +test.passes() diff --git a/test_regress/t/t_cover_lib_legacy.pl b/test_regress/t/t_cover_lib_legacy.pl deleted file mode 100755 index d63014f09..000000000 --- a/test_regress/t/t_cover_lib_legacy.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_cover_lib.v"); - -compile( - v_flags2 => ["--coverage t/t_cover_lib_c.cpp"], - verilator_flags2 => ["--exe -Wall -Wno-DECLFILENAME"], - make_flags => 'CPPFLAGS_ADD=-DTEST_OBJ_DIR="' . $Self->{obj_dir} . '"', - make_top_shell => 0, - make_main => 0, - ); - -execute( - check_finished => 1, - ); - -files_identical_sorted("$Self->{obj_dir}/coverage1.dat", "t/t_cover_lib_1.out"); -files_identical_sorted("$Self->{obj_dir}/coverage2.dat", "t/t_cover_lib_2.out"); -files_identical_sorted("$Self->{obj_dir}/coverage3.dat", "t/t_cover_lib_3.out"); -files_identical_sorted("$Self->{obj_dir}/coverage4.dat", "t/t_cover_lib_4.out"); - -ok(1); -1; diff --git a/test_regress/t/t_cover_lib_legacy.py b/test_regress/t/t_cover_lib_legacy.py new file mode 100755 index 000000000..28ce6b5bf --- /dev/null +++ b/test_regress/t/t_cover_lib_legacy.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_cover_lib.v" + +test.compile(v_flags2=["--coverage t/t_cover_lib_c.cpp"], + verilator_flags2=["--exe -Wall -Wno-DECLFILENAME"], + make_flags=['CPPFLAGS_ADD=-DTEST_OBJ_DIR="' + test.obj_dir + '"'], + make_top_shell=False, + make_main=False) + +test.execute() +test.files_identical_sorted(test.obj_dir + "/coverage1.dat", "t/t_cover_lib_1.out") +test.files_identical_sorted(test.obj_dir + "/coverage2.dat", "t/t_cover_lib_2.out") +test.files_identical_sorted(test.obj_dir + "/coverage3.dat", "t/t_cover_lib_3.out") +test.files_identical_sorted(test.obj_dir + "/coverage4.dat", "t/t_cover_lib_4.out") + +test.passes() diff --git a/test_regress/t/t_cover_line.out b/test_regress/t/t_cover_line.out index 4efcf9b6a..4ca952e78 100644 --- a/test_regress/t/t_cover_line.out +++ b/test_regress/t/t_cover_line.out @@ -46,10 +46,14 @@ // Inputs .clk (clk), .toggle (toggle)); + tab tab1 (/*AUTOINST*/ + // Inputs + .clk (clk)); + par par1 (/*AUTOINST*/); 000010 always @ (posedge clk) begin +000010 point: comment=block -%000000 if (cyc!=0) begin +~000010 if (cyc!=0) begin +000010 point: comment=if -000000 point: comment=else 000010 cyc <= cyc + 1; @@ -57,10 +61,10 @@ 000010 toggle <= '0; +000010 point: comment=if // Single and multiline if -%000001 if (cyc==3) $write(""); +%000009 if (cyc==3) $write(""); -000001 point: comment=if -000009 point: comment=else -%000001 if (cyc==3) +%000009 if (cyc==3) -000001 point: comment=if -000009 point: comment=else %000001 begin @@ -69,10 +73,10 @@ -000001 point: comment=if end // Single and multiline else -%000001 if (cyc==3) ; else $write(""); +%000009 if (cyc==3) ; else $write(""); -000001 point: comment=if -000009 point: comment=else -%000001 if (cyc==3) ; +%000009 if (cyc==3) ; -000001 point: comment=if -000009 point: comment=else else @@ -82,10 +86,10 @@ -000009 point: comment=else end // Single and multiline if else -%000001 if (cyc==3) $write(""); else $write(""); +%000009 if (cyc==3) $write(""); else $write(""); -000001 point: comment=if -000009 point: comment=else -%000001 if (cyc==3) +%000009 if (cyc==3) -000001 point: comment=if -000009 point: comment=else %000001 begin @@ -114,7 +118,7 @@ %000001 $write(""); -000001 point: comment=elsif end -%000001 else if (cyc==5) +%000007 else if (cyc==5) -000001 point: comment=if -000007 point: comment=else %000001 begin @@ -138,12 +142,12 @@ end %000000 do ; while (0); -000000 point: comment=block -%000000 do begin -+000010 point: comment=if +~000010 do begin -000000 point: comment=block -%000000 $write(""); +000010 point: comment=if +~000010 $write(""); -000000 point: comment=block ++000010 point: comment=if %000000 end while (0); -000000 point: comment=block //=== @@ -162,7 +166,7 @@ call_task(); `endif end -%000001 else if (cyc==10) begin +%000007 else if (cyc==10) begin -000001 point: comment=if -000007 point: comment=else %000001 $write("*-* All Finished *-*\n"); @@ -190,14 +194,14 @@ input toggle; 000020 always @ (posedge clk) begin +000020 point: comment=block -%000002 if (toggle) begin // CHECK_COVER(0,"top.t.a*",2) +~000018 if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) -000002 point: comment=if +000018 point: comment=else %000002 $write(""); -000002 point: comment=if // t.a1 and t.a2 collapse to a count of 2 end - 000018 if (toggle) begin + 000018 if (toggle) begin // *** t_cover_line.vlt turns this off +000018 point: comment=else $write(""); // CHECK_COVER_MISSING(0) // This doesn't even get added @@ -221,14 +225,14 @@ +000020 point: comment=block 000020 $write(""); // Always covered +000020 point: comment=block -%000000 if (0) begin // CHECK_COVER(0,"top.t.b*",0) +~000020 if (0) begin // CHECK_COVER(0,"top.t.b*",0) -000000 point: comment=if +000020 point: comment=else // Make sure that we don't optimize away zero buckets %000000 $write(""); -000000 point: comment=if end -%000002 if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) +~000018 if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) -000002 point: comment=if +000018 point: comment=else // t.b1 and t.b2 collapse to a count of 2 @@ -241,7 +245,7 @@ `ifdef ATTRIBUTE // verilator coverage_block_off `endif - begin end // Needed for .vlt to attach coverage_block_off + begin end // *** t_cover_line.vlt turns this off (so need begin/end) if (1) begin end // CHECK_COVER_MISSING(0) $write(""); // CHECK_COVER_MISSING(0) end @@ -254,7 +258,7 @@ -000001 point: comment=block %000001 m_toggle = toggle; -000001 point: comment=block -%000000 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) +%000001 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) -000001 point: comment=if -000000 point: comment=else %000001 $write(""); @@ -263,7 +267,7 @@ endfunction 000011 static function void fstatic(bit toggle); +000011 point: comment=block -%000000 if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) +~000011 if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) +000011 point: comment=if -000000 point: comment=else 000011 $write(""); @@ -272,7 +276,7 @@ endfunction 000011 function void fauto(); +000011 point: comment=block -%000000 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) +~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) +000011 point: comment=if -000000 point: comment=else 000011 $write(""); @@ -301,13 +305,13 @@ input external; 000011 begin +000011 point: comment=block -%000001 if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) +~000010 if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) -000001 point: comment=if +000010 point: comment=else %000001 $write(""); -000001 point: comment=if end -%000001 if (external) begin // CHECK_COVER(0,"top.t.t1",1) +~000010 if (external) begin // CHECK_COVER(0,"top.t.t1",1) -000001 point: comment=if +000010 point: comment=else %000001 $write("[%0t] Got external pulse\n", $time); @@ -324,7 +328,6 @@ +000011 point: comment=block end endtask - endmodule module off (/*AUTOARG*/ @@ -344,17 +347,71 @@ // verilator coverage_on 000010 always @ (posedge clk) begin +000010 point: comment=block -%000001 if (toggle) begin +%000009 if (toggle) begin -000001 point: comment=if -000009 point: comment=else // because under coverage_module_off %000001 $write(""); -000001 point: comment=if -%000000 if (0) ; // CHECK_COVER(0,"top.t.o1",1) +%000001 if (0) ; // CHECK_COVER(0,"top.t.o1",1) -000000 point: comment=if -000001 point: comment=else end end + endmodule + + module tab (input clk); + bit [3:0] cyc4; + int decoded; + + 000010 always @ (posedge clk) begin ++000010 point: comment=block + 000010 case (cyc4) ++000010 point: comment=block +%000001 1: decoded = 10; +-000001 point: comment=case +%000001 2: decoded = 20; +-000001 point: comment=case +%000001 3: decoded = 30; +-000001 point: comment=case +%000001 4: decoded = 40; +-000001 point: comment=case +%000001 5: decoded = 50; +-000001 point: comment=case +%000005 default: decoded = 0; +-000005 point: comment=case + endcase + end + + 000010 always @ (posedge clk) begin ++000010 point: comment=block + 000010 cyc4 <= cyc4 + 1; ++000010 point: comment=block + end + endmodule + + module par(); + localparam int CALLS_FUNC = param_func(1); + + // We don't currently count elaboration time use towards coverage. This + // seems safer for functions used both at elaboration time and not - but may + // revisit this. +%000000 function automatic int param_func(int i); +-000000 point: comment=block +%000000 if (i == 0) begin +-000000 point: comment=if +-000000 point: comment=else +%000000 i = 99; // Uncovered +-000000 point: comment=if + end +%000000 else begin +-000000 point: comment=else +%000000 i = i + 1; +-000000 point: comment=else + end +%000000 return i; +-000000 point: comment=block + endfunction endmodule diff --git a/test_regress/t/t_cover_line.v b/test_regress/t/t_cover_line.v index 49da71cdc..6baed34b9 100644 --- a/test_regress/t/t_cover_line.v +++ b/test_regress/t/t_cover_line.v @@ -43,6 +43,10 @@ module t (/*AUTOARG*/ // Inputs .clk (clk), .toggle (toggle)); + tab tab1 (/*AUTOINST*/ + // Inputs + .clk (clk)); + par par1 (/*AUTOINST*/); always @ (posedge clk) begin if (cyc!=0) begin @@ -130,11 +134,11 @@ module alpha (/*AUTOARG*/ input clk; input toggle; always @ (posedge clk) begin - if (toggle) begin // CHECK_COVER(0,"top.t.a*",2) + if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) $write(""); // t.a1 and t.a2 collapse to a count of 2 end - if (toggle) begin + if (toggle) begin // *** t_cover_line.vlt turns this off $write(""); // CHECK_COVER_MISSING(0) // This doesn't even get added `ifdef ATTRIBUTE @@ -168,7 +172,7 @@ module beta (/*AUTOARG*/ `ifdef ATTRIBUTE // verilator coverage_block_off `endif - begin end // Needed for .vlt to attach coverage_block_off + begin end // *** t_cover_line.vlt turns this off (so need begin/end) if (1) begin end // CHECK_COVER_MISSING(0) $write(""); // CHECK_COVER_MISSING(0) end @@ -189,7 +193,7 @@ class Cls; end endfunction function void fauto(); - if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) + if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) $write(""); end endfunction @@ -224,7 +228,6 @@ module tsk (/*AUTOARG*/ Cls::fstatic(1'b1); end endtask - endmodule module off (/*AUTOARG*/ @@ -249,5 +252,42 @@ module off (/*AUTOARG*/ if (0) ; // CHECK_COVER(0,"top.t.o1",1) end end +endmodule + +module tab (input clk); + bit [3:0] cyc4; + int decoded; + + always @ (posedge clk) begin + case (cyc4) + 1: decoded = 10; + 2: decoded = 20; + 3: decoded = 30; + 4: decoded = 40; + 5: decoded = 50; + default: decoded = 0; + endcase + end + + always @ (posedge clk) begin + cyc4 <= cyc4 + 1; + end +endmodule + +module par(); + localparam int CALLS_FUNC = param_func(1); + + // We don't currently count elaboration time use towards coverage. This + // seems safer for functions used both at elaboration time and not - but may + // revisit this. + function automatic int param_func(int i); + if (i == 0) begin + i = 99; // Uncovered + end + else begin + i = i + 1; + end + return i; + endfunction endmodule diff --git a/test_regress/t/t_cover_line.vlt b/test_regress/t/t_cover_line.vlt index a7303b6b5..2778e4d4d 100644 --- a/test_regress/t/t_cover_line.vlt +++ b/test_regress/t/t_cover_line.vlt @@ -6,6 +6,6 @@ `verilator_config -coverage_block_off -file "t/t_cover_line.v" -lines 137 -coverage_block_off -file "t/t_cover_line.v" -lines 171 +coverage_block_off -file "t/t_cover_line.v" -lines 141 +coverage_block_off -file "t/t_cover_line.v" -lines 175 coverage_block_off -module "beta" -block "block" diff --git a/test_regress/t/t_cover_line_cc.info.out b/test_regress/t/t_cover_line_cc.info.out new file mode 100644 index 000000000..72c9727ab --- /dev/null +++ b/test_regress/t/t_cover_line_cc.info.out @@ -0,0 +1,149 @@ +TN:verilator_coverage +SF:t/t_cover_line.v +DA:15,1 +DA:18,1 +DA:51,10 +DA:52,10 +BRDA:52,0,0,10 +BRDA:52,0,1,0 +DA:53,10 +DA:54,10 +DA:56,9 +BRDA:56,0,0,1 +BRDA:56,0,1,9 +DA:57,9 +BRDA:57,0,0,1 +BRDA:57,0,1,9 +DA:58,1 +DA:59,1 +DA:62,9 +BRDA:62,0,0,1 +BRDA:62,0,1,9 +DA:63,9 +BRDA:63,0,0,1 +BRDA:63,0,1,9 +DA:65,9 +DA:66,9 +DA:69,9 +BRDA:69,0,0,1 +BRDA:69,0,1,9 +DA:70,9 +BRDA:70,0,0,1 +BRDA:70,0,1,9 +DA:71,1 +DA:72,1 +DA:75,9 +DA:76,9 +DA:79,1 +DA:80,1 +DA:81,1 +DA:83,1 +DA:84,1 +DA:85,1 +DA:87,7 +BRDA:87,0,0,1 +BRDA:87,0,1,7 +DA:88,1 +DA:89,1 +DA:92,7 +DA:93,7 +DA:96,0 +DA:97,0 +DA:98,0 +DA:100,0 +DA:101,10 +BRDA:101,0,0,0 +BRDA:101,0,1,10 +DA:102,10 +BRDA:102,0,0,0 +BRDA:102,0,1,10 +DA:103,0 +DA:106,1 +DA:107,1 +DA:109,1 +DA:111,1 +DA:116,7 +BRDA:116,0,0,1 +BRDA:116,0,1,7 +DA:117,1 +DA:118,1 +DA:123,1 +DA:125,1 +DA:136,20 +DA:137,18 +BRDA:137,0,0,2 +BRDA:137,0,1,18 +DA:138,2 +DA:141,18 +DA:160,20 +DA:161,20 +DA:162,20 +BRDA:162,0,0,0 +BRDA:162,0,1,20 +DA:164,0 +DA:166,18 +BRDA:166,0,0,2 +BRDA:166,0,1,18 +DA:168,2 +DA:170,18 +DA:184,1 +DA:185,1 +DA:186,1 +BRDA:186,0,0,1 +BRDA:186,0,1,0 +DA:187,1 +DA:190,11 +DA:191,11 +BRDA:191,0,0,11 +BRDA:191,0,1,0 +DA:192,11 +DA:195,11 +DA:196,11 +BRDA:196,0,0,11 +BRDA:196,0,1,0 +DA:197,11 +DA:211,10 +DA:212,10 +DA:215,11 +DA:217,11 +DA:218,10 +BRDA:218,0,0,1 +BRDA:218,0,1,10 +DA:219,1 +DA:221,10 +BRDA:221,0,0,1 +BRDA:221,0,1,10 +DA:222,1 +DA:225,11 +DA:226,1 +DA:227,11 +DA:228,11 +DA:248,10 +DA:249,9 +BRDA:249,0,0,1 +BRDA:249,0,1,9 +DA:251,1 +DA:252,1 +BRDA:252,0,0,0 +BRDA:252,0,1,1 +DA:261,10 +DA:262,10 +DA:263,1 +DA:264,1 +DA:265,1 +DA:266,1 +DA:267,1 +DA:268,5 +DA:272,10 +DA:273,10 +DA:283,0 +DA:284,0 +BRDA:284,0,0,0 +BRDA:284,0,1,0 +DA:285,0 +DA:287,0 +DA:288,0 +DA:290,0 +BRF:44 +BRH:10 +end_of_record diff --git a/test_regress/t/t_cover_line_cc.pl b/test_regress/t/t_cover_line_cc.pl deleted file mode 100755 index 2451e5076..000000000 --- a/test_regress/t/t_cover_line_cc.pl +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cover_line.v"); -golden_filename("t/t_cover_line.out"); - -compile( - verilator_flags2 => ['--cc --coverage-line +define+ATTRIBUTE'], - ); - -execute( - check_finished => 1, - ); - -# Read the input .v file and do any CHECK_COVER requests -inline_checks(); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--annotate-points", - "--annotate", "$Self->{obj_dir}/annotated", - "$Self->{obj_dir}/coverage.dat"], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/annotated/t_cover_line.v", $Self->{golden_filename}); - -# Also try lcov -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--write-info", "$Self->{obj_dir}/coverage.info", - "$Self->{obj_dir}/coverage.dat"], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/coverage.info", $Self->{name} . ".info.out"); - -# If installed -if (`lcov --version` !~ /version/i - || `genhtml --version` !~ /version ([0-9.]+)/i) { - skip("lcov or genhtml not installed"); -} elsif ($1 < 1.14) { - skip("lcov or genhtml too old (version $1), need version >= 1.14"); -} else { - run(cmd => ["genhtml", - "$Self->{obj_dir}/coverage.info", - "--output-directory $Self->{obj_dir}/html", - ]); -} - - -ok(1); -1; diff --git a/test_regress/t/t_cover_line_cc.py b/test_regress/t/t_cover_line_cc.py new file mode 100755 index 000000000..5489f8dfc --- /dev/null +++ b/test_regress/t/t_cover_line_cc.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cover_line.v" +test.golden_filename = "t/t_cover_line.out" + +test.compile(verilator_flags2=['--cc --coverage-line +define+ATTRIBUTE']) + +test.execute() + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--annotate-points", + "--annotate", test.obj_dir + "/annotated", + test.obj_dir + "/coverage.dat"], + verilator_run=True) # yapf:disable + +test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", test.golden_filename) + +# Also try lcov +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--write-info", test.obj_dir + "/coverage.info", + test.obj_dir + "/coverage.dat"], + verilator_run=True) # yapf:disable + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +# If installed +nout = test.run_capture("lcov --version", check=False) +version_match = re.search(r'version ([0-9.]+)', nout, re.IGNORECASE) +if not version_match: + test.skip("lcov or genhtml not installed") + +if float(version_match.group(1)) < 1.14: + test.skip("lcov or genhtml too old (version " + version_match.group(1) + + ", need version >= 1.14") + +test.run(cmd=[ + "genhtml", test.obj_dir + "/coverage.info", "--branch-coverage", "--output-directory " + + test.obj_dir + "/html" +]) + +test.passes() diff --git a/test_regress/t/t_cover_line_cc_vlt.pl b/test_regress/t/t_cover_line_cc_vlt.pl deleted file mode 100755 index 8b4384702..000000000 --- a/test_regress/t/t_cover_line_cc_vlt.pl +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cover_line.v"); -golden_filename("t/t_cover_line.out"); - -compile( - verilator_flags2 => ['--cc', '--coverage-line', "t/t_cover_line.vlt"], - ); - -execute( - check_finished => 1, - ); - -# Read the input .v file and do any CHECK_COVER requests -inline_checks(); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--annotate-points", - "--annotate", "$Self->{obj_dir}/annotated", - "$Self->{obj_dir}/coverage.dat", - ], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/annotated/t_cover_line.v", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_cover_line_cc_vlt.py b/test_regress/t/t_cover_line_cc_vlt.py new file mode 100755 index 000000000..fd97596c4 --- /dev/null +++ b/test_regress/t/t_cover_line_cc_vlt.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cover_line.v" +test.golden_filename = "t/t_cover_line.out" + +test.compile(verilator_flags2=['--cc', '--coverage-line', "t/t_cover_line.vlt"]) + +test.execute() + +# Read the input .v file and do any CHECK_COVER requests +test.inline_checks() + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--annotate-points", + "--annotate", + test.obj_dir + "/annotated", + test.obj_dir + "/coverage.dat", +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cover_line_sc.pl b/test_regress/t/t_cover_line_sc.pl deleted file mode 100755 index 6fb074bfb..000000000 --- a/test_regress/t/t_cover_line_sc.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cover_line.v"); - -compile( - verilator_flags2 => ['--sc --coverage-line +define+ATTRIBUTE'], - ); - -execute( - check_finished => 1, - ); - -# Read the input .v file and do any CHECK_COVER requests -inline_checks(); - -ok(1); -1; diff --git a/test_regress/t/t_cover_line_sc.py b/test_regress/t/t_cover_line_sc.py new file mode 100755 index 000000000..ff73bf508 --- /dev/null +++ b/test_regress/t/t_cover_line_sc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cover_line.v" + +test.compile(verilator_flags2=['--sc --coverage-line +define+ATTRIBUTE']) + +test.execute() + +# Read the input .v file and do any CHECK_COVER requests +test.inline_checks() + +test.passes() diff --git a/test_regress/t/t_cover_line_trace.out b/test_regress/t/t_cover_line_trace.out index be7140138..4283c09c2 100644 --- a/test_regress/t/t_cover_line_trace.out +++ b/test_regress/t/t_cover_line_trace.out @@ -1,100 +1,118 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - $scope module top $end $scope module t $end - $var wire 1 X clk $end + $var wire 1 b clk $end $var wire 1 & toggle $end $var wire 32 # vlCoverageLineTrace_t_cover_line__15_block [31:0] $end $var wire 32 ' cyc [31:0] $end $var wire 32 $ vlCoverageLineTrace_t_cover_line__18_block [31:0] $end $var wire 8 ( cyc_copy [7:0] $end $scope module b1 $end - $var wire 1 X clk $end + $var wire 1 b clk $end $var wire 1 & toggle $end - $var wire 32 L vlCoverageLineTrace_t_cover_line__156_block [31:0] $end - $var wire 32 M vlCoverageLineTrace_t_cover_line__158_else [31:0] $end - $var wire 32 c vlCoverageLineTrace_t_cover_line__158_if [31:0] $end - $var wire 32 N vlCoverageLineTrace_t_cover_line__162_else [31:0] $end - $var wire 32 O vlCoverageLineTrace_t_cover_line__162_if [31:0] $end - $var wire 32 P vlCoverageLineTrace_t_cover_line__166_else [31:0] $end + $var wire 32 V vlCoverageLineTrace_t_cover_line__160_block [31:0] $end + $var wire 32 W vlCoverageLineTrace_t_cover_line__162_else [31:0] $end + $var wire 32 q vlCoverageLineTrace_t_cover_line__162_if [31:0] $end + $var wire 32 X vlCoverageLineTrace_t_cover_line__166_else [31:0] $end + $var wire 32 Y vlCoverageLineTrace_t_cover_line__166_if [31:0] $end + $var wire 32 Z vlCoverageLineTrace_t_cover_line__170_else [31:0] $end $upscope $end $scope module b2 $end - $var wire 1 X clk $end + $var wire 1 b clk $end $var wire 1 & toggle $end - $var wire 32 Q vlCoverageLineTrace_t_cover_line__156_block [31:0] $end - $var wire 32 R vlCoverageLineTrace_t_cover_line__158_else [31:0] $end - $var wire 32 d vlCoverageLineTrace_t_cover_line__158_if [31:0] $end - $var wire 32 S vlCoverageLineTrace_t_cover_line__162_else [31:0] $end - $var wire 32 T vlCoverageLineTrace_t_cover_line__162_if [31:0] $end - $var wire 32 U vlCoverageLineTrace_t_cover_line__166_else [31:0] $end + $var wire 32 [ vlCoverageLineTrace_t_cover_line__160_block [31:0] $end + $var wire 32 \ vlCoverageLineTrace_t_cover_line__162_else [31:0] $end + $var wire 32 r vlCoverageLineTrace_t_cover_line__162_if [31:0] $end + $var wire 32 ] vlCoverageLineTrace_t_cover_line__166_else [31:0] $end + $var wire 32 ^ vlCoverageLineTrace_t_cover_line__166_if [31:0] $end + $var wire 32 _ vlCoverageLineTrace_t_cover_line__170_else [31:0] $end $upscope $end $scope module t1 $end - $var wire 1 X clk $end + $var wire 1 b clk $end $var wire 1 & toggle $end - $var wire 32 V vlCoverageLineTrace_t_cover_line__207_block [31:0] $end - $var wire 32 Z vlCoverageLineTrace_t_cover_line__211_block [31:0] $end - $var wire 32 [ vlCoverageLineTrace_t_cover_line__214_else [31:0] $end - $var wire 32 \ vlCoverageLineTrace_t_cover_line__214_if [31:0] $end - $var wire 32 W vlCoverageLineTrace_t_cover_line__217_else [31:0] $end - $var wire 32 ] vlCoverageLineTrace_t_cover_line__217_if [31:0] $end - $var wire 32 % vlCoverageLineTrace_t_cover_line__222_block [31:0] $end + $var wire 32 ` vlCoverageLineTrace_t_cover_line__211_block [31:0] $end + $var wire 32 d vlCoverageLineTrace_t_cover_line__215_block [31:0] $end + $var wire 32 e vlCoverageLineTrace_t_cover_line__218_else [31:0] $end + $var wire 32 f vlCoverageLineTrace_t_cover_line__218_if [31:0] $end + $var wire 32 a vlCoverageLineTrace_t_cover_line__221_else [31:0] $end + $var wire 32 g vlCoverageLineTrace_t_cover_line__221_if [31:0] $end + $var wire 32 % vlCoverageLineTrace_t_cover_line__226_block [31:0] $end $upscope $end - $var wire 32 ) vlCoverageLineTrace_t_cover_line__47_block [31:0] $end - $var wire 32 * vlCoverageLineTrace_t_cover_line__48_else [31:0] $end - $var wire 32 + vlCoverageLineTrace_t_cover_line__48_if [31:0] $end - $var wire 32 , vlCoverageLineTrace_t_cover_line__52_else [31:0] $end - $var wire 32 - vlCoverageLineTrace_t_cover_line__52_if [31:0] $end - $var wire 32 . vlCoverageLineTrace_t_cover_line__53_else [31:0] $end - $var wire 32 / vlCoverageLineTrace_t_cover_line__53_if [31:0] $end - $var wire 32 0 vlCoverageLineTrace_t_cover_line__58_else [31:0] $end - $var wire 32 1 vlCoverageLineTrace_t_cover_line__58_if [31:0] $end - $var wire 32 2 vlCoverageLineTrace_t_cover_line__59_else [31:0] $end - $var wire 32 3 vlCoverageLineTrace_t_cover_line__59_if [31:0] $end - $var wire 32 4 vlCoverageLineTrace_t_cover_line__65_else [31:0] $end - $var wire 32 5 vlCoverageLineTrace_t_cover_line__65_if [31:0] $end - $var wire 32 6 vlCoverageLineTrace_t_cover_line__66_else [31:0] $end - $var wire 32 7 vlCoverageLineTrace_t_cover_line__66_if [31:0] $end - $var wire 32 8 vlCoverageLineTrace_t_cover_line__75_elsif [31:0] $end - $var wire 32 9 vlCoverageLineTrace_t_cover_line__79_elsif [31:0] $end - $var wire 32 : vlCoverageLineTrace_t_cover_line__83_else [31:0] $end - $var wire 32 ; vlCoverageLineTrace_t_cover_line__83_if [31:0] $end - $var wire 32 ^ vlCoverageLineTrace_t_cover_line__92_block [31:0] $end - $var wire 32 _ vlCoverageLineTrace_t_cover_line__93_block [31:0] $end - $var wire 32 ` vlCoverageLineTrace_t_cover_line__96_block [31:0] $end - $var wire 32 a vlCoverageLineTrace_t_cover_line__97_block [31:0] $end - $var wire 32 < vlCoverageLineTrace_t_cover_line__102_elsif [31:0] $end - $var wire 32 = vlCoverageLineTrace_t_cover_line__105_elsif [31:0] $end - $var wire 32 > vlCoverageLineTrace_t_cover_line__112_else [31:0] $end - $var wire 32 ? vlCoverageLineTrace_t_cover_line__112_if [31:0] $end - $var wire 32 Y vlCoverageLineTrace_t_cover_line__119_block [31:0] $end + $var wire 32 ) vlCoverageLineTrace_t_cover_line__51_block [31:0] $end + $var wire 32 * vlCoverageLineTrace_t_cover_line__52_else [31:0] $end + $var wire 32 + vlCoverageLineTrace_t_cover_line__52_if [31:0] $end + $var wire 32 , vlCoverageLineTrace_t_cover_line__56_else [31:0] $end + $var wire 32 - vlCoverageLineTrace_t_cover_line__56_if [31:0] $end + $var wire 32 . vlCoverageLineTrace_t_cover_line__57_else [31:0] $end + $var wire 32 / vlCoverageLineTrace_t_cover_line__57_if [31:0] $end + $var wire 32 0 vlCoverageLineTrace_t_cover_line__62_else [31:0] $end + $var wire 32 1 vlCoverageLineTrace_t_cover_line__62_if [31:0] $end + $var wire 32 2 vlCoverageLineTrace_t_cover_line__63_else [31:0] $end + $var wire 32 3 vlCoverageLineTrace_t_cover_line__63_if [31:0] $end + $var wire 32 4 vlCoverageLineTrace_t_cover_line__69_else [31:0] $end + $var wire 32 5 vlCoverageLineTrace_t_cover_line__69_if [31:0] $end + $var wire 32 6 vlCoverageLineTrace_t_cover_line__70_else [31:0] $end + $var wire 32 7 vlCoverageLineTrace_t_cover_line__70_if [31:0] $end + $var wire 32 8 vlCoverageLineTrace_t_cover_line__79_elsif [31:0] $end + $var wire 32 9 vlCoverageLineTrace_t_cover_line__83_elsif [31:0] $end + $var wire 32 : vlCoverageLineTrace_t_cover_line__87_else [31:0] $end + $var wire 32 ; vlCoverageLineTrace_t_cover_line__87_if [31:0] $end + $var wire 32 h vlCoverageLineTrace_t_cover_line__96_block [31:0] $end + $var wire 32 i vlCoverageLineTrace_t_cover_line__97_block [31:0] $end + $var wire 32 j vlCoverageLineTrace_t_cover_line__100_block [31:0] $end + $var wire 32 k vlCoverageLineTrace_t_cover_line__101_block [31:0] $end + $var wire 32 < vlCoverageLineTrace_t_cover_line__106_elsif [31:0] $end + $var wire 32 = vlCoverageLineTrace_t_cover_line__109_elsif [31:0] $end + $var wire 32 > vlCoverageLineTrace_t_cover_line__116_else [31:0] $end + $var wire 32 ? vlCoverageLineTrace_t_cover_line__116_if [31:0] $end + $var wire 32 c vlCoverageLineTrace_t_cover_line__123_block [31:0] $end $scope module a1 $end - $var wire 1 X clk $end + $var wire 1 b clk $end $var wire 1 & toggle $end - $var wire 32 @ vlCoverageLineTrace_t_cover_line__132_block [31:0] $end - $var wire 32 A vlCoverageLineTrace_t_cover_line__133_else [31:0] $end - $var wire 32 B vlCoverageLineTrace_t_cover_line__133_if [31:0] $end - $var wire 32 C vlCoverageLineTrace_t_cover_line__137_else [31:0] $end + $var wire 32 @ vlCoverageLineTrace_t_cover_line__136_block [31:0] $end + $var wire 32 A vlCoverageLineTrace_t_cover_line__137_else [31:0] $end + $var wire 32 B vlCoverageLineTrace_t_cover_line__137_if [31:0] $end + $var wire 32 C vlCoverageLineTrace_t_cover_line__141_else [31:0] $end $upscope $end $scope module a2 $end - $var wire 1 X clk $end + $var wire 1 b clk $end $var wire 1 & toggle $end - $var wire 32 D vlCoverageLineTrace_t_cover_line__132_block [31:0] $end - $var wire 32 E vlCoverageLineTrace_t_cover_line__133_else [31:0] $end - $var wire 32 F vlCoverageLineTrace_t_cover_line__133_if [31:0] $end - $var wire 32 G vlCoverageLineTrace_t_cover_line__137_else [31:0] $end + $var wire 32 D vlCoverageLineTrace_t_cover_line__136_block [31:0] $end + $var wire 32 E vlCoverageLineTrace_t_cover_line__137_else [31:0] $end + $var wire 32 F vlCoverageLineTrace_t_cover_line__137_if [31:0] $end + $var wire 32 G vlCoverageLineTrace_t_cover_line__141_else [31:0] $end $upscope $end $scope module o1 $end - $var wire 1 X clk $end + $var wire 1 b clk $end $var wire 1 & toggle $end - $var wire 32 H vlCoverageLineTrace_t_cover_line__245_block [31:0] $end - $var wire 32 I vlCoverageLineTrace_t_cover_line__246_else [31:0] $end - $var wire 32 J vlCoverageLineTrace_t_cover_line__246_if [31:0] $end - $var wire 32 K vlCoverageLineTrace_t_cover_line__249_else [31:0] $end - $var wire 32 b vlCoverageLineTrace_t_cover_line__249_if [31:0] $end + $var wire 32 H vlCoverageLineTrace_t_cover_line__248_block [31:0] $end + $var wire 32 I vlCoverageLineTrace_t_cover_line__249_else [31:0] $end + $var wire 32 J vlCoverageLineTrace_t_cover_line__249_if [31:0] $end + $var wire 32 K vlCoverageLineTrace_t_cover_line__252_else [31:0] $end + $var wire 32 l vlCoverageLineTrace_t_cover_line__252_if [31:0] $end + $upscope $end + $scope module par1 $end + $var wire 32 m CALLS_FUNC [31:0] $end + $var wire 32 n vlCoverageLineTrace_t_cover_line__283_block [31:0] $end + $var wire 32 o vlCoverageLineTrace_t_cover_line__284_else [31:0] $end + $var wire 32 p vlCoverageLineTrace_t_cover_line__284_if [31:0] $end + $upscope $end + $scope module tab1 $end + $var wire 1 b clk $end + $var wire 4 L cyc4 [3:0] $end + $var wire 32 M decoded [31:0] $end + $var wire 32 N vlCoverageLineTrace_t_cover_line__261_block [31:0] $end + $var wire 32 O vlCoverageLineTrace_t_cover_line__263_case [31:0] $end + $var wire 32 P vlCoverageLineTrace_t_cover_line__264_case [31:0] $end + $var wire 32 Q vlCoverageLineTrace_t_cover_line__265_case [31:0] $end + $var wire 32 R vlCoverageLineTrace_t_cover_line__266_case [31:0] $end + $var wire 32 S vlCoverageLineTrace_t_cover_line__267_case [31:0] $end + $var wire 32 T vlCoverageLineTrace_t_cover_line__268_case [31:0] $end + $var wire 32 U vlCoverageLineTrace_t_cover_line__272_block [31:0] $end $upscope $end $upscope $end - $var wire 1 X clk $end + $var wire 1 b clk $end $upscope $end $enddefinitions $end @@ -141,7 +159,7 @@ b00000000000000000000000000000000 H b00000000000000000000000000000000 I b00000000000000000000000000000000 J b00000000000000000000000000000000 K -b00000000000000000000000000000000 L +b0000 L b00000000000000000000000000000000 M b00000000000000000000000000000000 N b00000000000000000000000000000000 O @@ -153,7 +171,7 @@ b00000000000000000000000000000000 T b00000000000000000000000000000000 U b00000000000000000000000000000000 V b00000000000000000000000000000000 W -0X +b00000000000000000000000000000000 X b00000000000000000000000000000000 Y b00000000000000000000000000000000 Z b00000000000000000000000000000000 [ @@ -163,9 +181,23 @@ b00000000000000000000000000000000 ^ b00000000000000000000000000000000 _ b00000000000000000000000000000000 ` b00000000000000000000000000000000 a -b00000000000000000000000000000000 b +0b b00000000000000000000000000000000 c b00000000000000000000000000000000 d +b00000000000000000000000000000000 e +b00000000000000000000000000000000 f +b00000000000000000000000000000000 g +b00000000000000000000000000000000 h +b00000000000000000000000000000000 i +b00000000000000000000000000000000 j +b00000000000000000000000000000000 k +b00000000000000000000000000000000 l +b00000000000000000000000000000010 m +b00000000000000000000000000000000 n +b00000000000000000000000000000000 o +b00000000000000000000000000000000 p +b00000000000000000000000000000000 q +b00000000000000000000000000000000 r #10 b00000000000000000000000000000010 ' b00000010 ( @@ -187,21 +219,25 @@ b00000000000000000000000000000001 E b00000000000000000000000000000001 G b00000000000000000000000000000001 H b00000000000000000000000000000001 I -b00000000000000000000000000000001 L -b00000000000000000000000000000001 M +b0001 L b00000000000000000000000000000001 N -b00000000000000000000000000000001 P -b00000000000000000000000000000001 Q -b00000000000000000000000000000001 R -b00000000000000000000000000000001 S +b00000000000000000000000000000001 T b00000000000000000000000000000001 U b00000000000000000000000000000001 V b00000000000000000000000000000001 W -1X +b00000000000000000000000000000001 X b00000000000000000000000000000001 Z b00000000000000000000000000000001 [ +b00000000000000000000000000000001 \ +b00000000000000000000000000000001 ] +b00000000000000000000000000000001 _ +b00000000000000000000000000000001 ` +b00000000000000000000000000000001 a +1b +b00000000000000000000000000000001 d +b00000000000000000000000000000001 e #15 -0X +0b #20 b00000000000000000000000000000011 ' b00000011 ( @@ -223,21 +259,26 @@ b00000000000000000000000000000010 E b00000000000000000000000000000010 G b00000000000000000000000000000010 H b00000000000000000000000000000010 I -b00000000000000000000000000000010 L -b00000000000000000000000000000010 M +b0010 L +b00000000000000000000000000001010 M b00000000000000000000000000000010 N -b00000000000000000000000000000010 P -b00000000000000000000000000000010 Q -b00000000000000000000000000000010 R -b00000000000000000000000000000010 S +b00000000000000000000000000000001 O b00000000000000000000000000000010 U b00000000000000000000000000000010 V b00000000000000000000000000000010 W -1X +b00000000000000000000000000000010 X b00000000000000000000000000000010 Z b00000000000000000000000000000010 [ +b00000000000000000000000000000010 \ +b00000000000000000000000000000010 ] +b00000000000000000000000000000010 _ +b00000000000000000000000000000010 ` +b00000000000000000000000000000010 a +1b +b00000000000000000000000000000010 d +b00000000000000000000000000000010 e #25 -0X +0b #30 1& b00000000000000000000000000000100 ' @@ -260,21 +301,26 @@ b00000000000000000000000000000011 E b00000000000000000000000000000011 G b00000000000000000000000000000011 H b00000000000000000000000000000011 I -b00000000000000000000000000000011 L -b00000000000000000000000000000011 M +b0011 L +b00000000000000000000000000010100 M b00000000000000000000000000000011 N -b00000000000000000000000000000011 P -b00000000000000000000000000000011 Q -b00000000000000000000000000000011 R -b00000000000000000000000000000011 S +b00000000000000000000000000000001 P b00000000000000000000000000000011 U b00000000000000000000000000000011 V b00000000000000000000000000000011 W -1X +b00000000000000000000000000000011 X b00000000000000000000000000000011 Z b00000000000000000000000000000011 [ +b00000000000000000000000000000011 \ +b00000000000000000000000000000011 ] +b00000000000000000000000000000011 _ +b00000000000000000000000000000011 ` +b00000000000000000000000000000011 a +1b +b00000000000000000000000000000011 d +b00000000000000000000000000000011 e #35 -0X +0b #40 0& b00000000000000000000000000000101 ' @@ -296,19 +342,24 @@ b00000000000000000000000000000001 F b00000000000000000000000000000100 H b00000000000000000000000000000001 J b00000000000000000000000000000001 K -b00000000000000000000000000000100 L -b00000000000000000000000000000100 M -b00000000000000000000000000000001 O -b00000000000000000000000000000100 Q -b00000000000000000000000000000100 R -b00000000000000000000000000000001 T +b0100 L +b00000000000000000000000000011110 M +b00000000000000000000000000000100 N +b00000000000000000000000000000001 Q +b00000000000000000000000000000100 U b00000000000000000000000000000100 V b00000000000000000000000000000100 W -1X -b00000000000000000000000000000100 Z -b00000000000000000000000000000001 \ +b00000000000000000000000000000001 Y +b00000000000000000000000000000100 [ +b00000000000000000000000000000100 \ +b00000000000000000000000000000001 ^ +b00000000000000000000000000000100 ` +b00000000000000000000000000000100 a +1b +b00000000000000000000000000000100 d +b00000000000000000000000000000001 f #45 -0X +0b #50 b00000000000000000000000000000110 ' b00000110 ( @@ -330,23 +381,28 @@ b00000000000000000000000000000100 E b00000000000000000000000000000100 G b00000000000000000000000000000101 H b00000000000000000000000000000100 I -b00000000000000000000000000000101 L -b00000000000000000000000000000101 M -b00000000000000000000000000000100 N -b00000000000000000000000000000100 P -b00000000000000000000000000000101 Q -b00000000000000000000000000000101 R -b00000000000000000000000000000100 S -b00000000000000000000000000000100 U +b0101 L +b00000000000000000000000000101000 M +b00000000000000000000000000000101 N +b00000000000000000000000000000001 R +b00000000000000000000000000000101 U b00000000000000000000000000000101 V b00000000000000000000000000000101 W -1X -b00000000000000000000000000000001 Y -b00000000000000000000000000000110 Z +b00000000000000000000000000000100 X +b00000000000000000000000000000100 Z b00000000000000000000000000000101 [ -b00000000000000000000000000000001 ] +b00000000000000000000000000000101 \ +b00000000000000000000000000000100 ] +b00000000000000000000000000000100 _ +b00000000000000000000000000000101 ` +b00000000000000000000000000000101 a +1b +b00000000000000000000000000000001 c +b00000000000000000000000000000110 d +b00000000000000000000000000000101 e +b00000000000000000000000000000001 g #55 -0X +0b #60 b00000000000000000000000000000111 ' b00000111 ( @@ -368,21 +424,26 @@ b00000000000000000000000000000101 E b00000000000000000000000000000101 G b00000000000000000000000000000110 H b00000000000000000000000000000101 I -b00000000000000000000000000000110 L -b00000000000000000000000000000110 M -b00000000000000000000000000000101 N -b00000000000000000000000000000101 P -b00000000000000000000000000000110 Q -b00000000000000000000000000000110 R -b00000000000000000000000000000101 S -b00000000000000000000000000000101 U +b0110 L +b00000000000000000000000000110010 M +b00000000000000000000000000000110 N +b00000000000000000000000000000001 S +b00000000000000000000000000000110 U b00000000000000000000000000000110 V b00000000000000000000000000000110 W -1X -b00000000000000000000000000000111 Z +b00000000000000000000000000000101 X +b00000000000000000000000000000101 Z b00000000000000000000000000000110 [ +b00000000000000000000000000000110 \ +b00000000000000000000000000000101 ] +b00000000000000000000000000000101 _ +b00000000000000000000000000000110 ` +b00000000000000000000000000000110 a +1b +b00000000000000000000000000000111 d +b00000000000000000000000000000110 e #65 -0X +0b #70 b00000000000000000000000000001000 ' b00001000 ( @@ -404,21 +465,26 @@ b00000000000000000000000000000110 E b00000000000000000000000000000110 G b00000000000000000000000000000111 H b00000000000000000000000000000110 I -b00000000000000000000000000000111 L -b00000000000000000000000000000111 M -b00000000000000000000000000000110 N -b00000000000000000000000000000110 P -b00000000000000000000000000000111 Q -b00000000000000000000000000000111 R -b00000000000000000000000000000110 S -b00000000000000000000000000000110 U +b0111 L +b00000000000000000000000000000000 M +b00000000000000000000000000000111 N +b00000000000000000000000000000010 T +b00000000000000000000000000000111 U b00000000000000000000000000000111 V b00000000000000000000000000000111 W -1X -b00000000000000000000000000001000 Z +b00000000000000000000000000000110 X +b00000000000000000000000000000110 Z b00000000000000000000000000000111 [ +b00000000000000000000000000000111 \ +b00000000000000000000000000000110 ] +b00000000000000000000000000000110 _ +b00000000000000000000000000000111 ` +b00000000000000000000000000000111 a +1b +b00000000000000000000000000001000 d +b00000000000000000000000000000111 e #75 -0X +0b #80 b00000000000000000000000000001001 ' b00001001 ( @@ -440,21 +506,25 @@ b00000000000000000000000000000111 E b00000000000000000000000000000111 G b00000000000000000000000000001000 H b00000000000000000000000000000111 I -b00000000000000000000000000001000 L -b00000000000000000000000000001000 M -b00000000000000000000000000000111 N -b00000000000000000000000000000111 P -b00000000000000000000000000001000 Q -b00000000000000000000000000001000 R -b00000000000000000000000000000111 S -b00000000000000000000000000000111 U +b1000 L +b00000000000000000000000000001000 N +b00000000000000000000000000000011 T +b00000000000000000000000000001000 U b00000000000000000000000000001000 V b00000000000000000000000000001000 W -1X -b00000000000000000000000000001001 Z +b00000000000000000000000000000111 X +b00000000000000000000000000000111 Z b00000000000000000000000000001000 [ +b00000000000000000000000000001000 \ +b00000000000000000000000000000111 ] +b00000000000000000000000000000111 _ +b00000000000000000000000000001000 ` +b00000000000000000000000000001000 a +1b +b00000000000000000000000000001001 d +b00000000000000000000000000001000 e #85 -0X +0b #90 b00000000000000000000000000001010 ' b00001010 ( @@ -476,21 +546,25 @@ b00000000000000000000000000001000 E b00000000000000000000000000001000 G b00000000000000000000000000001001 H b00000000000000000000000000001000 I -b00000000000000000000000000001001 L -b00000000000000000000000000001001 M -b00000000000000000000000000001000 N -b00000000000000000000000000001000 P -b00000000000000000000000000001001 Q -b00000000000000000000000000001001 R -b00000000000000000000000000001000 S -b00000000000000000000000000001000 U +b1001 L +b00000000000000000000000000001001 N +b00000000000000000000000000000100 T +b00000000000000000000000000001001 U b00000000000000000000000000001001 V b00000000000000000000000000001001 W -1X -b00000000000000000000000000001010 Z +b00000000000000000000000000001000 X +b00000000000000000000000000001000 Z b00000000000000000000000000001001 [ +b00000000000000000000000000001001 \ +b00000000000000000000000000001000 ] +b00000000000000000000000000001000 _ +b00000000000000000000000000001001 ` +b00000000000000000000000000001001 a +1b +b00000000000000000000000000001010 d +b00000000000000000000000000001001 e #95 -0X +0b #100 b00000000000000000000000000001011 ' b00001011 ( @@ -512,16 +586,20 @@ b00000000000000000000000000001001 E b00000000000000000000000000001001 G b00000000000000000000000000001010 H b00000000000000000000000000001001 I -b00000000000000000000000000001010 L -b00000000000000000000000000001010 M -b00000000000000000000000000001001 N -b00000000000000000000000000001001 P -b00000000000000000000000000001010 Q -b00000000000000000000000000001010 R -b00000000000000000000000000001001 S -b00000000000000000000000000001001 U +b1010 L +b00000000000000000000000000001010 N +b00000000000000000000000000000101 T +b00000000000000000000000000001010 U b00000000000000000000000000001010 V b00000000000000000000000000001010 W -1X -b00000000000000000000000000001011 Z +b00000000000000000000000000001001 X +b00000000000000000000000000001001 Z b00000000000000000000000000001010 [ +b00000000000000000000000000001010 \ +b00000000000000000000000000001001 ] +b00000000000000000000000000001001 _ +b00000000000000000000000000001010 ` +b00000000000000000000000000001010 a +1b +b00000000000000000000000000001011 d +b00000000000000000000000000001010 e diff --git a/test_regress/t/t_cover_line_trace.pl b/test_regress/t/t_cover_line_trace.pl deleted file mode 100755 index 79f61b1bb..000000000 --- a/test_regress/t/t_cover_line_trace.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cover_line.v"); - -compile( - verilator_flags2 => ['--cc --coverage-line --trace --trace-coverage +define+ATTRIBUTE'], - ); - -execute( - check_finished => 1, - ); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--annotate-points", - "--annotate", "$Self->{obj_dir}/annotated", - "$Self->{obj_dir}/coverage.dat", - ], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/annotated/t_cover_line.v", "t/t_cover_line.out"); -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_cover_line_trace.py b/test_regress/t/t_cover_line_trace.py new file mode 100755 index 000000000..3a2fb4784 --- /dev/null +++ b/test_regress/t/t_cover_line_trace.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cover_line.v" + +test.compile(verilator_flags2=['--cc --coverage-line --trace --trace-coverage +define+ATTRIBUTE']) + +test.execute() + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--annotate-points", + "--annotate", + test.obj_dir + "/annotated", + test.obj_dir + "/coverage.dat", +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", "t/t_cover_line.out") +test.vcd_identical(test.trace_filename, test.golden_filename) +test.passes() diff --git a/test_regress/t/t_cover_main.out b/test_regress/t/t_cover_main.out index d762fd325..4194def02 100644 --- a/test_regress/t/t_cover_main.out +++ b/test_regress/t/t_cover_main.out @@ -1,2 +1,2 @@ # SystemC::Coverage-3 -C 'ft/t_cover_main.vl9n4pagev_line/toblockS9-11hTOP.t' 1 +C 'ft/t_cover_main.vl9n4pagev_line/toblockS9-11ht' 1 diff --git a/test_regress/t/t_cover_main.pl b/test_regress/t/t_cover_main.pl deleted file mode 100755 index efd553940..000000000 --- a/test_regress/t/t_cover_main.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --coverage-line'], - ); - -execute( - all_run_flags => [" +verilator+coverage+file+$Self->{obj_dir}/coverage_renamed.dat"], - check_finished => 1, - ); - -files_identical_sorted("$Self->{obj_dir}/coverage_renamed.dat", "t/t_cover_main.out"); - -ok(1); -1; diff --git a/test_regress/t/t_cover_main.py b/test_regress/t/t_cover_main.py new file mode 100755 index 000000000..9f3651d02 --- /dev/null +++ b/test_regress/t/t_cover_main.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --coverage-line']) + +test.execute(all_run_flags=[" +verilator+coverage+file+" + test.obj_dir + "/coverage_renamed.dat"]) + +test.files_identical_sorted(test.obj_dir + "/coverage_renamed.dat", "t/t_cover_main.out") +test.passes() diff --git a/test_regress/t/t_cover_sva_notflat.pl b/test_regress/t/t_cover_sva_notflat.pl deleted file mode 100755 index e4839f963..000000000 --- a/test_regress/t/t_cover_sva_notflat.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user'], - ); - -execute( - check_finished => 1, - ); - -#if ($Self->{nc}) ... # See t_assert_cover.pl for NC version - -# Allow old SystemC::Coverage format dump, or new binary dump -# Check that the hierarchy doesn't include __PVT__ -# Otherwise our coverage reports would look really ugly -if ($Self->{vlt_all}) { - file_grep($Self->{coverage_filename}, qr/(top\.t\.sub.*.cyc_eq_5)/); -} - -ok(1); -1; diff --git a/test_regress/t/t_cover_sva_notflat.py b/test_regress/t/t_cover_sva_notflat.py new file mode 100755 index 000000000..8202ac126 --- /dev/null +++ b/test_regress/t/t_cover_sva_notflat.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert --cc --coverage-user']) + +test.execute() + +#if test.nc: ... # See t_assert_cover.py for NC version + +# Allow old SystemC::Coverage format dump, or new binary dump +# Check that the hierarchy doesn't include __PVT__ +# Otherwise our coverage reports would look really ugly +if test.vlt_all: + test.file_grep(test.coverage_filename, r'(top\.t\.sub.*.cyc_eq_5)') + +test.passes() diff --git a/test_regress/t/t_cover_sva_trace.pl b/test_regress/t/t_cover_sva_trace.pl deleted file mode 100755 index aea072add..000000000 --- a/test_regress/t/t_cover_sva_trace.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cover_sva_notflat.v"); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user --trace --trace-coverage'], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_cover_sva_trace.py b/test_regress/t/t_cover_sva_trace.py new file mode 100755 index 000000000..5e5c25fdb --- /dev/null +++ b/test_regress/t/t_cover_sva_trace.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cover_sva_notflat.v" + +test.compile(verilator_flags2=['--assert --cc --coverage-user --trace --trace-coverage']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cover_toggle.out b/test_regress/t/t_cover_toggle.out index c5ede53c4..065e014a0 100644 --- a/test_regress/t/t_cover_toggle.out +++ b/test_regress/t/t_cover_toggle.out @@ -34,10 +34,10 @@ const reg aconst = '0; -%000000 reg [1:0][1:0] ptoggle; initial ptoggle=0; +%000002 reg [1:0][1:0] ptoggle; initial ptoggle=0; integer cyc; initial cyc=1; -%000000 wire [7:0] cyc_copy = cyc[7:0]; +~000011 wire [7:0] cyc_copy = cyc[7:0]; %000002 wire toggle_up; typedef struct { @@ -70,7 +70,7 @@ .clk (clk), .toggle (toggle)); -%000000 reg [1:0] memory[121:110]; +%000001 reg [1:0] memory[121:110]; wire [1023:0] largeish = {992'h0, cyc}; // CHECK_COVER_MISSING(-1) @@ -116,7 +116,7 @@ // CHECK_COVER(-1,"top.t.a*",4) // 2 edges * (t.a1 and t.a2) -%000000 input [7:0] cyc_copy; +~000022 input [7:0] cyc_copy; // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22) // CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10) // CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4) diff --git a/test_regress/t/t_cover_toggle.pl b/test_regress/t/t_cover_toggle.pl deleted file mode 100755 index 958a3d391..000000000 --- a/test_regress/t/t_cover_toggle.pl +++ /dev/null @@ -1,49 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --coverage-toggle --stats'], - ); - -execute( - check_finished => 1, - ); - -# Read the input .v file and do any CHECK_COVER requests -inline_checks(); - -file_grep_not("$Self->{obj_dir}/coverage.dat", "largeish"); - -file_grep($Self->{stats}, qr/Coverage, Toggle points joined\s+(\d+)/i, 23) - if $Self->{vlt_all}; - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--annotate", "$Self->{obj_dir}/annotated", - "$Self->{obj_dir}/coverage.dat", - ], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/annotated/$Self->{name}.v", $Self->{golden_filename}); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--annotate-points", - "--annotate", "$Self->{obj_dir}/annotated-points", - "$Self->{obj_dir}/coverage.dat", - ], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/annotated-points/$Self->{name}.v", "t/" . $Self->{name} . "_points.out"); - -ok(1); -1; diff --git a/test_regress/t/t_cover_toggle.py b/test_regress/t/t_cover_toggle.py new file mode 100755 index 000000000..a023aa31c --- /dev/null +++ b/test_regress/t/t_cover_toggle.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --coverage-toggle --stats']) + +test.execute() + +# Read the input .v file and do any CHECK_COVER requests +test.inline_checks() + +test.file_grep_not(test.obj_dir + "/coverage.dat", "largeish") + +if test.vlt_all: + test.file_grep(test.stats, r'Coverage, Toggle points joined\s+(\d+)', 23) + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--annotate", + test.obj_dir + "/annotated", + test.obj_dir + "/coverage.dat", +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/annotated/" + test.name + ".v", test.golden_filename) + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--annotate-points", + "--annotate", + test.obj_dir + "/annotated-points", + test.obj_dir + "/coverage.dat", +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/annotated-points/" + test.name + ".v", + "t/" + test.name + "_points.out") + +test.passes() diff --git a/test_regress/t/t_cover_toggle_min.info.out b/test_regress/t/t_cover_toggle_min.info.out new file mode 100644 index 000000000..a5581bcd2 --- /dev/null +++ b/test_regress/t/t_cover_toggle_min.info.out @@ -0,0 +1,14 @@ +TN:verilator_coverage +SF:t/t_cover_toggle_min.v +DA:10,1 +BRDA:10,0,0,1 +BRDA:10,0,1,0 +DA:11,1 +BRDA:11,0,0,0 +BRDA:11,0,1,1 +DA:12,2 +BRDA:12,0,0,2 +BRDA:12,0,1,1 +BRF:6 +BRH:0 +end_of_record diff --git a/test_regress/t/t_cover_toggle_min.pl b/test_regress/t/t_cover_toggle_min.pl deleted file mode 100755 index cf625bf5c..000000000 --- a/test_regress/t/t_cover_toggle_min.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary', '--coverage-toggle'], - ); - -execute( - all_run_flags => [" +verilator+coverage+file+$Self->{obj_dir}/coverage.dat"], - check_finished => 1, - ); - -if (-e ("$Self->{obj_dir}/coverage.dat")) { # Don't try to write .info if test was skipped - run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "-write-info", "$Self->{obj_dir}/coverage.info", - "$Self->{obj_dir}/coverage.dat", - ], - verilator_run => 1, - ); - - files_identical("$Self->{obj_dir}/coverage.info", $Self->{name} . ".info.out"); -} - -ok(1); -1; diff --git a/test_regress/t/t_cover_toggle_min.py b/test_regress/t/t_cover_toggle_min.py new file mode 100755 index 000000000..83bd0383a --- /dev/null +++ b/test_regress/t/t_cover_toggle_min.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary', '--coverage-toggle']) + +test.execute(all_run_flags=[" +verilator+coverage+file+" + test.obj_dir + "/coverage.dat"]) + +if os.path.exists(test.obj_dir + "/coverage.dat"): # Don't try to write .info if test was skipped + test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "-write-info", + test.obj_dir + "/coverage.info", + test.obj_dir + "/coverage.dat", + ], + verilator_run=True) + + test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_cover_toggle_points.out b/test_regress/t/t_cover_toggle_points.out index 6593bf99b..2154b19f1 100644 --- a/test_regress/t/t_cover_toggle_points.out +++ b/test_regress/t/t_cover_toggle_points.out @@ -40,14 +40,14 @@ const reg aconst = '0; -%000000 reg [1:0][1:0] ptoggle; initial ptoggle=0; +%000002 reg [1:0][1:0] ptoggle; initial ptoggle=0; -000002 point: comment=ptoggle[0][0] -000000 point: comment=ptoggle[0][1] -000000 point: comment=ptoggle[1][0] -000000 point: comment=ptoggle[1][1] integer cyc; initial cyc=1; -%000000 wire [7:0] cyc_copy = cyc[7:0]; +~000011 wire [7:0] cyc_copy = cyc[7:0]; +000011 point: comment=cyc_copy[0] -000005 point: comment=cyc_copy[1] -000002 point: comment=cyc_copy[2] @@ -89,7 +89,7 @@ .clk (clk), .toggle (toggle)); -%000000 reg [1:0] memory[121:110]; +%000001 reg [1:0] memory[121:110]; -000001 point: comment=memory[110][0] -000000 point: comment=memory[110][1] -000000 point: comment=memory[111][0] @@ -161,7 +161,7 @@ // CHECK_COVER(-1,"top.t.a*",4) // 2 edges * (t.a1 and t.a2) -%000000 input [7:0] cyc_copy; +~000022 input [7:0] cyc_copy; +000022 point: comment=cyc_copy[0] +000010 point: comment=cyc_copy[1] -000004 point: comment=cyc_copy[2] diff --git a/test_regress/t/t_cover_toggle_width.pl b/test_regress/t/t_cover_toggle_width.pl deleted file mode 100755 index f3823a558..000000000 --- a/test_regress/t/t_cover_toggle_width.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_cover_toggle.v"); - -compile( - verilator_flags2 => ['--cc --coverage-toggle --coverage-max-width 1025'], - ); - -execute( - check_finished => 1, - ); - -file_grep("$Self->{obj_dir}/coverage.dat", "largeish"); - -ok(1); -1; diff --git a/test_regress/t/t_cover_toggle_width.py b/test_regress/t/t_cover_toggle_width.py new file mode 100755 index 000000000..5b1711302 --- /dev/null +++ b/test_regress/t/t_cover_toggle_width.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_cover_toggle.v" + +test.compile(verilator_flags2=['--cc --coverage-toggle --coverage-max-width 1025']) + +test.execute() + +test.file_grep(test.obj_dir + "/coverage.dat", "largeish") + +test.passes() diff --git a/test_regress/t/t_cover_unused_bad.pl b/test_regress/t/t_cover_unused_bad.pl deleted file mode 100755 index 348cfc821..000000000 --- a/test_regress/t/t_cover_unused_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --coverage"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cover_unused_bad.py b/test_regress/t/t_cover_unused_bad.py new file mode 100755 index 000000000..6818d8256 --- /dev/null +++ b/test_regress/t/t_cover_unused_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --coverage"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_covergroup_unsup.pl b/test_regress/t/t_covergroup_unsup.pl deleted file mode 100755 index 7284ec30e..000000000 --- a/test_regress/t/t_covergroup_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert --error-limit 1000'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_covergroup_unsup.py b/test_regress/t/t_covergroup_unsup.py new file mode 100755 index 000000000..25f9960b8 --- /dev/null +++ b/test_regress/t/t_covergroup_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, + verilator_flags2=['--assert --error-limit 1000'], + fails=True) + +test.passes() diff --git a/test_regress/t/t_cuse_forward.pl b/test_regress/t/t_cuse_forward.pl deleted file mode 100755 index f17d7f547..000000000 --- a/test_regress/t/t_cuse_forward.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_cuse_forward.py b/test_regress/t/t_cuse_forward.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_cuse_forward.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_cxx_equal_to.pl b/test_regress/t/t_cxx_equal_to.pl deleted file mode 100755 index be05b3b5e..000000000 --- a/test_regress/t/t_cxx_equal_to.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cxx_equal_to.v"); - -compile( - verilator_flags2 => ['--binary --timing --trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cxx_equal_to.py b/test_regress/t/t_cxx_equal_to.py new file mode 100755 index 000000000..3ec7b82b4 --- /dev/null +++ b/test_regress/t/t_cxx_equal_to.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cxx_equal_to.v" + +test.compile(verilator_flags2=['--binary --timing --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_cxx_equal_to.v b/test_regress/t/t_cxx_equal_to.v index e35c8d6d6..09dd11f82 100644 --- a/test_regress/t/t_cxx_equal_to.v +++ b/test_regress/t/t_cxx_equal_to.v @@ -38,7 +38,7 @@ module t; end Test test(.out(out), .in(in), - .clk(clk), .rst(rst)); + .clk(clk), .rst(rst)); endmodule diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out index b9bf11b67..689bab73a 100644 --- a/test_regress/t/t_debug_emitv.out +++ b/test_regress/t/t_debug_emitv.out @@ -297,18 +297,20 @@ module Vt_debug_emitv_t; $display("%g", $acosh(r)); $display("%g", $atanh(r)); force sum = 'sha; - __Vrepeat0 = 'sh2; - while ((__Vrepeat0 > 32'h0)) begin - if ((sum != 'sha)) begin - $stop; + begin : unnamedblk1_1 + integer signed [31:0] __Vrepeat0; + __Vrepeat0 = 'sh2; + while ((__Vrepeat0 > 32'h0)) begin + if ((sum != 'sha)) begin + $stop; + end + __Vrepeat0 = (__Vrepeat0 - 32'h1); end - __Vrepeat0 = (__Vrepeat0 - 32'h1); end release sum; end end /*verilator public_flat_rw @(posedge clk) pubflat*/ - integer signed [31:0] __Vrepeat0; endmodule package Vt_debug_emitv___024unit; class Vt_debug_emitv_Cls; diff --git a/test_regress/t/t_debug_emitv.pl b/test_regress/t/t_debug_emitv.pl deleted file mode 100755 index 4af48a3e3..000000000 --- a/test_regress/t/t_debug_emitv.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions - # Likewise XML - v_flags => ["--lint-only --dumpi-tree 9 --dumpi-V3EmitV 9 --debug-emitv"], - ); - -files_identical(glob_one("$Self->{obj_dir}/$Self->{vm_prefix}_*_width.tree.v"), $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_debug_emitv.py b/test_regress/t/t_debug_emitv.py new file mode 100755 index 000000000..6063ac2c8 --- /dev/null +++ b/test_regress/t/t_debug_emitv.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions + # Likewise XML + v_flags=["--lint-only --dumpi-tree 9 --dumpi-V3EmitV 9 --debug-emitv"]) + +test.files_identical(test.glob_one(test.obj_dir + "/" + test.vm_prefix + "_*_width.tree.v"), + test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_debug_emitv_addrids.pl b/test_regress/t/t_debug_emitv_addrids.pl deleted file mode 100755 index 183f2dd13..000000000 --- a/test_regress/t/t_debug_emitv_addrids.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_debug_emitv.v"); - -lint( - # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions - # Likewise XML - v_flags => ["--lint-only --dumpi-tree 9 --dump-tree-addrids"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_emitv_addrids.py b/test_regress/t/t_debug_emitv_addrids.py new file mode 100755 index 000000000..84634c936 --- /dev/null +++ b/test_regress/t/t_debug_emitv_addrids.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_debug_emitv.v" + +test.lint( + # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions + # Likewise XML + v_flags=["--lint-only --dumpi-tree 9 --dump-tree-addrids"]) + +test.passes() diff --git a/test_regress/t/t_debug_exit_parse.pl b/test_regress/t/t_debug_exit_parse.pl deleted file mode 100755 index 2d41185e7..000000000 --- a/test_regress/t/t_debug_exit_parse.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t_EXAMPLE.v"); - -lint( - verilator_flags2 => ["--debug-exit-parse"], - expect => '--debug-exit-parse', - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_exit_parse.py b/test_regress/t/t_debug_exit_parse.py new file mode 100755 index 000000000..51dded575 --- /dev/null +++ b/test_regress/t/t_debug_exit_parse.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_EXAMPLE.v" + +test.lint(verilator_flags2=["--debug-exit-parse"]) + +test.file_grep(test.compile_log_filename, r'--debug-exit-parse') + +test.passes() diff --git a/test_regress/t/t_debug_fatalsrc_bad.pl b/test_regress/t/t_debug_fatalsrc_bad.pl deleted file mode 100755 index a0cc619db..000000000 --- a/test_regress/t/t_debug_fatalsrc_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (system("gdb --version")) { - skip("No gdb installed"); -} else { - lint( - verilator_flags2 => ["--debug-fatalsrc"], - fails => $Self->{vlt_all}, - expect => -'%Error: Internal Error: .*: --debug-fatal-src -.* See the manual .*', - ); - - ok(1); -} -1; diff --git a/test_regress/t/t_debug_fatalsrc_bad.py b/test_regress/t/t_debug_fatalsrc_bad.py new file mode 100755 index 000000000..9ca95762c --- /dev/null +++ b/test_regress/t/t_debug_fatalsrc_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +if not test.have_gdb: + test.skip("No gdb installed") + +test.lint(verilator_flags2=["--debug-fatalsrc"], fails=test.vlt_all) + +test.file_grep(test.compile_log_filename, r'%Error: Internal Error: .*: --debug-fatal-src') +test.file_grep(test.compile_log_filename, r'See the manual') + +test.passes() diff --git a/test_regress/t/t_debug_fatalsrc_bt_bad.pl b/test_regress/t/t_debug_fatalsrc_bt_bad.pl deleted file mode 100755 index 4471fbf46..000000000 --- a/test_regress/t/t_debug_fatalsrc_bt_bad.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if ($ENV{VERILATOR_TEST_NO_GDB}) { - skip("Skipping due to VERILATOR_TEST_NO_GDB"); -} elsif (system("gdb --version")) { - skip("No gdb installed"); -} else { - lint( - verilator_flags2 => ["--lint-only --debug --gdbbt --debug-fatalsrc"], - fails => 1, - expect => -'%Error: Internal Error: .*: --debug-fatal-src -.*See the manual .* -.*in V3Options::.* -.*%Error: Command Failed.*', - ); - ok(1); -} - -1; diff --git a/test_regress/t/t_debug_fatalsrc_bt_bad.py b/test_regress/t/t_debug_fatalsrc_bt_bad.py new file mode 100755 index 000000000..139ac83b1 --- /dev/null +++ b/test_regress/t/t_debug_fatalsrc_bt_bad.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +if 'VERILATOR_TEST_NO_GDB' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GDB") +if not test.have_gdb: + test.skip("No gdb installed") + +test.lint(verilator_flags2=["--lint-only --debug --gdbbt --debug-fatalsrc"], fails=True) + +test.file_grep(test.compile_log_filename, r'%Error: Internal Error: .*: --debug-fatal-src') +test.file_grep(test.compile_log_filename, r'See the manual') +test.file_grep(test.compile_log_filename, r'in V3Options::') + +test.passes() diff --git a/test_regress/t/t_debug_gate.pl b/test_regress/t/t_debug_gate.pl deleted file mode 100755 index 4867dec5d..000000000 --- a/test_regress/t/t_debug_gate.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # Check we can call dump() on graph, and other things - v_flags => ["--debug --debugi 0 --debugi-V3Graph 9"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_gate.py b/test_regress/t/t_debug_gate.py new file mode 100755 index 000000000..aa28d966e --- /dev/null +++ b/test_regress/t/t_debug_gate.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # Check we can call dump() on graph, and other things + v_flags=["--debug --debugi 0 --debugi-V3Graph 9"]) + +test.passes() diff --git a/test_regress/t/t_debug_graph_test.pl b/test_regress/t/t_debug_graph_test.pl deleted file mode 100755 index 64bc7a996..000000000 --- a/test_regress/t/t_debug_graph_test.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -$ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB"); - -lint( - # Check we can call dump() on graph, and other things - v_flags => ["--lint-only --debug --debugi-V3GraphTest 9 --debug-self-test"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_graph_test.py b/test_regress/t/t_debug_graph_test.py new file mode 100755 index 000000000..d88c7810b --- /dev/null +++ b/test_regress/t/t_debug_graph_test.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +if 'VERILATOR_TEST_NO_GDB' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GDB") + +test.lint( + # Check we can call dump() on graph, and other things + v_flags=["--lint-only --debug --debugi-V3GraphTest 9 --debug-self-test"]) + +test.passes() diff --git a/test_regress/t/t_debug_inputs.pl b/test_regress/t/t_debug_inputs.pl deleted file mode 100755 index 9b9054d09..000000000 --- a/test_regress/t/t_debug_inputs.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - v_flags => ["--debug --debugi 1 -Wno-MULTITOP t/t_debug_inputs_b.v"], - ); - -file_grep("$Self->{obj_dir}/V$Self->{name}__inputs.vpp", qr/module t_debug_inputs /); -file_grep("$Self->{obj_dir}/V$Self->{name}__inputs.vpp", qr/module t_debug_inputs_a /); -file_grep("$Self->{obj_dir}/V$Self->{name}__inputs.vpp", qr/module t_debug_inputs_b /); - -ok(1); -1; diff --git a/test_regress/t/t_debug_inputs.py b/test_regress/t/t_debug_inputs.py new file mode 100755 index 000000000..eb6b583f6 --- /dev/null +++ b/test_regress/t/t_debug_inputs.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(v_flags=["--debug --debugi 1 -Wno-MULTITOP t/t_debug_inputs_b.v"]) + +test.file_grep(test.obj_dir + "/V" + test.name + "__inputs.vpp", r'module t_debug_inputs ') +test.file_grep(test.obj_dir + "/V" + test.name + "__inputs.vpp", r'module t_debug_inputs_a ') +test.file_grep(test.obj_dir + "/V" + test.name + "__inputs.vpp", r'module t_debug_inputs_b ') + +test.passes() diff --git a/test_regress/t/t_debug_sigsegv_bad.pl b/test_regress/t/t_debug_sigsegv_bad.pl deleted file mode 100755 index ad73ac6f9..000000000 --- a/test_regress/t/t_debug_sigsegv_bad.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if ($ENV{VERILATOR_TEST_NO_GDB}) { - skip("Skipping due to VERILATOR_TEST_NO_GDB"); -} elsif (system("gdb --version")) { - skip("No gdb installed"); -} else { - lint( - v_flags => ["--debug-sigsegv"], - fails => 1, - sanitize => 0, - expect => -'%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt -%Error: Command Failed.*', - ); - - ok(1); -} -1; diff --git a/test_regress/t/t_debug_sigsegv_bad.py b/test_regress/t/t_debug_sigsegv_bad.py new file mode 100755 index 000000000..e05e1f470 --- /dev/null +++ b/test_regress/t/t_debug_sigsegv_bad.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +if 'VERILATOR_TEST_NO_GDB' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GDB") +if not test.have_gdb: + test.skip("No gdb installed") + +test.lint(v_flags=["--debug-sigsegv"], fails=True, sanitize=0) + +test.file_grep(test.compile_log_filename, + r'%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt') +test.file_grep(test.compile_log_filename, r'Command Failed') + +test.passes() diff --git a/test_regress/t/t_debug_sigsegv_bt_bad.pl b/test_regress/t/t_debug_sigsegv_bt_bad.pl deleted file mode 100755 index c6dd7a9a4..000000000 --- a/test_regress/t/t_debug_sigsegv_bt_bad.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -if ($ENV{VERILATOR_TEST_NO_GDB}) { - skip("Skipping due to VERILATOR_TEST_NO_GDB"); -} elsif (system("gdb --version")) { - skip("No gdb installed"); -} else { - lint( - verilator_flags2 => ["--lint-only --debug --gdbbt --debug-sigsegv"], - sanitize => 0, - fails => $Self->{vlt_all}, - expect => -'.* -Program received signal SIGSEGV, Segmentation fault. -.*in V3Options::.* -.*%Error: Command Failed.*', - ); - - ok(1); -} -1; diff --git a/test_regress/t/t_debug_sigsegv_bt_bad.py b/test_regress/t/t_debug_sigsegv_bt_bad.py new file mode 100755 index 000000000..c602172b0 --- /dev/null +++ b/test_regress/t/t_debug_sigsegv_bt_bad.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +if 'VERILATOR_TEST_NO_GDB' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GDB") +if not test.have_gdb: + test.skip("No gdb installed") + +test.lint(verilator_flags2=["--lint-only --debug --gdbbt --debug-sigsegv"], + sanitize=0, + fails=test.vlt_all) + +test.file_grep(test.compile_log_filename, r'Program received signal SIGSEGV') +test.file_grep(test.compile_log_filename, r'in V3Options::') + +test.passes() diff --git a/test_regress/t/t_debug_trace.pl b/test_regress/t/t_debug_trace.pl deleted file mode 100755 index e68e695f7..000000000 --- a/test_regress/t/t_debug_trace.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # Check we can call dump() on graph, and other things - v_flags => ["--trace --debug --debugi 0 --debugi-V3Trace 9"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_trace.py b/test_regress/t/t_debug_trace.py new file mode 100755 index 000000000..ecf01e167 --- /dev/null +++ b/test_regress/t/t_debug_trace.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # Check we can call dump() on graph, and other things + v_flags=["--trace --debug --debugi 0 --debugi-V3Trace 9"]) + +test.passes() diff --git a/test_regress/t/t_debug_width.out b/test_regress/t/t_debug_width.out index 5400328e1..c3dcead67 100644 --- a/test_regress/t/t_debug_width.out +++ b/test_regress/t/t_debug_width.out @@ -1,4 +1,4 @@ -%Error: Internal Error: t/t_const_opt.v:534:34: ../V3Ast.cpp:#: widthMismatch detected 'lhsp()->widthMin() != rhsp()->widthMin()' @ ../V3AstNodes.cpp:#OUT:(G/wu32/1) LHS:(G/w32) RHS:(G/wu32/1) +%Error: Internal Error: t/t_opt_const.v:534:34: ../V3Ast.cpp:#: widthMismatch detected 'lhsp()->widthMin() != rhsp()->widthMin()' @ ../V3AstNodes.cpp:#OUT:(G/wu32/1) LHS:(G/w32) RHS:(G/wu32/1) 534 | always_ff @(posedge clkin_data[0], posedge myfirst, posedge mysecond) | ^ ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_debug_width.pl b/test_regress/t/t_debug_width.pl deleted file mode 100755 index b4ae3a10c..000000000 --- a/test_regress/t/t_debug_width.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_const_opt.v"); -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--lint-only", "--debug-width"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_width.py b/test_regress/t/t_debug_width.py new file mode 100755 index 000000000..1b7346266 --- /dev/null +++ b/test_regress/t/t_debug_width.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_opt_const.v" + +test.lint(verilator_flags2=["--lint-only", "--debug-width"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dedupe_clk_gate.pl b/test_regress/t/t_dedupe_clk_gate.pl deleted file mode 100755 index a82d856ba..000000000 --- a/test_regress/t/t_dedupe_clk_gate.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["--no-json-edit-nums", "--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"t.f0.clock_gate.clken_latched","addr":"[^"]*","loc":"\w,44:[^"]*","dtypep":"\(\w+\)",.*"origName":"clken_latched",.*"isLatched":true,.*"dtypeName":"logic"/); - file_grep($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 4); -} - -ok(1); -1; diff --git a/test_regress/t/t_dedupe_clk_gate.py b/test_regress/t/t_dedupe_clk_gate.py new file mode 100755 index 000000000..29a1ccf68 --- /dev/null +++ b/test_regress/t/t_dedupe_clk_gate.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=["--no-json-edit-nums", "--stats"]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.f0.clock_gate.clken_latched","addr":"[^"]*","loc":"\w,44:[^"]*","dtypep":"\(\w+\)",.*"origName":"clken_latched",.*"isLatched":true,.*"dtypeName":"logic"' + ) + test.file_grep(test.stats, r'Optimizations, Gate sigs deduped\s+(\d+)', 4) + +test.passes() diff --git a/test_regress/t/t_dedupe_seq_logic.pl b/test_regress/t/t_dedupe_seq_logic.pl deleted file mode 100755 index e6f7ecd72..000000000 --- a/test_regress/t/t_dedupe_seq_logic.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 6); -} - -ok(1); -1; diff --git a/test_regress/t/t_dedupe_seq_logic.py b/test_regress/t/t_dedupe_seq_logic.py new file mode 100755 index 000000000..32c90c0e9 --- /dev/null +++ b/test_regress/t/t_dedupe_seq_logic.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Gate sigs deduped\s+(\d+)', 6) + +test.passes() diff --git a/test_regress/t/t_delay.pl b/test_regress/t/t_delay.pl deleted file mode 100755 index 3e8a3c919..000000000 --- a/test_regress/t/t_delay.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wno-STMTDLY -Wno-ASSIGNDLY --no-timing'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_delay.py b/test_regress/t/t_delay.py new file mode 100755 index 000000000..231b3a573 --- /dev/null +++ b/test_regress/t/t_delay.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wno-STMTDLY -Wno-ASSIGNDLY --no-timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_delay_compare.pl b/test_regress/t/t_delay_compare.pl deleted file mode 100755 index c8f2eacfe..000000000 --- a/test_regress/t/t_delay_compare.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt}; - -ok(1); -1; diff --git a/test_regress/t/t_delay_compare.py b/test_regress/t/t_delay_compare.py new file mode 100755 index 000000000..1806fa071 --- /dev/null +++ b/test_regress/t/t_delay_compare.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +if not test.vlt: + test.execute() + +test.passes() diff --git a/test_regress/t/t_delay_incr.pl b/test_regress/t/t_delay_incr.pl deleted file mode 100755 index ff38a8470..000000000 --- a/test_regress/t/t_delay_incr.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --no-timing -Wno-STMTDLY -Wno-ASSIGNDLY'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_delay_incr.py b/test_regress/t/t_delay_incr.py new file mode 100755 index 000000000..621069809 --- /dev/null +++ b/test_regress/t/t_delay_incr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --no-timing -Wno-STMTDLY -Wno-ASSIGNDLY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_delay_incr_timing.pl b/test_regress/t/t_delay_incr_timing.pl deleted file mode 100755 index d60b1c8bd..000000000 --- a/test_regress/t/t_delay_incr_timing.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 10e-7 / 10e-9; - -top_filename("t/t_delay_incr.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ['--binary --timing -Wno-ZERODLY'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_delay_incr_timing.py b/test_regress/t/t_delay_incr_timing.py new file mode 100755 index 000000000..eaed68537 --- /dev/null +++ b/test_regress/t/t_delay_incr_timing.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_delay_incr.v" +test.main_time_multiplier = 10e-7 / 10e-9 + +test.compile(timing_loop=True, verilator_flags2=['--binary --timing -Wno-ZERODLY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_delay_stmtdly_bad.pl b/test_regress/t/t_delay_stmtdly_bad.pl deleted file mode 100755 index 59820b3fb..000000000 --- a/test_regress/t/t_delay_stmtdly_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_delay.v"); - -lint( - verilator_flags2 => ['--no-timing -Wall -Wno-DECLFILENAME'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_delay_stmtdly_bad.py b/test_regress/t/t_delay_stmtdly_bad.py new file mode 100755 index 000000000..a542f3311 --- /dev/null +++ b/test_regress/t/t_delay_stmtdly_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_delay.v" + +test.lint(verilator_flags2=['--no-timing -Wall -Wno-DECLFILENAME'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_delay_timing.pl b/test_regress/t/t_delay_timing.pl deleted file mode 100755 index 9514aafb4..000000000 --- a/test_regress/t/t_delay_timing.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 10e-7 / 10e-9; - -top_filename("t/t_delay.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ['--timing -Wno-ZERODLY'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_delay_timing.py b/test_regress/t/t_delay_timing.py new file mode 100755 index 000000000..bcaa61195 --- /dev/null +++ b/test_regress/t/t_delay_timing.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_delay.v" +test.main_time_multiplier = 10e-7 / 10e-9 + +test.compile(timing_loop=True, verilator_flags2=['--timing -Wno-ZERODLY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_delay_var.pl b/test_regress/t/t_delay_var.pl deleted file mode 100755 index c8f2eacfe..000000000 --- a/test_regress/t/t_delay_var.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt}; - -ok(1); -1; diff --git a/test_regress/t/t_delay_var.py b/test_regress/t/t_delay_var.py new file mode 100755 index 000000000..1806fa071 --- /dev/null +++ b/test_regress/t/t_delay_var.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +if not test.vlt: + test.execute() + +test.passes() diff --git a/test_regress/t/t_depth_flop.pl b/test_regress/t/t_depth_flop.pl deleted file mode 100755 index 8b4ad07ec..000000000 --- a/test_regress/t/t_depth_flop.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); # Note issue shows up with --threads - -compile( - verilator_flags2 => ['--compiler clang -Wno-UNOPTTHREADS'], - threads => 2 - ); - -ok(1); -1; diff --git a/test_regress/t/t_depth_flop.py b/test_regress/t/t_depth_flop.py new file mode 100755 index 000000000..a38d51df9 --- /dev/null +++ b/test_regress/t/t_depth_flop.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') # Note issue shows up with --threads + +test.compile(verilator_flags2=['--compiler clang -Wno-UNOPTTHREADS'], threads=2) + +test.passes() diff --git a/test_regress/t/t_detectarray_1.pl b/test_regress/t/t_detectarray_1.pl deleted file mode 100755 index 973a951a0..000000000 --- a/test_regress/t/t_detectarray_1.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_detectarray_1.py b/test_regress/t/t_detectarray_1.py new file mode 100755 index 000000000..c37bc018e --- /dev/null +++ b/test_regress/t/t_detectarray_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_detectarray_2.pl b/test_regress/t/t_detectarray_2.pl deleted file mode 100755 index 973a951a0..000000000 --- a/test_regress/t/t_detectarray_2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_detectarray_2.py b/test_regress/t/t_detectarray_2.py new file mode 100755 index 000000000..c37bc018e --- /dev/null +++ b/test_regress/t/t_detectarray_2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_detectarray_3.pl b/test_regress/t/t_detectarray_3.pl deleted file mode 100755 index 4294291d7..000000000 --- a/test_regress/t/t_detectarray_3.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT -Wno-WIDTH"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_detectarray_3.py b/test_regress/t/t_detectarray_3.py new file mode 100755 index 000000000..bf411aade --- /dev/null +++ b/test_regress/t/t_detectarray_3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT -Wno-WIDTH"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dfg_3676.pl b/test_regress/t/t_dfg_3676.pl deleted file mode 100755 index 84ae125be..000000000 --- a/test_regress/t/t_dfg_3676.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_3676.py b/test_regress/t/t_dfg_3676.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_3676.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_3679.pl b/test_regress/t/t_dfg_3679.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_dfg_3679.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_3679.py b/test_regress/t/t_dfg_3679.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dfg_3679.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dfg_3726.pl b/test_regress/t/t_dfg_3726.pl deleted file mode 100755 index 84ae125be..000000000 --- a/test_regress/t/t_dfg_3726.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_3726.py b/test_regress/t/t_dfg_3726.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_3726.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_3817.pl b/test_regress/t/t_dfg_3817.pl deleted file mode 100755 index 31e4367f7..000000000 --- a/test_regress/t/t_dfg_3817.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_3817.py b/test_regress/t/t_dfg_3817.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_3817.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_3872.pl b/test_regress/t/t_dfg_3872.pl deleted file mode 100755 index 31e4367f7..000000000 --- a/test_regress/t/t_dfg_3872.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_3872.py b/test_regress/t/t_dfg_3872.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_3872.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_4104.pl b/test_regress/t/t_dfg_4104.pl deleted file mode 100755 index 32bdf873d..000000000 --- a/test_regress/t/t_dfg_4104.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_4104.py b/test_regress/t/t_dfg_4104.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_4104.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_4943.pl b/test_regress/t/t_dfg_4943.pl deleted file mode 100755 index 019703eb0..000000000 --- a/test_regress/t/t_dfg_4943.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_4943.py b/test_regress/t/t_dfg_4943.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_4943.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_circular.pl b/test_regress/t/t_dfg_circular.pl deleted file mode 100755 index a4e59f8b5..000000000 --- a/test_regress/t/t_dfg_circular.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--dumpi-dfg 9"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_circular.py b/test_regress/t/t_dfg_circular.py new file mode 100755 index 000000000..ce29ad309 --- /dev/null +++ b/test_regress/t/t_dfg_circular.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--dumpi-dfg 9"]) + +test.passes() diff --git a/test_regress/t/t_dfg_inline_forced.pl b/test_regress/t/t_dfg_inline_forced.pl deleted file mode 100755 index 3d5530ff3..000000000 --- a/test_regress/t/t_dfg_inline_forced.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_inline_forced.py b/test_regress/t/t_dfg_inline_forced.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_inline_forced.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.pl b/test_regress/t/t_dfg_multidriver_dfg_bad.pl deleted file mode 100755 index 9325bb095..000000000 --- a/test_regress/t/t_dfg_multidriver_dfg_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.py b/test_regress/t/t_dfg_multidriver_dfg_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_dfg_multidriver_dfg_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dfg_multidriver_non_dfg.pl b/test_regress/t/t_dfg_multidriver_non_dfg.pl deleted file mode 100755 index 84ae125be..000000000 --- a/test_regress/t/t_dfg_multidriver_non_dfg.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_multidriver_non_dfg.py b/test_regress/t/t_dfg_multidriver_non_dfg.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_multidriver_non_dfg.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_peephole.pl b/test_regress/t/t_dfg_peephole.pl deleted file mode 100755 index 5838a8ff3..000000000 --- a/test_regress/t/t_dfg_peephole.pl +++ /dev/null @@ -1,100 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - $Self->{sim_time} = 2000000; - - # Read optimizations - my @optimizations = (); - { - my $hdrFile = "../src/V3DfgPeephole.h"; - my $hdrFh = IO::File->new("<$hdrFile") or error("$! $hdrFile"); - my $prevOpt = ""; - my $lineno = 0; - while (defined(my $line = $hdrFh->getline)) { - $lineno = $lineno + 1; - next if $line !~ /^\s*_FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY\(macro, (\w+)\)/; - my $opt = $1; - error("$hdrFile:$linenno: '$opt; is not in sorted order") if $prevOpt gt $opt; - $prevOpt = $opt; - push @optimizations, $opt; - } - error("no optimizations defined in $hdrFile") if scalar @optimizations == 0; - } - - # Generate the equivalence checks and declaration boilerplate - my $rdFile = "$Self->{top_filename}"; - my $plistFile = "$Self->{obj_dir}/portlist.vh"; - my $pdeclFile = "$Self->{obj_dir}/portdecl.vh"; - my $checkFile = "$Self->{obj_dir}/checks.h"; - my $rdFh = IO::File->new("<$rdFile") or error("$! $rdFile"); - my $plistFh = IO::File->new(">$plistFile") or error("$! $plistFile"); - my $pdeclFh = IO::File->new(">$pdeclFile") or error("$! $pdeclFile"); - my $checkFh = IO::File->new(">$checkFile") or error("$! $checkFile"); - while (defined(my $line = $rdFh->getline)) { - next if $line !~ /^\s*.*`signal\((\w+),/; - my $signal = $1; - print $plistFh "$signal,\n"; - print $pdeclFh "output $signal;\n"; - print $checkFh "if (ref.$signal != opt.$signal) {\n"; - print $checkFh " std::cout << \"Mismatched $signal\" << std::endl;\n"; - print $checkFh " std::cout << \"Ref: 0x\" << std::hex << (ref.$signal + 0) << std::endl;\n"; - print $checkFh " std::cout << \"Opt: 0x\" << std::hex << (opt.$signal + 0) << std::endl;\n"; - print $checkFh " std::exit(1);\n"; - print $checkFh "}\n"; - } - close $rdFile; - close $wrFile; - - - # Compile un-optimized - compile( - verilator_flags2 => ["--stats", "--build", "-fno-dfg", "+incdir+$Self->{obj_dir}", - "-Mdir", "$Self->{obj_dir}/obj_ref", "--prefix", "Vref"], - ); - - # Compile optimized - also builds executable - compile( - verilator_flags2 => ["--stats", "--build", "--exe", "+incdir+$Self->{obj_dir}", - "-Mdir", "$Self->{obj_dir}/obj_opt", "--prefix", "Vopt", - "-fno-const-before-dfg", # Otherwise V3Const makes testing painful - "--dump-dfg", # To fill code coverage - "-CFLAGS \"-I .. -I ../obj_ref\"", - "../obj_ref/Vref__ALL.a", - "../../t/$Self->{name}.cpp"], - ); - - # Execute test to check equivalence - execute( - executable => "$Self->{obj_dir}/obj_opt/Vopt", - check_finished => 1, - ); - - sub check { - my $name = shift; - $name = lc $name; - $name =~ s/_/ /g; - file_grep("$Self->{obj_dir}/obj_opt/Vopt__stats.txt", qr/DFG\s+(pre|post) inline Peephole, ${name}\s+([1-9]\d*)/i); - } - - # Check all optimizations defined in - foreach my $opt (@optimizations) { - check($opt); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dfg_peephole.py b/test_regress/t/t_dfg_peephole.py new file mode 100755 index 000000000..dcb2cae87 --- /dev/null +++ b/test_regress/t/t_dfg_peephole.py @@ -0,0 +1,106 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.sim_time = 2000000 + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +# Read optimizations +optimizations = [] + +hdrFile = "../src/V3DfgPeephole.h" +with open(hdrFile, 'r', encoding="utf8") as hdrFh: + prevOpt = "" + lineno = 0 + for line in hdrFh: + lineno += 1 + m = re.search(r'^\s*_FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY\(macro, (\w+)\)', line) + if not m: + continue + opt = m.group(1) + if prevOpt > opt: + test.error(hdrFile + ":" + str(lineno) + ": '" + opt + "; is not in sorted order") + prevOpt = opt + optimizations.append(opt) + +if len(optimizations) < 1: + test.error("no optimizations defined in " + hdrFile) + +# Generate the equivalence checks and declaration boilerplate +rdFile = test.top_filename +plistFile = test.obj_dir + "/portlist.vh" +pdeclFile = test.obj_dir + "/portdecl.vh" +checkFile = test.obj_dir + "/checks.h" +with open(rdFile, 'r', encoding="utf8") as rdFh, \ + open(plistFile, 'w', encoding="utf8") as plistFh, \ + open(pdeclFile, 'w', encoding="utf8") as pdeclFh, \ + open(checkFile, 'w', encoding="utf8") as checkFh: + for line in rdFh: + m = re.search(r'^\s*.*`signal\((\w+),', line) + if not m: + continue + sig = m.group(1) + plistFh.write(sig + ",\n") + pdeclFh.write("output " + sig + ";\n") + checkFh.write("if (ref." + sig + " != opt." + sig + ") {\n") + checkFh.write(" std::cout << \"Mismatched " + sig + "\" << std::endl;\n") + checkFh.write(" std::cout << \"Ref: 0x\" << std::hex << (ref." + sig + + " + 0) << std::endl;\n") + checkFh.write(" std::cout << \"Opt: 0x\" << std::hex << (opt." + sig + + " + 0) << std::endl;\n") + checkFh.write(" std::exit(1);\n") + checkFh.write("}\n") + +# Compile un-optimized +test.compile(verilator_flags2=[ + "--stats", + "--build", + "-fno-dfg", + "+incdir+" + test.obj_dir, + "-Mdir", test.obj_dir + "/obj_ref", + "--prefix", "Vref" +]) # yapf:disable + +# Compile optimized - also builds executable +test.compile(verilator_flags2=[ + "--stats", + "--build", + "--exe", + "+incdir+" + test.obj_dir, + "-Mdir", test.obj_dir + "/obj_opt", + "--prefix", "Vopt", + "-fno-const-before-dfg", # Otherwise V3Const makes testing painful + "--dump-dfg", # To fill code coverage + "-CFLAGS \"-I .. -I ../obj_ref\"", + "../obj_ref/Vref__ALL.a", + "../../t/" + test.name + ".cpp" +]) # yapf:disable + +# Execute test to check equivalence +test.execute(executable=test.obj_dir + "/obj_opt/Vopt") + + +def check(name): + name = name.lower() + name = re.sub(r'_', ' ', name) + test.file_grep(test.obj_dir + "/obj_opt/Vopt__stats.txt", + r'DFG\s+(pre|post) inline Peephole, ' + name + r'\s+([1-9]\d*)') + + +# Check all optimizations defined in +for opt in optimizations: + check(opt) + +test.passes() diff --git a/test_regress/t/t_dfg_peephole.v b/test_regress/t/t_dfg_peephole.v index b6745ef93..a453cc51a 100644 --- a/test_regress/t/t_dfg_peephole.v +++ b/test_regress/t/t_dfg_peephole.v @@ -7,11 +7,11 @@ `define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr module t ( -`include "portlist.vh" // Boilerplate generated by t_dfg_peephole.pl +`include "portlist.vh" // Boilerplate generated by t_dfg_peephole.py rand_a, rand_b, srand_a, srand_b ); -`include "portdecl.vh" // Boilerplate generated by t_dfg_peephole.pl +`include "portdecl.vh" // Boilerplate generated by t_dfg_peephole.py input rand_a; input rand_b; diff --git a/test_regress/t/t_dfg_regularize_circular.pl b/test_regress/t/t_dfg_regularize_circular.pl deleted file mode 100755 index 3d5530ff3..000000000 --- a/test_regress/t/t_dfg_regularize_circular.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_regularize_circular.py b/test_regress/t/t_dfg_regularize_circular.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_regularize_circular.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_regularize_driver_of_sc_var.pl b/test_regress/t/t_dfg_regularize_driver_of_sc_var.pl deleted file mode 100755 index 9158675cc..000000000 --- a/test_regress/t/t_dfg_regularize_driver_of_sc_var.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--sc"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_regularize_driver_of_sc_var.py b/test_regress/t/t_dfg_regularize_driver_of_sc_var.py new file mode 100755 index 000000000..01c227501 --- /dev/null +++ b/test_regress/t/t_dfg_regularize_driver_of_sc_var.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--sc"]) + +test.passes() diff --git a/test_regress/t/t_dfg_stats_patterns_post_inline.pl b/test_regress/t/t_dfg_stats_patterns_post_inline.pl deleted file mode 100755 index d417bbaee..000000000 --- a/test_regress/t/t_dfg_stats_patterns_post_inline.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_dfg_stats_patterns.v"); - -compile( - verilator_flags2 => ["--stats --no-skip-identical -fno-dfg-pre-inline"], - ); - -my $f = glob_one("$Self->{obj_dir}/$Self->{vm_prefix}__stats_dfg_patterns*"); -files_identical($f, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_stats_patterns_post_inline.py b/test_regress/t/t_dfg_stats_patterns_post_inline.py new file mode 100755 index 000000000..0813e38de --- /dev/null +++ b/test_regress/t/t_dfg_stats_patterns_post_inline.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_dfg_stats_patterns.v" + +test.compile(verilator_flags2=["--stats --no-skip-identical -fno-dfg-pre-inline"]) + +fn = test.glob_one(test.obj_dir + "/" + test.vm_prefix + "__stats_dfg_patterns*") +test.files_identical(fn, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dfg_stats_patterns_pre_inline.pl b/test_regress/t/t_dfg_stats_patterns_pre_inline.pl deleted file mode 100755 index c457e5470..000000000 --- a/test_regress/t/t_dfg_stats_patterns_pre_inline.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_dfg_stats_patterns.v"); - -compile( - verilator_flags2 => ["--stats --no-skip-identical -fno-dfg-post-inline"], - ); - -my $f = glob_one("$Self->{obj_dir}/$Self->{vm_prefix}__stats_dfg_patterns*"); -files_identical($f, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_stats_patterns_pre_inline.py b/test_regress/t/t_dfg_stats_patterns_pre_inline.py new file mode 100755 index 000000000..4fac195a5 --- /dev/null +++ b/test_regress/t/t_dfg_stats_patterns_pre_inline.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_dfg_stats_patterns.v" + +test.compile(verilator_flags2=["--stats --no-skip-identical -fno-dfg-post-inline"]) + +fn = test.glob_one(test.obj_dir + "/" + test.vm_prefix + "__stats_dfg_patterns*") +test.files_identical(fn, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dfg_unhandled.pl b/test_regress/t/t_dfg_unhandled.pl deleted file mode 100755 index f37a397d3..000000000 --- a/test_regress/t/t_dfg_unhandled.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -file_grep($Self->{stats}, qr/Optimizations, DFG pre inline Ast2Dfg, non-representable \(impure\)\s+(\d+)/i, 1); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_unhandled.py b/test_regress/t/t_dfg_unhandled.py new file mode 100755 index 000000000..f60c4d682 --- /dev/null +++ b/test_regress/t/t_dfg_unhandled.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--stats"]) + +test.file_grep(test.stats, + r'Optimizations, DFG pre inline Ast2Dfg, non-representable \(impure\)\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_difftree.pl b/test_regress/t/t_difftree.pl deleted file mode 100755 index da5f5e571..000000000 --- a/test_regress/t/t_difftree.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -if (!-x "$ENV{VERILATOR_ROOT}/bin/verilator_difftree") { - skip("No verilator_difftree available") -} -else { - run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_difftree" - . " $Self->{t_dir}/t_difftree.a.tree $Self->{t_dir}/t_difftree.b.tree > diff.log"], - check_finished => 0); - - files_identical("$Self->{obj_dir}/diff.log", $Self->{golden_filename}, 'logfile'); -} - -ok(1); - -1; diff --git a/test_regress/t/t_difftree.py b/test_regress/t/t_difftree.py new file mode 100755 index 000000000..38ba0f004 --- /dev/null +++ b/test_regress/t/t_difftree.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +if not os.path.exists(os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree"): + test.skip("No verilator_difftree available") + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree", + test.t_dir + "/t_difftree.a.tree", test.t_dir + "/t_difftree.b.tree > diff.log" +], + check_finished=False) + +test.files_identical(test.obj_dir + "/diff.log", test.golden_filename, 'logfile') + +test.passes() diff --git a/test_regress/t/t_disable.pl b/test_regress/t/t_disable.pl deleted file mode 100755 index e68534982..000000000 --- a/test_regress/t/t_disable.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--lint-only --timing'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable.py b/test_regress/t/t_disable.py new file mode 100755 index 000000000..cf9cba66e --- /dev/null +++ b/test_regress/t/t_disable.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only --timing'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_disable_fork1.pl b/test_regress/t/t_disable_fork1.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_disable_fork1.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable_fork1.py b/test_regress/t/t_disable_fork1.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_disable_fork1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_disable_fork2.pl b/test_regress/t/t_disable_fork2.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_disable_fork2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable_fork2.py b/test_regress/t/t_disable_fork2.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_disable_fork2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_disable_fork3.pl b/test_regress/t/t_disable_fork3.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_disable_fork3.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable_fork3.py b/test_regress/t/t_disable_fork3.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_disable_fork3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_disable_fork_notiming.pl b/test_regress/t/t_disable_fork_notiming.pl deleted file mode 100755 index 4994b95cb..000000000 --- a/test_regress/t/t_disable_fork_notiming.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - expect_filename => $Self->{golden_filename}, - v_flags2 => ["--no-timing"], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable_fork_notiming.py b/test_regress/t/t_disable_fork_notiming.py new file mode 100755 index 000000000..01b7497f3 --- /dev/null +++ b/test_regress/t/t_disable_fork_notiming.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(expect_filename=test.golden_filename, v_flags2=["--no-timing"], fails=True) + +test.passes() diff --git a/test_regress/t/t_disable_iff_multi_bad.pl b/test_regress/t/t_disable_iff_multi_bad.pl deleted file mode 100755 index 7fdfc93e0..000000000 --- a/test_regress/t/t_disable_iff_multi_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable_iff_multi_bad.py b/test_regress/t/t_disable_iff_multi_bad.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_disable_iff_multi_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display.out b/test_regress/t/t_display.out index 0c5fe4274..dee744f90 100644 --- a/test_regress/t/t_display.out +++ b/test_regress/t/t_display.out @@ -65,6 +65,7 @@ assoc_c='{} [0] hello, from a very long string. Percent %s are literally substituted in. hello, from a concatenated string. hello, from a concatenated format string [0]. +two 2 args 3with commas extra argument: 0 0 : pre argument after empty: > < diff --git a/test_regress/t/t_display.pl b/test_regress/t/t_display.pl deleted file mode 100755 index 88b7809fc..000000000 --- a/test_regress/t/t_display.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_display.py b/test_regress/t/t_display.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display.v b/test_regress/t/t_display.v index 2cf490fc2..c1c5634fd 100644 --- a/test_regress/t/t_display.v +++ b/test_regress/t/t_display.v @@ -164,6 +164,7 @@ module t; "hel", "lo, fr", "om a very long string. Percent %s are literally substituted in."); $display("hel", "lo, fr", "om a concatenated string."); $write("hel", "lo, fr", "om a concatenated format string [%0t].\n", $time); + $display("two %d", 2, " args %d", 3, "with commas"); $display("extra argument: ", $time); $display($time,, ": pre argument",, "after"); $display("empty: >%s<", ""); diff --git a/test_regress/t/t_display_bad.pl b/test_regress/t/t_display_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_display_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_bad.py b/test_regress/t/t_display_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_display_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_concat.pl b/test_regress/t/t_display_concat.pl deleted file mode 100755 index 03b63c1a0..000000000 --- a/test_regress/t/t_display_concat.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_concat.py b/test_regress/t/t_display_concat.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_concat2.pl b/test_regress/t/t_display_concat2.pl deleted file mode 100755 index 1576259ea..000000000 --- a/test_regress/t/t_display_concat2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_concat2.py b/test_regress/t/t_display_concat2.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_concat2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_cwide_bad.pl b/test_regress/t/t_display_cwide_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_display_cwide_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_cwide_bad.py b/test_regress/t/t_display_cwide_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_display_cwide_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_esc_bad.pl b/test_regress/t/t_display_esc_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_display_esc_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_esc_bad.py b/test_regress/t/t_display_esc_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_display_esc_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_impure.pl b/test_regress/t/t_display_impure.pl deleted file mode 100755 index 576ac0d3d..000000000 --- a/test_regress/t/t_display_impure.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_impure.py b/test_regress/t/t_display_impure.py new file mode 100755 index 000000000..90d5ab862 --- /dev/null +++ b/test_regress/t/t_display_impure.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_io.pl b/test_regress/t/t_display_io.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_display_io.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_io.py b/test_regress/t/t_display_io.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_display_io.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_display_l.pl b/test_regress/t/t_display_l.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_display_l.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_l.py b/test_regress/t/t_display_l.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_display_l.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_display_mcd.pl b/test_regress/t/t_display_mcd.pl deleted file mode 100755 index 88b7809fc..000000000 --- a/test_regress/t/t_display_mcd.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_display_mcd.py b/test_regress/t/t_display_mcd.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_mcd.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_merge.pl b/test_regress/t/t_display_merge.pl deleted file mode 100755 index 0de4e1ed6..000000000 --- a/test_regress/t/t_display_merge.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -file_grep("$Self->{obj_dir}/$Self->{vm_prefix}__stats.txt", - qr/Node count, DISPLAY \s+ 44 \s+ 27 \s+ 27 \s+ 6/); - -ok(1); -1; diff --git a/test_regress/t/t_display_merge.py b/test_regress/t/t_display_merge.py new file mode 100755 index 000000000..03f439c26 --- /dev/null +++ b/test_regress/t/t_display_merge.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +test.execute(expect_filename=test.golden_filename) + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "__stats.txt", + r'Node count, DISPLAY \s+ 44 \s+ 27 \s+ 27 \s+ 6') + +test.passes() diff --git a/test_regress/t/t_display_noopt.pl b/test_regress/t/t_display_noopt.pl deleted file mode 100755 index ced4aa8a5..000000000 --- a/test_regress/t/t_display_noopt.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_display.v"); -golden_filename("t/t_display.out"); - -compile( - verilator_flags2 => ["-O0"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_display_noopt.py b/test_regress/t/t_display_noopt.py new file mode 100755 index 000000000..9b159b6ba --- /dev/null +++ b/test_regress/t/t_display_noopt.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_display.v" +test.golden_filename = "t/t_display.out" + +test.compile(verilator_flags2=["-O0"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_qqq.pl b/test_regress/t/t_display_qqq.pl deleted file mode 100755 index 3db494e80..000000000 --- a/test_regress/t/t_display_qqq.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_display_qqq.py b/test_regress/t/t_display_qqq.py new file mode 100755 index 000000000..97abb660e --- /dev/null +++ b/test_regress/t/t_display_qqq.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_real.pl b/test_regress/t/t_display_real.pl deleted file mode 100755 index 1576259ea..000000000 --- a/test_regress/t/t_display_real.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_real.py b/test_regress/t/t_display_real.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_real.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_real_noopt.pl b/test_regress/t/t_display_real_noopt.pl deleted file mode 100755 index a41a102e4..000000000 --- a/test_regress/t/t_display_real_noopt.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_display_real.v"); -golden_filename("t/t_display_real.out"); - -compile( - verilator_flags2 => ["-O0"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_real_noopt.py b/test_regress/t/t_display_real_noopt.py new file mode 100755 index 000000000..ad0f55e3e --- /dev/null +++ b/test_regress/t/t_display_real_noopt.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_display_real.v" +test.golden_filename = "t/t_display_real.out" + +test.compile(verilator_flags2=["-O0"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_realtime.pl b/test_regress/t/t_display_realtime.pl deleted file mode 100755 index 4e42b8db0..000000000 --- a/test_regress/t/t_display_realtime.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_display_realtime.py b/test_regress/t/t_display_realtime.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_display_realtime.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_display_recurse.pl b/test_regress/t/t_display_recurse.pl deleted file mode 100755 index 6e4e9e231..000000000 --- a/test_regress/t/t_display_recurse.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_recurse.py b/test_regress/t/t_display_recurse.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_recurse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_signed.pl b/test_regress/t/t_display_signed.pl deleted file mode 100755 index 1576259ea..000000000 --- a/test_regress/t/t_display_signed.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_signed.py b/test_regress/t/t_display_signed.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_signed_noopt.pl b/test_regress/t/t_display_signed_noopt.pl deleted file mode 100755 index e113d374d..000000000 --- a/test_regress/t/t_display_signed_noopt.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_display_signed.v"); -golden_filename("t/t_display_signed.out"); - -compile( - verilator_flags2 => ["-O0"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_signed_noopt.py b/test_regress/t/t_display_signed_noopt.py new file mode 100755 index 000000000..e80552d48 --- /dev/null +++ b/test_regress/t/t_display_signed_noopt.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_display_signed.v" +test.golden_filename = "t/t_display_signed.out" + +test.compile(verilator_flags2=["-O0"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_string.pl b/test_regress/t/t_display_string.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_display_string.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_string.py b/test_regress/t/t_display_string.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_time.pl b/test_regress/t/t_display_time.pl deleted file mode 100755 index 1576259ea..000000000 --- a/test_regress/t/t_display_time.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_time.py b/test_regress/t/t_display_time.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_time.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_type_bad.pl b/test_regress/t/t_display_type_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_display_type_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_type_bad.py b/test_regress/t/t_display_type_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_display_type_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_wide.pl b/test_regress/t/t_display_wide.pl deleted file mode 100755 index 1576259ea..000000000 --- a/test_regress/t/t_display_wide.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_wide.py b/test_regress/t/t_display_wide.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_wide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dist_attributes/mt_disabled.h b/test_regress/t/t_dist_attributes/mt_disabled.h index e47a7be8a..a39202444 100644 --- a/test_regress/t/t_dist_attributes/mt_disabled.h +++ b/test_regress/t/t_dist_attributes/mt_disabled.h @@ -17,8 +17,6 @@ #include "verilatedos.h" -#include "V3ThreadSafety.h" - void unannotatedMtDisabledFunctionBad(); // Duplicate to check that every declaration is reported diff --git a/test_regress/t/t_dist_attributes/mt_enabled.h b/test_regress/t/t_dist_attributes/mt_enabled.h index b13f0f9e8..045b80067 100644 --- a/test_regress/t/t_dist_attributes/mt_enabled.h +++ b/test_regress/t/t_dist_attributes/mt_enabled.h @@ -282,7 +282,7 @@ public: class ConstructorCallsUnsafeLocalFunction { public: - void unsafe_function() VL_MT_UNSAFE{}; + void unsafe_function() VL_MT_UNSAFE {}; ConstructorCallsUnsafeLocalFunction() { unsafe_function(); } }; class ConstructorCallsStaticFunctionNoAnnotation { @@ -367,6 +367,27 @@ public: ConstructorCallsGlobalObjectMember() { dummyGlobalVar.d.dummy_function2(); } }; +namespace VirtualInheritance { +struct Base1 { + virtual int func(int a, int b) const VL_PURE = 0; + virtual ~Base1() = default; +}; + +struct Base2 { + virtual int func() const VL_PURE = 0; + virtual ~Base2() = default; +}; + +struct Derived final : public Base1, Base2 { + int func(int a, int b) const override VL_PURE { return notPure(); } + int func() const override VL_PURE { return notPure(); } + static int notPure() { + static int s_counter; + return ++s_counter; + } +}; +} //namespace VirtualInheritance + class TestClassConstructor { void safe_function_unsafe_constructor_bad() VL_MT_SAFE { ConstructorCallsUnsafeLocalFunction f{}; @@ -408,6 +429,7 @@ class TestClassConstructor { void safe_function_calls_constructor_global_object_member_bad() VL_MT_STABLE { ConstructorCallsGlobalObjectMember f{}; } + void virtual_function_mismatch() { VirtualInheritance::Derived pd{}; } }; #endif // T_DIST_ATTRIBUTES_MT_ENABLED_H_ diff --git a/test_regress/t/t_dist_attributes_bad.out b/test_regress/t/t_dist_attributes_bad.out index e5cfe9c4a..e9514927b 100644 --- a/test_regress/t/t_dist_attributes_bad.out +++ b/test_regress/t/t_dist_attributes_bad.out @@ -1,1209 +1,1186 @@ %Error: "TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [mt_safe] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_safe] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [mt_safe_postinit] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, mt_safe_postinit, pure] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_safe_postinit] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, mt_safe_postinit, pure] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_START(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [mt_start] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_start, mt_safe, pure] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_start, requires] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_start, mt_safe, pure, requires] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, mt_unsafe, pure] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, mt_unsafe, pure] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_PURE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [pure] TestClass::cm_ae_VL_PURE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure] TestClass::cm_ae_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [pure] TestClass::cm_ae_VL_PURE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure] TestClass::cm_ae_VL_PURE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_RELEASE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:204: [requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.cpp:155: [mt_safe] TestClass::cm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:155: [mt_safe] TestClass::cm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.cpp:155: [mt_start] TestClass::cm_test_caller_smethod_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:155: [mt_start, requires] TestClass::cm_test_caller_smethod_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.cpp:155: [pure] TestClass::cm_test_caller_smethod_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [] TestClass::cm_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_safe] TestClass::cm_au_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_safe_postinit] TestClass::cm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_start] TestClass::cm_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [requires] TestClass::cm_au_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [] TestClass::cm_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_safe] TestClass::cm_aa_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_safe_postinit] TestClass::cm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_start] TestClass::cm_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [requires] TestClass::cm_aa_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_safe] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_safe_postinit] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_start] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:155: [pure] TestClass::cm_test_caller_smethod_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [] TestClass::cm_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_safe] TestClass::cm_au_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_safe_postinit] TestClass::cm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_start, requires] TestClass::cm_au_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [requires] TestClass::cm_au_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [] TestClass::cm_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_safe] TestClass::cm_aa_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_safe_postinit] TestClass::cm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_start, requires] TestClass::cm_aa_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [requires] TestClass::cm_aa_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_safe] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_safe_postinit] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_start, requires] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:212: [mt_safe] TestClass::cm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:212: [mt_safe] TestClass::cm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.h:212: [mt_start] TestClass::cm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:212: [mt_start, requires] TestClass::cm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.h:212: [pure] TestClass::cm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [] TestClass::cm_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_safe] TestClass::cm_au_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_safe_postinit] TestClass::cm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_start] TestClass::cm_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:191: [requires] TestClass::cm_au_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [] TestClass::cm_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_safe] TestClass::cm_aa_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_safe_postinit] TestClass::cm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_start] TestClass::cm_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:199: [requires] TestClass::cm_aa_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_safe] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_safe_postinit] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_start] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:204: [requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:212: [pure] TestClass::cm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [] TestClass::cm_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_safe] TestClass::cm_au_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_safe_postinit] TestClass::cm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_start, requires] TestClass::cm_au_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:191: [requires] TestClass::cm_au_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [] TestClass::cm_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_safe] TestClass::cm_aa_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_safe_postinit] TestClass::cm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_start, requires] TestClass::cm_aa_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:199: [requires] TestClass::cm_aa_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_safe] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_safe_postinit] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_start, requires] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:204: [requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [acquire] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [acquire] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [acquire] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [acquire] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [excludes] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [excludes] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [mt_safe] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [mt_safe] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [excludes] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [excludes] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [mt_safe_postinit] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [mt_safe_postinit] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_START(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [mt_start] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [mt_start, requires] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [mt_unsafe] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [mt_unsafe] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [mt_unsafe_one] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [mt_unsafe_one] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_PURE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_PURE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [pure] TestClass::cm_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_PURE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [pure] TestClass::cm_ua_VL_PURE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_RELEASE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [release] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [release] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [release] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [release] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:137: [requires] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:137: [requires] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::guarded_by_test_fail()" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:269: [mt_safe] TestClass::guarded_by_test_fail() -t/t_dist_attributes/mt_enabled.h:104: [] GuardMe::safe_if_guarded_or_local() -t/t_dist_attributes/mt_enabled.h:106: [] GuardMe::operator int() -t/t_dist_attributes/mt_enabled.h:108: [] GuardMe::operator+=(int) +t/t_dist_attributes/mt_enabled.h:269: [mt_safe] TestClass::guarded_by_test_fail() +t/t_dist_attributes/mt_enabled.h:104: [] GuardMe::safe_if_guarded_or_local() +t/t_dist_attributes/mt_enabled.h:106: [] GuardMe::operator int() +t/t_dist_attributes/mt_enabled.h:108: [] GuardMe::operator+=(int) %Error: "TestClass::icm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.cpp:175: [mt_safe] TestClass::icm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:175: [mt_safe] TestClass::icm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::icm_test_caller_smethod_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.cpp:175: [mt_start] TestClass::icm_test_caller_smethod_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:175: [mt_start, requires] TestClass::icm_test_caller_smethod_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::icm_test_caller_smethod_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.cpp:175: [pure] TestClass::icm_test_caller_smethod_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [] TestClass::icm_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_safe] TestClass::icm_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_safe_postinit] TestClass::icm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_start] TestClass::icm_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [requires] TestClass::icm_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:175: [pure] TestClass::icm_test_caller_smethod_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [] TestClass::icm_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_safe] TestClass::icm_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_safe_postinit] TestClass::icm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_start, requires] TestClass::icm_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [requires] TestClass::icm_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::icm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:238: [mt_safe] TestClass::icm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:238: [mt_safe] TestClass::icm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::icm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.h:238: [mt_start] TestClass::icm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:238: [mt_start, requires] TestClass::icm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::icm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.h:238: [pure] TestClass::icm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [] TestClass::icm_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_safe] TestClass::icm_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_safe_postinit] TestClass::icm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_start] TestClass::icm_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:235: [requires] TestClass::icm_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:238: [pure] TestClass::icm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [] TestClass::icm_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_safe] TestClass::icm_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_safe_postinit] TestClass::icm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_start, requires] TestClass::icm_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:235: [requires] TestClass::icm_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.cpp:119: [mt_safe] TestClass::iscm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_start] TestClass::iscm_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:119: [mt_safe] TestClass::iscm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.cpp:119: [mt_start] TestClass::iscm_test_caller_smethod_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_start] TestClass::iscm_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:119: [mt_start, requires] TestClass::iscm_test_caller_smethod_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.cpp:119: [pure] TestClass::iscm_test_caller_smethod_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_safe] TestClass::iscm_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_safe_postinit] TestClass::iscm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_start] TestClass::iscm_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [requires] TestClass::iscm_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:119: [pure] TestClass::iscm_test_caller_smethod_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_safe] TestClass::iscm_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_safe_postinit] TestClass::iscm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_start, requires] TestClass::iscm_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [requires] TestClass::iscm_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:173: [mt_safe] TestClass::iscm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_start] TestClass::iscm_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:173: [mt_safe] TestClass::iscm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.h:173: [mt_start] TestClass::iscm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_start] TestClass::iscm_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:173: [mt_start, requires] TestClass::iscm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.h:173: [pure] TestClass::iscm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_safe] TestClass::iscm_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_safe_postinit] TestClass::iscm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_start] TestClass::iscm_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:170: [requires] TestClass::iscm_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:173: [pure] TestClass::iscm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_safe] TestClass::iscm_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_safe_postinit] TestClass::iscm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_start, requires] TestClass::iscm_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:170: [requires] TestClass::iscm_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [mt_safe] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_safe] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [mt_safe_postinit] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, mt_safe_postinit, pure] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_safe_postinit] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, mt_safe_postinit, pure] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_START(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [mt_start] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_start, mt_safe, pure] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_start, requires] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_start, mt_safe, pure, requires] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, mt_unsafe, pure] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, mt_unsafe, pure] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_PURE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [pure] TestClass::scm_ae_VL_PURE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure] TestClass::scm_ae_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [pure] TestClass::scm_ae_VL_PURE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure] TestClass::scm_ae_VL_PURE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_RELEASE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:133: [requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.cpp:93: [mt_safe] TestClass::scm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_start] TestClass::scm_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_start] TestClass::scm_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_start] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:93: [mt_safe] TestClass::scm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.cpp:93: [mt_start] TestClass::scm_test_caller_smethod_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_start] TestClass::scm_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_start] TestClass::scm_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_start] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:93: [mt_start, requires] TestClass::scm_test_caller_smethod_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.cpp:93: [pure] TestClass::scm_test_caller_smethod_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_safe] TestClass::scm_au_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_safe_postinit] TestClass::scm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_start] TestClass::scm_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [requires] TestClass::scm_au_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_safe] TestClass::scm_aa_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_safe_postinit] TestClass::scm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_start] TestClass::scm_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [requires] TestClass::scm_aa_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_safe] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_safe_postinit] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_start] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:93: [pure] TestClass::scm_test_caller_smethod_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_safe] TestClass::scm_au_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_safe_postinit] TestClass::scm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_start, requires] TestClass::scm_au_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [requires] TestClass::scm_au_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_safe] TestClass::scm_aa_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_safe_postinit] TestClass::scm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_start, requires] TestClass::scm_aa_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [requires] TestClass::scm_aa_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_safe] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_safe_postinit] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_start, requires] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:141: [mt_safe] TestClass::scm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_start] TestClass::scm_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_start] TestClass::scm_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_start] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:141: [mt_safe] TestClass::scm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.h:141: [mt_start] TestClass::scm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_start] TestClass::scm_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_start] TestClass::scm_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_start] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:141: [mt_start, requires] TestClass::scm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.h:141: [pure] TestClass::scm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_safe] TestClass::scm_au_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_safe_postinit] TestClass::scm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_start] TestClass::scm_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:120: [requires] TestClass::scm_au_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_safe] TestClass::scm_aa_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_safe_postinit] TestClass::scm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_start] TestClass::scm_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:128: [requires] TestClass::scm_aa_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_safe] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_safe_postinit] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_start] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:133: [requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:141: [pure] TestClass::scm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_safe] TestClass::scm_au_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_safe_postinit] TestClass::scm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_start, requires] TestClass::scm_au_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:120: [requires] TestClass::scm_au_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_safe] TestClass::scm_aa_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_safe_postinit] TestClass::scm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_start, requires] TestClass::scm_aa_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:128: [requires] TestClass::scm_aa_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_safe] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_safe_postinit] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_start, requires] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:133: [requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [acquire] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [acquire] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [acquire] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [acquire] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [excludes] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [excludes] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [mt_safe] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [mt_safe] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [excludes] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [excludes] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [mt_safe_postinit] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [mt_safe_postinit] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_START(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [mt_start] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [mt_start, requires] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [mt_unsafe] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [mt_unsafe] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [mt_unsafe_one] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [mt_unsafe_one] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_PURE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [pure] TestClass::scm_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [pure] TestClass::scm_ua_VL_PURE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_RELEASE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [release] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [release] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [release] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [release] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:75: [requires] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:75: [requires] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) %Error: "TestClassConstructor::safe_function_calls_constructor_global_object_bad()" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.h:405: [stable_tree] TestClassConstructor::safe_function_calls_constructor_global_object_bad() -t/t_dist_attributes/mt_enabled.h:355: [] DummyClass::dummy_function() +t/t_dist_attributes/mt_enabled.h:426: [stable_tree] TestClassConstructor::safe_function_calls_constructor_global_object_bad() +t/t_dist_attributes/mt_enabled.h:355: [] DummyClass::dummy_function() %Error: "TestClassConstructor::safe_function_calls_constructor_global_object_member_bad()" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.h:408: [stable_tree] TestClassConstructor::safe_function_calls_constructor_global_object_member_bad() -t/t_dist_attributes/mt_enabled.h:350: [] DummyClass2::dummy_function2() +t/t_dist_attributes/mt_enabled.h:429: [stable_tree] TestClassConstructor::safe_function_calls_constructor_global_object_member_bad() +t/t_dist_attributes/mt_enabled.h:350: [] DummyClass2::dummy_function2() %Error: "TestClassConstructor::safe_function_calls_constructor_local_calls_class_global_bad()" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:402: [mt_safe] TestClassConstructor::safe_function_calls_constructor_local_calls_class_global_bad() -t/t_dist_attributes/mt_enabled.h:280: [] StaticClass::static_class_function() +t/t_dist_attributes/mt_enabled.h:423: [mt_safe] TestClassConstructor::safe_function_calls_constructor_local_calls_class_global_bad() +t/t_dist_attributes/mt_enabled.h:280: [] StaticClass::static_class_function() %Error: "TestClassConstructor::safe_function_calls_constructor_local_calls_global_bad()" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:399: [mt_safe] TestClassConstructor::safe_function_calls_constructor_local_calls_global_bad() -t/t_dist_attributes/mt_enabled.h:276: [] static_function() +t/t_dist_attributes/mt_enabled.h:420: [mt_safe] TestClassConstructor::safe_function_calls_constructor_local_calls_global_bad() +t/t_dist_attributes/mt_enabled.h:276: [] static_function() %Error: "TestClassConstructor::safe_function_calls_constructor_with_unsafepointer_bad()" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:391: [mt_safe] TestClassConstructor::safe_function_calls_constructor_with_unsafepointer_bad() -t/t_dist_attributes/mt_enabled.h:311: [mt_unsafe] UnsafeFunction::unsafe_function() +t/t_dist_attributes/mt_enabled.h:412: [mt_safe] TestClassConstructor::safe_function_calls_constructor_with_unsafepointer_bad() +t/t_dist_attributes/mt_enabled.h:311: [mt_unsafe] UnsafeFunction::unsafe_function() %Error: "TestClassConstructor::safe_function_calls_constructor_with_unsafereference_bad()" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:395: [mt_safe] TestClassConstructor::safe_function_calls_constructor_with_unsafereference_bad() -t/t_dist_attributes/mt_enabled.h:311: [mt_unsafe] UnsafeFunction::unsafe_function() +t/t_dist_attributes/mt_enabled.h:416: [mt_safe] TestClassConstructor::safe_function_calls_constructor_with_unsafereference_bad() +t/t_dist_attributes/mt_enabled.h:311: [mt_unsafe] UnsafeFunction::unsafe_function() %Error: "TestClassConstructor::safe_function_local_function_global_bad()" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:377: [mt_safe] TestClassConstructor::safe_function_local_function_global_bad() -t/t_dist_attributes/mt_enabled.h:276: [] static_function() +t/t_dist_attributes/mt_enabled.h:398: [mt_safe] TestClassConstructor::safe_function_local_function_global_bad() +t/t_dist_attributes/mt_enabled.h:276: [] static_function() %Error: "TestClassConstructor::safe_function_static_constructor_bad()" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:374: [mt_safe] TestClassConstructor::safe_function_static_constructor_bad() -t/t_dist_attributes/mt_enabled.h:276: [] static_function() +t/t_dist_attributes/mt_enabled.h:395: [mt_safe] TestClassConstructor::safe_function_static_constructor_bad() +t/t_dist_attributes/mt_enabled.h:276: [] static_function() %Error: "TestClassConstructor::safe_function_unsafe_constructor_bad()" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:371: [mt_safe] TestClassConstructor::safe_function_unsafe_constructor_bad() -t/t_dist_attributes/mt_enabled.h:285: [mt_unsafe] ConstructorCallsUnsafeLocalFunction::unsafe_function() +t/t_dist_attributes/mt_enabled.h:392: [mt_safe] TestClassConstructor::safe_function_unsafe_constructor_bad() +t/t_dist_attributes/mt_enabled.h:285: [mt_unsafe] ConstructorCallsUnsafeLocalFunction::unsafe_function() %Error: "UnannotatedMtDisabledClass::unannotatedMtDisabledMethodBad()" defined in a file marked as VL_MT_DISABLED_CODE_UNIT has declaration(s) without VL_MT_DISABLED annotation -t/t_dist_attributes/mt_disabled.cpp:23: [mt_disabled, requires] UnannotatedMtDisabledClass::unannotatedMtDisabledMethodBad() -t/t_dist_attributes/mt_disabled.h:29: [] UnannotatedMtDisabledClass::unannotatedMtDisabledMethodBad() +t/t_dist_attributes/mt_disabled.h:27: [mt_disabled, excludes] UnannotatedMtDisabledClass::unannotatedMtDisabledMethodBad() [declaration] +t/t_dist_attributes/mt_disabled.cpp:23: [] UnannotatedMtDisabledClass::unannotatedMtDisabledMethodBad() +t/t_dist_attributes/mt_disabled.h:27: [] UnannotatedMtDisabledClass::unannotatedMtDisabledMethodBad() %Error: "UnannotatedMtDisabledClass::unannotatedMtDisabledStaticMethodBad()" defined in a file marked as VL_MT_DISABLED_CODE_UNIT has declaration(s) without VL_MT_DISABLED annotation -t/t_dist_attributes/mt_disabled.cpp:26: [mt_disabled, requires] UnannotatedMtDisabledClass::unannotatedMtDisabledStaticMethodBad() -t/t_dist_attributes/mt_disabled.h:30: [] UnannotatedMtDisabledClass::unannotatedMtDisabledStaticMethodBad() +t/t_dist_attributes/mt_disabled.h:28: [mt_disabled, excludes] UnannotatedMtDisabledClass::unannotatedMtDisabledStaticMethodBad() [declaration] +t/t_dist_attributes/mt_disabled.cpp:26: [] UnannotatedMtDisabledClass::unannotatedMtDisabledStaticMethodBad() +t/t_dist_attributes/mt_disabled.h:28: [] UnannotatedMtDisabledClass::unannotatedMtDisabledStaticMethodBad() + +%Error: "VirtualInheritance::Base1::func(int, int)" is pure but calls non-pure function(s) +t/t_dist_attributes/mt_enabled.h:382: [pure] VirtualInheritance::Base1::func(int, int) +t/t_dist_attributes/mt_enabled.h:384: [] VirtualInheritance::Derived::notPure() + +%Error: "VirtualInheritance::Base2::func()" is pure but calls non-pure function(s) +t/t_dist_attributes/mt_enabled.h:383: [pure] VirtualInheritance::Base2::func() +t/t_dist_attributes/mt_enabled.h:384: [] VirtualInheritance::Derived::notPure() %Error: "ifh_test_caller_func_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.cpp:53: [mt_safe] ifh_test_caller_func_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_start] ifh_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:53: [mt_safe] ifh_test_caller_func_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "ifh_test_caller_func_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.cpp:53: [mt_start] ifh_test_caller_func_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_start] ifh_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:53: [mt_start, requires] ifh_test_caller_func_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "ifh_test_caller_func_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.cpp:53: [pure] ifh_test_caller_func_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_safe] ifh_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_safe_postinit] ifh_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_start] ifh_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [requires] ifh_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:53: [pure] ifh_test_caller_func_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_safe] ifh_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_safe_postinit] ifh_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_start, requires] ifh_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [requires] ifh_VL_REQUIRES(VerilatedMutex &) %Error: "ifh_test_caller_func_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:97: [mt_safe] ifh_test_caller_func_hdr_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_start] ifh_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:97: [mt_safe] ifh_test_caller_func_hdr_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "ifh_test_caller_func_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.h:97: [mt_start] ifh_test_caller_func_hdr_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_start] ifh_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:97: [mt_start, requires] ifh_test_caller_func_hdr_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "ifh_test_caller_func_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.h:97: [pure] ifh_test_caller_func_hdr_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_safe] ifh_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_safe_postinit] ifh_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_start] ifh_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:94: [requires] ifh_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:97: [pure] ifh_test_caller_func_hdr_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_safe] ifh_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_safe_postinit] ifh_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_start, requires] ifh_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:94: [requires] ifh_VL_REQUIRES(VerilatedMutex &) %Error: "nsf_ae_NO_ANNOTATION(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure] nsf_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure] nsf_ae_NO_ANNOTATION(VerilatedMutex &) %Error: "nsf_ae_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) %Error: "nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "nsf_ae_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) %Error: "nsf_ae_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [mt_safe] nsf_ae_VL_MT_SAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure] nsf_ae_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_safe] nsf_ae_VL_MT_SAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure] nsf_ae_VL_MT_SAFE(VerilatedMutex &) %Error: "nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [mt_safe_postinit] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, mt_safe_postinit, pure] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_safe_postinit] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, mt_safe_postinit, pure] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "nsf_ae_VL_MT_START(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [mt_start] nsf_ae_VL_MT_START(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_start, mt_safe, pure] nsf_ae_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_start, requires] nsf_ae_VL_MT_START(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_start, mt_safe, pure, requires] nsf_ae_VL_MT_START(VerilatedMutex &) %Error: "nsf_ae_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, mt_unsafe, pure] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, mt_unsafe, pure] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) %Error: "nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, mt_unsafe_one, pure] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, mt_unsafe_one, pure] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_ae_VL_PURE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [pure] nsf_ae_VL_PURE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure] nsf_ae_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [pure] nsf_ae_VL_PURE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure] nsf_ae_VL_PURE(VerilatedMutex &) %Error: "nsf_ae_VL_RELEASE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, release] nsf_ae_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, release] nsf_ae_VL_RELEASE(VerilatedMutex &) %Error: "nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "nsf_ae_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:75: [requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) %Error: "nsf_test_caller_func_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.cpp:42: [mt_safe] nsf_test_caller_func_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_start] nsf_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_start] nsf_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_start] nsf_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:42: [mt_safe] nsf_test_caller_func_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_test_caller_func_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.cpp:42: [mt_start] nsf_test_caller_func_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_start] nsf_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_start] nsf_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_start] nsf_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:42: [mt_start, requires] nsf_test_caller_func_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_test_caller_func_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.cpp:42: [pure] nsf_test_caller_func_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_safe] nsf_au_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_safe_postinit] nsf_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_start] nsf_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [requires] nsf_au_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_safe] nsf_aa_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_safe_postinit] nsf_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_start] nsf_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [requires] nsf_aa_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_safe] nsf_ae_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_safe_postinit] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_start] nsf_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:42: [pure] nsf_test_caller_func_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_safe] nsf_au_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_safe_postinit] nsf_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_start, requires] nsf_au_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [requires] nsf_au_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_safe] nsf_aa_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_safe_postinit] nsf_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_start, requires] nsf_aa_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [requires] nsf_aa_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_safe] nsf_ae_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_safe_postinit] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_start, requires] nsf_ae_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) %Error: "nsf_test_caller_func_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.h:83: [mt_safe] nsf_test_caller_func_hdr_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_start] nsf_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_start] nsf_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_start] nsf_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:83: [mt_safe] nsf_test_caller_func_hdr_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_test_caller_func_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.h:83: [mt_start] nsf_test_caller_func_hdr_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_start] nsf_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_start] nsf_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_start] nsf_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:83: [mt_start, requires] nsf_test_caller_func_hdr_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_test_caller_func_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.h:83: [pure] nsf_test_caller_func_hdr_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_safe] nsf_au_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_safe_postinit] nsf_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_start] nsf_au_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:62: [requires] nsf_au_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_safe] nsf_aa_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_safe_postinit] nsf_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_start] nsf_aa_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:70: [requires] nsf_aa_VL_REQUIRES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_safe] nsf_ae_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_safe_postinit] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_start] nsf_ae_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.h:75: [requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:83: [pure] nsf_test_caller_func_hdr_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_safe] nsf_au_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_safe_postinit] nsf_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_start, requires] nsf_au_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:62: [requires] nsf_au_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_safe] nsf_aa_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_safe_postinit] nsf_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_start, requires] nsf_aa_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:70: [requires] nsf_aa_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_safe] nsf_ae_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_safe_postinit] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_start, requires] nsf_ae_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:75: [requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) %Error: "nsf_ua_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [acquire] nsf_ua_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [acquire] nsf_ua_VL_ACQUIRE(VerilatedMutex &) %Error: "nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [acquire] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [acquire] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "nsf_ua_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [excludes] nsf_ua_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [excludes] nsf_ua_VL_EXCLUDES(VerilatedMutex &) %Error: "nsf_ua_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [mt_safe] nsf_ua_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [mt_safe] nsf_ua_VL_MT_SAFE(VerilatedMutex &) %Error: "nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [excludes] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [excludes] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [mt_safe_postinit] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [mt_safe_postinit] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "nsf_ua_VL_MT_START(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [mt_start] nsf_ua_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [mt_start, requires] nsf_ua_VL_MT_START(VerilatedMutex &) %Error: "nsf_ua_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [mt_unsafe] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [mt_unsafe] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) %Error: "nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [mt_unsafe_one] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [mt_unsafe_one] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_ua_VL_PURE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [pure] nsf_ua_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [pure] nsf_ua_VL_PURE(VerilatedMutex &) %Error: "nsf_ua_VL_RELEASE(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [release] nsf_ua_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [release] nsf_ua_VL_RELEASE(VerilatedMutex &) %Error: "nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [release] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [release] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "nsf_ua_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition -t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) [declaration] -t/t_dist_attributes/mt_enabled.cpp:25: [requires] nsf_ua_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) [declaration] +t/t_dist_attributes/mt_enabled.cpp:25: [requires] nsf_ua_VL_REQUIRES(VerilatedMutex &) %Error: "sfc_test_caller_func_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) -t/t_dist_attributes/mt_enabled.cpp:63: [mt_safe] sfc_test_caller_func_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [] sfc_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [mt_start] sfc_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe] sfc_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe_one] sfc_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:63: [mt_safe] sfc_test_caller_func_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [] sfc_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe] sfc_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe_one] sfc_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "sfc_test_caller_func_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe -t/t_dist_attributes/mt_enabled.cpp:63: [mt_start] sfc_test_caller_func_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [] sfc_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [mt_start] sfc_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe] sfc_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe_one] sfc_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:63: [mt_start, requires] sfc_test_caller_func_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [] sfc_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe] sfc_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe_one] sfc_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "sfc_test_caller_func_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) -t/t_dist_attributes/mt_enabled.cpp:63: [pure] sfc_test_caller_func_VL_PURE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [] sfc_NO_ANNOTATION(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [acquire] sfc_VL_ACQUIRE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [acquire] sfc_VL_ACQUIRE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [excludes] sfc_VL_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [mt_safe] sfc_VL_MT_SAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [excludes] sfc_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [mt_safe_postinit] sfc_VL_MT_SAFE_POSTINIT(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [mt_start] sfc_VL_MT_START(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe] sfc_VL_MT_UNSAFE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe_one] sfc_VL_MT_UNSAFE_ONE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [release] sfc_VL_RELEASE(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [release] sfc_VL_RELEASE_SHARED(VerilatedMutex &) -t/t_dist_attributes/mt_enabled.cpp:60: [requires] sfc_VL_REQUIRES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:63: [pure] sfc_test_caller_func_VL_PURE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [] sfc_NO_ANNOTATION(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [acquire] sfc_VL_ACQUIRE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [acquire] sfc_VL_ACQUIRE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [excludes] sfc_VL_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [mt_safe] sfc_VL_MT_SAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [excludes] sfc_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [mt_safe_postinit] sfc_VL_MT_SAFE_POSTINIT(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [mt_start, requires] sfc_VL_MT_START(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe] sfc_VL_MT_UNSAFE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe_one] sfc_VL_MT_UNSAFE_ONE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [release] sfc_VL_RELEASE(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [release] sfc_VL_RELEASE_SHARED(VerilatedMutex &) +t/t_dist_attributes/mt_enabled.cpp:60: [requires] sfc_VL_REQUIRES(VerilatedMutex &) %Error: "unannotatedMtDisabledFunctionBad()" defined in a file marked as VL_MT_DISABLED_CODE_UNIT has declaration(s) without VL_MT_DISABLED annotation -t/t_dist_attributes/mt_disabled.cpp:20: [mt_disabled, requires] unannotatedMtDisabledFunctionBad() -t/t_dist_attributes/mt_disabled.h:22: [] unannotatedMtDisabledFunctionBad() -t/t_dist_attributes/mt_disabled.h:25: [] unannotatedMtDisabledFunctionBad() -Number of functions reported unsafe: 229 +t/t_dist_attributes/mt_disabled.h:20: [mt_disabled, excludes] unannotatedMtDisabledFunctionBad() [declaration] +t/t_dist_attributes/mt_disabled.cpp:20: [] unannotatedMtDisabledFunctionBad() +t/t_dist_attributes/mt_disabled.h:20: [] unannotatedMtDisabledFunctionBad() +t/t_dist_attributes/mt_disabled.h:23: [] unannotatedMtDisabledFunctionBad() +Number of functions reported unsafe: 230 diff --git a/test_regress/t/t_dist_attributes_bad.pl b/test_regress/t/t_dist_attributes_bad.pl deleted file mode 100755 index 35579d8f9..000000000 --- a/test_regress/t/t_dist_attributes_bad.pl +++ /dev/null @@ -1,102 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use Cwd qw(abs_path); -use JSON::PP; -use IO::File; - -scenarios(dist => 1); - -my $root = ".."; - -if ($ENV{VERILATOR_TEST_NO_ATTRIBUTES}) { - skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES"); -} elsif (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - check(); -} - -sub gen_compile_commands_json { - my $json = JSON::PP->new->utf8->pretty; - $json->canonical(); # Sort hash keys on ouptut - - my $root_dir = abs_path(".."); - my $srcs_dir = abs_path("./t/t_dist_attributes"); - my @common_args = ("clang++", - "-std=c++14", - "-I$root_dir/include", - "-I$root_dir/src", - "-c"); - - my $ccjson = [ - {"directory" => "$srcs_dir", - "file" => "$srcs_dir/mt_enabled.cpp", - "output" => undef, - "arguments" => [@common_args]}, - {"directory" => "$srcs_dir", - "file" => "$srcs_dir/mt_disabled.cpp", - "output" => undef, - "arguments" => [@common_args]}, - ]; - - my @srcfiles; - foreach my $entry (@$ccjson) { - # Add "output" key - ($entry->{"output"} = $entry->{"file"}) =~ s/\.cpp$/.o/; - # Add "-o src.o src.cpp" arguments - push @{$entry->{"arguments"}}, ("-o", $entry->{"output"}, $entry->{"file"}); - - push @srcfiles, $entry->{"file"}; - } - - return ( - \@srcfiles, - $json->encode($ccjson) - ); -} - -sub check { - my $root = abs_path(".."); - my $ccjson_file = "$Self->{obj_dir}/compile_commands.json"; - my ($srcfiles, $ccjson) = gen_compile_commands_json(); - my $srcfiles_str = join(" ", @$srcfiles); - { - my $fh = IO::File->new(">$ccjson_file") or die "%Error: $! $ccjson_file"; - print $fh $ccjson; - $fh->close(); - } - - sub run_clang_check { - { - my $cmd = qq{python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";}; - print "\t$cmd\n" if $::Debug; - my $out = `$cmd`; - if (!$out || $out !~ /Clang imported/) { skip("No libclang installed\n"); return 1; } - } - run(logfile => $Self->{run_log_filename}, - tee => 1, - # With `--verilator-root` set to the current directory - # (i.e. `test_regress`) the script will skip annotation issues in - # headers from the `../include` directory. - cmd => ["python3", - "$root/nodist/clang_check_attributes", - "--verilator-root=.", - "--compile-commands-dir=$Self->{obj_dir}", - "$srcfiles_str"]); - - files_identical($Self->{run_log_filename}, $Self->{golden_filename}); - } - - run_clang_check(); -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_attributes_bad.py b/test_regress/t/t_dist_attributes_bad.py new file mode 100755 index 000000000..14b04ec27 --- /dev/null +++ b/test_regress/t/t_dist_attributes_bad.py @@ -0,0 +1,82 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import json +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + + +def have_clang_check(): + cmd = 'python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";' + if test.verbose: + print("\t" + cmd) + nout = test.run_capture(cmd, check=False) + if not nout or not re.search(r'Clang imported', nout): + return False + return True + + +if 'VERILATOR_TEST_NO_ATTRIBUTES' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES") +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") +if not have_clang_check(): + test.skip("No libclang installed\n") + +aroot = os.path.abspath(root) +ccjson_file = test.obj_dir + "/compile_commands.json" + +aroot_dir = os.path.abspath(root) +srcs_dir = os.path.abspath("./t/t_dist_attributes") +common_args = [ + "clang++", "-std=c++14", "-I" + aroot_dir + "/include", "-I" + aroot_dir + "/src", "-c" +] + +ccjson = [ + { + "directory": srcs_dir, + "file": srcs_dir + "/mt_enabled.cpp", + "output": srcs_dir + "/mt_enabled.o", + "arguments": + [*common_args, "-o", srcs_dir + "/mt_enabled.o", srcs_dir + "/mt_enabled.cpp"] + }, + { + "directory": srcs_dir, + "file": srcs_dir + "/mt_disabled.cpp", + "output": srcs_dir + "/mt_disabled.o", + "arguments": + [*common_args, "-o", srcs_dir + "/mt_enabled.o", srcs_dir + "/mt_enabled.cpp"] + }, +] +ccjson_str = json.dumps(ccjson) + +srcfiles = [] +for entry in ccjson: + srcfiles.append(entry["file"]) +srcfiles_str = ' '.join(srcfiles) + +test.write_wholefile(ccjson_file, ccjson_str) + +test.run( + logfile=test.run_log_filename, + tee=True, + # With `--verilator-root` set to the current directory + # (i.e. `test_regress`) the script will skip annotation issues in + # headers from the `../include` directory. + cmd=[ + "python3", aroot + "/nodist/clang_check_attributes", "--verilator-root=.", + "--compile-commands-dir=" + test.obj_dir, "--jobs=1", srcfiles_str + ]) + +test.files_identical(test.run_log_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dist_cinclude.pl b/test_regress/t/t_dist_cinclude.pl deleted file mode 100755 index f006eae01..000000000 --- a/test_regress/t/t_dist_cinclude.pl +++ /dev/null @@ -1,61 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use File::Spec::Functions 'catfile'; - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; - -if (!-r catfile($root, ".git")) { - skip("Not in a git repository"); -} else { - ### Must trim output before and after our file list - my $files = `cd $root && git ls-files --exclude-standard`; - print "ST $files\n" if $Debug; - foreach my $file (split /\n/, $files) { - next if $file =~ m!include/vltstd/vpi_user.h!; # IEEE Standard file - can't change it - next if $file =~ m!include/gtkwave/!; # Standard file - can't change it - my $filename = catfile($root, $file); - next if !-r $filename; - @lines = split /\n/, file_contents($filename); - @include_lines = grep(/include/, @lines); - foreach my $line (@include_lines) { - my $hit; - $hit = 1 if $line =~ /\bassert\.h/; - $hit = 1 if $line =~ /\bctype\.h/; - $hit = 1 if $line =~ /\berrno\.h/; - $hit = 1 if $line =~ /\bfloat\.h/; - $hit = 1 if $line =~ /\blimits\.h/; - $hit = 1 if $line =~ /\blocale\.h/; - $hit = 1 if $line =~ /\bmath\.h/; - $hit = 1 if $line =~ /\bsetjmp\.h/; - $hit = 1 if $line =~ /\bsignal\.h/; - $hit = 1 if $line =~ /\bstdarg\.h/; - $hit = 1 if $line =~ /\bstdbool\.h/; - $hit = 1 if $line =~ /\bstddef\.h/; - #Not yet: $hit = 1 if $line =~ /\bstdint\.h/; - $hit = 1 if $line =~ /\bstdio\.h/; - $hit = 1 if $line =~ /\bstdlib\.h/; - $hit = 1 if $line =~ /\bstring\.h/; - $hit = 1 if $line =~ /\btime\.h/ && $line !~ m!sys/time.h!; - next if !$hit; - $names{"$filename: $line"} = 1; - } - } - if (keys %names) { - error("Files like stdint.h instead of cstdint:\n ", join("\n ", sort keys %names)); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_cinclude.py b/test_regress/t/t_dist_cinclude.py new file mode 100755 index 000000000..a7ee86009 --- /dev/null +++ b/test_regress/t/t_dist_cinclude.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +### Must trim output before and after our file list +cmd = "cd " + root + " && git ls-files --exclude-standard" +files = test.run_capture(cmd) +if test.verbose: + print("ST " + files) +names = {} +for filename in files.split(): + if "include/vltstd/vpi_user.h" in filename: # IEEE Standard file - can't change it + continue + if "include/gtkwave/" in filename: # Standard file - can't change it + continue + filename = os.path.join(root, filename) + if not os.path.exists(filename): + continue + with open(filename, 'r', encoding='latin-1') as fh: + for line in fh: + if "include" not in line: + continue + line = line.rstrip() + hit = (re.search(r'\bassert\.h', line) or re.search(r'\bctype\.h', line) + or re.search(r'\berrno\.h', line) or re.search(r'\bfloat\.h', line) + or re.search(r'\blimits\.h', line) or re.search(r'\blocale\.h', line) + or re.search(r'\bmath\.h', line) or re.search(r'\bsetjmp\.h', line) + or re.search(r'\bsignal\.h', line) or re.search(r'\bstdarg\.h', line) + or re.search(r'\bstdbool\.h', line) or re.search(r'\bstddef\.h', line) + or re.search(r'\bstdio\.h', line) or re.search(r'\bstdlib\.h', line) + or re.search(r'\bstring\.h', line) + or (re.search(r'\btime\.h', line) and not re.search(r'sys/time.h', line))) + #Not yet: r'\bstdint\.h' + if not hit: + continue + names[filename + ": " + line] = True + +if len(names): + test.error("Files like stdint.h instead of cstdint:\n " + + "\n ".join(sorted(names.keys()))) + +test.passes() diff --git a/test_regress/t/t_dist_contributors.pl b/test_regress/t/t_dist_contributors.pl deleted file mode 100755 index a4b4db5a4..000000000 --- a/test_regress/t/t_dist_contributors.pl +++ /dev/null @@ -1,85 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; -my %Contributors = ('github action' => 1); -my %Authors; - -if ($ENV{VERILATOR_TEST_NO_CONTRIBUTORS}) { - skip("Skipping due to VERILATOR_TEST_NO_CONTRIBUTORS"); -} elsif (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - check(); -} - -ok(1); -1; - -sub check { - read_contributors("$root/docs/CONTRIBUTORS"); - read_user(); - read_authors(); - for my $author (sort keys %Authors) { - print "Check: $author\n" if $Self->{verbose}; - if (!$Contributors{$author}) { - error("Certify your contribution by sorted-inserting '$author' into docs/CONTRIBUTORS.\n" - . " If '$author' is not your real name, please fix 'name=' in ~/.gitconfig\n" - . " Also check your https://github.com account's Settings->Profile->Name\n" - . " matches your ~/.gitconfig 'name='.\n"); - } - } -} - -sub read_contributors { - my $filename = shift; - my $fh = IO::File->new("<$filename") - or error("$! $filename"); - # Assumes git .mailmap format - while (my $line = ($fh && $fh->getline)) { - while ($line =~ /(.*)/g) { - $line =~ s/ *<[^>]*>//; - $Contributors{$1} = 1; - } - } -} - -sub read_user { - my $changes = `cd $root ; git diff-index --quiet HEAD --`; - chomp $changes; - if (!$changes) { - print "No git changes\n" if $Self->{verbose}; - } else { - # Uncommitted changes, so check the user's git name - my $user = `git config user.name`; - chomp $user; - my $email = `git config user.email`; - chomp $email; - if ($user && $email) { - $Authors{"$user <$email>"} = 1; - } - } -} - -sub read_authors { - # Check recent commits in case did commit - my $git_auths = `git log '--pretty=format:%aN <%aE>' | head -5`; - foreach my $line (split /\n/, $git_auths) { - $line =~ s/ *<[^>]*>//; - $Authors{$line} = 1; - } -} diff --git a/test_regress/t/t_dist_contributors.py b/test_regress/t/t_dist_contributors.py new file mode 100755 index 000000000..f1a1c4664 --- /dev/null +++ b/test_regress/t/t_dist_contributors.py @@ -0,0 +1,75 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +Contributors = {'github action': True} +Authors = {} + + +def read_contributors(filename): + with open(filename, 'r', encoding="utf8") as fh: + # Assumes git .mailmap format + for line in fh: + line = line.rstrip() + line = re.sub(r' *<[^>]*>', '', line) + Contributors[line] = True + + +def read_user(): + cmd = "cd " + root + " && git diff-index --quiet HEAD --" + changes = test.run_capture(cmd, check=False) + changes = changes.rstrip() + if changes == "": + if test.verbose: + print("No git changes") + else: + # Uncommitted changes, so check the user's git name + user = test.run_capture("git config user.name") + user = user.rstrip() + if user: + Authors[user] = True + + +def read_authors(): + # Check recent commits in case did commit + cmd = "git log '--pretty=format:%aN <%aE>' | head -5" + git_auths = test.run_capture(cmd) + for line in git_auths.splitlines(): + line = re.sub(r' *<[^>]*>', '', line) + Authors[line] = True + + +def check(): + read_contributors(root + "/docs/CONTRIBUTORS") + read_user() + read_authors() + for author in sorted(Authors.keys()): + if test.verbose: + print("Check: " + author) + if author not in Contributors: + test.error("Certify your contribution by sorted-inserting '" + author + + "' into docs/CONTRIBUTORS.\n" + " If '" + author + + "' is not your real name, please fix 'name=' in ~/.gitconfig\n" + " Also check your https://github.com account's Settings->Profile->Name\n" + " matches your ~/.gitconfig 'name='.\n") + + +if 'VERILATOR_TEST_NO_CONTRIBUTORS' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_CONTRIBUTORS") +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +check() +test.passes() diff --git a/test_regress/t/t_dist_copyright.pl b/test_regress/t/t_dist_copyright.pl deleted file mode 100755 index e235a8338..000000000 --- a/test_regress/t/t_dist_copyright.pl +++ /dev/null @@ -1,229 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use POSIX qw(strftime); -use strict; -use File::Spec::Functions 'catfile'; - -scenarios(dist => 1); - -our $Release_Ok_Re = qr!(^test_regress/t/|^examples/)!; -our $Exempt_Author_Re = qr!(^ci/|^nodist/fastcov.py|^nodist/fuzzer|^test_regress/t/.*\.(v|cpp|h)$)!; -our $Exempt_Files_Re = qr!(^\.|/\.|\.gitignore$|\.dat|\.gprof|\.mem|\.out$|\.png$|\.tree|\.vc$|\.vcd$|^\.)!; -our @Exempt_Files_List = qw( - Artistic - CITATION.cff - CPPLINT.cfg - LICENSE - README.rst - ci/ci-win-compile.ps1 - ci/ci-win-test.ps1 - ci/codecov - docs/CONTRIBUTING.rst - docs/CONTRIBUTORS - docs/README.rst - docs/_static - docs/gen - docs/spelling.txt - docs/verilated.dox - include/gtkwave - include/vltstd - install-sh - src/mkinstalldirs - test_regress/t/t_altera_lpm.v - test_regress/t/t_flag_f__3.v - test_regress/t/t_fuzz_eof_bad.v - test_regress/t/t_incr_void.v - test_regress/t/t_timing_trace_fst.pl - test_regress/t/t_uvm_pkg_all.vh - test_regress/t/t_uvm_pkg_todo.vh - test_regress/t/t_wrapper_context.pl - test_regress/t/t_wrapper_context_fst.pl - test_regress/t/t_wrapper_context_seq.pl - test_regress/t/t_wrapper_del_context_bad.pl - test_regress/t/tsub/t_flag_f_tsub.v - test_regress/t/tsub/t_flag_f_tsub_inc.v - verilator.pc.in - ); - -our @Exempt_Files_Copyright = qw( - test_regress/t/t_assert_disable_bad.pl - test_regress/t/t_clocking_bad1.pl - test_regress/t/t_clocking_bad2.pl - test_regress/t/t_clocking_bad3.pl - test_regress/t/t_clocking_bad4.pl - test_regress/t/t_clocking_notiming.pl - test_regress/t/t_clocking_timing2.pl - test_regress/t/t_clocking_unsup1.pl - test_regress/t/t_clocking_unsup2.pl - test_regress/t/t_comb_input_0.pl - test_regress/t/t_comb_input_1.pl - test_regress/t/t_comb_input_2.pl - test_regress/t/t_comb_loop_through_unpacked_array.pl - test_regress/t/t_const_bitoptree_bug3096.pl - test_regress/t/t_const_sel_sel_extend.pl - test_regress/t/t_delay_incr_timing.pl - test_regress/t/t_delay_timing.pl - test_regress/t/t_dfg_3676.pl - test_regress/t/t_dfg_3726.pl - test_regress/t/t_dfg_circular.pl - test_regress/t/t_dfg_multidriver_dfg_bad.pl - test_regress/t/t_dfg_multidriver_non_dfg.pl - test_regress/t/t_dfg_peephole.pl - test_regress/t/t_dfg_unhandled.pl - test_regress/t/t_dist_cppstyle.pl - test_regress/t/t_dpi_arg_inout_type.pl - test_regress/t/t_dpi_arg_inout_unpack.pl - test_regress/t/t_dpi_arg_input_type.pl - test_regress/t/t_dpi_arg_input_unpack.pl - test_regress/t/t_dpi_arg_output_type.pl - test_regress/t/t_dpi_arg_output_unpack.pl - test_regress/t/t_dpi_import_hdr_only.pl - test_regress/t/t_dpi_open_query.pl - test_regress/t/t_dpi_result_type.pl - test_regress/t/t_dpi_result_type_bad.pl - test_regress/t/t_dump_dfg.pl - test_regress/t/t_event_control_expr.pl - test_regress/t/t_event_control_expr_unsup.pl - test_regress/t/t_event_control_timing.pl - test_regress/t/t_flag_build_jobs_and_j.pl - test_regress/t/t_flag_prefix.pl - test_regress/t/t_flag_quiet_exit.pl - test_regress/t/t_flag_structs_packed.pl - test_regress/t/t_flag_values_deprecated.pl - test_regress/t/t_fork_timing.pl - test_regress/t/t_format_wide_decimal.pl - test_regress/t/t_gate_basic_timing.pl - test_regress/t/t_gate_delay_unsup.pl - test_regress/t/t_gate_loop.pl - test_regress/t/t_lib.pl - test_regress/t/t_lib_nolib.pl - test_regress/t/t_lib_prot.pl - test_regress/t/t_lib_prot_clk_gated.pl - test_regress/t/t_lib_prot_comb.pl - test_regress/t/t_lib_prot_delay_bad.pl - test_regress/t/t_lib_prot_inout_bad.pl - test_regress/t/t_lib_prot_secret.pl - test_regress/t/t_lib_prot_shared.pl - test_regress/t/t_lint_wait_bad.pl - test_regress/t/t_merge_cond_blowup.pl - test_regress/t/t_merge_cond_bug_3409.pl - test_regress/t/t_merge_cond_no_extend.pl - test_regress/t/t_merge_cond_no_motion.pl - test_regress/t/t_net_delay.pl - test_regress/t/t_net_delay_timing_sc.pl - test_regress/t/t_notiming.pl - test_regress/t/t_notiming_off.pl - test_regress/t/t_order_timing.pl - test_regress/t/t_param_real2_collision.pl - test_regress/t/t_recursive_module_bug.pl - test_regress/t/t_recursive_module_bug_2.pl - test_regress/t/t_sampled_expr_unsup.pl - test_regress/t/t_scheduling_5.pl - test_regress/t/t_scope_map.pl - test_regress/t/t_std_identifier_bad.pl - test_regress/t/t_timing_clkgen_unsup.pl - test_regress/t/t_timing_cmake.pl - test_regress/t/t_timing_debug1.pl - test_regress/t/t_timing_debug2.pl - test_regress/t/t_timing_dpi_unsup.pl - test_regress/t/t_timing_fork_comb.pl - test_regress/t/t_timing_func_bad.pl - test_regress/t/t_timing_intra_assign.pl - test_regress/t/t_timing_localevent_unsup.pl - test_regress/t/t_timing_protect.pl - test_regress/t/t_timing_unset1.pl - test_regress/t/t_timing_unset2.pl - test_regress/t/t_timing_unset3.pl - test_regress/t/t_timing_zerodly_unsup.pl - test_regress/t/t_trace_abort.pl - test_regress/t/t_trace_abort_fst.pl - test_regress/t/t_trace_abort_fst_sc.pl - test_regress/t/t_trace_ascendingrange.pl - test_regress/t/t_trace_ascendingrange_fst.pl - test_regress/t/t_trace_ascendingrange_fst_sc.pl - test_regress/t/t_trace_param_override.pl - test_regress/t/t_trace_timing1.pl - test_regress/t/t_type_param_collision.pl - test_regress/t/t_wait_timing.pl - test_regress/t/t_while_timing_control.pl - test_regress/t/t_x_assign_0.pl - test_regress/t/t_x_assign_1.pl - test_regress/t/t_x_assign_unique_0.pl - test_regress/t/t_x_assign_unique_1.pl - ); - -my $root = ".."; -my $Debug; - -my $Exempt_Files_List_Re = '^(' . join('|', (map { quotemeta $_ } @Exempt_Files_List)) . ")"; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - my $out = `cd $root && git ls-files --exclude-standard`; - my $year = strftime("%Y", localtime); - my %files; - $out =~ s/\s+/ /g; - foreach my $filename (split /\s+/, $out) { - next if $filename =~ /$Exempt_Files_Re/; - next if $filename =~ /$Exempt_Files_List_Re/; - $files{$filename} = 1; - } - - # Exempt files added before Jun 1 2023, when we added this check - # List hardcoded now, but obtained from: - # $out = `cd $root && git ls-tree -r \`git rev-list -1 --before="Jun 1 2023" HEAD\` --name-only`; - my %oldFile; - foreach my $file (@Exempt_Files_Copyright) { $oldFile{$file} = 1; } - - foreach my $file (sort keys %files) { - my $filename = catfile($root, $file); - next if !-r $filename; - my $fh = IO::File->new("<$filename") or error("$! $filename"); - next if !$fh; - my $spdx; - my $copyright; - my $release; - while (my $line = $fh->getline) { - if ($line =~ /SPDX-License-Identifier:/) { - $spdx = $line; - } elsif ($line =~ /Copyright 20[0-9][0-9]/) { - $copyright = $line; - if ($line =~ /Wilson Snyder/) { - } elsif ($oldFile{$file} && $line =~ /Antmicro|Geza Lore|Todd Strader/) { - } elsif ($file =~ /$Exempt_Author_Re/) { - } else { - my $yeardash = ($file =~ m!test_regress/t!) ? $year : $year."-".$year; - warn " ".$copyright; - error("$file: Please use standard 'Copyright $yeardash by Wilson Snyder'"); - } - } elsif ($line =~ m!Creative Commons Public Domain! - || $line =~ m!freely copied and/or distributed! - || $line =~ m!placed into the Public Domain!) { - $release = 1; - } - } - my $release_note; - if ($release && $file !~ /$Release_Ok_Re/) { - $release_note = " (has copyright release, but not part of $Release_Ok_Re)"; - } - if (!$copyright && (!$release || $release_note)) { - error("$file: Please add standard 'Copyright $year ...', similar to in other files" . $release_note); - } - if (!$spdx) { - error("$file: Please add standard 'SPDX-License_Identifier: ...', similar to in other files"); - } - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_copyright.py b/test_regress/t/t_dist_copyright.py new file mode 100755 index 000000000..33f1ea63f --- /dev/null +++ b/test_regress/t/t_dist_copyright.py @@ -0,0 +1,119 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import datetime + +test.scenarios('dist') + +RELEASE_OK_RE = r'(^test_regress/t/.*\.(cpp|h|mk|sv|v|vlt)|^test_regress/t_done/|^examples/)' + +EXEMPT_AUTHOR_RE = r'(^ci/|^nodist/fastcov.py|^nodist/fuzzer|^test_regress/t/.*\.(cpp|h|v|vlt)$)' + +EXEMPT_FILES_RE = r'(^\.|/\.|\.gitignore$|\.dat|\.gprof|\.mem|\.out$|\.png$|\.tree|\.vc$|\.vcd$|^\.)' + +EXEMPT_FILES_LIST = """ + Artistic + CITATION.cff + CPPLINT.cfg + LICENSE + README.rst + ci/ci-win-compile.ps1 + ci/ci-win-test.ps1 + ci/codecov + docs/CONTRIBUTING.rst + docs/CONTRIBUTORS + docs/README.rst + docs/_static + docs/gen + docs/spelling.txt + docs/verilated.dox + include/gtkwave + include/vltstd + install-sh + src/mkinstalldirs + test_regress/t/t_altera_lpm.v + test_regress/t/t_flag_f__3.v + test_regress/t/t_fuzz_eof_bad.v + test_regress/t/t_incr_void.v + test_regress/t/t_uvm_pkg_all.vh + test_regress/t/t_uvm_pkg_todo.vh + test_regress/t/tsub/t_flag_f_tsub.v + test_regress/t/tsub/t_flag_f_tsub_inc.v + verilator.pc.in + """ + +root = ".." + +Exempt_Files_List_Re = list(map(re.escape, EXEMPT_FILES_LIST.split())) +Exempt_Files_List_Re = '^(' + '|'.join(Exempt_Files_List_Re) + ")" +# pprint(Exempt_Files_List_Re) + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +cmd = "cd " + root + " && git ls-files --exclude-standard" +out = test.run_capture(cmd) + +year = datetime.datetime.now().year + +files = {} +out = re.sub(r'\s+', ' ', out) +for filename in out.split(): + if re.search(EXEMPT_FILES_RE, filename): + continue + if re.search(Exempt_Files_List_Re, filename): + continue + files[filename] = True + +for filename in files: + open_filename = os.path.join(root, filename) + if not os.path.exists(open_filename): + continue + with open(open_filename, 'r', encoding="utf8") as fh: + spdx = None + copyright_msg = None + release = False + for line in fh: + line = line.rstrip() + if 'SPDX-License-Identifier:' in line: + spdx = line + elif re.search(r'Copyright 20[0-9][0-9]', line): + copyright_msg = line + if 'Wilson Snyder' in line: + pass + elif re.search(r'\.pl$', filename): + pass + elif re.search(EXEMPT_AUTHOR_RE, filename): + pass + else: + if "test_regress/t" in filename: + yeardash = str(year) + else: + yeardash = str(year) + '-' + str(year) + print(" " + copyright_msg) + test.error_keep_going(filename + ": Please use standard 'Copyright " + + yeardash + " by Wilson Snyder'") + elif (('Creative Commons Public Domain' in line) + or ('freely copied and/or distributed' in line) + or ('placed into the Public Domain' in line)): + release = True + + release_note = "" + if not re.search(RELEASE_OK_RE, filename): + release_note = " (has copyright release, but not part of " + RELEASE_OK_RE + ")" + if not copyright_msg and (not release or release_note): + test.error_keep_going(filename + ": Please add standard 'Copyright " + str(year) + + " ...', similar to in other files" + release_note) + if not spdx: + test.error_keep_going( + filename + + ": Please add standard 'SPDX-License_Identifier: ...', similar to in other files") + +test.passes() diff --git a/test_regress/t/t_dist_cppstyle.pl b/test_regress/t/t_dist_cppstyle.pl deleted file mode 100755 index 222addde0..000000000 --- a/test_regress/t/t_dist_cppstyle.pl +++ /dev/null @@ -1,81 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Primitive C++ style checker -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; - -### Must trim output before and after our file list -my %files = %{get_source_files($root)}; - -foreach my $file (sort keys %files) { - my $filename = "$root/$file"; - next if !-f $filename; # git file might be deleted but not yet staged - next unless $file =~ /\.(h|c|cpp)(\.in)?$/; - next if $file =~ /gtkwave/; - - my $contents = file_contents($filename); - - checkPattern($filename, $contents, - qr/[^\/]*virtual[^{};]+override/, - "'virtual' keyword is redundant on 'override' method"); - - checkPattern($filename, $contents, - qr/ \s*(\w+ )*\s*(inline) [^;]+?\([^;]*?\)[^;]+?(?:{|:|=\s*default)/, - "'inline' keyword is redundant on method definitions inside classes"); - - checkPattern($filename, $contents, - qr/(?\n)inline \S+ [^;:(]+::[^;:(]+\([^;]*\)[^;]+{/, - "Use 'inline' only on declaration inside classes (except for template specializatoins)"); - - if ($file =~ /\.(c|cpp)/) { - checkPattern($filename, $contents, - qr/(\w+\s+)*(inline)/, - "'inline' keyword is on functions defined in .cpp files"); - } -} - -ok(1); -1; - -sub get_source_files { - my $root = shift; - my $git_files = `cd $root && git ls-files`; - print "MF $git_files\n" if $Self->{verbose}; - my %files; - foreach my $file (split /\s+/, $git_files) { - next if $file eq ''; - $files{$file} |= 1; - } - return \%files; -} - -sub checkPattern { - my $filename = shift; - my $contents = shift; - my $pattern = shift; - my $message = shift; - - my $lineno = 0; - my $buffer; - foreach my $line (split(/\n/, $contents . "\n\n")) { - ++$lineno; - if ($line ne "") { - # Don't do whole file at once - see issue #4085 - # Build a buffer until a newline so we check a block at a time. - $buffer .= $line . "\n"; - next; - } - if ($buffer =~ s/.*?^($pattern)//sm) { - error("$filename:$lineno: $message"); - } - $buffer = ""; - } -} diff --git a/test_regress/t/t_dist_cppstyle.py b/test_regress/t/t_dist_cppstyle.py new file mode 100755 index 000000000..40815115d --- /dev/null +++ b/test_regress/t/t_dist_cppstyle.py @@ -0,0 +1,77 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Primitive C++ style checker +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + + +def get_source_files(root): + git_files = test.run_capture("cd " + root + " && git ls-files") + if test.verbose: + print("MF " + git_files) + files = {} + for filename in git_files.split(): + if filename == '': + continue + files[filename] = True + return files + + +def check_pattern(filename, contents, pattern, not_pattern, message): + lineno = 0 + buffer = "\n" + for line in contents.splitlines(): + lineno += 1 + if line != "": + # Don't do whole file at once - see issue #4085 + # Build a buffer until a newline so we check a block at a time. + buffer += line + "\n" + continue + if re.search(r"\n" + pattern, buffer): + if not not_pattern or not re.search(not_pattern, buffer): + test.error(filename + ":" + str(lineno) + ": " + message) + buffer = "\n" + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +files = get_source_files(root) + +for filename in sorted(files.keys()): + filename = os.path.join(root, filename) + if not os.path.exists(filename): # git file might be deleted but not yet staged + continue + if not re.search(r'\.(h|c|cpp)(\.in)?$', filename): + continue + if '/gtkwave/' in filename: + continue + + contents = test.file_contents(filename) + "\n\n" + + check_pattern(filename, contents, r"[^\']*virtual[^{};\n]+override", None, + "'virtual' keyword is redundant on 'override' method") + + check_pattern(filename, contents, + r' \s*(\w+ )*\s*(inline) [^;]+?\([^;]*?\)[^;]+?(?:{|:|=\s*default)', None, + "'inline' keyword is redundant on method definitions inside classes") + + check_pattern( + filename, contents, r'inline \S+ [^;:(]+::[^;:(]+\([^;]*\)[^;]+{', r'template', + "Use 'inline' only on declaration inside classes" + " (except for template specializations)") + + if re.search(r'\.(c|cpp)', filename): + check_pattern(filename, contents, r'(\w+\s+)*(inline)', None, + "'inline' keyword is on functions defined in .cpp files") + +test.passes() diff --git a/test_regress/t/t_dist_docs_style.pl b/test_regress/t/t_dist_docs_style.pl deleted file mode 100755 index 55ce56858..000000000 --- a/test_regress/t/t_dist_docs_style.pl +++ /dev/null @@ -1,68 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Primitive C++ style checker -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; - -### Must trim output before and after our file list -my %files = %{get_source_files($root)}; - -foreach my $file (sort keys %files) { - my $filename = "$root/$file"; - next if !-f $filename; # git file might be deleted but not yet staged - next unless $file =~ /\.rst$/; - - my $contents = file_contents($filename); - - checkPattern($filename, $contents, - qr/.*[a-z](?{verbose}; - my %files; - foreach my $file (split /\s+/, $git_files) { - next if $file eq ''; - $files{$file} |= 1; - } - return \%files; -} - -sub checkPattern { - my $filename = shift; - my $contents = shift; - my $pattern = shift; - my $message = shift; - - my $offset = 0; - my $buffer = $contents; - while ($buffer =~ s/.*?^($pattern)//sm) { - my $lineno = offset_to_lineno($contents, $offset + $-[-1]); - $offset += $+[1]; - error("$filename:$lineno: $message"); - } -} - -sub offset_to_lineno { - my $contents = shift; - my $offset = shift; - my $count = (substr $contents, 0, $offset) =~ tr/\n//; - return $count + 1; -} diff --git a/test_regress/t/t_dist_docs_style.py b/test_regress/t/t_dist_docs_style.py new file mode 100755 index 000000000..6acdf983e --- /dev/null +++ b/test_regress/t/t_dist_docs_style.py @@ -0,0 +1,61 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Primitive C++ style checker +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + + +def get_source_files(root): + git_files = test.run_capture("cd " + root + " && git ls-files") + if test.verbose: + print("MF " + git_files) + files = {} + for filename in git_files.split(): + if filename == '': + continue + files[filename] = True + return files + + +def check_pattern(filename, contents, pattern, message): + lineno = 1 + buf = contents + while True: + m = re.match(r'^(.*?^(' + pattern + '))(.*)', buf) + if not m: + break + lineno += m.group(1).count("\n") + buf = m.group(3) + test.error(filename + ":" + str(lineno) + ": " + message) + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +### Must trim output before and after our file list +files = get_source_files(root) + +for filename in sorted(files.keys()): + filename = os.path.join(root, filename) + if not os.path.exists(filename): # git file might be deleted but not yet staged + continue + if not re.search(r'\.rst$', filename): + continue + + contents = test.file_contents(filename) + + check_pattern(filename, contents, r'.*[a-z](? 1); - -my $root = ".."; - -my @Waivers = - ( - '+verilator+prof+threads+file+', # Deprecated - '+verilator+prof+threads+start+', # Deprecated - '+verilator+prof+threads+window+', # Deprecated - '-fno-', # Documented differently - '-no-lineno', # Deprecated - '-no-order-clock-delay', # Deprecated - '-prof-threads', # Deprecated - ); - -my %sums = %{get_summary_opts($root)}; -my %docs = %{get_docs_opts($root)}; - -my %both = (%sums, %docs); -my %waiver = map { $_ => 1; } @Waivers; -foreach my $opt (sort keys %both) { - next if $waiver{$opt}; - my $sum_ok = 0; - my $docs_ok = 0; - for my $alt (alt_names($opt)) { - $sum_ok = 1 if $sums{$alt}; - print "$sum_ok SAC '$opt' -> '$alt'\n" if $Self->{verbose}; - } - $sum_ok = 1 if $opt =~ /-fno-/; # Minimal-documented optimization option - for my $alt (alt_names($opt)) { - $docs_ok = 1 if $docs{$alt}; - print "$sum_ok DAC '$opt' -> '$alt'\n" if $Self->{verbose}; - } - if (!$sum_ok) { - error($docs{$opt}.": Option documented in docs/guide '$opt'" - ." not found in bin/* ARGUMENT SUMMARY documentation"); - } elsif (!$docs_ok) { - error($sums{$opt}.": Option documented in bin/ ARGUMENT SUMMARY '$opt'" - ." not found in docs/guide documentation"); - } else { - print($docs{$opt}.": ok '$opt'\n") if $Self->{verbose}; - } -} - -ok(1); -1; - -sub get_summary_opts { - my $root = shift; - my %args = (); - foreach my $file (glob "$root/bin/*") { - my $fc = file_contents($file); - my $on = 0; - my $lineno = 0; - foreach my $line (split(/\n/, $fc)) { - ++$lineno; - if ($line =~ /ARGUMENT SUMMARY/) { - $on = 1; - } elsif ($line =~ /=head1/) { - $on = 0; - } elsif ($on && $line =~ /^\s+([---+]+[^ ]+)/) { - my $opt = opt_clean($1); - print "S '$opt' $line\n" if $Self->{verbose}; - $args{$opt} = "$file:$lineno"; - } elsif ($line =~ /parser.add_argument\('([---+][^']+)'/) { - my $opt = opt_clean($1); - print "S '$opt' $line\n" if $Self->{verbose}; - $args{$opt} = "$file:$lineno"; - } - } - } - return \%args; -} - -sub get_docs_opts { - my $root = shift; - my %args = (); - foreach my $file (glob "$root/docs/guide/*.rst") { - my $fc = file_contents($file); - my $lineno = 0; - foreach my $line (split(/\n/, $fc)) { - ++$lineno; - if ($line =~ /option:: ([---+]+[^ `]+)/ - || $line =~ /:vlopt:`[^`]+ <([^>]+)>/ - || $line =~ /:vlopt:`([---+]+[^ `]+)/) { - my $opt = opt_clean($1); - print "D '$opt' $line\n" if $Self->{verbose}; - $args{$opt} = "$file:$lineno"; - } - } - } - return \%args; -} - -sub opt_clean { - my $opt = shift; - $opt =~ s/--/-/; - $opt =~ s/<.*//; - $opt =~ s/\\//; - return $opt; -} - -sub alt_names { - my $opt = shift; - my @opts = ($opt); - push @opts, "-no".$opt if $opt =~ /^-/; - push @opts, $1 if $opt =~ /^-no(-.*)/; - return @opts; -} diff --git a/test_regress/t/t_dist_docs_summary.py b/test_regress/t/t_dist_docs_summary.py new file mode 100755 index 000000000..ad2ff316c --- /dev/null +++ b/test_regress/t/t_dist_docs_summary.py @@ -0,0 +1,132 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Primitive C++ style checker +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +Waivers = [ + '+verilator+prof+threads+file+', # Deprecated + '+verilator+prof+threads+start+', # Deprecated + '+verilator+prof+threads+window+', # Deprecated + '-fno-', # Documented differently + '-no-lineno', # Deprecated + '-no-order-clock-delay', # Deprecated + '-prof-threads', # Deprecated) +] + + +def get_summary_opts(root): + args = {} + for filename in test.glob_some(root + "/bin/*"): + with open(filename, "r", encoding="latin-1") as fh: + on = False + lineno = 0 + for line in fh: + lineno += 1 + line = line.rstrip() + m1 = re.search(r'^\s+((-|\+)+[^ ]+)', line) + m2 = re.search(r"parser.add_argument\('((-|\+)[^']+)'", line) + if re.search(r'ARGUMENT SUMMARY', line): + on = True + elif re.search(r'=head1', line): + on = False + elif on and m1: + opt = opt_clean(m1.group(1)) + if test.verbose: + print("S '" + opt + "' " + line) + args[opt] = filename + ":" + str(lineno) + elif m2: + opt = opt_clean(m2.group(1)) + if test.verbose: + print("S '" + opt + "' " + line) + args[opt] = filename + ":" + str(lineno) + return args + + +def get_docs_opts(root): + args = {} + for filename in test.glob_some(root + "/docs/guide/*.rst"): + with open(filename, "r", encoding="latin-1") as fh: + lineno = 0 + for line in fh: + lineno += 1 + line = line.rstrip() + m = re.search(r'option:: ((-|\+)+[^ `]+)', line) + if not m: + m = re.search(r':vlopt:`[^`]+ <([^>]+)>', line) + if not m: + m = re.search(r':vlopt:`((-|\+)+[^ `]+)', line) + if m: + opt = opt_clean(m.group(1)) + if test.verbose: + print("D '" + opt + "' " + line) + args[opt] = filename + ":" + str(lineno) + return args + + +def opt_clean(opt): + opt = re.sub(r'--', '-', opt) + opt = re.sub(r'<.*', '', opt) + opt = re.sub(r'\\', '', opt) + return opt + + +def alt_names(opt): + opts = [opt] + if re.search(r'^-', opt): + opts.append("-no" + opt) + m = re.search(r'^-no(-.*)', opt) + if m: + opts.append(m.group(1)) + return opts + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +sums = get_summary_opts(root) +docs = get_docs_opts(root) + +both = {} +both.update(sums) +both.update(docs) + +waiver = {k: 1 for k in Waivers} + +for opt in sorted(both.keys()): + if opt in waiver: + continue + sum_ok = False + docs_ok = False + for alt in alt_names(opt): + if alt in sums: + sum_ok = True + if test.verbose: + print(str(sum_ok) + " SAC '" + opt + "' -> '" + alt + "'") + if re.search(r'-fno-', opt): # Minimal-documented optimization option + sum_ok = True + for alt in alt_names(opt): + if alt in docs: + docs_ok = True + if test.verbose: + print(str(docs_ok) + " DAC '" + opt + "' -> '" + alt + "'") + + if not sum_ok: + test.error(docs[opt] + ": Option documented in docs/guide '" + opt + + "' not found in bin/* ARGUMENT SUMMARY documentation") + elif not docs_ok: + test.error(sums[opt] + ": Option documented in bin/ ARGUMENT SUMMARY '" + opt + + "' not found in docs/guide documentation") + elif test.verbose: + print(": ok '" + opt) + +test.passes() diff --git a/test_regress/t/t_dist_error_format.pl b/test_regress/t/t_dist_error_format.pl deleted file mode 100755 index dd0b32dfa..000000000 --- a/test_regress/t/t_dist_error_format.pl +++ /dev/null @@ -1,79 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - formats(); -} - -ok(1); - -# Check all error messages match our standard format -# This assumes .out files cover all important errors - -sub formats { - my $files = "../test_regress/t/*.out"; - my %warns; - my $lnmatch = 0; - foreach my $file (glob $files) { - my $wholefile = file_contents($file); - $file =~ s!.*/!!; - if ($wholefile =~ /Exiting due to/ - || $wholefile =~ /%(Error|Warning)/) { - my $lineno = 0; - foreach my $line (split /\n/, $wholefile) { - ++$lineno; - $line =~ s/(\$display|\$write).*\".*%(Error|Warning)//; - if ($line =~ /(Error|Warning)/ - && $line !~ /^\s*{verbose}; - } - # Error no fileline - # For testing only: we assume any : is single quoted - elsif ($match =~ /^%(Error|Warning)(-[A-Z0-9_]+)?: [^:']+/) { - print "ok-en $file $line\n" if $Self->{verbose}; - } - else { - #print "FF $file $line\n"; - $warns{$file . ":" . $lineno} = - "Non-standard warning/error: $file:$lineno: $line"; - } - } - } - } - } - $lnmatch or error("Check line number regexp is correct, no matches"); - if (keys %warns) { - # First warning lists everything as that's shown in the driver summary - error($summary . " ", join(' ', sort keys %warns)); - foreach my $file (sort keys %warns) { - error($warns{$file}); - } - } -} - -1; diff --git a/test_regress/t/t_dist_error_format.py b/test_regress/t/t_dist_error_format.py new file mode 100755 index 000000000..473dffb57 --- /dev/null +++ b/test_regress/t/t_dist_error_format.py @@ -0,0 +1,70 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +# Check all error messages match our standard format +# This assumes .out files cover all important errors + + +def formats(): + files = root + "/test_regress/t/*.out" + warns = {} + lnmatch = 0 + for filename in test.glob_some(files): + wholefile = test.file_contents(filename) + filename = os.path.basename(filename) + if re.search(r'(Exiting due to|%Error|%Warning)', wholefile): + lineno = 0 + for line in wholefile.splitlines(): + lineno += 1 + line = re.sub(r'(\$display|\$write).*\".*%(Error|Warning)', '', line) + if (re.search(r'(Error|Warning)', line) + and not re.search(r'^\s* 1); - -my $root = ".."; -my $Debug; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - ### Must trim output before and after our file list - my $files = `cd $root && git ls-files --exclude-standard`; - print "ST $files\n" if $Debug; - my %names; - - $files =~ s/\s+/ /g; - my @batch; - my $n = 0; - my $re = qr/(FIX[M]E|BO[Z]O)/; - foreach my $file (split /\s+/, $files) { - my $filename = catfile($root, $file); - next if !-r $filename; - my $wholefile = file_contents($filename); - if ($wholefile =~ /$re/) { - $names{$file} = 1; - } - } - if (scalar(%names) >= 1) { - error("Files with FIX" . "MEs: ", join(' ', sort keys %names)); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_fixme.py b/test_regress/t/t_dist_fixme.py new file mode 100755 index 000000000..168ab7e9e --- /dev/null +++ b/test_regress/t/t_dist_fixme.py @@ -0,0 +1,41 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +### Must trim output before and after our file list +files = test.run_capture("cd " + root + " && git ls-files --exclude-standard") +if test.verbose: + print("ST " + files) + +names = {} +files = re.sub(r'\s+', ' ', files) + +regex = r'(FIX[M]E|BO[Z]O)' +for filename in files.split(): + if re.search(regex, filename): + names[filename] = True + filename = os.path.join(root, filename) + if not os.path.exists(filename): + continue + wholefile = test.file_contents(filename) + if re.search(regex, wholefile): + names[filename] = True + +if len(names): + test.error("Files with FIX" + "MEs: " + ' '.join(sorted(names.keys()))) + +test.passes() diff --git a/test_regress/t/t_dist_getsetorder.pl b/test_regress/t/t_dist_getsetorder.pl deleted file mode 100755 index f06501759..000000000 --- a/test_regress/t/t_dist_getsetorder.pl +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Hacky import order checker, used to ensure all getters -# come before setters for consistent codegen when using autocxx (#5182) -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; - -### Must trim output before and after our file list -my %files = %{get_source_files($root)}; - -foreach my $file (sort keys %files) { - my $filename = "$root/$file"; - next if !-f $filename; # git file might be deleted but not yet staged - next unless $file =~ /include.*verilated.*\.[ch].*$/; - next if $file =~ /gtkwave/; - - my $contents = file_contents($filename); - my %seen_setters; - my %seen_getters; - foreach my $line (split(/\n/, $contents . "\n\n")) { - next if $line =~ /^\s*\/\//; # skip commented lines - if ($line =~ /\s*void\s+([a-zA-Z0-9_]+)\([a-zA-Z0-9_]+.*/) { - my $setter_name = $1; - $seen_setters{$setter_name} = 1; - } else { - next unless $line =~ /\s*[a-zA-Z0-9_]+\s+([a-zA-Z0-9_]+)\(\s*\)/; - my $getter_name = $1; - if ($file =~ /verilated_sc_trace/ and $getter_name == "cycle") { - next; # hardcoded check for cycle() which looks like a setter but isn't - } - if (exists $seen_setters{$getter_name} and not (exists $seen_getters{$getter_name})) { - error("$file: '$getter_name()' came after its setter; suggest swap order"); - } - $seen_getters{$getter_name} = 1; - } - } -} - -ok(1); -1; - -sub get_source_files { - my $root = shift; - my $git_files = `cd $root && git ls-files`; - print "MF $git_files\n" if $Self->{verbose}; - my %files; - foreach my $file (split /\s+/, $git_files) { - next if $file eq ''; - $files{$file} |= 1; - } - return \%files; -} diff --git a/test_regress/t/t_dist_getsetorder.py b/test_regress/t/t_dist_getsetorder.py new file mode 100755 index 000000000..350c77136 --- /dev/null +++ b/test_regress/t/t_dist_getsetorder.py @@ -0,0 +1,78 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Hacky import order checker, used to ensure all getters +# come before setters for consistent codegen when using autocxx (#5182) +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + + +def get_source_files(root): + git_files = test.run_capture("cd " + root + " && git ls-files") + if test.verbose: + print("MF " + git_files) + files = {} + for filename in git_files.split(): + if filename == '': + continue + files[filename] = True + return files + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +### Must trim output before and after our file list +files = get_source_files(root) + +for filename in sorted(files.keys()): + filename = os.path.join(root, filename) + if not os.path.exists(filename): # git file might be deleted but not yet staged + continue + if not re.search(r'include.*verilated.*\.[ch].*$', filename): + continue + if re.search(r'gtkwave', filename): + continue + + contents = test.file_contents(filename) + "\n\n" + seen_setters = {} + seen_getters = {} + lineno = 0 + for line in contents.splitlines(): + lineno += 1 + if re.search(r'^\s*\/\/', line): # skip commented lines + continue + #print("L "+line) + if re.search(r'^class', line): + seen_setters = {} + seen_getters = {} + if test.verbose: + print("C " + line) + continue + m = re.search(r'\s*void\s+([a-zA-Z0-9_]+)\([a-zA-Z0-9_]+.*', line) + if m: + setter_name = m.group(1) + if test.verbose: + print("S " + setter_name + " " + line) + seen_setters[setter_name] = True + m = re.search(r'\s*[a-zA-Z0-9_]+\s+([a-zA-Z0-9_]+)\(\s*\)', line) + if m: + getter_name = m.group(1) + if getter_name == "cycle" and re.search(r'verilated_sc_trace', filename): + continue # hardcoded check for cycle() which looks like a setter but isn't + if test.verbose: + print("G " + setter_name + " " + line) + if getter_name in seen_setters and getter_name not in seen_getters: + test.error(filename + ":" + str(lineno) + ": '" + getter_name + + "()' came after its setter; swap order") + seen_getters[getter_name] = True + +test.passes() diff --git a/test_regress/t/t_dist_header_cc.pl b/test_regress/t/t_dist_header_cc.pl deleted file mode 100755 index e51a12901..000000000 --- a/test_regress/t/t_dist_header_cc.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - - -use Cwd; - -scenarios(dist => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - run(cmd => ["cd $root/src/obj_dbg && $ENV{MAKE} -j 4 -k -f ../Makefile_obj VL_NOOPT=1 header_cc"], - check_finished => 0); -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_header_cc.py b/test_regress/t/t_dist_header_cc.py new file mode 100755 index 000000000..c25395442 --- /dev/null +++ b/test_regress/t/t_dist_header_cc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.run(cmd=[ + "cd " + root + "/src/obj_dbg && " + os.environ['MAKE'] + + " -j 4 -k -f ../Makefile_obj VL_NOOPT=1 header_cc" +], + check_finished=False) + +test.passes() diff --git a/test_regress/t/t_dist_inctree.pl b/test_regress/t/t_dist_inctree.pl deleted file mode 100755 index acbbaa079..000000000 --- a/test_regress/t/t_dist_inctree.pl +++ /dev/null @@ -1,86 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; -my %Files; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - print "-Test is only for occasional cleanup, never completely clean\n"; - #inctree(); -} - -ok(1); - -sub inctree { - # Note do not do test_regress, as VPI files need to compile without verilatedos.h - my $files = "src/*.c* src/*.h include/*.c* include/*.h"; - my $cmd = "cd $root && grep -n -P '^(# *include)' $files | sort"; - print "C $cmd\n"; - my $grep = `$cmd`; - foreach my $line (split /\n/, $grep) { - if ($line =~ /^(\S+):(\d+):#\s*include\s*(\S+)/) { - my $filename = $1; my $line = $2 + 0; my $inc = $3; - (my $base = $filename) =~ s!.*/(.*?)!$1!; - $inc =~ s/[<>"]//g; - $Files{$base}{filename} = $filename; - $Files{$base}{incs}{$inc} = $line; - #print "I $fileline $base $inc\n"; - } else { - warn "%Warning: Strange line: $line\n"; - } - } - foreach my $base (keys %Files) { - _inctree_recurse($base); - } - #use Data::Dumper; print Dumper(\%Files); - foreach my $base (sort keys %Files) { - my $fileref = $Files{$base}; - foreach my $subinc (sort keys %{$fileref->{incs}}) { - my $subline = $fileref->{incs}{$subinc}; - if (my $subsubinfo = $fileref->{subincs}{$subinc}) { - if ($subsubinfo->{line} < $subline) { - error("$fileref->{filename}:$subline: Include of $subinc is also included by earlier include ($subsubinfo->{name})"); - } - } - } - } -} - -sub _inctree_recurse { - my $basename = shift; - my $fileref = $Files{$basename}; - - return if $fileref->{subincs}; - $fileref->{subincs} = {}; - foreach my $subinc (keys %{$fileref->{incs}}) { - _inctree_recurse($subinc); - } - foreach my $subinc (keys %{$fileref->{incs}}) { - my $subline = $fileref->{incs}{$subinc}; - foreach my $subsubinc (keys %{$Files{$subinc}{incs}}) { - if (!$fileref->{subincs}{$subsubinc} - || $fileref->{subincs}{$subsubinc}{line} < $subline) { - $fileref->{subincs}{$subsubinc} - = {line => $subline, - name => $subinc, }; - } - } - } -} - -1; diff --git a/test_regress/t/t_dist_install.pl b/test_regress/t/t_dist_install.pl deleted file mode 100755 index 1c92e19ac..000000000 --- a/test_regress/t/t_dist_install.pl +++ /dev/null @@ -1,56 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use Cwd; - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - my $cwd = getcwd(); - my $destdir = "$cwd/" . $Self->{obj_dir}; - # Start clean - run(cmd => ["rm -rf $destdir && mkdir -p $destdir"], - check_finished => 0); - # Install into temp area - print "Install...\n"; - run(cmd => ["cd $root && $ENV{MAKE} DESTDIR=$destdir install-all"], - check_finished => 0); - - # Check we can run a test - # Unfortunately the prefix was hardcoded in the exec at a different place, - # so we can't do much here. - #print "Check install...\n"; - - # Uninstall - print "Uninstall...\n"; - run(cmd => ["cd $root && $ENV{MAKE} DESTDIR=$destdir uninstall"], - check_finished => 0); - - # Check empty - my @files; - $finds = `find $destdir -type f -print`; - foreach my $file (split /\n/, $finds) { - next if $file =~ /\.status/; # Made by driver.pl, not Verilator - print "\tLEFT: $file\n"; - $file =~ s!^$cwd!.!; - push @files, $file; - } - if ($#files >= 0) { - error("Uninstall missed files: ", join(' ', @files)); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_install.py b/test_regress/t/t_dist_install.py new file mode 100755 index 000000000..84bfabc16 --- /dev/null +++ b/test_regress/t/t_dist_install.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +cwd = os.getcwd() +destdir = cwd + "/" + test.obj_dir + +# Start clean +test.run(cmd=["rm -rf " + destdir + " && mkdir -p " + destdir], check_finished=False) + +# Install into temp area +print("Install...") +test.run(cmd=["cd " + root + " && " + os.environ["MAKE"] + " DESTDIR=" + destdir + " install-all"], + check_finished=False) + +# Check we can run a test +# Unfortunately the prefix was hardcoded in the exec at a different place, +# so we can't do much here. +#print("Check install...") + +# Uninstall +print("Uninstall...\n") +test.run(cmd=["cd " + root + " && " + os.environ["MAKE"] + " DESTDIR=" + destdir + " uninstall"], + check_finished=False) + +# Check empty +files = [] +finds = test.run_capture("find " + destdir + " -type f -print") +for filename in finds.split(): + if re.search(r'\.status', filename): # Made by driver.py, not Verilator + continue + print("\tLEFT: " + filename) + filename = re.sub(r'^' + re.escape(cwd), '.', filename) + files.append(filename) + +if len(files) > 0: + test.error("Uninstall missed files: " + ' '.join(files)) + +test.passes() diff --git a/test_regress/t/t_dist_lint_py.py b/test_regress/t/t_dist_lint_py.py new file mode 100755 index 000000000..8c8b9a2f6 --- /dev/null +++ b/test_regress/t/t_dist_lint_py.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if 'VERILATOR_TEST_NO_LINT_PY' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_LINT_PY") +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.run(cmd=["cd " + root + " && make lint-py"]) + +test.passes() diff --git a/test_regress/t/t_dist_pl.py b/test_regress/t/t_dist_pl.py new file mode 100755 index 000000000..f0bc335a2 --- /dev/null +++ b/test_regress/t/t_dist_pl.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +for pl in sorted(glob.glob(root + "/test_regress/t/*.pl")): + if 'bootstrap.pl' in pl: + continue + py = re.sub(r'\.pl', '.py', pl) + test.error_keep_going(pl + ":1: Perl test needs conversion into a Python test '" + + os.path.basename(py) + "'") + +test.passes() diff --git a/test_regress/t/t_dist_portability.pl b/test_regress/t/t_dist_portability.pl deleted file mode 100755 index c9db4eb9a..000000000 --- a/test_regress/t/t_dist_portability.pl +++ /dev/null @@ -1,111 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - printfll(); - cstr(); - vsnprintf(); - final(); -} - -ok(1); - -sub printfll { - my $files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h"; - my $cmd = "cd $root && fgrep -n ll $files | sort"; - print "C $cmd\n"; - my $grep = `$cmd`; - my %names; - foreach my $line (split /\n/, $grep) { - next if $line !~ /%[a-z0-9]*ll/; - next if $line !~ /\blong\S+long\b/; # Assume a cast - print "$line\n"; - if ($line =~ /^([^:]+)/) { - $names{$1} = 1; - } else { - $names{UNKNOWN} = 1; - } - } - if (keys %names) { - error("Files with %ll instead of PRIx64: ", join(' ', sort keys %names)); - } -} - -sub cstr { - my $files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h"; - my $cmd = "cd $root && grep -n -P 'c_str|begin|end' $files | sort"; - print "C $cmd\n"; - my $grep = `$cmd`; - my %names; - foreach my $line (split /\n/, $grep) { - if ($line =~ /^([^:]+)[^"]*\(\)[a-z0-9_().->]*[.->]+(c_str|r?begin|r?end)\(\)/) { - next if $line =~ /lintok-begin-on-ref/; - print "$line\n"; - $names{$1} = 1; - } - } - if (keys %names) { - error("Files with potential c_str() lifetime issue: ", join(' ', sort keys %names)); - } -} - -sub vsnprintf { - # Note do not do test_regress, as VPI files need to compile without verilatedos.h - my $files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c*"; - my $cmd = "cd $root && grep -n -P '(snprintf|vsnprintf)' $files | sort"; - print "C $cmd\n"; - my $grep = `$cmd`; - my %names; - foreach my $line (split /\n/, $grep) { - if ($line =~ /\b(snprintf|vsnprintf)\b/) { - next if $line =~ /# *define\s*VL_V?SNPRINTF/; - print "$line\n"; - $names{$1} = 1; - } - } - if (keys %names) { - error("Files with vsnprintf, use VL_VSNPRINTF: ", join(' ', sort keys %names)); - } -} - -sub final { - # Note do not do test_regress, as VPI files need to compile without verilatedos.h - my $files = "src/*.c* src/*.h include/*.c* include/*.h"; - my $cmd = "cd $root && grep -n -P '(class|struct)' $files | sort"; - print "C $cmd\n"; - my $grep = `$cmd`; - my %names; - foreach my $line (split /\n/, $grep) { - if ($line =~ /:\s*(class|struct) /) { - next if $line =~ /final|VL_NOT_FINAL/; - next if $line =~ /{}/; # e.g. 'class Foo {};' - next if $line =~ /;/; # e.g. 'class Foo;' - next if $line =~ /(class|struct)\s+{/; # e.g. anon 'class {' - next if $line =~ /struct std::/; - next if $line !~ /{/; - print "$line\n"; - $names{$1} = 1; - } - } - if (keys %names) { - error("Files with classes without final/VL_NOT_FINAL: ", join(' ', sort keys %names)); - } -} - -1; diff --git a/test_regress/t/t_dist_portability.py b/test_regress/t/t_dist_portability.py new file mode 100755 index 000000000..d76293db6 --- /dev/null +++ b/test_regress/t/t_dist_portability.py @@ -0,0 +1,100 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + + +def line_filename(line): + m = re.search(r'^([^:]+)', line) + return m.group(1) if m else 'UNKNOWN' + + +def printfll(): + files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h" + cmd = "cd " + root + " && fgrep -n ll " + files + " | sort" + grep = test.run_capture(cmd, check=False) + names = {} + for line in grep.splitlines(): + if not re.search(r'%[a-z0-9]*ll', line): + continue + if re.search(r'lintok-format-ll', line): + continue + print(line) + names[line_filename(line)] = True + if len(names): + test.error("Files with %ll instead of PRIx64: " + ' '.join(sorted(names.keys()))) + + +def cstr(): + files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h" + cmd = "cd " + root + " && grep -n -P 'c_str|begin|end' " + files + " | sort" + grep = test.run_capture(cmd, check=False) + names = {} + for line in grep.splitlines(): + if re.search(r'^([^:]+)[^"]*\(\)[a-z0-9_().->]*[.->]+(c_str|r?begin|r?end)\(\)', line): + if re.search(r'lintok-begin-on-ref', line): + continue + print(line) + names[line_filename(line)] = True + if len(names): + test.error("Files with potential c_str() lifetime issue: " + + ' '.join(sorted(names.keys()))) + + +def vsnprintf(): + # Note do not do test_regress, as VPI files need to compile without verilatedos.h + files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c*" + cmd = "cd " + root + " && grep -n -P '(snprintf|vsnprintf)' " + files + " | sort" + grep = test.run_capture(cmd, check=False) + names = {} + for line in grep.splitlines(): + if re.search(r'\b(snprintf|vsnprintf)\b', line): + if re.search(r'# *define\s*VL_V?SNPRINTF', line): + continue + print(line) + names[line_filename(line)] = True + if len(names): + test.error("Files with vsnprintf, use VL_VSNPRINTF: " + ' '.join(sorted(names.keys()))) + + +def final(): + # Note do not do test_regress, as VPI files need to compile without verilatedos.h + files = "src/*.c* src/*.h include/*.c* include/*.h" + cmd = "cd " + root + " && grep -n -P '(class|struct)' " + files + " | sort" + grep = test.run_capture(cmd, check=False) + names = {} + for line in grep.splitlines(): + if re.search(r':\s*(class|struct) ', line): + if (re.search(r'final|VL_NOT_FINAL', line) # + or re.search(r'{}', line) # e.g. 'class Foo {};' + or re.search(r';', line) # e.g. 'class Foo;' + or re.search(r'(class|struct)\s+{', line) # e.g. anon 'class {' + or re.search(r'struct std::', line) # + or not re.search(r'{', line)): + continue + print(line) + names[line_filename(line)] = True + if len(names): + test.error("Files with classes without final/VL_NOT_FINAL: " + + ' '.join(sorted(names.keys()))) + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +printfll() +cstr() +vsnprintf() +final() + +test.passes() diff --git a/test_regress/t/t_dist_tabs.pl b/test_regress/t/t_dist_tabs.pl deleted file mode 100755 index bc5f0c1a9..000000000 --- a/test_regress/t/t_dist_tabs.pl +++ /dev/null @@ -1,121 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; - -my $Make_Style_Re = qr!(Makefile)|(\.mk$)|(\.mk\.in$)!; -my $Tabs_Exempt_Re = qr!(\.out$)|(/gtkwave)|(Makefile)|(\.mk$)|(\.mk\.in$)!; -#my $Wide_Exempt_Re = qr!(\.l$)|(\.y$)!; -my $Wide_Exempt_Re = qr!.*!; # clang-tidy generally cleans up - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - ### Must trim output before and after our file list - my %warns; - my $prefix; - my $summary = ""; - { - my $diff = `cd $root && git diff HEAD`; - #print "DS $diff\n" if $Debug; - my $file; - my $atab; - my $btab; - my $lineno = 0; - foreach my $line ((split /\n/, $diff), "+++ b/_the_end") { - $fline = $line; - $fline =~ s!^(\+)#\t!$1!; # special case, lines starting with #\t are OK in Makefiles - if ($line =~ m!^\+\+\+ b/(.*)!) { - if ($file && !$astab && $bstab - && $file =~ $Make_Style_Re) { - $summary = "File modifications add new stray tabs (please untabify the patch):"; - $warns{$file} = "File modification adds new stray tabs (please untabify the patch): $file"; - } - if ($file && !$atab && $btab - && $file !~ $Tabs_Exempt_Re) { - $summary = "File modifications add new tabs (please untabify the patch):"; - $warns{$file} = "File modification adds new tabs (please untabify the patch): $file"; - } - # Next - $file = $1; - $atab = 0; - $btab = 0; - print " File $file\n" if $Self->{verbose}; - } - elsif ($line =~ m!^@@ -?[0-9]+,?[0-9]* \+?([0-9]+)!) { - $lineno = $1 - 1; - } - elsif ($line =~ m!^ !) { - ++$lineno; - if ($line =~ m!^[- ].*\t!) { - print " Had tabs\n" if $Self->{verbose} && !$atab; - $atab = 1; - } - } - elsif ($fline =~ m!^-.+[^\t]\t!) { - print " Had stray tabs\n" if $Self->{verbose} && !$astab; - $astab = 1; - } - elsif ($fline =~ m!^+.+[^\t]\t!) { - print " Inserts stray tabs\n" if $Self->{verbose} && !$bstab; - $bstab = 1; - } - elsif ($line =~ m!^-.*\t!) { - print " Had tabs\n" if $Self->{verbose} && !$atab; - $atab = 1; - } - elsif ($line =~ m!^\+.*\t!) { - ++$lineno; - print " Inserts tabs\n" if $Self->{verbose} && !$btab; - $btab = 1; - } - elsif ($line =~ m!^\+(.*)!) { - ++$lineno; - if ($line =~ /\r/) { - $summary = "File modification adds carriage return (remove them):" if !$summary; - $warns{$file} = "File modification adds carriage return (remove them): $file:$lineno"; - } - my $len = length($1); - if ($len >= 100 - && $file !~ $Tabs_Exempt_Re - && $file !~ $Wide_Exempt_Re) { - print " Wide $line\n" if $Self->{verbose}; - $summary = "File modification adds a new >100 column line:" if !$summary; - $warns{$file} = "File modification adds a new >100 column line: $file:$lineno"; - } - } - } - } - if (keys %warns) { - # First warning lists everything as that's shown in the driver summary - error($summary . " ", join(' ', sort keys %warns)); - foreach my $file (sort keys %warns) { - error($warns{$file}); - } - } -} - -sub _has_tabs { - my $filename = shift; - my $contents = file_contents($filename); - if ($filename =~ /\.out$/) { - # Ignore golden files - } elsif ($contents =~ /[\001\002\003\004\005\006]/) { - # Ignore binary files - } elsif ($contents =~ /\t/) { - return 1; - } - return 0; -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_untracked.pl b/test_regress/t/t_dist_untracked.pl deleted file mode 100755 index a8f155d03..000000000 --- a/test_regress/t/t_dist_untracked.pl +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - ### Must trim output before and after our file list - my %warns; - my $prefix; - my $summary; - { - my $status = `cd $root && git ls-files -o --exclude-standard`; - print "ST $status\n" if $Debug; - foreach my $file (sort split /\n/, $status) { - next if $file =~ /nodist/; - if (_has_tabs("$root/$file")) { - $warns{$file} = "File not in git or .gitignore (with tabs): $file"; - $summary = "Files untracked in git or .gitignore (with tabs):"; - } else { - $warns{$file} = "File not in git or .gitignore: $file"; - $summary ||= "Files untracked in git or .gitignore:"; - } - } - } - if (keys %warns) { - # First warning lists everything as that's shown in the driver summary - error($summary . " ", join(' ', sort keys %warns)); - foreach my $file (sort keys %warns) { - error($warns{$file}); - } - } -} - -sub _has_tabs { - my $filename = shift; - my $contents = file_contents($filename); - if ($filename =~ /\.out$/) { - # Ignore golden files - } elsif ($contents =~ /[\001\002\003\004\005\006]/) { - # Ignore binary files - } elsif ($contents =~ /\t/) { - return 1; - } - return 0; -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_untracked.py b/test_regress/t/t_dist_untracked.py new file mode 100755 index 000000000..15545b1d1 --- /dev/null +++ b/test_regress/t/t_dist_untracked.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +### Must trim output before and after our file list +warns = {} +summary = None + +status = test.run_capture("cd " + root + " && git ls-files -o --exclude-standard") + +if test.verbose: + print("-ST " + status) +for filename in sorted(status.split()): + if re.search('nodist', filename): + continue + warns[filename] = "File not in git or .gitignore: " + filename + summary = "Files untracked in git or .gitignore:" + +if summary: + # First warning lists everything as that's shown in the driver summary + test.error(summary + " " + ' '.join(sorted(warns.keys()))) + for filename in sorted(warns.keys()): + test.error(warns[filename]) + +test.passes() diff --git a/test_regress/t/t_dist_warn_coverage.pl b/test_regress/t/t_dist_warn_coverage.pl deleted file mode 100755 index e19159d45..000000000 --- a/test_regress/t/t_dist_warn_coverage.pl +++ /dev/null @@ -1,214 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(dist => 1); - -my $root = ".."; -my $Debug = $Self->{verbose}; -my %Messages; -my %Outputs; - -my %Suppressed; -foreach my $s ( - ' exited with ', # Is hit; driver.pl filters out - 'EOF in unterminated string', # Instead get normal unterminated - 'Enum names without values only allowed on numeric types', # Hard to hit - 'Enum ranges must be integral, per spec', # Hard to hit - 'Return with return value isn\'t underneath a function', # Hard to hit, get other bad return messages - 'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance ', # Instead get syntax error - 'Syntax error parsing real: \'', # Instead can't lex the number - 'Unsupported: Ranges ignored in port-lists', # Hard to hit - 'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error - # Not yet analyzed - ' loading non-variable', - '--pipe-filter protocol error, unexpected: ', - '/*verilator sformat*/ can only be applied to last argument of ', - 'Argument needed for string.', - 'Array initialization has too few elements, need element ', - 'Assigned pin is neither input nor output', - 'Assignment pattern with no members', - 'Can\'t find varpin scope of ', - 'Can\'t resolve module reference: \'', - 'Cannot write preprocessor output: ', - 'Circular logic when ordering code (non-cutable edge loop)', - 'Define or directive not defined: `', - 'Exceeded limit of ', - 'Extern declaration\'s scope is not a defined class', - 'Format to $display-like function must have constant format string', - 'Forward typedef used as class/package does not resolve to class/package: ', - 'Illegal +: or -: select; type already selected, or bad dimension: ', - 'Illegal bit or array select; type already selected, or bad dimension: ', - 'Illegal range select; type already selected, or bad dimension: ', - 'Interface port ', - 'Member selection of non-struct/union object \'', - 'Modport item is not a function/task: ', - 'Modport item is not a variable: ', - 'Modport item not found: ', - 'Modport not referenced as .', - 'Modport not referenced from underneath an interface: ', - 'Non-interface used as an interface: ', - 'Parameter type pin value isn\'t a type: Param ', - 'Parameter type variable isn\'t a type: Param ', - 'Pattern replication value of 0 is not legal.', - 'Signals inside functions/tasks cannot be marked forceable', - 'Slice size cannot be zero.', - 'Slices of arrays in assignments have different unpacked dimensions, ', - 'String of ', - 'Symbol matching ', - 'Unexpected connection to arrayed port', - 'Unsized numbers/parameters not allowed in streams.', - 'Unsupported RHS tristate construct: ', - 'Unsupported or syntax error: Unsized range in instance or other declaration', - 'Unsupported pullup/down (weak driver) construct.', - 'Unsupported tristate construct (not in propagation graph): ', - 'Unsupported tristate port expression: ', - 'Unsupported/Illegal: Assignment pattern', - 'Unsupported/unknown built-in dynamic array method ', - 'Unsupported: $bits for queue', - 'Unsupported: $c can\'t generate wider than 64 bits', - 'Unsupported: 4-state numbers in this context', - 'Unsupported: Concatenation to form ', - 'Unsupported: Non-variable on LHS of built-in method \'', - 'Unsupported: Only one PSL clock allowed per assertion', - 'Unsupported: Per-bit array instantiations ', - 'Unsupported: Public functions with >64 bit outputs; ', - 'Unsupported: RHS of ==? or !=? must be ', - 'Unsupported: Replication to form ', - 'Unsupported: Shifting of by over 32-bit number isn\'t supported.', - 'Unsupported: Signal strengths are unsupported ', - 'Unsupported: Size-changing cast on non-basic data type', - 'Unsupported: Slice of non-constant bounds', - 'Unsupported: Unclocked assertion', - 'Unsupported: don\'t know how to deal with ', - 'Unsupported: event arrays', - 'Unsupported: modport export', - 'Unsupported: no_inline for tasks', - 'Unsupported: static cast to ', - 'Unsupported: super', - ) { $Suppressed{$s} = 1; } - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - check(); -} - -ok(1); -1; - -sub check { - read_messages(); - read_outputs(); - - print "Number of suppressions = ", scalar(keys %Suppressed), "\n"; - print "Coverage = ", 100 - int(100 * scalar(keys %Suppressed) / scalar(keys %Messages)), "%\n"; - print "\n"; - - print "Checking for v3error/v3warn messages in sources without coverage in test_regress/t/*.out:\n"; - print "(Developers: If a message is impossible, use UASSERT or v3fatalSrc instead of v3error)"; - print "\n"; - - my %used_suppressed; - msg: - for my $msg (sort {$Messages{$a}{fileline} cmp $Messages{$b}{fileline}} keys %Messages) { - my $fileline = $Messages{$msg}{fileline}; - for my $output (keys %Outputs) { - if (index($output, $msg) != -1) { - # print "$fileline: M '$msg' HIT '$output'\n"; - next msg; - } - } - # Some exceptions - next msg if ($msg =~ /internal:/i); - - my $line = $Messages{$msg}{line}; - chomp $line; - $line =~ s/^\s+//; - - if (%Suppressed{$msg}) { - $used_suppressed{$msg} = 1; - print "$fileline: Suppressed check for message in source: '$msg'\n" if $Debug; - } else { - error("$fileline: Missing test_regress/t/*.out test for message in source: '$msg'"); - print(" Line is: ", $line, "\n") if $Debug; - } - } - print "\n"; - - for my $msg (sort keys %Suppressed) { - if (!$used_suppressed{$msg}) { - print "Suppression not used: '$msg'\n"; - } - } - print "\n"; -} - -sub read_messages { - foreach my $filename (glob "$root/src/*") { - my $fh = IO::File->new("<$filename") - or error("$! $filename"); - my $lineno = 0; - my $read_next; - line: - while (my $origline = ($fh && $fh->getline)) { - my $line = $origline; - next if $line =~ m!^\s*//!; - next if $line =~ m!^\s*/\*!; - ++$lineno; - if ($line =~ /\b(v3error|v3warn)\b\($/g) { - $read_next = 1 if $line !~ /LCOV_EXCL_LINE/; - next line; - } - if ($line =~ s/.*\b(v3error|v3warn)\b//g) { - $read_next = 1 if $line !~ /LCOV_EXCL_LINE/; - } - if ($read_next) { - $read_next = 0; - next if $line =~ /LCOV_EXCL_LINE/; - next if $line =~ /\\/; # \" messes up next part - if ($line =~ /"([^"]*)"/) { - my $msg = $1; - my $fileline = $filename . ":" . $lineno; - # print "FFFF $fileline: $msg LL $line\n"; - $Messages{$msg}{fileline} = $fileline; - $Messages{$msg}{line} = $origline; - } - } - } - } - print "Number of messages = ",scalar(keys %Messages), "\n"; -} - -sub read_outputs { - file: - foreach my $filename (glob ("$root/test_regress/t/*.pl" - . " $root/test_regress/t/*.out" - . " $root/docs/gen/*.rst")) { - next if $filename =~ /t_dist_warn_coverage/; # Avoid our own suppressions - my $fh = IO::File->new("<$filename") - or error("$! $filename"); - while (my $line = ($fh && $fh->getline)) { - if ($line =~ /^\$date/) { - # Assume it is a VCD file - next file; - } - $Outputs{$line} = 1; - } - } - print "Number of outputs = ",scalar(keys %Outputs), "\n"; -} - -# Local Variables: -# compile-command:"./t_dist_warn_coverage.pl" -# End: diff --git a/test_regress/t/t_dist_warn_coverage.py b/test_regress/t/t_dist_warn_coverage.py new file mode 100755 index 000000000..3ad81cedc --- /dev/null +++ b/test_regress/t/t_dist_warn_coverage.py @@ -0,0 +1,259 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +Messages = {} +Outputs = {} +Suppressed = {} + +for s in [ + ' exited with ', # Is hit; driver.py filters out + 'EOF in unterminated string', # Instead get normal unterminated + 'Enum names without values only allowed on numeric types', # Hard to hit + 'Enum ranges must be integral, per spec', # Hard to hit + 'Import package not found: ', # Errors earlier, until future parser released + 'Return with return value isn\'t underneath a function', # Hard to hit, get other bad return messages + 'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance ', # Instead get syntax error + 'Syntax error parsing real: \'', # Instead can't lex the number + 'Unsupported: Ranges ignored in port-lists', # Hard to hit + 'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error + # Not yet analyzed + ' loading non-variable', + '--pipe-filter protocol error, unexpected: ', + '/*verilator sformat*/ can only be applied to last argument of ', + 'Argument needed for string.', + 'Array initialization has too few elements, need element ', + 'Assigned pin is neither input nor output', + 'Assignment pattern with no members', + 'Can\'t find varpin scope of ', + 'Can\'t resolve module reference: \'', + 'Cannot write preprocessor output: ', + 'Circular logic when ordering code (non-cutable edge loop)', + 'Define or directive not defined: `', + 'Exceeded limit of ', + 'Extern declaration\'s scope is not a defined class', + 'Format to $display-like function must have constant format string', + 'Forward typedef used as class/package does not resolve to class/package: ', + 'Illegal +: or -: select; type already selected, or bad dimension: ', + 'Illegal bit or array select; type already selected, or bad dimension: ', + 'Illegal range select; type already selected, or bad dimension: ', + 'Interface port ', + 'Member selection of non-struct/union object \'', + 'Modport item is not a function/task: ', + 'Modport item is not a variable: ', + 'Modport item not found: ', + 'Modport not referenced as .', + 'Modport not referenced from underneath an interface: ', + 'Non-interface used as an interface: ', + 'Parameter type pin value isn\'t a type: Param ', + 'Parameter type variable isn\'t a type: Param ', + 'Pattern replication value of 0 is not legal.', + 'Signals inside functions/tasks cannot be marked forceable', + 'Slice size cannot be zero.', + 'Slices of arrays in assignments have different unpacked dimensions, ', + 'String of ', + 'Symbol matching ', + 'Unexpected connection to arrayed port', + 'Unsized numbers/parameters not allowed in streams.', + 'Unsupported RHS tristate construct: ', + 'Unsupported or syntax error: Unsized range in instance or other declaration', + 'Unsupported pullup/down (weak driver) construct.', + 'Unsupported tristate construct (not in propagation graph): ', + 'Unsupported tristate port expression: ', + 'Unsupported/unknown built-in dynamic array method ', + 'Unsupported: $bits for queue', + 'Unsupported: $c can\'t generate wider than 64 bits', + 'Unsupported: &&& expression', + 'Unsupported: \'default :/\' constraint', + 'Unsupported: \'{} .* patterns', + 'Unsupported: \'{} tagged patterns', + 'Unsupported: +%- range', + 'Unsupported: +/- range', + 'Unsupported: 4-state numbers in this context', + 'Unsupported: Bind with instance list', + 'Unsupported: Concatenation to form ', + 'Unsupported: Modport clocking', + 'Unsupported: Modport dotted port name', + 'Unsupported: Modport export with prototype', + 'Unsupported: Modport import with prototype', + 'Unsupported: Non-variable on LHS of built-in method \'', + 'Unsupported: Only one PSL clock allowed per assertion', + 'Unsupported: Per-bit array instantiations ', + 'Unsupported: Public functions with >64 bit outputs; ', + 'Unsupported: RHS of ==? or !=? must be ', + 'Unsupported: Randomize \'local::\'', + 'Unsupported: Replication to form ', + 'Unsupported: Shifting of by over 32-bit number isn\'t supported.', + 'Unsupported: Signal strengths are unsupported ', + 'Unsupported: Size-changing cast on non-basic data type', + 'Unsupported: Slice of non-constant bounds', + 'Unsupported: Unclocked assertion', + 'Unsupported: Verilog 1995 deassign', + 'Unsupported: Verilog 1995 gate primitive: ', + 'Unsupported: [] dimensions', + 'Unsupported: always[] (in property expression)', + 'Unsupported: assertion items in clocking blocks', + 'Unsupported: covergroup within class', + 'Unsupported: default clocking identifier', + 'Unsupported: don\'t know how to deal with ', + 'Unsupported: eventually[] (in property expression)', + 'Unsupported: extern forkjoin', + 'Unsupported: extern interface', + 'Unsupported: extern module', + 'Unsupported: extern task', + 'Unsupported: interface decls within interface decls', + 'Unsupported: interface decls within module decls', + 'Unsupported: module decls within module decls', + 'Unsupported: program decls within interface decls', + 'Unsupported: program decls within module decls', + 'Unsupported: property port \'local\'', + 'Unsupported: randsequence production list', + 'Unsupported: randsequence repeat', + 'Unsupported: repeat event control', + 'Unsupported: s_always (in property expression)', + 'Unsupported: this.super', + 'Unsupported: trireg', + 'Unsupported: wand', + 'Unsupported: with[] stream expression', + 'Unsupported: wor', + 'Unsupported: event arrays', + 'Unsupported: modport export', + 'Unsupported: no_inline for tasks', + 'Unsupported: static cast to ', + 'Unsupported: super', +]: + Suppressed[s] = True + + +def read_messages(): + for filename in test.glob_some(root + "/src/*"): + if not os.path.isfile(filename): + continue + with open(filename, 'r', encoding="utf8") as fh: + lineno = 0 + read_next = None + + for origline in fh: + line = origline + lineno += 1 + if re.match(r'^\s*//', line): + continue + if re.match(r'^\s*/\*', line): + continue + if re.search(r'\b(v3error|v3warn|BBUNSUP)\b\($', line): + if 'LCOV_EXCL_LINE' not in line: + read_next = True + continue + m = re.search(r'.*\b(v3error|v3warn|BBUNSUP)\b(.*)', line) + if m: + line = m.group(2) + if 'LCOV_EXCL_LINE' not in line: + read_next = True + if read_next: + read_next = False + if 'LCOV_EXCL_LINE' in line: + continue + if "\\" in line: # \" messes up next part + continue + m = re.search(r'"([^"]*)"', line) + if m: + msg = m.group(1) + fileline = filename + ":" + str(lineno) + # print("FFFF " + fileline + ": " + msg + " LL " + line) + Messages[msg] = {} + Messages[msg]['fileline'] = fileline + Messages[msg]['line'] = origline + + print("Number of messages = " + str(len(Messages))) + + +def read_outputs(): + for filename in (test.glob_some(root + "/test_regress/t/*.py") + + test.glob_some(root + "/test_regress/t/*.out") + + test.glob_some(root + "/docs/gen/*.rst")): + if "t_dist_warn_coverage" in filename: # Avoid our own suppressions + continue + with open(filename, 'r', encoding="latin-1") as fh: + for line in fh: + if re.match(r'^\$date', line): # Assume it is a VCD file + break + line = line.lstrip().rstrip() + Outputs[line] = True + + print("Number of outputs = " + str(len(Outputs))) + + +def check(): + read_messages() + read_outputs() + + print("Number of suppressions = " + str(len(Suppressed))) + print("Coverage = ", str(100 - int(100 * len(Suppressed) / len(Messages)))) + print() + + print("Checking for v3error/v3warn messages in sources without") + print("coverage in test_regress/t/*.out:") + print("(Developers: If a message is impossible to test, use UASSERT or") + print("v3fatalSrc instead of v3error)") + print() + + used_suppressed = {} + + for msg in sorted(Messages.keys()): + fileline = Messages[msg]['fileline'] + next_msg = False + for output in Outputs: + if msg in output: + # print(fileline+": M '" + msg + "' HIT '" + output) + next_msg = True + break + + if next_msg: + continue + + # Some exceptions + if re.match(r'internal:', msg, re.IGNORECASE): + continue + + line = Messages[msg]['line'] + line = line.lstrip().rstrip() + + if msg in Suppressed: + used_suppressed[msg] = True + if test.verbose: + print(fileline + ": Suppressed check for message in source: '" + msg + "'") + else: + test.error_keep_going(fileline + + ": Missing test_regress/t/*.out test for message in source: '" + + msg + "'") + if test.verbose: + print(" Line is: " + line) + + print() + for msg in sorted(Suppressed.keys()): + if msg not in used_suppressed: + print("Suppression not used: '" + msg + "'") + print() + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +check() + +test.passes() + +# Local Variables: +# compile-command:"./t_dist_warn_coverage.py" +# End: diff --git a/test_regress/t/t_dist_whitespace.pl b/test_regress/t/t_dist_whitespace.pl deleted file mode 100755 index f1c28607e..000000000 --- a/test_regress/t/t_dist_whitespace.pl +++ /dev/null @@ -1,112 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - my $root = ".."; - my $Debug; - - ### Must trim output before and after our file list - my %files = %{get_source_files($root)}; - - my $any = 0; - foreach my $file (sort keys %files) { - my $filename = "$root/$file"; - next if !-f $filename; # git file might be deleted but not yet staged - my $contents = file_contents($filename); - if ($file =~ /(\.out|\.dat)$/) { - # Ignore golden files - next; - } elsif ($contents =~ /[\001\002\003\004\005\006]/) { - # Ignore binary files - next; - } - if ($contents !~ /\n$/s && $contents ne "") { - $warns{$file} = "Missing trailing newline in $file"; - } - if ($contents =~ /[ \t]\n/ - || $contents =~ m/\n\n+$/) { # Regexp repeated below - my $eol_ws_exempt = ($file =~ /spelling.txt$/ - || $file =~ m!/gtkwave/!); - next if $eol_ws_exempt; - if ($ENV{HARNESS_UPDATE_GOLDEN}) { - my $changes = undef; - $changes = 1 if ($contents =~ s/[ \t]+\n/\n/g); - $changes = 1 if (!$eol_ws_exempt && $contents =~ s/\n\n+$/\n/g); - next if (!$changes); - $warns{$file} = "Updated whitespace at $file"; - write_wholefile($filename, $contents); - next; - } - my @lines = split(/\n/, $contents); - my $line_no = 0; - foreach my $line (@lines) { - $line_no++; - # Trim trailing carriage-return (ASCII 0x0d) and form feed (0x0c), - # as we expect a few of those - $line =~ s/[\x{d}\x{c}]//g; - if ($line =~ /\s$/) { - $warns{$file} = "Trailing whitespace at $file:$line_no"; - $warns{$file} .= " (last character is ASCII " . ord(substr($line, -1, 1)) . ")"; - } - } - if ($contents =~ m/\n\n+$/ && !$eol_ws_exempt) { # Regexp repeated above - $warns{$file} = "Trailing newlines at EOF in $file"; - } - } - # Unicode checker; should this be done in another file? - # No way to auto-fix. - # Files with \r are flagged elsewhere, right? - if ($contents =~ /[^[:alnum:][:punct:] \t\r\n]/) { - my $unicode_exempt = ($file =~ /Changes$/ - || $file =~ /CONTRIBUTORS$/ - || $file =~ /contributors.rst$/ - || $file =~ /spelling.txt$/); - next if $unicode_exempt; - $warns{$file} = "Warning: non-ASCII contents in $file\n"; - } - ++$any; - } - $any > 50 or error("Too few source files found"); - - if (keys %warns) { - # First warning lists everything as that's shown in the driver summary - if ($ENV{HARNESS_UPDATE_GOLDEN}) { - error("Updated files with whitespace errors: ", join(' ', sort keys %warns)); - error("To auto-fix: HARNESS_UPDATE_GOLDEN=1 {command} or --golden"); - } else { - error("Files have whitespace errors: ", join(' ', sort keys %warns)); - error("To auto-fix: HARNESS_UPDATE_GOLDEN=1 {command} or --golden"); - } - foreach my $file (sort keys %warns) { - error($warns{$file}); - } - } -} - -ok(1); -1; - -sub get_source_files { - my $root = shift; - my $git_files = `cd $root && git ls-files`; - print "MF $git_files\n" if $Self->{verbose}; - my %files; - foreach my $file (split /\s+/, $git_files) { - next if $file eq ''; - $files{$file} |= 1; - } - return \%files; -} diff --git a/test_regress/t/t_dist_whitespace.py b/test_regress/t/t_dist_whitespace.py new file mode 100755 index 000000000..1c9da5b27 --- /dev/null +++ b/test_regress/t/t_dist_whitespace.py @@ -0,0 +1,115 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +Tabs_Exempt_Re = r'(\.out$)|(/gtkwave)|(Makefile)|(\.mk$)|(\.mk\.in$)|test_regress/t/t_preproc\.v|install-sh' + + +def get_source_files(root): + git_files = test.run_capture("cd " + root + " && git ls-files") + if test.verbose: + print("MF " + git_files) + files = {} + for filename in git_files.split(): + if filename == '': + continue + files[filename] = True + return files + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +root = ".." + +files = get_source_files(root) + +warns = {} +fcount = 0 +for filename in sorted(files.keys()): + filename = os.path.join(root, filename) + if not os.path.exists(filename): # git file might be deleted but not yet staged + continue + contents = test.file_contents(filename) + if re.search(r'(\.out|\.dat)$', filename): + continue # Ignore golden files + if re.search(r'[\001\002\003\004\005\006]', contents): + continue # Ignore binary files + if contents != "" and contents[-1] != "\n": + contents += "\n" + warns[filename] = "Missing trailing newline (add one) in " + filename + if "\r" in contents: + contents = re.sub(r'\r', '', contents) + warns[filename] = "Carriage returns (remove them) in: " + filename + if "\f" in contents: + contents = re.sub(r'\f', '', contents) + warns[filename] = "Form-feeds (remove them) in: " + filename + if "\t" in contents and not re.search(Tabs_Exempt_Re, filename): + warns[filename] = "Tabs (cannot --gold fix) in " + filename + + if (re.search(r'[ \t]\n', contents) + or re.search(r'\n\n+$', contents)): # Regexp repeated below + eol_ws_exempt = ('spelling.txt' in filename or '/gtkwave/' in filename) + if eol_ws_exempt: + continue + if 'HARNESS_UPDATE_GOLDEN' in os.environ: + changes = False + (contents, n) = re.subn(r'[ \t]+\n', '\n', contents) + if n: + changes = True + if not eol_ws_exempt: + (contents, n) = re.subn(r'\n\n+$', '\n', contents) + if n: + changes = True + if not changes: + continue + warns[filename] = "Updated whitespace at " + filename + test.write_wholefile(filename, contents) + continue + + lineno = 0 + for line in contents.splitlines(): + lineno += 1 + if re.search(r'\s$', line): + warns[filename] = "Trailing whitespace at " + filename + ":" + str(lineno) + warns[filename] += " (last character is ASCII " + str(ord(line[-1])) + ")" + + if not eol_ws_exempt and re.search(r'\n\n+$', contents): # Regexp repeated above + warns[filename] = "Trailing newlines at EOF in " + filename + + # Unicode checker; should this be done in another file? + # No way to auto-fix. + unicode_exempt = (re.search(r'Changes$', filename) or re.search(r'CONTRIBUTORS$', filename) + or re.search(r'contributors.rst$', filename) + or re.search(r'spelling.txt$', filename)) + if not unicode_exempt and re.search(r'[^ \t\r\n\x20-\x7e]', contents): + warns[filename] = "Warning: non-ASCII contents in " + filename + + fcount += 1 + +if fcount < 50: + test.error("Too few source files found") + +if len(warns): + # First warning lists everything as that's shown in the driver summary + if 'HARNESS_UPDATE_GOLDEN' in os.environ: + test.error("Updated files with whitespace errors: " + ' '.join(sorted(warns.keys()))) + test.error("To auto-fix: HARNESS_UPDATE_GOLDEN=1 {command} or --golden") + else: + test.error("Files have whitespace errors: " + ' '.join(sorted(warns.keys()))) + test.error("To auto-fix: HARNESS_UPDATE_GOLDEN=1 {command} or --golden") + for filename in sorted(warns.keys()): + test.error(warns[filename]) + +test.passes() diff --git a/test_regress/t/t_do_not_convert_to_comb.pl b/test_regress/t/t_do_not_convert_to_comb.pl deleted file mode 100755 index c6db81d38..000000000 --- a/test_regress/t/t_do_not_convert_to_comb.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -# We must not convert these blocks into combinational blocks -file_grep($Self->{stats}, qr/Scheduling, size of class: combinational\s+(\d+)/i, 0); - -ok(1); -1; diff --git a/test_regress/t/t_do_not_convert_to_comb.py b/test_regress/t/t_do_not_convert_to_comb.py new file mode 100755 index 000000000..a5c94d9ff --- /dev/null +++ b/test_regress/t/t_do_not_convert_to_comb.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats"]) + +# We must not convert these blocks into combinational blocks +test.file_grep(test.stats, r'Scheduling, size of class: combinational\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_do_while.pl b/test_regress/t/t_do_while.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_do_while.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_do_while.py b/test_regress/t/t_do_while.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_do_while.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dos.pl b/test_regress/t/t_dos.pl deleted file mode 100755 index f2ebe7037..000000000 --- a/test_regress/t/t_dos.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wall -Wno-DECLFILENAME'], # To check EOFNEWLINE with DOS CRs - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dos.py b/test_regress/t/t_dos.py new file mode 100755 index 000000000..c3fb5ff74 --- /dev/null +++ b/test_regress/t/t_dos.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wall -Wno-DECLFILENAME']) # To check EOFNEWLINE with DOS CRs + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dotfiles.pl b/test_regress/t/t_dotfiles.pl deleted file mode 100755 index e0c05a270..000000000 --- a/test_regress/t/t_dotfiles.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -# Use a top file which we are sure to be parallelizable -top_filename("t/t_gen_alw.v"); - -compile( - v_flags2 => ["--dumpi-graph 6"], - threads => 2 - ); - -foreach my $dotname ("linkcells", "task_call", "gate_graph", "gate_final", - "acyc_simp", "orderg_pre", "orderg_acyc", "orderg_order", "orderg_domain", - "ordermv_initial", "ordermv_hazards", "ordermv_contraction", - "ordermv_transitive1", "orderg_done", "schedule") { - # Some files with identical prefix are generated multiple times during - # Verilation. Ensure that at least one of each $dotname-prefixed file is generated. - @dotFiles = glob("$Self->{obj_dir}/*$dotname.dot"); - if (scalar @dotFiles == 0) { - error("Found no dotfiles with pattern *$dotname.dot"); - } - foreach my $dotFilename (@dotFiles) { - file_grep($dotFilename, qr/digraph v3graph/); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dotfiles.py b/test_regress/t/t_dotfiles.py new file mode 100755 index 000000000..3930a139e --- /dev/null +++ b/test_regress/t/t_dotfiles.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') + +# Use a top file which we are sure to be parallelizable +test.top_filename = "t/t_gen_alw.v" + +test.compile(v_flags2=["--dumpi-graph 6"], threads=2) + +for dotname in [ + "linkcells", "task_call", "gate_graph", "gate_final", "acyc_simp", "orderg_pre", + "orderg_acyc", "orderg_order", "orderg_domain", "ordermv_initial", "ordermv_hazards", + "ordermv_contraction", "ordermv_transitive1", "orderg_done", "schedule" +]: + # Some files with identical prefix are generated multiple times during + # Verilation. Ensure that at least one of each dotname-prefixed file is generated. + dotFiles = test.glob_some(test.obj_dir + "/*" + dotname + ".dot") + for dotFilename in dotFiles: + test.file_grep(dotFilename, r'digraph v3graph') + +test.passes() diff --git a/test_regress/t/t_dpi_2exp_bad.pl b/test_regress/t/t_dpi_2exp_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_2exp_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_2exp_bad.py b/test_regress/t/t_dpi_2exp_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_2exp_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_2exparg_bad.pl b/test_regress/t/t_dpi_2exparg_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_2exparg_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_2exparg_bad.py b/test_regress/t/t_dpi_2exparg_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_2exparg_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_accessors.pl b/test_regress/t/t_dpi_accessors.pl deleted file mode 100755 index a21fb1c27..000000000 --- a/test_regress/t/t_dpi_accessors.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# 8-Mar-2012: Modifications for this test contributed by Jeremy Bennett and -# Jie Xu. - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["-Wno-BLKANDNBLK -language 1800-2005 --exe $Self->{t_dir}/$Self->{name}.cpp"], ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_accessors.py b/test_regress/t/t_dpi_accessors.py new file mode 100755 index 000000000..13bbc4ed4 --- /dev/null +++ b/test_regress/t/t_dpi_accessors.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# 8-Mar-2012: Modifications for this test contributed by Jeremy Bennett and +# Jie Xu. + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["-Wno-BLKANDNBLK -language 1800-2005 --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_arg_inout_type.pl b/test_regress/t/t_dpi_arg_inout_type.pl deleted file mode 100755 index 3bab51d49..000000000 --- a/test_regress/t/t_dpi_arg_inout_type.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_inout_type.py b/test_regress/t/t_dpi_arg_inout_type.py new file mode 100755 index 000000000..50423db37 --- /dev/null +++ b/test_regress/t/t_dpi_arg_inout_type.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_arg_inout_unpack.pl b/test_regress/t/t_dpi_arg_inout_unpack.pl deleted file mode 100755 index f58b3fb94..000000000 --- a/test_regress/t/t_dpi_arg_inout_unpack.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_inout_unpack.py b/test_regress/t/t_dpi_arg_inout_unpack.py new file mode 100755 index 000000000..866c0c9db --- /dev/null +++ b/test_regress/t/t_dpi_arg_inout_unpack.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_arg_input_type.pl b/test_regress/t/t_dpi_arg_input_type.pl deleted file mode 100755 index 3bab51d49..000000000 --- a/test_regress/t/t_dpi_arg_input_type.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_input_type.py b/test_regress/t/t_dpi_arg_input_type.py new file mode 100755 index 000000000..50423db37 --- /dev/null +++ b/test_regress/t/t_dpi_arg_input_type.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_arg_input_unpack.pl b/test_regress/t/t_dpi_arg_input_unpack.pl deleted file mode 100755 index f58b3fb94..000000000 --- a/test_regress/t/t_dpi_arg_input_unpack.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_input_unpack.py b/test_regress/t/t_dpi_arg_input_unpack.py new file mode 100755 index 000000000..866c0c9db --- /dev/null +++ b/test_regress/t/t_dpi_arg_input_unpack.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_arg_output_type.pl b/test_regress/t/t_dpi_arg_output_type.pl deleted file mode 100755 index 3bab51d49..000000000 --- a/test_regress/t/t_dpi_arg_output_type.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_output_type.py b/test_regress/t/t_dpi_arg_output_type.py new file mode 100755 index 000000000..50423db37 --- /dev/null +++ b/test_regress/t/t_dpi_arg_output_type.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_arg_output_unpack.pl b/test_regress/t/t_dpi_arg_output_unpack.pl deleted file mode 100755 index f58b3fb94..000000000 --- a/test_regress/t/t_dpi_arg_output_unpack.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_output_unpack.py b/test_regress/t/t_dpi_arg_output_unpack.py new file mode 100755 index 000000000..866c0c9db --- /dev/null +++ b/test_regress/t/t_dpi_arg_output_unpack.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_argtype_bad.pl b/test_regress/t/t_dpi_argtype_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_argtype_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_argtype_bad.py b/test_regress/t/t_dpi_argtype_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_argtype_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_binary.py b/test_regress/t/t_dpi_binary.py new file mode 100755 index 000000000..1663c1d56 --- /dev/null +++ b/test_regress/t/t_dpi_binary.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_dpi_binary_c.cpp" + +test.compile(v_flags2=[test.pli_filename], verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_binary.v b/test_regress/t/t_dpi_binary.v new file mode 100644 index 000000000..320ba11f4 --- /dev/null +++ b/test_regress/t/t_dpi_binary.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module t (); + + initial begin + // All Finished is in dpic_final + $finish; + end + + import "DPI-C" context function void dpic_final(); + final dpic_final(); + +endmodule diff --git a/test_regress/t/t_dpi_binary_c.cpp b/test_regress/t/t_dpi_binary_c.cpp new file mode 100644 index 000000000..ffe6049d1 --- /dev/null +++ b/test_regress/t/t_dpi_binary_c.cpp @@ -0,0 +1,25 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#include "t_dpi_binary_c.h" + +#include "svdpi.h" + +#include + +//====================================================================== + +extern "C" void dpic_final(); + +void dpic_final() { + printf("%s:\n", __func__); + printf("*-* All Finished *-*\n"); +} diff --git a/test_regress/t/t_dpi_binary_c.h b/test_regress/t/t_dpi_binary_c.h new file mode 100644 index 000000000..d15da366a --- /dev/null +++ b/test_regress/t/t_dpi_binary_c.h @@ -0,0 +1,12 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +// Empty file just to check that GCC finds it properly diff --git a/test_regress/t/t_dpi_context.pl b/test_regress/t/t_dpi_context.pl deleted file mode 100755 index c0096e960..000000000 --- a/test_regress/t/t_dpi_context.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_context_c.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_context.py b/test_regress/t/t_dpi_context.py new file mode 100755 index 000000000..8f4de8825 --- /dev/null +++ b/test_regress/t/t_dpi_context.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_context_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_context_noopt.pl b/test_regress/t/t_dpi_context_noopt.pl deleted file mode 100755 index cff6b4ed4..000000000 --- a/test_regress/t/t_dpi_context_noopt.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_dpi_context.v"); - -compile( - v_flags2 => ["t/t_dpi_context_c.cpp"], - verilator_flags2 => [$Self->{vlt_all} ? "-O0" : ""], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_context_noopt.py b/test_regress/t/t_dpi_context_noopt.py new file mode 100755 index 000000000..c9ef10cd5 --- /dev/null +++ b/test_regress/t/t_dpi_context_noopt.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_dpi_context.v" + +test.compile(v_flags2=["t/t_dpi_context_c.cpp"], + verilator_flags2=[("-O0" if test.vlt_all else "")]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_display.pl b/test_regress/t/t_dpi_display.pl deleted file mode 100755 index 5babe0a06..000000000 --- a/test_regress/t/t_dpi_display.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_display_c.cpp"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_display.py b/test_regress/t/t_dpi_display.py new file mode 100755 index 000000000..54a8c8ece --- /dev/null +++ b/test_regress/t/t_dpi_display.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_display_c.cpp"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_dup_bad.pl b/test_regress/t/t_dpi_dup_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_dup_bad.py b/test_regress/t/t_dpi_dup_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_export.pl b/test_regress/t/t_dpi_export.pl deleted file mode 100755 index 57bdaf055..000000000 --- a/test_regress/t/t_dpi_export.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end - -scenarios(simulator => 1); - -compile( - # Amazingly VCS, NC and Verilator all just accept the C file here! - v_flags2 => ["t/t_dpi_export_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -no-l2name"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export.py b/test_regress/t/t_dpi_export.py new file mode 100755 index 000000000..481162f17 --- /dev/null +++ b/test_regress/t/t_dpi_export.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_export_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -no-l2name"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_export.v b/test_regress/t/t_dpi_export.v index ad27183a8..c224b1fae 100644 --- a/test_regress/t/t_dpi_export.v +++ b/test_regress/t/t_dpi_export.v @@ -66,6 +66,9 @@ module t; `endif task dpix_t_time(input time i, output time o); o = ~i; endtask + export "DPI-C" function dpix__under___score; + function int dpix__under___score(input int i); return i + 1; endfunction + int lineno; initial begin diff --git a/test_regress/t/t_dpi_export_bad.pl b/test_regress/t/t_dpi_export_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_dpi_export_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export_bad.py b/test_regress/t/t_dpi_export_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_dpi_export_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_export_c.cpp b/test_regress/t/t_dpi_export_c.cpp index 8b60a1c66..5f6cd45f3 100644 --- a/test_regress/t/t_dpi_export_c.cpp +++ b/test_regress/t/t_dpi_export_c.cpp @@ -59,6 +59,8 @@ extern void dpix_t_reg15(const svLogicVecVal* i, svLogicVecVal* o); extern void dpix_t_reg95(const svLogicVecVal* i, svLogicVecVal* o); extern void dpix_t_integer(const svLogicVecVal* i, svLogicVecVal* o); extern void dpix_t_time(const svLogicVecVal* i, svLogicVecVal* o); + +extern int dpix__under___score(int i); } #endif @@ -225,6 +227,8 @@ int dpix_run_tests() { } #endif + CHECK_RESULT(int, dpix__under___score(77), 78); + if (int bad = check_sub("top.t.a", 1)) return bad; if (int bad = check_sub("top.t.b", 2)) return bad; diff --git a/test_regress/t/t_dpi_export_context2_bad.pl b/test_regress/t/t_dpi_export_context2_bad.pl deleted file mode 100755 index 93b856ef1..000000000 --- a/test_regress/t/t_dpi_export_context2_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--exe $Self->{t_dir}/t_dpi_export_context2_bad.cpp"], - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export_context2_bad.py b/test_regress/t/t_dpi_export_context2_bad.py new file mode 100755 index 000000000..b84ad228c --- /dev/null +++ b/test_regress/t/t_dpi_export_context2_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--exe", test.pli_filename], make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_export_context_bad.pl b/test_regress/t/t_dpi_export_context_bad.pl deleted file mode 100755 index 3bf347339..000000000 --- a/test_regress/t/t_dpi_export_context_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--exe $Self->{t_dir}/t_dpi_export_context_bad.cpp"], - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export_context_bad.py b/test_regress/t/t_dpi_export_context_bad.py new file mode 100755 index 000000000..b84ad228c --- /dev/null +++ b/test_regress/t/t_dpi_export_context_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--exe", test.pli_filename], make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_export_noopt.pl b/test_regress/t/t_dpi_export_noopt.pl deleted file mode 100755 index 4ad49a952..000000000 --- a/test_regress/t/t_dpi_export_noopt.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end - -scenarios(simulator => 1); - -top_filename("t/t_dpi_export.v"); - -compile( - # Amazingly VCS, NC and Verilator all just accept the C file here! - v_flags2 => ["t/t_dpi_export_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -no-l2name", - $Self->{vlt_all} ? "-O0" : ""], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export_noopt.py b/test_regress/t/t_dpi_export_noopt.py new file mode 100755 index 000000000..d6f865acf --- /dev/null +++ b/test_regress/t/t_dpi_export_noopt.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_dpi_export.v" + +test.compile( + v_flags2=["t/t_dpi_export_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -no-l2name", ("-O0" if test.vlt_all else "")]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_export_scope_bad.pl b/test_regress/t/t_dpi_export_scope_bad.pl deleted file mode 100755 index 5b97a7901..000000000 --- a/test_regress/t/t_dpi_export_scope_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export_scope_bad.py b/test_regress/t/t_dpi_export_scope_bad.py new file mode 100755 index 000000000..b84ad228c --- /dev/null +++ b/test_regress/t/t_dpi_export_scope_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--exe", test.pli_filename], make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_if_cond.pl b/test_regress/t/t_dpi_if_cond.pl deleted file mode 100755 index 4fd6c9020..000000000 --- a/test_regress/t/t_dpi_if_cond.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_if_cond_c.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_if_cond.py b/test_regress/t/t_dpi_if_cond.py new file mode 100755 index 000000000..7323376c7 --- /dev/null +++ b/test_regress/t/t_dpi_if_cond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_if_cond_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_imp_gen.pl b/test_regress/t/t_dpi_imp_gen.pl deleted file mode 100755 index fd2d1a9f3..000000000 --- a/test_regress/t/t_dpi_imp_gen.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_imp_gen_c.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_imp_gen.py b/test_regress/t/t_dpi_imp_gen.py new file mode 100755 index 000000000..54580144a --- /dev/null +++ b/test_regress/t/t_dpi_imp_gen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_imp_gen_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_import.pl b/test_regress/t/t_dpi_import.pl deleted file mode 100755 index ecb8a264f..000000000 --- a/test_regress/t/t_dpi_import.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Amazingly VCS, NC and Verilator all just accept the C file here! - v_flags2 => ["t/t_dpi_import_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_import.py b/test_regress/t/t_dpi_import.py new file mode 100755 index 000000000..c1a90041a --- /dev/null +++ b/test_regress/t/t_dpi_import.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_import_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_import.v b/test_regress/t/t_dpi_import.v index bc35b3161..abe7d18d6 100644 --- a/test_regress/t/t_dpi_import.v +++ b/test_regress/t/t_dpi_import.v @@ -99,6 +99,9 @@ module t (/*AUTOARG*/ import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i); + // Check Verilator doesn't convert double underscores + import "DPI-C" pure function int dpii__under___score(input int i); + bit i_b, o_b; bit [7:0] i_b8; bit [8:0] i_b9; @@ -256,6 +259,8 @@ module t (/*AUTOARG*/ if (oth_f_int1(32'd123) !== ~32'd123) $stop; if (oth_f_int2(32'd124) !== ~32'd124) $stop; + if (dpii__under___score(32'd60) != 32'd61) $stop; + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_dpi_import_c.cpp b/test_regress/t/t_dpi_import_c.cpp index e48b261a3..8bd090c6e 100644 --- a/test_regress/t/t_dpi_import_c.cpp +++ b/test_regress/t/t_dpi_import_c.cpp @@ -183,6 +183,8 @@ void dpii_v_bit96(const svBitVecVal* i, svBitVecVal* o) { int dpii_f_strlen(const char* i) { return strlen(i); } +int dpii__under___score(int i) { return i + 1; } + //====================================================================== void dpii_f_void() {} diff --git a/test_regress/t/t_dpi_import_hdr_only.pl b/test_regress/t/t_dpi_import_hdr_only.pl deleted file mode 100755 index b497878f2..000000000 --- a/test_regress/t/t_dpi_import_hdr_only.pl +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use File::Temp; -use File::Compare; - -scenarios(simulator => 1); - -top_filename("t/t_dpi_import.v"); - -my $tmp_dir = File::Temp->newdir(); - -compile( - # Override default flags also - verilator_flags => ["-Wall -Wno-DECLFILENAME -Mdir " . $tmp_dir . " --dpi-hdr-only"], - verilator_make_gmake => 0, - ); - -my @files = glob($tmp_dir . "/*"); - -error("Did not produce DPI header") if scalar(@files) == 0; -error("Too many files created:" . join(', ', @files)) if scalar(@files) > 1; - -my $tmp_header = $files[0]; -print("============" . $tmp_header . "\n"); -error("Unexpected file $tmp_header") unless $tmp_header =~ /__Dpi\.h$/; - -compile( - verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], - verilator_make_gmake => 0, - ); - -@files = glob($Self->obj_dir . "/*__Dpi.h"); -my $header = $files[0]; - -if (compare($tmp_header, $header) != 0) { - error("DPI header files are not the same"); -} - -ok(1); -1; diff --git a/test_regress/t/t_dpi_import_hdr_only.py b/test_regress/t/t_dpi_import_hdr_only.py new file mode 100755 index 000000000..edb00f4b9 --- /dev/null +++ b/test_regress/t/t_dpi_import_hdr_only.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import filecmp + +test.scenarios('simulator') +test.top_filename = "t/t_dpi_import.v" + +tmp_dir = test.obj_dir + "/dpi-hdr" +test.mkdir_ok(tmp_dir) + +test.compile( + # Override default flags also + verilator_flags=["-Wall -Wno-DECLFILENAME -Mdir " + tmp_dir + " --dpi-hdr-only"], + verilator_make_gmake=False) + +files = glob.glob(tmp_dir + "/*") + +if len(files) < 1: + test.error("Did not produce DPI header") +if len(files) > 1: + test.error("Too many files created:" + ', '.join(files)) + +tmp_header = files[0] +print("============" + tmp_header) + +if not re.search(r'__Dpi\.h$', tmp_header): + test.error("Unexpected file " + tmp_header) + +test.compile(verilator_flags2=["-Wall -Wno-DECLFILENAME"], verilator_make_gmake=False) + +files = glob.glob(test.obj_dir + "/*__Dpi.h") +header = files[0] + +if not filecmp.cmp(tmp_header, header): + test.error("DPI header files are not the same") + +test.passes() diff --git a/test_regress/t/t_dpi_import_mix_bad.pl b/test_regress/t/t_dpi_import_mix_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_dpi_import_mix_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_import_mix_bad.py b/test_regress/t/t_dpi_import_mix_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_dpi_import_mix_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_lib.pl b/test_regress/t/t_dpi_lib.pl deleted file mode 100755 index 896a5502c..000000000 --- a/test_regress/t/t_dpi_lib.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_lib_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_lib.py b/test_regress/t/t_dpi_lib.py new file mode 100755 index 000000000..f193c7954 --- /dev/null +++ b/test_regress/t/t_dpi_lib.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_lib_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_name_bad.out b/test_regress/t/t_dpi_name_bad.out index a061f6f78..04f4e97ba 100644 --- a/test_regress/t/t_dpi_name_bad.out +++ b/test_regress/t/t_dpi_name_bad.out @@ -1,4 +1,7 @@ -%Error: t/t_dpi_name_bad.v:12:32: DPI function has illegal characters in C identifier name: 'badly.named' - 12 | import "DPI-C" function int \badly.named (int i); +%Error: t/t_dpi_name_bad.v:11:32: DPI function has illegal characters in C identifier name: badly.named + 11 | import "DPI-C" function int \badly.named (int i); | ^~~~~~~~~~~~ +%Error: t/t_dpi_name_bad.v:14:17: DPI function has illegal characters in C identifier name: badly.expt + 14 | function int \badly.expt ; return 0; endfunction + | ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_name_bad.pl b/test_regress/t/t_dpi_name_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_name_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_name_bad.py b/test_regress/t/t_dpi_name_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_name_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_name_bad.v b/test_regress/t/t_dpi_name_bad.v index e8c066912..bf07235c0 100644 --- a/test_regress/t/t_dpi_name_bad.v +++ b/test_regress/t/t_dpi_name_bad.v @@ -8,9 +8,11 @@ module t (); - // Can't handle logic (yet?) import "DPI-C" function int \badly.named (int i); + export "DPI-C" function \badly.expt ; + function int \badly.expt ; return 0; endfunction + initial begin $stop; end diff --git a/test_regress/t/t_dpi_open.pl b/test_regress/t/t_dpi_open.pl deleted file mode 100755 index 099d9a2e7..000000000 --- a/test_regress/t/t_dpi_open.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_open_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -unroll-count 1"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_open.py b/test_regress/t/t_dpi_open.py new file mode 100755 index 000000000..159176896 --- /dev/null +++ b/test_regress/t/t_dpi_open.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_open_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_open_elem.pl b/test_regress/t/t_dpi_open_elem.pl deleted file mode 100755 index ab9367bf0..000000000 --- a/test_regress/t/t_dpi_open_elem.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_open_elem_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -unroll-count 1"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_open_elem.py b/test_regress/t/t_dpi_open_elem.py new file mode 100755 index 000000000..447d00f22 --- /dev/null +++ b/test_regress/t/t_dpi_open_elem.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_open_elem_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_open_oob_bad.pl b/test_regress/t/t_dpi_open_oob_bad.pl deleted file mode 100755 index 8f02d74a8..000000000 --- a/test_regress/t/t_dpi_open_oob_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["t/t_dpi_open_oob_bad_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -unroll-count 1"], - ); - -execute( - fails => 0, # DPI warnings are not errors - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_open_oob_bad.py b/test_regress/t/t_dpi_open_oob_bad.py new file mode 100755 index 000000000..a2a8336aa --- /dev/null +++ b/test_regress/t/t_dpi_open_oob_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["t/t_dpi_open_oob_bad_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) + +test.execute( + fails=False, # DPI warnings are not errors + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_open_query.pl b/test_regress/t/t_dpi_open_query.pl deleted file mode 100755 index 32c447dfd..000000000 --- a/test_regress/t/t_dpi_open_query.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/t_dpi_open_query.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_open_query.py b/test_regress/t/t_dpi_open_query.py new file mode 100755 index 000000000..347bb962e --- /dev/null +++ b/test_regress/t/t_dpi_open_query.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=["+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h"]) + +test.compile( + v_flags2=["t/t_dpi_open_query.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_open_vecval.pl b/test_regress/t/t_dpi_open_vecval.pl deleted file mode 100755 index 542b88469..000000000 --- a/test_regress/t/t_dpi_open_vecval.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_open_vecval_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -unroll-count 1"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_open_vecval.py b/test_regress/t/t_dpi_open_vecval.py new file mode 100755 index 000000000..e2ea46c98 --- /dev/null +++ b/test_regress/t/t_dpi_open_vecval.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_open_vecval_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_open_vecval_c.cpp b/test_regress/t/t_dpi_open_vecval_c.cpp index 014db3f38..077aea0a6 100644 --- a/test_regress/t/t_dpi_open_vecval_c.cpp +++ b/test_regress/t/t_dpi_open_vecval_c.cpp @@ -46,6 +46,8 @@ extern int dpii_failure(); int errors = 0; int dpii_failure() { return errors; } +#define TEST_MAX_NELEMS 1024 + static void _invert(int bits, svBitVecVal o[], const svBitVecVal i[]) { for (int w = 0; w < SV_PACKED_DATA_NELEMS(bits); ++w) o[w] = ~i[w]; o[SV_PACKED_DATA_NELEMS(bits) - 1] &= SV_MASK(bits & 31); @@ -91,9 +93,13 @@ static void _dpii_bit_vecval_ux(int bits, int p, int u, const svOpenArrayHandle TEST_CHECK_HEX_EQ(dim, u); #endif - svBitVecVal vv[SV_PACKED_DATA_NELEMS(bits)]; - svBitVecVal vv2[SV_PACKED_DATA_NELEMS(bits)]; - svBitVecVal vo[SV_PACKED_DATA_NELEMS(bits)]; + if (SV_PACKED_DATA_NELEMS(bits) > TEST_MAX_NELEMS) { + fprintf(stderr, "%%Error: Increase TEST_MAX_NELEMS\n"); + abort(); + } + svBitVecVal vv[TEST_MAX_NELEMS]; + svBitVecVal vv2[TEST_MAX_NELEMS]; + svBitVecVal vo[TEST_MAX_NELEMS]; for (int a = svLow(i, 1); a <= svHigh(i, 1); ++a) { fflush(stdout); if (dim == 1) { @@ -162,9 +168,13 @@ static void _dpii_logic_vecval_ux(int bits, int p, int u, const svOpenArrayHandl TEST_CHECK_HEX_EQ(dim, u); #endif - svLogicVecVal vv[SV_PACKED_DATA_NELEMS(bits)]; - svLogicVecVal vv2[SV_PACKED_DATA_NELEMS(bits)]; - svLogicVecVal vo[SV_PACKED_DATA_NELEMS(bits)]; + if (SV_PACKED_DATA_NELEMS(bits) > TEST_MAX_NELEMS) { + fprintf(stderr, "%%Error: Increase TEST_MAX_NELEMS\n"); + abort(); + } + svLogicVecVal vv[TEST_MAX_NELEMS]; + svLogicVecVal vv2[TEST_MAX_NELEMS]; + svLogicVecVal vo[TEST_MAX_NELEMS]; for (int a = svLow(i, 1); a <= svHigh(i, 1); ++a) { fflush(stdout); if (dim == 1) { diff --git a/test_regress/t/t_dpi_openfirst.pl b/test_regress/t/t_dpi_openfirst.pl deleted file mode 100755 index c8f69c0fe..000000000 --- a/test_regress/t/t_dpi_openfirst.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_openfirst_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_openfirst.py b/test_regress/t/t_dpi_openfirst.py new file mode 100755 index 000000000..13eebeba0 --- /dev/null +++ b/test_regress/t/t_dpi_openfirst.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_openfirst_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_qw.pl b/test_regress/t/t_dpi_qw.pl deleted file mode 100755 index f5c98cf48..000000000 --- a/test_regress/t/t_dpi_qw.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_qw_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -Wno-UNOPTFLAT -no-l2name"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_qw.py b/test_regress/t/t_dpi_qw.py new file mode 100755 index 000000000..6e3f18c06 --- /dev/null +++ b/test_regress/t/t_dpi_qw.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_qw_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -Wno-UNOPTFLAT -no-l2name"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_result_type.pl b/test_regress/t/t_dpi_result_type.pl deleted file mode 100755 index 3bab51d49..000000000 --- a/test_regress/t/t_dpi_result_type.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_result_type.py b/test_regress/t/t_dpi_result_type.py new file mode 100755 index 000000000..50423db37 --- /dev/null +++ b/test_regress/t/t_dpi_result_type.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_result_type_bad.pl b/test_regress/t/t_dpi_result_type_bad.pl deleted file mode 100755 index 4d9f82122..000000000 --- a/test_regress/t/t_dpi_result_type_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ["-Wall --error-limit 0"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_result_type_bad.py b/test_regress/t/t_dpi_result_type_bad.py new file mode 100755 index 000000000..bedc7eb77 --- /dev/null +++ b/test_regress/t/t_dpi_result_type_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, + expect_filename=test.golden_filename, + verilator_flags2=["-Wall --error-limit 0"]) + +test.passes() diff --git a/test_regress/t/t_dpi_shortcircuit.pl b/test_regress/t/t_dpi_shortcircuit.pl deleted file mode 100755 index b109f6b46..000000000 --- a/test_regress/t/t_dpi_shortcircuit.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["t/t_dpi_shortcircuit_c.cpp"], - verilator_flags2 => ["-Wno-DECLFILENAME"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_shortcircuit.py b/test_regress/t/t_dpi_shortcircuit.py new file mode 100755 index 000000000..349844c9a --- /dev/null +++ b/test_regress/t/t_dpi_shortcircuit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["t/t_dpi_shortcircuit_c.cpp"], verilator_flags2=["-Wno-DECLFILENAME"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_shortcircuit2.pl b/test_regress/t/t_dpi_shortcircuit2.pl deleted file mode 100755 index e53f3f9eb..000000000 --- a/test_regress/t/t_dpi_shortcircuit2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Amazingly VCS, NC and Verilator all just accept the C file here! - v_flags2 => ["t/t_dpi_shortcircuit_c.cpp"], - verilator_flags2 => ["-Wno-DECLFILENAME"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_shortcircuit2.py b/test_regress/t/t_dpi_shortcircuit2.py new file mode 100755 index 000000000..4dffb1ad7 --- /dev/null +++ b/test_regress/t/t_dpi_shortcircuit2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_shortcircuit_c.cpp"], verilator_flags2=["-Wno-DECLFILENAME"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_string.pl b/test_regress/t/t_dpi_string.pl deleted file mode 100755 index f694b5065..000000000 --- a/test_regress/t/t_dpi_string.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_string_c.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_string.py b/test_regress/t/t_dpi_string.py new file mode 100755 index 000000000..b45da9e3c --- /dev/null +++ b/test_regress/t/t_dpi_string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_string_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_sys.pl b/test_regress/t/t_dpi_sys.pl deleted file mode 100755 index d47ed0147..000000000 --- a/test_regress/t/t_dpi_sys.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_sys_c.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_sys.py b/test_regress/t/t_dpi_sys.py new file mode 100755 index 000000000..292a39802 --- /dev/null +++ b/test_regress/t/t_dpi_sys.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_sys_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_threads.pl b/test_regress/t/t_dpi_threads.pl deleted file mode 100755 index 9529c0495..000000000 --- a/test_regress/t/t_dpi_threads.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2018 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -compile( - v_flags2 => ["t/t_dpi_threads_c.cpp --no-threads-coarsen"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_threads.py b/test_regress/t/t_dpi_threads.py new file mode 100755 index 000000000..f13ae5199 --- /dev/null +++ b/test_regress/t/t_dpi_threads.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') + +test.compile(v_flags2=["t/t_dpi_threads_c.cpp --no-threads-coarsen"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_threads.v b/test_regress/t/t_dpi_threads.v index 2a80f029a..b8637e62c 100644 --- a/test_regress/t/t_dpi_threads.v +++ b/test_regress/t/t_dpi_threads.v @@ -40,12 +40,12 @@ module t (clk); // Alternatively, the test may be run with "--threads-dpi all" in which case // it should confirm that the calls do run concurrently and do detect a // collision (they should, if the test is set up right.) This is - // t_dpi_threads_collide.pl. + // t_dpi_threads_collide.py. // // Q) Is it a risk that the partitioner will merge or serialize these always // blocks, just by luck, even if the DPI-call serialization code fails? // - // A) Yes, that's why t_dpi_threads_collide.pl also passes + // A) Yes, that's why t_dpi_threads_collide.py also passes // --no-threads-do-coaren to disable MTask coarsening. This ensures that // the MTask graph at the end of FixDataHazards (where we resolve DPI // hazards) is basically the final MTasks graph, and that data hazards diff --git a/test_regress/t/t_dpi_threads_collide.pl b/test_regress/t/t_dpi_threads_collide.pl deleted file mode 100755 index dff046d94..000000000 --- a/test_regress/t/t_dpi_threads_collide.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2018 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -$Self->skip_if_too_few_cores(); - -scenarios(vltmt => 1); - -top_filename("t/t_dpi_threads.v"); - -compile( - v_flags2 => ["t/t_dpi_threads_c.cpp --threads-dpi all --no-threads-coarsen"], - ); - -# Similar to t_dpi_threads, which confirms that Verilator can prevent a -# race between DPI import calls, this test confirms that the race exists -# and that the DPI C code can detect it under --threads-dpi all -# mode. -# -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_threads_collide.py b/test_regress/t/t_dpi_threads_collide.py new file mode 100755 index 000000000..fe226e43a --- /dev/null +++ b/test_regress/t/t_dpi_threads_collide.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_dpi_threads.v" + +test.skip_if_too_few_cores() + +test.compile(v_flags2=["t/t_dpi_threads_c.cpp --threads-dpi all --no-threads-coarsen"]) + +# Similar to t_dpi_threads, which confirms that Verilator can prevent a +# race between DPI import calls, this test confirms that the race exists +# and that the DPI C code can detect it under --threads-dpi all +# mode. +# +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_dpi_type_bad.pl b/test_regress/t/t_dpi_type_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_type_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_type_bad.py b/test_regress/t/t_dpi_type_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_type_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_unpack_bad.pl b/test_regress/t/t_dpi_unpack_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_dpi_unpack_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_unpack_bad.py b/test_regress/t/t_dpi_unpack_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_dpi_unpack_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_vams.pl b/test_regress/t/t_dpi_vams.pl deleted file mode 100755 index 68f1f0e47..000000000 --- a/test_regress/t/t_dpi_vams.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_vams.py b/test_regress/t/t_dpi_vams.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_dpi_vams.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_var.pl b/test_regress/t/t_dpi_var.pl deleted file mode 100755 index d2c38c1d8..000000000 --- a/test_regress/t/t_dpi_var.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--no-json-edit-nums", "-DATTRIBUTES --exe --no-l2name $Self->{t_dir}/t_dpi_var.cpp"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"formatted",.*"loc":"e,56:[^"]*",.*"origName":"formatted",.*"direction":"INPUT",.*"dtypeName":"string",.*"attrSFormat":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.in",.*"loc":"e,77:[^"]*",.*"origName":"in",.*"dtypeName":"int",.*"isSigUserRdPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.fr_a",.*"loc":"e,78:[^"]*",.*"origName":"fr_a",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.fr_b",.*"loc":"e,79:[^"]*",.*"origName":"fr_b",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_var.py b/test_regress/t/t_dpi_var.py new file mode 100755 index 000000000..87e0c90a1 --- /dev/null +++ b/test_regress/t/t_dpi_var.py @@ -0,0 +1,41 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile( + make_top_shell=False, + make_main=False, + verilator_flags2=["--no-json-edit-nums", "-DATTRIBUTES --exe --no-l2name", test.pli_filename]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"formatted",.*"loc":"e,56:[^"]*",.*"origName":"formatted",.*"direction":"INPUT",.*"dtypeName":"string",.*"attrSFormat":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.in",.*"loc":"e,77:[^"]*",.*"origName":"in",.*"dtypeName":"int",.*"isSigUserRdPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.fr_a",.*"loc":"e,78:[^"]*",.*"origName":"fr_a",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.fr_b",.*"loc":"e,79:[^"]*",.*"origName":"fr_b",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_var_vlt.pl b/test_regress/t/t_dpi_var_vlt.pl deleted file mode 100755 index 1962e20ba..000000000 --- a/test_regress/t/t_dpi_var_vlt.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_dpi_var.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--no-json-edit-nums", "--exe --no-l2name $Self->{t_dir}/t_dpi_var.vlt $Self->{t_dir}/t_dpi_var.cpp"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"formatted","addr":"[^"]*","loc":"f,58:[^"]*",.*"origName":"formatted",.*"direction":"INPUT",.*"dtypeName":"string",.*"attrSFormat":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.in","addr":"[^"]*","loc":"f,81:[^"]*",.*"origName":"in",.*"dtypeName":"int",.*"isSigUserRdPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.fr_a","addr":"[^"]*","loc":"f,82:[^"]*",.*"origName":"fr_a",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.fr_b","addr":"[^"]*","loc":"f,83:[^"]*",.*"origName":"fr_b",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_var_vlt.py b/test_regress/t/t_dpi_var_vlt.py new file mode 100755 index 000000000..b625c8c09 --- /dev/null +++ b/test_regress/t/t_dpi_var_vlt.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_dpi_var.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + "--no-json-edit-nums", "--exe --no-l2name", test.t_dir + "/t_dpi_var.vlt", + test.t_dir + "/t_dpi_var.cpp" + ]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"formatted","addr":"[^"]*","loc":"f,58:[^"]*",.*"origName":"formatted",.*"direction":"INPUT",.*"dtypeName":"string",.*"attrSFormat":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.in","addr":"[^"]*","loc":"f,81:[^"]*",.*"origName":"in",.*"dtypeName":"int",.*"isSigUserRdPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.fr_a","addr":"[^"]*","loc":"f,82:[^"]*",.*"origName":"fr_a",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.fr_b","addr":"[^"]*","loc":"f,83:[^"]*",.*"origName":"fr_b",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_driver_random.pl b/test_regress/t/t_driver_random.pl deleted file mode 100755 index 482afba94..000000000 --- a/test_regress/t/t_driver_random.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use Time::HiRes; - -scenarios(dist => 1); - -if (!$ENV{VERILATOR_TEST_RANDOM_FAILURE}) { - print("Test is for harness checking only, setenv VERILATOR_TEST_RANDOM_FAILURE=1\n"); - ok(1); -} else { - # Randomly fail to test driver.pl - my ($ign, $t) = Time::HiRes::gettimeofday(); - if ($t % 2) { - error("random failure " . $t); - } - else { - ok(1); - } -} -1; diff --git a/test_regress/t/t_driver_random.py b/test_regress/t/t_driver_random.py new file mode 100755 index 000000000..83ab65bdd --- /dev/null +++ b/test_regress/t/t_driver_random.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import time + +test.scenarios('dist') + +if 'VERILATOR_TEST_RANDOM_FAILURE' not in os.environ: + print("Test is for harness checking only, setenv VERILATOR_TEST_RANDOM_FAILURE=1") + test.passes() +else: + # Randomly fail to test driver.py + t = time.time() + if t % 2: + test.error("random failure " + str(t)) + + test.passes() diff --git a/test_regress/t/t_dump_dfg.pl b/test_regress/t/t_dump_dfg.pl deleted file mode 100755 index 2164a894c..000000000 --- a/test_regress/t/t_dump_dfg.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# For code coverage of graph dumping, so does not matter much what the input is -top_filename("t/t_bench_mux4k.v"); - -compile( - verilator_flags2 => ["--dump-dfg", "--dumpi-dfg 9"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_dump_dfg.py b/test_regress/t/t_dump_dfg.py new file mode 100755 index 000000000..6c72c0fc0 --- /dev/null +++ b/test_regress/t/t_dump_dfg.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# For code coverage of graph dumping, so does not matter much what the input is +test.top_filename = "t/t_bench_mux4k.v" + +test.compile(verilator_flags2=["--dump-dfg", "--dumpi-dfg 9"]) + +test.passes() diff --git a/test_regress/t/t_dump_json.out b/test_regress/t/t_dump_json.out index 40959ac43..4a302d04d 100644 --- a/test_regress/t/t_dump_json.out +++ b/test_regress/t/t_dump_json.out @@ -399,7 +399,7 @@ ]} ], "thensp": [ - {"type":"STOP","name":"","addr":"(NG)","loc":"d,55:44,55:49"} + {"type":"STOP","name":"","addr":"(NG)","loc":"d,55:44,55:49","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(OG)","loc":"d,58:10,58:12", "condp": [ @@ -412,7 +412,7 @@ ]} ], "thensp": [ - {"type":"STOP","name":"","addr":"(SG)","loc":"d,58:44,58:49"} + {"type":"STOP","name":"","addr":"(SG)","loc":"d,58:44,58:49","isFatal":false} ],"elsesp": []}, {"type":"DISPLAY","name":"","addr":"(TG)","loc":"d,59:10,59:16", "fmtp": [ diff --git a/test_regress/t/t_dump_json.pl b/test_regress/t/t_dump_json.pl deleted file mode 100755 index 435b25067..000000000 --- a/test_regress/t/t_dump_json.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_dump.v"); - -lint( - v_flags => ["--dump-tree-json --no-json-edit-nums"], - ); - -files_identical("$Self->{obj_dir}/Vt_dump_json_001_cells.tree.json", $Self->{golden_filename}, 'logfile'); - -ok(1); - -1; diff --git a/test_regress/t/t_dump_json.py b/test_regress/t/t_dump_json.py new file mode 100755 index 000000000..d0cc13c96 --- /dev/null +++ b/test_regress/t/t_dump_json.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_dump.v" + +test.lint(v_flags=["--dump-tree-json --no-json-edit-nums"]) + +test.files_identical(test.obj_dir + "/Vt_dump_json_001_cells.tree.json", test.golden_filename, + 'logfile') + +test.passes() diff --git a/test_regress/t/t_dump_tree_dot.pl b/test_regress/t/t_dump_tree_dot.pl deleted file mode 100755 index 8caebed51..000000000 --- a/test_regress/t/t_dump_tree_dot.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_EXAMPLE.v"); - -lint( - v_flags => ["--lint-only --dump-tree-dot"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_dump_tree_dot.py b/test_regress/t/t_dump_tree_dot.py new file mode 100755 index 000000000..70a3a8d47 --- /dev/null +++ b/test_regress/t/t_dump_tree_dot.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_EXAMPLE.v" + +test.lint(v_flags=["--lint-only --dump-tree-dot"]) + +test.passes() diff --git a/test_regress/t/t_dynarray.pl b/test_regress/t/t_dynarray.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_dynarray.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray.py b/test_regress/t/t_dynarray.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray.v b/test_regress/t/t_dynarray.v index 68d25c463..85221dbe4 100644 --- a/test_regress/t/t_dynarray.v +++ b/test_regress/t/t_dynarray.v @@ -6,7 +6,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t (/*AUTOARG*/ diff --git a/test_regress/t/t_dynarray_bad.pl b/test_regress/t/t_dynarray_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_dynarray_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_bad.py b/test_regress/t/t_dynarray_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_dynarray_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dynarray_bits.pl b/test_regress/t/t_dynarray_bits.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_dynarray_bits.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_bits.py b/test_regress/t/t_dynarray_bits.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_dynarray_bits.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dynarray_cast_write.py b/test_regress/t/t_dynarray_cast_write.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_cast_write.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_cast_write.v b/test_regress/t/t_dynarray_cast_write.v new file mode 100644 index 000000000..3cf66f7a8 --- /dev/null +++ b/test_regress/t/t_dynarray_cast_write.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +class Foo; + int x = 1; +endclass + +class Bar extends Foo; + function new; + x = 2; + endfunction +endclass + +module t (/*AUTOARG*/); + initial begin + int sel_bit = 3; + Bar bar = new; + Foo foo = bar; + Bar bars[] = new[4]; + $cast(bars[0], foo); + if (bars[0].x != 2) $stop; + + $cast(bars[sel_bit[0]], foo); + if (bars[1].x != 2) $stop; + + $cast(bars[bars[0].x], foo); + if (bars[2].x != 2) $stop; + + $cast(bars[sel_bit[1:0]], foo); + if (bars[3].x != 2) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_dynarray_concat.pl b/test_regress/t/t_dynarray_concat.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_dynarray_concat.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_concat.py b/test_regress/t/t_dynarray_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_init.pl b/test_regress/t/t_dynarray_init.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_dynarray_init.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_init.py b/test_regress/t/t_dynarray_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_method.pl b/test_regress/t/t_dynarray_method.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_dynarray_method.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_method.py b/test_regress/t/t_dynarray_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_method.v b/test_regress/t/t_dynarray_method.v index 290ef7d2b..33712ad83 100644 --- a/test_regress/t/t_dynarray_method.v +++ b/test_regress/t/t_dynarray_method.v @@ -1,16 +1,14 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); -`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); - module t (/*AUTOARG*/); string s[] = { "hello", "sad", "sad", "world" }; diff --git a/test_regress/t/t_dynarray_method_bad.out b/test_regress/t/t_dynarray_method_bad.out new file mode 100644 index 000000000..e08898cd9 --- /dev/null +++ b/test_regress/t/t_dynarray_method_bad.out @@ -0,0 +1,27 @@ +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:19:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. + : ... note: In instance 't' + 19 | i = s.sum with (item.len); + | ^ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:21:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. + : ... note: In instance 't' + 21 | i = s.product with (item.len); + | ^ +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:23:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. + : ... note: In instance 't' + 23 | b = s.sum with (item == "hello"); + | ^ +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:25:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. + : ... note: In instance 't' + 25 | b = s.sum with (item == ""); + | ^ +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:27:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. + : ... note: In instance 't' + 27 | b = s.product with (item inside {"hello", "sad"}); + | ^ +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:29:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. + : ... note: In instance 't' + 29 | b = s.product with (item inside { "hello", "sad", "world" }); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_dynarray_method_bad.py b/test_regress/t/t_dynarray_method_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_dynarray_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dynarray_method_bad.v b/test_regress/t/t_dynarray_method_bad.v new file mode 100644 index 000000000..1f0ead380 --- /dev/null +++ b/test_regress/t/t_dynarray_method_bad.v @@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); + +module t (/*AUTOARG*/); + string s[] = { "hello", "sad", "sad", "world" }; + + initial begin + int i; + bit b; + + i = s.sum with (item.len); + `checkh(i, 10); + i = s.product with (item.len); + `checkh(i, 24); + b = s.sum with (item == "hello"); + `checkh(b, 1'b1); + b = s.sum with (item == ""); + `checkh(b, 1'b0); + b = s.product with (item inside {"hello", "sad"}); + `checkh(b, 1'b0); + b = s.product with (item inside { "hello", "sad", "world" }); + `checkh(b, 1'b1); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_dynarray_multid.pl b/test_regress/t/t_dynarray_multid.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_dynarray_multid.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_multid.py b/test_regress/t/t_dynarray_multid.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_multid.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_multid.v b/test_regress/t/t_dynarray_multid.v index dd73a10cb..d8bb20f16 100644 --- a/test_regress/t/t_dynarray_multid.v +++ b/test_regress/t/t_dynarray_multid.v @@ -196,6 +196,14 @@ module t (/*AUTOARG*/); `checkh(qa1[0].size, 4); qa1[0].delete; + qa1[$-1].delete; + `checkh(qa1[$-1].size, 0); + + qa1.delete; + `checkh(qa1.size, 0); + `checkh(qa1[$-1].size, 0); + `checkh(qa1.size, 0); + s1.a = new [4]; `checkh(s1.a.size, 4); s1.a.delete; diff --git a/test_regress/t/t_dynarray_param.pl b/test_regress/t/t_dynarray_param.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_dynarray_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_param.py b/test_regress/t/t_dynarray_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_unpacked.pl b/test_regress/t/t_dynarray_unpacked.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_dynarray_unpacked.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_unpacked.py b/test_regress/t/t_dynarray_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_embed1.pl b/test_regress/t/t_embed1.pl deleted file mode 100755 index 5de7bb286..000000000 --- a/test_regress/t/t_embed1.pl +++ /dev/null @@ -1,55 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use File::Spec; - -scenarios(simulator => 1); - -my $self = $Self; -my $child_dir = "$Self->{obj_dir}_child"; -mkdir $child_dir; - -# Compile the child -{ - my @cmdargs = $Self->compile_vlt_cmd - (vm_prefix => "$Self->{vm_prefix}_child", - top_filename => "$Self->{name}_child.v", - verilator_flags => ["-cc", "-Mdir", "${child_dir}", "--debug-check"], - # Can't use multi threading (like hier blocks), but needs to be thread safe - threads => 1, - ); - - run(logfile => "${child_dir}/vlt_compile.log", - cmd => \@cmdargs); - - run(logfile => "${child_dir}/vlt_gcc.log", - cmd => ["cd ${child_dir} && ", - $ENV{MAKE}, "-f" . getcwd() . "/Makefile_obj", - "CPPFLAGS_DRIVER=-D" . uc($self->{name}), - ($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" : ""), - "VM_PREFIX=$self->{vm_prefix}_child", - "V$self->{name}_child__ALL.a", # bypass default rule, make archive - ($param{make_flags}||""), - ]); -} - -# Compile the parent (might be with other than verilator) -compile( - v_flags2 => [File::Spec->rel2abs("${child_dir}/V$self->{name}_child__ALL.a"), - # TODO would be nice to have this in embedded archive - "t/t_embed1_c.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_embed1.py b/test_regress/t/t_embed1.py new file mode 100755 index 000000000..ff5997985 --- /dev/null +++ b/test_regress/t/t_embed1.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +child_dir = test.obj_dir + "_child" +test.mkdir_ok(child_dir) + +# Compile the child +while True: + cmdargs = test.compile_vlt_cmd( + vm_prefix=test.vm_prefix + "_child", + top_filename=test.name + "_child.v", + verilator_flags=["-cc", "-Mdir", child_dir, "--debug-check"], + # Can't use multi threading (like hier blocks), but needs to be thread safe + threads=1) # yapf:disable + + test.run(logfile=child_dir + "/vlt_compile.log", cmd=cmdargs) + + test.run( + logfile=child_dir + "/vlt_gcc.log", + cmd=[os.environ["MAKE"], "-C", child_dir, + "-f" + os.getcwd() + "/Makefile_obj", + "CPPFLAGS_DRIVER=-D"+test.name.upper(), + ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if test.verbose else ""), + "VM_PREFIX=" + test.vm_prefix + "_child", + "V" + test.name + "_child__ALL.a" # bypass default rule, make archive + ]) # yapf:disable + + break + +# Compile the parent (might be with other than verilator) +test.compile(v_flags2=[os.path.abspath(child_dir + "/V" + test.name + "_child__ALL.a"), + # TODO would be nice to have this in embedded archive + "t/t_embed1_c.cpp"]) # yapf:disable + +test.execute() + +test.passes() diff --git a/test_regress/t/t_emit_accessors.pl b/test_regress/t/t_emit_accessors.pl deleted file mode 100755 index 533483c87..000000000 --- a/test_regress/t/t_emit_accessors.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_main => 0, - verilator_flags2 => [ - "--emit-accessors", - "--exe", - "$Self->{t_dir}/$Self->{name}.cpp" - ], -); - -ok(1); -1; diff --git a/test_regress/t/t_emit_accessors.py b/test_regress/t/t_emit_accessors.py new file mode 100755 index 000000000..a85bb33eb --- /dev/null +++ b/test_regress/t/t_emit_accessors.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_main=False, verilator_flags2=["--emit-accessors", "--exe", test.pli_filename]) + +test.passes() diff --git a/test_regress/t/t_emit_constw.pl b/test_regress/t/t_emit_constw.pl deleted file mode 100755 index 8f7895804..000000000 --- a/test_regress/t/t_emit_constw.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_emit_constw.py b/test_regress/t/t_emit_constw.py new file mode 100755 index 000000000..32620aed3 --- /dev/null +++ b/test_regress/t/t_emit_constw.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_emit_memb_limit.pl b/test_regress/t/t_emit_memb_limit.pl deleted file mode 100755 index 39e3eb212..000000000 --- a/test_regress/t/t_emit_memb_limit.pl +++ /dev/null @@ -1,61 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; - -# Very slow on vltmt, and doesn't test much of value there, so disabled -scenarios(vlt => 1); - -sub gen { - my $filename = shift; - my $n = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_emit_memb_limit.pl\n"); - $fh->print("module t (i, clk, o);\n"); - $fh->print(" input clk;\n"); - $fh->print(" input i;\n"); - $fh->print(" output logic o;\n"); - for (my $i = 0; $i < ($n + 1); ++$i) { - $fh->print(" logic r$i;\n"); - } - $fh->print(" always @ (posedge clk) begin\n"); - $fh->print(" r0 <= i;\n"); - for (my $i = 1; $i < $n; ++$i) { - $fh->print(" r" . ($i+1) . " <= r$i;\n"); - } - $fh->print(" o <= r$n;\n"); - $fh->print(' $write("*-* All Finished *-*\n");', "\n"); - $fh->print(' $finish;', "\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_emit_memb_limit.v"); - -# Current limit is 50, so want to test at least 50*50 cases -gen($Self->{top_filename}, 6000); - -compile( - verilator_flags2=>["-x-assign fast --x-initial fast", - "-Wno-UNOPTTHREADS", - # The slow V3Partition asserts are just too slow - # in this test. They're disabled just for performance - # reasons: - "--no-debug-partition"], - ); - -execute( - check_finished => 1, - ); - -file_grep("$Self->{obj_dir}/$Self->{vm_prefix}___024root.h", qr/struct \{/); - -ok(1); -1; diff --git a/test_regress/t/t_emit_memb_limit.py b/test_regress/t/t_emit_memb_limit.py new file mode 100755 index 000000000..a6d6ef4d1 --- /dev/null +++ b/test_regress/t/t_emit_memb_limit.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +# Very slow on vltmt, and doesn't test much of value there, so disabled +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_emit_memb_limit.v" + + +def gen(filename, n): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_emit_memb_limit.py\n") + fh.write("module t (i, clk, o);\n") + fh.write(" input clk;\n") + fh.write(" input i;\n") + fh.write(" output logic o;\n") + for i in range(0, n + 1): + fh.write(" logic r" + str(i) + ";\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(" r0 <= i;\n") + for i in range(1, n): + fh.write(" r" + str(i + 1) + " <= r" + str(i) + ";\n") + fh.write(" o <= r" + str(n) + ";\n") + fh.write(' $write("*-* All Finished *-*\\n");' + "\n") + fh.write(' $finish;' + "\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +# Current limit is 50, so want to test at least 50*50 cases +gen(test.top_filename, 6000) + +test.compile(verilator_flags2=[ + "-x-assign fast --x-initial fast", + "-Wno-UNOPTTHREADS", + # The slow V3Partition asserts are just too slow + # in this test. They're disabled just for performance + # reasons: + "--no-debug-partition" +]) + +test.execute() + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "___024root.h", r'struct \{') + +test.passes() diff --git a/test_regress/t/t_enum.pl b/test_regress/t/t_enum.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enum.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum.py b/test_regress/t/t_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_bad_cell.pl b/test_regress/t/t_enum_bad_cell.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_enum_bad_cell.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_cell.py b/test_regress/t/t_enum_bad_cell.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_enum_bad_cell.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_bad_circdecl.pl b/test_regress/t/t_enum_bad_circdecl.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_enum_bad_circdecl.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_circdecl.py b/test_regress/t/t_enum_bad_circdecl.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_enum_bad_circdecl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_bad_dup.pl b/test_regress/t/t_enum_bad_dup.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_enum_bad_dup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_dup.py b/test_regress/t/t_enum_bad_dup.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_enum_bad_dup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_bad_hide.pl b/test_regress/t/t_enum_bad_hide.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_enum_bad_hide.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_hide.py b/test_regress/t/t_enum_bad_hide.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_enum_bad_hide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_bad_value.pl b/test_regress/t/t_enum_bad_value.pl deleted file mode 100755 index 0a723255a..000000000 --- a/test_regress/t/t_enum_bad_value.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--Wno-fatal"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_value.py b/test_regress/t/t_enum_bad_value.py new file mode 100755 index 000000000..176cdf75d --- /dev/null +++ b/test_regress/t/t_enum_bad_value.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--Wno-fatal"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_bad_wrap.pl b/test_regress/t/t_enum_bad_wrap.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_enum_bad_wrap.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_wrap.py b/test_regress/t/t_enum_bad_wrap.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_enum_bad_wrap.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_const_methods.pl b/test_regress/t/t_enum_const_methods.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enum_const_methods.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_const_methods.py b/test_regress/t/t_enum_const_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_const_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_enumvalue_struct_bad.pl b/test_regress/t/t_enum_enumvalue_struct_bad.pl deleted file mode 100755 index 58225a99e..000000000 --- a/test_regress/t/t_enum_enumvalue_struct_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_enumvalue_struct_bad.py b/test_regress/t/t_enum_enumvalue_struct_bad.py new file mode 100755 index 000000000..069c1f01e --- /dev/null +++ b/test_regress/t/t_enum_enumvalue_struct_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(expect_filename=test.golden_filename, fails=True) + +test.passes() diff --git a/test_regress/t/t_enum_func.pl b/test_regress/t/t_enum_func.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enum_func.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_func.py b/test_regress/t/t_enum_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_huge_methods.pl b/test_regress/t/t_enum_huge_methods.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enum_huge_methods.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_huge_methods.py b/test_regress/t/t_enum_huge_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_huge_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_huge_methods.v b/test_regress/t/t_enum_huge_methods.v index 24bdbdba0..0c7e1de6d 100644 --- a/test_regress/t/t_enum_huge_methods.v +++ b/test_regress/t/t_enum_huge_methods.v @@ -6,7 +6,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_enum_huge_methods_bad.out b/test_regress/t/t_enum_huge_methods_bad.out index 6671d5dc9..664d2ba24 100644 --- a/test_regress/t/t_enum_huge_methods_bad.out +++ b/test_regress/t/t_enum_huge_methods_bad.out @@ -1,9 +1,8 @@ %Error: t/t_enum_huge_methods_bad.v:15:18: Value too wide for 64-bits expected in this context 160'h12344567abcd12344567abcd 15 | ELARGE = 160'h1234_4567_abcd_1234_4567_abcd | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_enum_huge_methods_bad.v:30:21: Unsupported: enum next/prev/name method on enum with > 64 bits - : ... note: In instance 't' +%Error-UNSUPPORTED: t/t_enum_huge_methods_bad.v:30:19: Unsupported: enum next/prev/name method on enum with > 64 bits 30 | $display(e.name); - | ^~~~ + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_enum_huge_methods_bad.pl b/test_regress/t/t_enum_huge_methods_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_enum_huge_methods_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_huge_methods_bad.py b/test_regress/t/t_enum_huge_methods_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_enum_huge_methods_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_int.pl b/test_regress/t/t_enum_int.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enum_int.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_int.py b/test_regress/t/t_enum_int.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_int.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_large_methods.pl b/test_regress/t/t_enum_large_methods.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enum_large_methods.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_large_methods.py b/test_regress/t/t_enum_large_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_large_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_large_methods.v b/test_regress/t/t_enum_large_methods.v index ff9b69763..4ab01f2c9 100644 --- a/test_regress/t/t_enum_large_methods.v +++ b/test_regress/t/t_enum_large_methods.v @@ -6,7 +6,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_enum_name2.pl b/test_regress/t/t_enum_name2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enum_name2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_name2.py b/test_regress/t/t_enum_name2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_name2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_name3.pl b/test_regress/t/t_enum_name3.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enum_name3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_name3.py b/test_regress/t/t_enum_name3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_name3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_name_sformatf.py b/test_regress/t/t_enum_name_sformatf.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_name_sformatf.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_name_sformatf.v b/test_regress/t/t_enum_name_sformatf.v new file mode 100644 index 000000000..f629d1896 --- /dev/null +++ b/test_regress/t/t_enum_name_sformatf.v @@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module sub #(parameter int param_a, parameter bit [1:0] enum_param = '0) (); + typedef enum logic [1:0] { + FOO = enum_param, + BAR, + BAZ + } enum_t; + enum_t the_enum = enum_t'(1); + + initial $display("%s", the_enum.name()); +endmodule + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // finish report + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + sub #(.param_a(1)) the_sub1(); + sub #(.param_a(2)) the_sub2(); + sub #(.param_a(2), .enum_param(2'd1)) the_sub3(); + +endmodule diff --git a/test_regress/t/t_enum_overlap_bad.pl b/test_regress/t/t_enum_overlap_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_enum_overlap_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_overlap_bad.py b/test_regress/t/t_enum_overlap_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_overlap_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_param_class.pl b/test_regress/t/t_enum_param_class.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enum_param_class.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_param_class.py b/test_regress/t/t_enum_param_class.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_param_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_public.pl b/test_regress/t/t_enum_public.pl deleted file mode 100755 index 345560283..000000000 --- a/test_regress/t/t_enum_public.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{vlt_all}) { - compile( - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - make_top_shell => 0, - make_main => 0, - ); -} else { - compile( - ); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_public.py b/test_regress/t/t_enum_public.py new file mode 100755 index 000000000..0916bd913 --- /dev/null +++ b/test_regress/t/t_enum_public.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.vlt_all: + test.compile(verilator_flags2=["--exe", test.pli_filename], + make_top_shell=False, + make_main=False) +else: + test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_recurse_bad.pl b/test_regress/t/t_enum_recurse_bad.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_enum_recurse_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_recurse_bad.py b/test_regress/t/t_enum_recurse_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_recurse_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_recurse_bad2.pl b/test_regress/t/t_enum_recurse_bad2.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_enum_recurse_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_recurse_bad2.py b/test_regress/t/t_enum_recurse_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_recurse_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_size.pl b/test_regress/t/t_enum_size.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_enum_size.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_size.py b/test_regress/t/t_enum_size.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_size.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_size.v b/test_regress/t/t_enum_size.v index 8cc2992f9..e69abadba 100644 --- a/test_regress/t/t_enum_size.v +++ b/test_regress/t/t_enum_size.v @@ -4,11 +4,7 @@ // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); // verilator lint_off WIDTH typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs; diff --git a/test_regress/t/t_enum_type_bad.pl b/test_regress/t/t_enum_type_bad.pl deleted file mode 100755 index a083f46f5..000000000 --- a/test_regress/t/t_enum_type_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_type_bad.py b/test_regress/t/t_enum_type_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_enum_type_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_type_methods.pl b/test_regress/t/t_enum_type_methods.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enum_type_methods.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_type_methods.py b/test_regress/t/t_enum_type_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_type_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_type_methods.v b/test_regress/t/t_enum_type_methods.v index 3b1d500f0..b391f659b 100644 --- a/test_regress/t/t_enum_type_methods.v +++ b/test_regress/t/t_enum_type_methods.v @@ -6,7 +6,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_enum_type_methods_bad.pl b/test_regress/t/t_enum_type_methods_bad.pl deleted file mode 100755 index 3c938d615..000000000 --- a/test_regress/t/t_enum_type_methods_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_type_methods_bad.py b/test_regress/t/t_enum_type_methods_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_type_methods_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_type_nomethod_bad.pl b/test_regress/t/t_enum_type_nomethod_bad.pl deleted file mode 100755 index 3c938d615..000000000 --- a/test_regress/t/t_enum_type_nomethod_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_type_nomethod_bad.py b/test_regress/t/t_enum_type_nomethod_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_type_nomethod_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_type_pins.pl b/test_regress/t/t_enum_type_pins.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enum_type_pins.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_type_pins.py b/test_regress/t/t_enum_type_pins.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_type_pins.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_value_assign.pl b/test_regress/t/t_enum_value_assign.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_enum_value_assign.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_value_assign.py b/test_regress/t/t_enum_value_assign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_value_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_x_bad.pl b/test_regress/t/t_enum_x_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_enum_x_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_x_bad.py b/test_regress/t/t_enum_x_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_x_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enumeration.pl b/test_regress/t/t_enumeration.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_enumeration.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enumeration.py b/test_regress/t/t_enumeration.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enumeration.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event.pl b/test_regress/t/t_event.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_event.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event.py b/test_regress/t/t_event.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_event.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event.v b/test_regress/t/t_event.v index 566657dd0..4a0e98da6 100644 --- a/test_regress/t/t_event.v +++ b/test_regress/t/t_event.v @@ -18,6 +18,7 @@ module t(/*AUTOARG*/ event e1; event e2; + event e3; `ifndef IVERILOG event ev [3:0]; `endif @@ -50,16 +51,21 @@ module t(/*AUTOARG*/ if (last_event != 0) $stop; -> e1; if (!e1.triggered) $stop; + if (e3.triggered) $stop; + -> e3; + if (!e3.triggered) $stop; end 11: begin if (last_event != 32'b10) $stop; last_event = 0; + if (e3.triggered) $stop; end // 13: begin if (last_event != 0) $stop; ->> e2; if (e2.triggered) $stop; + if (e3.triggered) $stop; end 14: begin if (last_event != 32'b100) $stop; diff --git a/test_regress/t/t_event_control.pl b/test_regress/t/t_event_control.pl deleted file mode 100755 index 1047a4907..000000000 --- a/test_regress/t/t_event_control.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--no-timing'], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control.py b/test_regress/t/t_event_control.py new file mode 100755 index 000000000..330e93cb7 --- /dev/null +++ b/test_regress/t/t_event_control.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--no-timing'], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_event_control_assign.pl b/test_regress/t/t_event_control_assign.pl deleted file mode 100755 index 06ac175ad..000000000 --- a/test_regress/t/t_event_control_assign.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - make_main => 0, - # Multithreading would cause a warning on event assignments - threads => 1, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_assign.py b/test_regress/t/t_event_control_assign.py new file mode 100755 index 000000000..9516162d0 --- /dev/null +++ b/test_regress/t/t_event_control_assign.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + verilator_flags2=["--exe --main --timing"], + make_main=False, + # Multithreading would cause a warning on event assignments + threads=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event_control_expr.pl b/test_regress/t/t_event_control_expr.pl deleted file mode 100755 index 133221d43..000000000 --- a/test_regress/t/t_event_control_expr.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # do not test classes for multithreaded, as V3InstrCount doesn't handle MemberSel - verilator_flags2 => $Self->{vltmt} ? ['-DNO_CLASS'] : [], - ); - -execute( - check_finished => 1, - ); - -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp")) { - # Check that these simple expressions are not stored in temp variables - file_grep_not($file, qr/__Vtrigcurr__expression_.* = vlSelf->clk;/); - file_grep_not($file, qr/__Vtrigcurr__expression_.* = vlSelf->t__DOT__q.at\(0U\);/); - file_grep_not($file, qr/__Vtrigcurr__expression_.* = .*vlSelf->t__DOT____Vcellinp__u_array__t/); - file_grep_not($file, qr/__Vtrigcurr__expression_.* = .*vlSymsp->TOP__t__DOT__u_class.__PVT__obj/); - # The line below should only be generated if concats/replicates aren't converted to separate senitems - file_grep_not($file, qr/__Vtrigcurr__expression_.* = .*vlSelf->t__DOT__a/); -} - -ok(1); -1; diff --git a/test_regress/t/t_event_control_expr.py b/test_regress/t/t_event_control_expr.py new file mode 100755 index 000000000..ad96efae9 --- /dev/null +++ b/test_regress/t/t_event_control_expr.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # do not test classes for multithreaded, as V3InstrCount doesn't handle MemberSel + verilator_flags2=(['-DNO_CLASS'] if test.vltmt else [])) + +test.execute() + +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp"): + # Check that these simple expressions are not stored in temp variables + test.file_grep_not(filename, r'__Vtrigcurr__expression_.* = vlSelf->clk;') + test.file_grep_not(filename, r'__Vtrigcurr__expression_.* = vlSelf->t__DOT__q.at\(0U\);') + test.file_grep_not(filename, + r'__Vtrigcurr__expression_.* = .*vlSelf->t__DOT____Vcellinp__u_array__t') + test.file_grep_not(filename, + r'__Vtrigcurr__expression_.* = .*vlSymsp->TOP__t__DOT__u_class.__PVT__obj') + # The line below should only be generated if concats/replicates aren't converted to separate senitems + test.file_grep_not(filename, r'__Vtrigcurr__expression_.* = .*vlSelf->t__DOT__a') + +test.passes() diff --git a/test_regress/t/t_event_control_expr.v b/test_regress/t/t_event_control_expr.v index 23fc5bc55..74456d898 100644 --- a/test_regress/t/t_event_control_expr.v +++ b/test_regress/t/t_event_control_expr.v @@ -142,7 +142,7 @@ module t(/*AUTOARG*/ `endif `endif - t_cstmt u_cstmt; + t_cstmt u_cstmt(); int cyc = 0; diff --git a/test_regress/t/t_event_control_expr_unsup.pl b/test_regress/t/t_event_control_expr_unsup.pl deleted file mode 100755 index 2f43f3687..000000000 --- a/test_regress/t/t_event_control_expr_unsup.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); # no vltmt, as AstMemberSel is unhandled in V3InstrCount - -top_filename("t_event_control_expr.v"); - -lint( - verilator_flags2 => ['-DUNSUP'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_expr_unsup.py b/test_regress/t/t_event_control_expr_unsup.py new file mode 100755 index 000000000..dbee9633e --- /dev/null +++ b/test_regress/t/t_event_control_expr_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') # no vltmt, as AstMemberSel is unhandled in V3InstrCount +test.top_filename = "t_event_control_expr.v" + +test.lint(verilator_flags2=['-DUNSUP'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_event_control_pass.pl b/test_regress/t/t_event_control_pass.pl deleted file mode 100755 index 0cb201e30..000000000 --- a/test_regress/t/t_event_control_pass.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - threads => 1, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_pass.py b/test_regress/t/t_event_control_pass.py new file mode 100755 index 000000000..483af3382 --- /dev/null +++ b/test_regress/t/t_event_control_pass.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"], threads=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event_control_prev_name_collision.pl b/test_regress/t/t_event_control_prev_name_collision.pl deleted file mode 100755 index 0fa78eb28..000000000 --- a/test_regress/t/t_event_control_prev_name_collision.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_prev_name_collision.py b/test_regress/t/t_event_control_prev_name_collision.py new file mode 100755 index 000000000..54de0aad4 --- /dev/null +++ b/test_regress/t/t_event_control_prev_name_collision.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event_control_prev_name_collision.v b/test_regress/t/t_event_control_prev_name_collision.v index 2b95b86c5..ef9a9c660 100644 --- a/test_regress/t/t_event_control_prev_name_collision.v +++ b/test_regress/t/t_event_control_prev_name_collision.v @@ -44,7 +44,7 @@ module Q( endmodule module Test( - input reset, + input reset, output valid ); wire ready_e; diff --git a/test_regress/t/t_event_control_scope_var.pl b/test_regress/t/t_event_control_scope_var.pl deleted file mode 100755 index d78b3ff03..000000000 --- a/test_regress/t/t_event_control_scope_var.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-fno-inline', '-Wno-WIDTHTRUNC'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_scope_var.py b/test_regress/t/t_event_control_scope_var.py new file mode 100755 index 000000000..e1fb39066 --- /dev/null +++ b/test_regress/t/t_event_control_scope_var.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-fno-inline', '-Wno-WIDTHTRUNC']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event_control_star.pl b/test_regress/t/t_event_control_star.pl deleted file mode 100755 index 68471ddd3..000000000 --- a/test_regress/t/t_event_control_star.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_star.py b/test_regress/t/t_event_control_star.py new file mode 100755 index 000000000..c8abf435a --- /dev/null +++ b/test_regress/t/t_event_control_star.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_event_control_timing.pl b/test_regress/t/t_event_control_timing.pl deleted file mode 100755 index 750ff60c9..000000000 --- a/test_regress/t/t_event_control_timing.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_event_control.v"); - -compile( - verilator_flags2 => ["--timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_timing.py b/test_regress/t/t_event_control_timing.py new file mode 100755 index 000000000..dc5a3dbd2 --- /dev/null +++ b/test_regress/t/t_event_control_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_event_control.v" + +test.compile(verilator_flags2=["--timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_event_copy.pl b/test_regress/t/t_event_copy.pl deleted file mode 100755 index bce8f74ca..000000000 --- a/test_regress/t/t_event_copy.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - threads => 1, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_event_copy.py b/test_regress/t/t_event_copy.py new file mode 100755 index 000000000..a61e23c88 --- /dev/null +++ b/test_regress/t/t_event_copy.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename, threads=1) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_event_method_bad.pl b/test_regress/t/t_event_method_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_event_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_method_bad.py b/test_regress/t/t_event_method_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_event_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_exit.pl b/test_regress/t/t_exit.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_exit.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_exit.py b/test_regress/t/t_exit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_exit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_expect.pl b/test_regress/t/t_expect.pl deleted file mode 100755 index 7da2a2cb5..000000000 --- a/test_regress/t/t_expect.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert --timing'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_expect.py b/test_regress/t/t_expect.py new file mode 100755 index 000000000..f0ed5d34b --- /dev/null +++ b/test_regress/t/t_expect.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert --timing'], fails=True) + +test.passes() diff --git a/test_regress/t/t_export_packed_struct.pl b/test_regress/t/t_export_packed_struct.pl deleted file mode 100755 index 7f8f6c442..000000000 --- a/test_regress/t/t_export_packed_struct.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp -Wno-SYMRSVDWORD"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_export_packed_struct.py b/test_regress/t/t_export_packed_struct.py new file mode 100755 index 000000000..a08f8ed86 --- /dev/null +++ b/test_regress/t/t_export_packed_struct.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "-Wno-SYMRSVDWORD"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_export_packed_struct2.pl b/test_regress/t/t_export_packed_struct2.pl deleted file mode 100755 index 8ff32055a..000000000 --- a/test_regress/t/t_export_packed_struct2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_export_packed_struct2.py b/test_regress/t/t_export_packed_struct2.py new file mode 100755 index 000000000..9d1dcec8d --- /dev/null +++ b/test_regress/t/t_export_packed_struct2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_expr_incr_unsup.pl b/test_regress/t/t_expr_incr_unsup.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_expr_incr_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_expr_incr_unsup.py b/test_regress/t/t_expr_incr_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_expr_incr_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_extend.pl b/test_regress/t/t_extend.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_extend.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_extend.py b/test_regress/t/t_extend.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_extend.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_extend_class.pl b/test_regress/t/t_extend_class.pl deleted file mode 100755 index d14b969d1..000000000 --- a/test_regress/t/t_extend_class.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_flags => "CPPFLAGS_ADD=-I$Self->{t_dir}", - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_extend_class.py b/test_regress/t/t_extend_class.py new file mode 100755 index 000000000..6795aaac5 --- /dev/null +++ b/test_regress/t/t_extend_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_flags=["CPPFLAGS_ADD=-I" + test.t_dir]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_extract_static_const.pl b/test_regress/t/t_extract_static_const.pl deleted file mode 100755 index 1f112f083..000000000 --- a/test_regress/t/t_extract_static_const.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Prelim extracted value to ConstPool\s+(\d+)/i, - 8); - file_grep($Self->{stats}, qr/ConstPool, Constants emitted\s+(\d+)/i, - 1); -} - -ok(1); -1; diff --git a/test_regress/t/t_extract_static_const.py b/test_regress/t/t_extract_static_const.py new file mode 100755 index 000000000..c48009a42 --- /dev/null +++ b/test_regress/t/t_extract_static_const.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats"]) + +test.execute(expect_filename=test.golden_filename) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Prelim extracted value to ConstPool\s+(\d+)', 8) + test.file_grep(test.stats, r'ConstPool, Constants emitted\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_extract_static_const_multimodule.pl b/test_regress/t/t_extract_static_const_multimodule.pl deleted file mode 100755 index 1f112f083..000000000 --- a/test_regress/t/t_extract_static_const_multimodule.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Prelim extracted value to ConstPool\s+(\d+)/i, - 8); - file_grep($Self->{stats}, qr/ConstPool, Constants emitted\s+(\d+)/i, - 1); -} - -ok(1); -1; diff --git a/test_regress/t/t_extract_static_const_multimodule.py b/test_regress/t/t_extract_static_const_multimodule.py new file mode 100755 index 000000000..c48009a42 --- /dev/null +++ b/test_regress/t/t_extract_static_const_multimodule.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats"]) + +test.execute(expect_filename=test.golden_filename) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Prelim extracted value to ConstPool\s+(\d+)', 8) + test.file_grep(test.stats, r'ConstPool, Constants emitted\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_extract_static_const_no_merge.pl b/test_regress/t/t_extract_static_const_no_merge.pl deleted file mode 100755 index f656fe455..000000000 --- a/test_regress/t/t_extract_static_const_no_merge.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_extract_static_const.v"); -golden_filename("t/t_extract_static_const.out"); - -compile( - verilator_flags2 => ["--stats", "--fno-merge-const-pool"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Prelim extracted value to ConstPool\s+(\d+)/i, - 8); - file_grep($Self->{stats}, qr/ConstPool, Constants emitted\s+(\d+)/i, - 2); -} - -ok(1); -1; diff --git a/test_regress/t/t_extract_static_const_no_merge.py b/test_regress/t/t_extract_static_const_no_merge.py new file mode 100755 index 000000000..8c3835a5d --- /dev/null +++ b/test_regress/t/t_extract_static_const_no_merge.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_extract_static_const.v" +test.golden_filename = "t/t_extract_static_const.out" + +test.compile(verilator_flags2=["--stats", "--fno-merge-const-pool"]) + +test.execute(expect_filename=test.golden_filename) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Prelim extracted value to ConstPool\s+(\d+)', 8) + test.file_grep(test.stats, r'ConstPool, Constants emitted\s+(\d+)', 2) + +test.passes() diff --git a/test_regress/t/t_f_bad.pl b/test_regress/t/t_f_bad.pl deleted file mode 100755 index bebe33c0c..000000000 --- a/test_regress/t/t_f_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -f file_will_not_exist.vc"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_f_bad.py b/test_regress/t/t_f_bad.py new file mode 100755 index 000000000..9d256232c --- /dev/null +++ b/test_regress/t/t_f_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -f file_will_not_exist.vc"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fallback_bad.out b/test_regress/t/t_fallback_bad.out new file mode 100644 index 000000000..31a449042 --- /dev/null +++ b/test_regress/t/t_fallback_bad.out @@ -0,0 +1,30 @@ +%Error: t/t_fallback_bad.v:26:16: Can't find definition of task/function: 'tsk' + 26 | super.tsk; + | ^~~ +%Error: t/t_fallback_bad.v:27:15: Can't find definition of task/function: 'tsk' + 27 | this.tsk; + | ^~~ +%Error: t/t_fallback_bad.v:28:16: Can't find definition of variable: 'f' + 28 | super.f = 8; + | ^ +%Error: t/t_fallback_bad.v:29:15: Can't find definition of variable: 'f' + 29 | this.f = 8; + | ^ +%Error: t/t_fallback_bad.v:30:20: Can't find definition of 'tsk' in dotted task/function: 'sub1.sub2.tsk' + 30 | sub1.sub2.tsk; + | ^~~ + ... Known scopes under 'tsk': sub2 +%Error: t/t_fallback_bad.v:31:15: Can't find definition of scope/variable/func: 'f' + 31 | pkg::f = 8; + | ^ +%Error: t/t_fallback_bad.v:32:15: Can't find definition of task/function: 'tsk' + 32 | pkg::tsk(); + | ^~~ +%Error: t/t_fallback_bad.v:33:20: Can't find definition of 'f' in dotted variable: 'sub1.sub2.f' + 33 | sub1.sub2.f = 8; + | ^ +%Error: t/t_fallback_bad.v:34:20: Can't find definition of 'f' in dotted scope/variable: 'sub1.sub2.f' + 34 | sub1.sub2.f.f = 8; + | ^ + ... Known scopes under 'sub1.sub2': +%Error: Exiting due to diff --git a/test_regress/t/t_fallback_bad.py b/test_regress/t/t_fallback_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fallback_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fallback_bad.v b/test_regress/t/t_fallback_bad.v new file mode 100644 index 000000000..6722238a7 --- /dev/null +++ b/test_regress/t/t_fallback_bad.v @@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +int f = 5; +task tsk; endtask + +package pkg; +endpackage + +module subm; +endmodule + +module submo; + subm sub2(); +endmodule + +module t; + submo sub1(); + + class Base;endclass + class Cls extends Base; + task calltsk; + super.tsk; + this.tsk; + super.f = 8; + this.f = 8; + sub1.sub2.tsk; + pkg::f = 8; + pkg::tsk(); + sub1.sub2.f = 8; + sub1.sub2.f.f = 8; + endtask + endclass + + Cls obj = new; + initial begin + obj.calltsk; + if (f != 5) $stop; + end +endmodule diff --git a/test_regress/t/t_final.pl b/test_regress/t/t_final.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_final.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_final.py b/test_regress/t/t_final.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_final.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_bboxsys.pl b/test_regress/t/t_flag_bboxsys.pl deleted file mode 100755 index f3d98428b..000000000 --- a/test_regress/t/t_flag_bboxsys.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--bbox-sys"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_bboxsys.py b/test_regress/t/t_flag_bboxsys.py new file mode 100755 index 000000000..9cdbf53a8 --- /dev/null +++ b/test_regress/t/t_flag_bboxsys.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--bbox-sys"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_binary.pl b/test_regress/t/t_flag_binary.pl deleted file mode 100755 index ba2c15de6..000000000 --- a/test_regress/t/t_flag_binary.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_main.v"); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--binary'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_binary.py b/test_regress/t/t_flag_binary.py new file mode 100755 index 000000000..3aca74af7 --- /dev/null +++ b/test_regress/t/t_flag_binary.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_main.v" + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir", test.obj_dir, "--debug-check" + ], + verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_binary_parallel.pl b/test_regress/t/t_flag_binary_parallel.pl deleted file mode 100755 index f97b78cf8..000000000 --- a/test_regress/t/t_flag_binary_parallel.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_main.v"); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--binary', '--output-split 1'], - make_main => 0, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_binary_parallel.py b/test_regress/t/t_flag_binary_parallel.py new file mode 100755 index 000000000..3d881a0f1 --- /dev/null +++ b/test_regress/t/t_flag_binary_parallel.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_main.v" + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir", test.obj_dir, "--debug-check" + ], + verilator_flags2=['--binary', '--output-split 1'], + make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_build.pl b/test_regress/t/t_flag_build.pl deleted file mode 100755 index 985c72304..000000000 --- a/test_regress/t/t_flag_build.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_flag_make_cmake.v"); - -compile( # Don't call cmake nor gmake from driver.pl - verilator_flags2 => ['--exe --cc --build -j 2', - '../' . $Self->{main_filename}, - '-MAKEFLAGS -p --trace'], - ); - -execute( - check_finished => 1, - ); - -# If '-MAKEFLAGS --trace' is not properly processed, -# the log will not contain 'CMAKE_BUILD_TYPE:STRING=Debug'. -file_grep($Self->{obj_dir} . '/vlt_compile.log', /^Vt_flag_build_make.mk:\d+: update target \'(\w+)\' due to:/, 'Vt_flag_build'); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build.py b/test_regress/t/t_flag_build.py new file mode 100755 index 000000000..e7603f123 --- /dev/null +++ b/test_regress/t/t_flag_build.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_make_cmake.v" + +test.compile( # Don't call cmake nor gmake from driver.py + verilator_flags2=[ + '--exe --cc --build -j 2', '../' + test.main_filename, '-MAKEFLAGS -p --trace' + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_build_bad.pl b/test_regress/t/t_flag_build_bad.pl deleted file mode 100755 index a1ce4734f..000000000 --- a/test_regress/t/t_flag_build_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--build --make gmake"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -compile( - verilator_flags2 => ["--build --make cmake"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build_bad.py b/test_regress/t/t_flag_build_bad.py new file mode 100755 index 000000000..6161025f1 --- /dev/null +++ b/test_regress/t/t_flag_build_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--build --make gmake"], + fails=True, + expect_filename=test.golden_filename) + +test.compile(verilator_flags2=["--build --make cmake"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_build_bad2.pl b/test_regress/t/t_flag_build_bad2.pl deleted file mode 100755 index b61a1b234..000000000 --- a/test_regress/t/t_flag_build_bad2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_flag_make_cmake.v"); - -compile( - # Need --no-print-directory so golden file doesn't compare directory names - verilator_flags2 => ["--build --MAKEFLAGS --no-print-directory" - ." --MAKEFLAGS illegal-flag-to-fail-make"], - fails => 1, - # Recursive make breaks the golden compare - #expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build_bad2.py b/test_regress/t/t_flag_build_bad2.py new file mode 100755 index 000000000..c25924cf5 --- /dev/null +++ b/test_regress/t/t_flag_build_bad2.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_make_cmake.v" + +test.compile( + # Need --no-print-directory so golden file doesn't compare directory names + verilator_flags2=[ + "--build --MAKEFLAGS --no-print-directory", " --MAKEFLAGS illegal-flag-to-fail-make" + ], + # Recursive make breaks the golden compare + #expect_filename = test.golden_filename + fails=True) + +test.passes() diff --git a/test_regress/t/t_flag_build_dep_bin.pl b/test_regress/t/t_flag_build_dep_bin.pl deleted file mode 100755 index 95eda3687..000000000 --- a/test_regress/t/t_flag_build_dep_bin.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ['--build-dep-bin', 'path_to_exe'], - ); - -file_grep("$Self->{obj_dir}/$Self->{vm_prefix}__ver.d", qr/path_to_exe/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build_dep_bin.py b/test_regress/t/t_flag_build_dep_bin.py new file mode 100755 index 000000000..fc4874e71 --- /dev/null +++ b/test_regress/t/t_flag_build_dep_bin.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=['--build-dep-bin', 'path_to_exe']) + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "__ver.d", r'path_to_exe') + +test.passes() diff --git a/test_regress/t/t_flag_build_jobs_and_j.pl b/test_regress/t/t_flag_build_jobs_and_j.pl deleted file mode 100755 index bd8c6da26..000000000 --- a/test_regress/t/t_flag_build_jobs_and_j.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd.. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_flag_make_cmake.v"); - -compile( - verilator_flags2 => ['--exe --cc --build -j 10 --build-jobs 2 --stats', - '../' . $Self->{main_filename}], - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{stats}, qr/Build jobs: 2/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build_jobs_and_j.py b/test_regress/t/t_flag_build_jobs_and_j.py new file mode 100755 index 000000000..bdc9b5ee9 --- /dev/null +++ b/test_regress/t/t_flag_build_jobs_and_j.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_make_cmake.v" + +test.compile(verilator_flags2=[ + '--exe --cc --build -j 10 --build-jobs 2 --stats', '../' + test.main_filename +]) + +test.execute() + +test.file_grep(test.stats, r'Build jobs: 2') + +test.passes() diff --git a/test_regress/t/t_flag_build_jobs_bad.pl b/test_regress/t/t_flag_build_jobs_bad.pl deleted file mode 100755 index 8432e74c6..000000000 --- a/test_regress/t/t_flag_build_jobs_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - verilator_flags => [qw(--build-jobs -1 --build)], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build_jobs_bad.py b/test_regress/t/t_flag_build_jobs_bad.py new file mode 100755 index 000000000..d944bef02 --- /dev/null +++ b/test_regress/t/t_flag_build_jobs_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, + verilator_flags=["--build-jobs -1 --build"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_comp_limit_parens.pl b/test_regress/t/t_flag_comp_limit_parens.pl deleted file mode 100755 index 444c84256..000000000 --- a/test_regress/t/t_flag_comp_limit_parens.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--comp-limit-parens 2"], - ); - -execute( - check_finished => 1, - ); - -my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root__DepSet*__Slow.cpp"); -file_grep_any(\@files, qr/Vdeeptemp/i); - -ok(1); -1; diff --git a/test_regress/t/t_flag_comp_limit_parens.py b/test_regress/t/t_flag_comp_limit_parens.py new file mode 100755 index 000000000..fd7df3778 --- /dev/null +++ b/test_regress/t/t_flag_comp_limit_parens.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--comp-limit-parens 2"]) + +test.execute() + +files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root__DepSet*__Slow.cpp") +test.file_grep_any(files, r'Vdeeptemp') + +test.passes() diff --git a/test_regress/t/t_flag_compiler_bad.pl b/test_regress/t/t_flag_compiler_bad.pl deleted file mode 100755 index 0bf39f727..000000000 --- a/test_regress/t/t_flag_compiler_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--compiler bad_one"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_compiler_bad.py b/test_regress/t/t_flag_compiler_bad.py new file mode 100755 index 000000000..bd99f7973 --- /dev/null +++ b/test_regress/t/t_flag_compiler_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--compiler bad_one"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_compiler_clang.pl b/test_regress/t/t_flag_compiler_clang.pl deleted file mode 100755 index edd331316..000000000 --- a/test_regress/t/t_flag_compiler_clang.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_compiler.v"); - -compile( - verilator_flags2 => ["--compiler clang"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_compiler_clang.py b/test_regress/t/t_flag_compiler_clang.py new file mode 100755 index 000000000..b3f8bb752 --- /dev/null +++ b/test_regress/t/t_flag_compiler_clang.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_compiler.v" + +test.compile(verilator_flags2=["--compiler clang"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_compiler_gcc.pl b/test_regress/t/t_flag_compiler_gcc.pl deleted file mode 100755 index faaedc67a..000000000 --- a/test_regress/t/t_flag_compiler_gcc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_compiler.v"); - -compile( - verilator_flags2 => ["--compiler gcc"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_compiler_gcc.py b/test_regress/t/t_flag_compiler_gcc.py new file mode 100755 index 000000000..e868fd2f5 --- /dev/null +++ b/test_regress/t/t_flag_compiler_gcc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_compiler.v" + +test.compile(verilator_flags2=["--compiler gcc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_compiler_msvc.pl b/test_regress/t/t_flag_compiler_msvc.pl deleted file mode 100755 index 01c70152c..000000000 --- a/test_regress/t/t_flag_compiler_msvc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_compiler.v"); - -compile( - verilator_flags2 => ["--compiler msvc"], # Bug requires msvc - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_compiler_msvc.py b/test_regress/t/t_flag_compiler_msvc.py new file mode 100755 index 000000000..33ce62dd2 --- /dev/null +++ b/test_regress/t/t_flag_compiler_msvc.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_compiler.v" + +test.compile( + # Bug requires msvc + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_context_bad.pl b/test_regress/t/t_flag_context_bad.pl deleted file mode 100755 index 054b31aac..000000000 --- a/test_regress/t/t_flag_context_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -Wno-context"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_context_bad.py b/test_regress/t/t_flag_context_bad.py new file mode 100755 index 000000000..b5c4b0655 --- /dev/null +++ b/test_regress/t/t_flag_context_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME -Wno-context"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_csplit.pl b/test_regress/t/t_flag_csplit.pl deleted file mode 100755 index bcb3f9eef..000000000 --- a/test_regress/t/t_flag_csplit.pl +++ /dev/null @@ -1,129 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -while (1) { - # This rule requires GNU make > 4.1 (or so, known broken in 3.81) - #%__Slow.o: %__Slow.cpp - # $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< - if (make_version() < 4.1) { - skip("Test requires GNU Make version >= 4.1"); - last; - } - - compile( - v_flags2 => ["--trace --output-split 1 --output-split-cfuncs 1 --exe ../$Self->{main_filename}"], - verilator_make_gmake => 0, - ); - - # We don't use the standard test_regress rules, as want to test the rules - # properly build - run(logfile => "$Self->{obj_dir}/vlt_gcc.log", - tee => $self->{verbose}, - cmd=>[$ENV{MAKE}, - "-C " . $Self->{obj_dir}, - "-f $Self->{vm_prefix}.mk", - "-j 4", - "VM_PREFIX=$Self->{vm_prefix}", - "TEST_OBJ_DIR=$Self->{obj_dir}", - "CPPFLAGS_DRIVER=-D".uc($Self->{name}), - ($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" : ""), - "OPT_FAST=-O2", - "OPT_SLOW=-O0", - "OPT_GLOBAL=-Os", - ($param{make_flags}||""), - ]); - - execute( - check_finished => 1, - ); - - # Splitting should set VM_PARALLEL_BUILDS to 1 by default - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}_classes.mk", qr/VM_PARALLEL_BUILDS\s*=\s*1/); - check_splits(); - check_no_all_file(); - check_gcc_flags("$Self->{obj_dir}/vlt_gcc.log"); - - ok(1); - last; -} -1; - -sub check_splits { - my $got1; - my $gotSyms1; - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - if ($file =~ /Syms__1/) { - $gotSyms1 = 1; - } elsif ($file =~ /__1/) { - $got1 = 1; - } - check_cpp($file); - } - $got1 or error("No __1 split file found"); - $gotSyms1 or error("No Syms__1 split file found"); -} - -sub check_no_all_file { - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - if ($file =~ qr/__ALL.cpp/) { - error("__ALL.cpp file found: $file"); - } - } -} - -sub check_cpp { - my $filename = shift; - my $size = -s $filename; - printf " File %6d %s\n", $size, $filename if $Self->{verbose}; - my $fh = IO::File->new("<$filename") or error("$! $filenme"); - my @funcs; - while (defined(my $line = $fh->getline)) { - if ($line =~ /^(void|IData)\s+(.*::.*){/) { - my $func = $2; - $func =~ s/\(.*$//; - print "\tFunc $func\n" if $Self->{verbose}; - if ($func !~ /::_eval_initial_loop$/ - && $func !~ /::__Vconfigure$/ - && $func !~ /::trace$/ - && $func !~ /::traceInit$/ - && $func !~ /::traceFull$/ - && $func !~ /::final$/ - && $func !~ /::prepareClone$/ - && $func !~ /::atClone$/ - ) { - push @funcs, $func; - } - } - } - if ($#funcs > 0) { - error("Split had multiple functions in $filename\n\t" . join("\n\t", @funcs)); - } -} - -sub check_gcc_flags { - my $filename = shift; - my $fh = IO::File->new("<$filename") or error("$! $filenme"); - while (defined(my $line = $fh->getline)) { - chomp $line; - print ":log: $line\n" if $Self->{verbose}; - if ($line =~ /$Self->{vm_prefix}\S*\.cpp/) { - my $filetype = ($line =~ /Slow|Syms/) ? "slow" : "fast"; - my $opt = ($line !~ /-O2/) ? "slow" : "fast"; - print "$filetype, $opt, $line\n" if $Self->{verbose}; - if ($filetype ne $opt) { - error("${filetype} file compiled as if was ${opt}: $line"); - } - } elsif ($line =~ /\.cpp/ and $line !~ /-Os/) { - error("library file not compiled with OPT_GLOBAL: $line"); - } - } -} diff --git a/test_regress/t/t_flag_csplit.py b/test_regress/t/t_flag_csplit.py new file mode 100755 index 000000000..d05df9e3c --- /dev/null +++ b/test_regress/t/t_flag_csplit.py @@ -0,0 +1,115 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + + +def check_splits(): + got1 = False + gotSyms1 = False + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'Syms__1', filename): + gotSyms1 = True + elif re.search(r'__1', filename): + got1 = True + if not got1: + test.error("No __1 split file found") + if not gotSyms1: + test.error("No Syms__1 split file found") + + +def check_no_all_file(): + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'__ALL.cpp', filename): + test.error("__ALL.cpp file found: " + filename) + + +def check_cpp(filename): + size = os.path.getsize(filename) + if test.verbose: + print(" File %6d %s\n" % (size, filename)) + funcs = [] + with open(filename, 'r', encoding="utf8") as fh: + for line in fh: + m = re.search(r'^(void|IData)\s+(.*::.*){', line) + if not m: + continue + func = m.group(2) + func = re.sub(r'\(.*$', '', func) + if test.verbose: + print("\tFunc " + func) + if (re.search(r'(::_eval_initial_loop$', func) or re.search(r'::__Vconfigure$', func) + or re.search(r'::trace$', func) or re.search(r'::traceInit$', func) + or re.search(r'::traceFull$', func) or re.search(r'::final$', func) + or re.search(r'::prepareClone$', func) or re.search(r'::atClone$', func)): + continue + funcs.append(func) + + if len(funcs) > 0: + test.error("Split had multiple functions in $filename\n\t" + "\n\t".join(funcs)) + + +def check_gcc_flags(filename): + with open(filename, 'r', encoding="utf8") as fh: + for line in fh: + line = line.rstrip() + if test.verbose: + print(":log: " + line) + if re.search(r'' + test.vm_prefix + r'\S*\.cpp', line): + filetype = "slow" if re.search(r'(Slow|Syms)', line) else "fast" + opt = "fast" if re.search(r'-O2', line) else "slow" + if test.verbose: + print(filetype + ", " + opt + ", " + line) + if filetype != opt: + test.error(filetype + " file compiled as if was " + opt + ": " + line) + elif re.search(r'.cpp', line) and not re.search(r'-Os', line): + test.error("library file not compiled with OPT_GLOBAL: " + line) + + +# This rule requires GNU make > 4.1 (or so, known broken in 3.81) +#%__Slow.o: %__Slow.cpp +# $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< +if not test.make_version or float(test.make_version) < 4.1: + test.skip("Test requires GNU Make version >= 4.1") + +test.compile(v_flags2=["--trace", + "--output-split 1", + "--output-split-cfuncs 1", + "--exe", + "../" + test.main_filename], + verilator_make_gmake=False) # yapf:disable + +# We don't use the standard test_regress rules, as want to test the rules +# properly build +test.run(logfile=test.obj_dir + "/vlt_gcc.log", + tee=test.verbose, + cmd=[os.environ["MAKE"], + "-C " + test.obj_dir, + "-f "+test.vm_prefix+".mk", + "-j 4", + "VM_PREFIX="+test.vm_prefix, + "TEST_OBJ_DIR="+test.obj_dir, + "CPPFLAGS_DRIVER=-D"+test.name.upper(), + ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if test.verbose else ""), + "OPT_FAST=-O2", + "OPT_SLOW=-O0", + "OPT_GLOBAL=-Os", + ]) # yapf:disable + +test.execute() + +# Splitting should set VM_PARALLEL_BUILDS to 1 by default +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*1') +check_splits() +check_no_all_file() +check_gcc_flags(test.obj_dir + "/vlt_gcc.log") + +test.passes() diff --git a/test_regress/t/t_flag_csplit_eval.pl b/test_regress/t/t_flag_csplit_eval.pl deleted file mode 100755 index 3b44c3193..000000000 --- a/test_regress/t/t_flag_csplit_eval.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -sub check_evals { - my $got = 0; - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - my $fh = IO::File->new("<$file"); - local $/; undef $/; - my $wholefile = <$fh>; - - if ($wholefile =~ /__eval_nba__[0-9]+\(.*\)\s*{/) { - ++$got; - } - } - $got >= 2 or error("Too few _eval functions found: $got"); -} - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--output-split 1 --output-split-cfuncs 20"], - verilator_make_gmake => 0, # Slow to compile, so skip it - ); - -check_evals(); - -ok(1); -1; diff --git a/test_regress/t/t_flag_csplit_eval.py b/test_regress/t/t_flag_csplit_eval.py new file mode 100755 index 000000000..55d94dcc2 --- /dev/null +++ b/test_regress/t/t_flag_csplit_eval.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + + +def check_evals(): + got = 0 + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + wholefile = test.file_contents(filename) + if re.search(r'__eval_nba__[0-9]+\(.*\)\s*{', wholefile): + got += 1 + + if got < 3: + test.error("Too few _eval functions found: " + str(got)) + + +test.compile(v_flags2=["--output-split 1 --output-split-cfuncs 20"], + verilator_make_gmake=False) # Slow to compile, so skip it) + +check_evals() + +test.passes() diff --git a/test_regress/t/t_flag_csplit_groups.py b/test_regress/t/t_flag_csplit_groups.py new file mode 100755 index 000000000..8fe9707ba --- /dev/null +++ b/test_regress/t/t_flag_csplit_groups.py @@ -0,0 +1,125 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.top_filename = "t/t_flag_csplit.v" + + +def check_splits(): + got1 = False + gotSyms1 = False + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'Syms__1', filename): + gotSyms1 = True + elif re.search(r'__1', filename): + got1 = True + if not got1: + test.error("No __1 split file found") + if not gotSyms1: + test.error("No Syms__1 split file found") + + +def check_no_all_file(): + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'__ALL.cpp', filename): + test.error("__ALL.cpp file found: " + filename) + + +def check_cpp(filename): + size = os.path.getsize(filename) + if test.verbose: + print(" File %6d %s\n" % (size, filename)) + funcs = [] + with open(filename, 'r', encoding="utf8") as fh: + for line in fh: + m = re.search(r'^(void|IData)\s+(.*::.*){', line) + if not m: + continue + func = m.group(2) + func = re.sub(r'\(.*$', '', func) + if test.verbose: + print("\tFunc " + func) + if (re.search(r'(::_eval_initial_loop$', func) or re.search(r'::__Vconfigure$', func) + or re.search(r'::trace$', func) or re.search(r'::traceInit$', func) + or re.search(r'::traceFull$', func) or re.search(r'::final$', func) + or re.search(r'::prepareClone$', func) or re.search(r'::atClone$', func)): + continue + funcs.append(func) + + if len(funcs) > 0: + test.error("Split had multiple functions in $filename\n\t" + "\n\t".join(funcs)) + + +def check_gcc_flags(filename): + with open(filename, 'r', encoding="utf8") as fh: + for line in fh: + line = line.rstrip() + if test.verbose: + print(":log: " + line) + if re.search(r'' + test.vm_prefix + r'\S*\.cpp', line): + filetype = "slow" if re.search(r'(Slow|Syms)', line) else "fast" + opt = "fast" if re.search(r'-O2', line) else "slow" + if test.verbose: + print(filetype + ", " + opt + ", " + line) + if filetype != opt: + test.error(filetype + " file compiled as if was " + opt + ": " + line) + elif re.search(r'.cpp', line) and not re.search(r'-Os', line): + test.error("library file not compiled with OPT_GLOBAL: " + line) + + +# This rule requires GNU make > 4.1 (or so, known broken in 3.81) +#%__Slow.o: %__Slow.cpp +# $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< +if not test.make_version or float(test.make_version) < 4.1: + test.skip("Test requires GNU Make version >= 4.1") + +test.compile(v_flags2=["--trace", + "--output-split 1", + "--output-groups 2", + "--output-split-cfuncs 1", + "--exe", + "../" + test.main_filename], + verilator_make_gmake=False) # yapf:disable + +# We don't use the standard test_regress rules, as want to test the rules +# properly build +test.run(logfile=test.obj_dir + "/vlt_gcc.log", + tee=test.verbose, + cmd=[os.environ["MAKE"], + "-C " + test.obj_dir, + "-f "+test.vm_prefix+".mk", + "-j 4", + "VM_PREFIX="+test.vm_prefix, + "TEST_OBJ_DIR="+test.obj_dir, + "CPPFLAGS_DRIVER=-D"+test.name.upper(), + ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if test.verbose else ""), + "OPT_FAST=-O2", + "OPT_SLOW=-O0", + "OPT_GLOBAL=-Os", + ]) # yapf:disable + +test.execute() + +# Splitting should set VM_PARALLEL_BUILDS to 1 by default +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*1') +check_splits() +check_no_all_file() +check_gcc_flags(test.obj_dir + "/vlt_gcc.log") + +# Check that only vm_classes_*.cpp are to be compiled +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "sub") +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_Slow_1") +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_1") +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_Slow_2") +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_2") + +test.passes() diff --git a/test_regress/t/t_flag_csplit_off.pl b/test_regress/t/t_flag_csplit_off.pl deleted file mode 100755 index 64d8e466a..000000000 --- a/test_regress/t/t_flag_csplit_off.pl +++ /dev/null @@ -1,89 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_flag_csplit.v"); - -while (1) { - # This rule requires GNU make > 4.1 (or so, known broken in 3.81) - #%__Slow.o: %__Slow.cpp - # $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< - if (make_version() < 4.1) { - skip("Test requires GNU Make version >= 4.1"); - last; - } - - compile( - v_flags2 => ["--trace --output-split 0 --exe ../$Self->{main_filename}"], - verilator_make_gmake => 0, - ); - - # We don't use the standard test_regress rules, as want to test the rules - # properly build - run(logfile => "$Self->{obj_dir}/vlt_gcc.log", - tee => $self->{verbose}, - cmd=>[$ENV{MAKE}, - "-C " . $Self->{obj_dir}, - "-f $Self->{vm_prefix}.mk", - "-j 4", - "VM_PREFIX=$Self->{vm_prefix}", - "TEST_OBJ_DIR=$Self->{obj_dir}", - "CPPFLAGS_DRIVER=-D".uc($Self->{name}), - ($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" : ""), - "OPT_FAST=-O2", - "OPT_SLOW=-O0", - ($param{make_flags}||""), - ]); - - execute( - check_finished => 1, - ); - - # Never spliting, so should set VM_PARALLEL_BUILDS to 0 by default - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}_classes.mk", qr/VM_PARALLEL_BUILDS\s*=\s*0/); - check_no_splits(); - check_all_file(); - check_gcc_flags("$Self->{obj_dir}/vlt_gcc.log"); - - ok(1); - last; -} -1; - -sub check_no_splits { - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - $file =~ s/__024root//; - if ($file =~ qr/__[1-9]/) { - error("Split file found: $file"); - } - } -} - -sub check_all_file { - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - if ($file =~ qr/__ALL.cpp/) { - return; - } - } - error("__ALL.cpp file not found"); -} - -sub check_gcc_flags { - my $filename = shift; - my $fh = IO::File->new("<$filename") or error("$! $filenme"); - while (defined(my $line = $fh->getline)) { - chomp $line; - print ":log: $line\n" if $Self->{verbose}; - if ($line =~ /\.cpp/ && $line =~ qr/-O0/) { - error("File built as slow (should be in __ALL.cpp) : $line"); - } - } -} diff --git a/test_regress/t/t_flag_csplit_off.py b/test_regress/t/t_flag_csplit_off.py new file mode 100755 index 000000000..bdad4a618 --- /dev/null +++ b/test_regress/t/t_flag_csplit_off.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_flag_csplit.v" + + +def check_no_splits(): + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + filename = re.sub(r'__024root', '', filename) + if re.search(r'__[1-9]', filename): + test.error("Split file found: " + filename) + + +def check_all_file(): + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'__ALL.cpp', filename): + return + + +def check_gcc_flags(filename): + with open(filename, 'r', encoding="utf8") as fh: + for line in fh: + line = line.rstrip() + if test.verbose: + print(":log: " + line) + if re.search(r'\.cpp', line) and re.search('-O0', line): + test.error("File built as slow (should be in __ALL.cpp) : " + line) + + +# This rule requires GNU make > 4.1 (or so, known broken in 3.81) +#%__Slow.o: %__Slow.cpp +# $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< +if not test.make_version or float(test.make_version) < 4.1: + test.skip("Test requires GNU Make version >= 4.1") + +test.compile(v_flags2=["--trace --output-split 0 --exe ../" + test.main_filename], + verilator_make_gmake=False) + +# We don't use the standard test_regress rules, as want to test the rules +# properly build +test.run(logfile=test.obj_dir + "/vlt_gcc.log", + tee=test.verbose, + cmd=[ + os.environ["MAKE"], "-C " + test.obj_dir, "-f " + test.vm_prefix + ".mk", "-j 4", + "VM_PREFIX=" + test.vm_prefix, "TEST_OBJ_DIR=" + test.obj_dir, + "CPPFLAGS_DRIVER=-D" + test.name.upper(), + ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if test.verbose else ""), "OPT_FAST=-O2", + "OPT_SLOW=-O0" + ]) + +test.execute() + +# Never spliting, so should set VM_PARALLEL_BUILDS to 0 by default +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*0') +check_no_splits() +check_all_file() +check_gcc_flags(test.obj_dir + "/vlt_gcc.log") + +test.passes() diff --git a/test_regress/t/t_flag_debug_noleak.pl b/test_regress/t/t_flag_debug_noleak.pl deleted file mode 100755 index aad25c780..000000000 --- a/test_regress/t/t_flag_debug_noleak.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--debug --no-debug-leak"], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_debug_noleak.py b/test_regress/t/t_flag_debug_noleak.py new file mode 100755 index 000000000..effa05d68 --- /dev/null +++ b/test_regress/t/t_flag_debug_noleak.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--debug --no-debug-leak"], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.passes() diff --git a/test_regress/t/t_flag_debugi9.pl b/test_regress/t/t_flag_debugi9.pl deleted file mode 100755 index 6db7a5c95..000000000 --- a/test_regress/t/t_flag_debugi9.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--debug --debugi 9"], - tee => 0, - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_debugi9.py b/test_regress/t/t_flag_debugi9.py new file mode 100755 index 000000000..c0da0071a --- /dev/null +++ b/test_regress/t/t_flag_debugi9.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--debug --debugi 9"], + tee=False, + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.passes() diff --git a/test_regress/t/t_flag_decoration.pl b/test_regress/t/t_flag_decoration.pl deleted file mode 100755 index 82d6aeddc..000000000 --- a/test_regress/t/t_flag_decoration.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_decoration.v"); - -compile( - verilator_flags2 => ["--decoration"], - ); - -file_grep_not("$Self->{obj_dir}/V$Self->{name}.h", qr!\n// CONSTRUCTORS!); -file_grep("$Self->{obj_dir}/V$Self->{name}.h", qr!\n // CONSTRUCTORS!); -file_grep_not("$Self->{obj_dir}/V$Self->{name}.h", qr!/\*t/t_flag_decoration!); - -ok(1); -1; diff --git a/test_regress/t/t_flag_decoration.py b/test_regress/t/t_flag_decoration.py new file mode 100755 index 000000000..55807f346 --- /dev/null +++ b/test_regress/t/t_flag_decoration.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_decoration.v" + +test.compile(verilator_flags2=["--decoration"]) + +test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'\n// CONSTRUCTORS') +test.file_grep(test.obj_dir + "/V" + test.name + ".h", r'\n // CONSTRUCTORS') +test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'/\*t/t_flag_decoration') + +test.passes() diff --git a/test_regress/t/t_flag_decoration_no.pl b/test_regress/t/t_flag_decoration_no.pl deleted file mode 100755 index 9f2f6a84b..000000000 --- a/test_regress/t/t_flag_decoration_no.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_decoration.v"); - -compile( - verilator_flags2 => ["--no-decoration"], - ); - -file_grep("$Self->{obj_dir}/V$Self->{name}.h", qr!\n// CONSTRUCTORS!); -file_grep_not("$Self->{obj_dir}/V$Self->{name}.h", qr!\n // CONSTRUCTORS!); -file_grep_not("$Self->{obj_dir}/V$Self->{name}.h", qr!/\*t/t_flag_decoration!); - -ok(1); -1; diff --git a/test_regress/t/t_flag_decoration_no.py b/test_regress/t/t_flag_decoration_no.py new file mode 100755 index 000000000..af6c9f21b --- /dev/null +++ b/test_regress/t/t_flag_decoration_no.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_decoration.v" + +test.compile(verilator_flags2=["--no-decoration"]) + +test.file_grep(test.obj_dir + "/V" + test.name + ".h", r'\n// CONSTRUCTORS') +test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'\n // CONSTRUCTORS') +test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'/\*t/t_flag_decoration') + +test.passes() diff --git a/test_regress/t/t_flag_decorations_bad.pl b/test_regress/t/t_flag_decorations_bad.pl deleted file mode 100755 index 238b5dfc0..000000000 --- a/test_regress/t/t_flag_decorations_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_decoration.v"); - -lint( - verilator_flags2 => ["-decorations BAD"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_decorations_bad.py b/test_regress/t/t_flag_decorations_bad.py new file mode 100755 index 000000000..081a6cc01 --- /dev/null +++ b/test_regress/t/t_flag_decorations_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_decoration.v" + +test.lint(verilator_flags2=["-decorations BAD"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_decorations_node.pl b/test_regress/t/t_flag_decorations_node.pl deleted file mode 100755 index e611e91ba..000000000 --- a/test_regress/t/t_flag_decorations_node.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_decoration.v"); - -compile( - verilator_flags2 => ["--decorations node"], - ); - -file_grep_not("$Self->{obj_dir}/V$Self->{name}.h", qr!\n// CONSTRUCTORS!); -file_grep("$Self->{obj_dir}/V$Self->{name}.h", qr!\n // CONSTRUCTORS!); -file_grep("$Self->{obj_dir}/V$Self->{name}.h", qr!/\*t/t_flag_decoration!); - -ok(1); -1; diff --git a/test_regress/t/t_flag_decorations_node.py b/test_regress/t/t_flag_decorations_node.py new file mode 100755 index 000000000..a3f6e7efe --- /dev/null +++ b/test_regress/t/t_flag_decorations_node.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_decoration.v" + +test.compile(verilator_flags2=["--decorations node"]) + +test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", "\n// CONSTRUCTORS") +test.file_grep(test.obj_dir + "/V" + test.name + ".h", "\n // CONSTRUCTORS") +test.file_grep(test.obj_dir + "/V" + test.name + ".h", r'/\*t/t_flag_decoration') + +test.passes() diff --git a/test_regress/t/t_flag_define.pl b/test_regress/t/t_flag_define.pl deleted file mode 100755 index 35f485834..000000000 --- a/test_regress/t/t_flag_define.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["-f t/t_flag_define.vc -DCMD_DEF -DCMD_UNDEF -UCMD_UNDEF +define+CMD_DEF2"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_define.py b/test_regress/t/t_flag_define.py new file mode 100755 index 000000000..68eca8398 --- /dev/null +++ b/test_regress/t/t_flag_define.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["-f t/t_flag_define.vc -DCMD_DEF -DCMD_UNDEF -UCMD_UNDEF +define+CMD_DEF2"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_deprecated_bad.pl b/test_regress/t/t_flag_deprecated_bad.pl deleted file mode 100755 index ba2b1d388..000000000 --- a/test_regress/t/t_flag_deprecated_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--trace-fst-thread --order-clock-delay"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_deprecated_bad.py b/test_regress/t/t_flag_deprecated_bad.py new file mode 100755 index 000000000..8cdf75fef --- /dev/null +++ b/test_regress/t/t_flag_deprecated_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--trace-fst-thread --order-clock-delay"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_errorlimit_bad.pl b/test_regress/t/t_flag_errorlimit_bad.pl deleted file mode 100755 index 6f645f2c0..000000000 --- a/test_regress/t/t_flag_errorlimit_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --error-limit 2"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_errorlimit_bad.py b/test_regress/t/t_flag_errorlimit_bad.py new file mode 100755 index 000000000..41ee4fce1 --- /dev/null +++ b/test_regress/t/t_flag_errorlimit_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --error-limit 2"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_expand_limit.pl b/test_regress/t/t_flag_expand_limit.pl deleted file mode 100755 index 4bbbb8f4e..000000000 --- a/test_regress/t/t_flag_expand_limit.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--expand-limit 1 --stats -fno-dfg'], - ); - -file_grep($Self->{stats}, qr/Optimizations, expand limited\s+(\d+)/i, 3); - -ok(1); -1; diff --git a/test_regress/t/t_flag_expand_limit.py b/test_regress/t/t_flag_expand_limit.py new file mode 100755 index 000000000..c5e6b9338 --- /dev/null +++ b/test_regress/t/t_flag_expand_limit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--expand-limit 1 --stats -fno-dfg']) + +test.file_grep(test.stats, r'Optimizations, expand limited\s+(\d+)', 3) + +test.passes() diff --git a/test_regress/t/t_flag_f.pl b/test_regress/t/t_flag_f.pl deleted file mode 100755 index d2925619a..000000000 --- a/test_regress/t/t_flag_f.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["-f t/t_flag_f.vc"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_f.py b/test_regress/t/t_flag_f.py new file mode 100755 index 000000000..340eb7020 --- /dev/null +++ b/test_regress/t/t_flag_f.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["-f t/t_flag_f.vc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_f_bad_cmt.pl b/test_regress/t/t_flag_f_bad_cmt.pl deleted file mode 100755 index 24d8b0de5..000000000 --- a/test_regress/t/t_flag_f_bad_cmt.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - v_flags2 => ["-f t/t_flag_f_bad_cmt.vc"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_f_bad_cmt.py b/test_regress/t/t_flag_f_bad_cmt.py new file mode 100755 index 000000000..19aee7a96 --- /dev/null +++ b/test_regress/t/t_flag_f_bad_cmt.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(v_flags2=["-f t/t_flag_f_bad_cmt.vc"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_fi.pl b/test_regress/t/t_flag_fi.pl deleted file mode 100755 index b8bc97594..000000000 --- a/test_regress/t/t_flag_fi.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["-FI $Self->{t_dir}/t_flag_fi_h.h", - "--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_fi.py b/test_regress/t/t_flag_fi.py new file mode 100755 index 000000000..8bc5976ef --- /dev/null +++ b/test_regress/t/t_flag_fi.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["-FI", test.t_dir + "/t_flag_fi_h.h", "--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_future.pl b/test_regress/t/t_flag_future.pl deleted file mode 100755 index 5216b1dfd..000000000 --- a/test_regress/t/t_flag_future.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => [qw(--lint-only --future0 thefuture --future1 thefuturei --thefuture -thefuture +thefuture --thefuturei 1 -Wfuture-FUTURE1 -Wfuture-FUTURE2)], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_future.py b/test_regress/t/t_flag_future.py new file mode 100755 index 000000000..68aa7e65a --- /dev/null +++ b/test_regress/t/t_flag_future.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=[ + "--lint-only --future0 thefuture --future1 thefuturei --thefuture -thefuture +thefuture --thefuturei 1 -Wfuture-FUTURE1 -Wfuture-FUTURE2" +]) + +test.passes() diff --git a/test_regress/t/t_flag_future_bad.pl b/test_regress/t/t_flag_future_bad.pl deleted file mode 100755 index 60a812ac4..000000000 --- a/test_regress/t/t_flag_future_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_future.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_future_bad.py b/test_regress/t/t_flag_future_bad.py new file mode 100755 index 000000000..761b8b708 --- /dev/null +++ b/test_regress/t/t_flag_future_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_future.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_generate_key.pl b/test_regress/t/t_flag_generate_key.pl deleted file mode 100755 index 3458cfd36..000000000 --- a/test_regress/t/t_flag_generate_key.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--generate-key"], - expect => qr/VL-KEY/, - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_generate_key.py b/test_regress/t/t_flag_generate_key.py new file mode 100755 index 000000000..4565feae4 --- /dev/null +++ b/test_regress/t/t_flag_generate_key.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--generate-key"], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.file_grep(test.compile_log_filename, r'VL-KEY') + +test.passes() diff --git a/test_regress/t/t_flag_getenv.pl b/test_regress/t/t_flag_getenv.pl deleted file mode 100755 index 0c000760d..000000000 --- a/test_regress/t/t_flag_getenv.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -setenv('FOOBARTEST', "gotit"); - -run( - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --getenv FOOBARTEST"], - expect => 'gotit -', - logfile => "$Self->{obj_dir}/simx.log", - verilator_run => 1, - ); - -foreach my $var (qw(MAKE PERL PYTHON3 SYSTEMC SYSTEMC_ARCH SYSTEMC_LIBDIR VERILATOR_ROOT)) { - run( - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --getenv ${var}"], - logfile => "$Self->{obj_dir}/simx.log", - verilator_run => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_flag_getenv.py b/test_regress/t/t_flag_getenv.py new file mode 100755 index 000000000..82aee49d3 --- /dev/null +++ b/test_regress/t/t_flag_getenv.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.setenv('FOOBARTEST', "gotit") + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --getenv FOOBARTEST"], + logfile=test.compile_log_filename, + verilator_run=True) + +test.file_grep(test.compile_log_filename, r'gotit') + +for var in [ + 'MAKE', 'PERL', 'PYTHON3', 'SYSTEMC', 'SYSTEMC_ARCH', 'SYSTEMC_LIBDIR', 'VERILATOR_ROOT' +]: + test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--getenv", var], + logfile=test.obj_dir + "/simx.log", + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_flag_help.pl b/test_regress/t/t_flag_help.pl deleted file mode 100755 index 274c8d40d..000000000 --- a/test_regress/t/t_flag_help.pl +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use File::Basename; - -scenarios(dist => 1); - -# See also t_flag_version.pl - -sub check { - my $interpreter = shift; - my $prog = shift; - - my $logfile = "$Self->{obj_dir}/t_help__" . basename($prog) . ".log"; - - run(fails => 0, - cmd => [$interpreter, $prog, "--help"], - logfile => $logfile, - tee => 0, - verilator_run => 1, - ); - - file_grep($logfile, qr/(DISTRIBUTION|usage:)/i); -} - -check("perl", "$ENV{VERILATOR_ROOT}/bin/verilator"); -check("perl", "$ENV{VERILATOR_ROOT}/bin/verilator_coverage"); - -check("python3", "$ENV{VERILATOR_ROOT}/bin/verilator_ccache_report"); -check("python3", "$ENV{VERILATOR_ROOT}/bin/verilator_gantt"); -check("python3", "$ENV{VERILATOR_ROOT}/bin/verilator_profcfunc"); - -if (-x "$ENV{VERILATOR_ROOT}/bin/verilator_difftree") { - check("python3", "$ENV{VERILATOR_ROOT}/bin/verilator_difftree"); -} - -ok(1); -1; diff --git a/test_regress/t/t_flag_help.py b/test_regress/t/t_flag_help.py new file mode 100755 index 000000000..262ed934f --- /dev/null +++ b/test_regress/t/t_flag_help.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +# See also t_flag_version.py + + +def check(prog): + logfile = test.obj_dir + "/t_help__" + os.path.basename(prog) + ".log" + + test.run(fails=False, cmd=[prog, "--help"], logfile=logfile, tee=False, verilator_run=True) + + test.file_grep(logfile, r'(DISTRIBUTION|usage:)') + + +check(os.environ["VERILATOR_ROOT"] + "/bin/verilator") +check(os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage") + +check(os.environ["VERILATOR_ROOT"] + "/bin/verilator_ccache_report") +check(os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt") +check(os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc") + +if os.path.exists(os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree"): + check(os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree") + +test.passes() diff --git a/test_regress/t/t_flag_help_valgrind.pl b/test_regress/t/t_flag_help_valgrind.pl deleted file mode 100755 index 47fa4e396..000000000 --- a/test_regress/t/t_flag_help_valgrind.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -run(fails => 0, - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator", "--help", "--valgrind"], - tee => 0, - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_help_valgrind.py b/test_regress/t/t_flag_help_valgrind.py new file mode 100755 index 000000000..3969109d8 --- /dev/null +++ b/test_regress/t/t_flag_help_valgrind.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +test.run(fails=False, + cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--help", "--valgrind"], + tee=False, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_flag_hier0_bad.pl b/test_regress/t/t_flag_hier0_bad.pl deleted file mode 100755 index fb589c623..000000000 --- a/test_regress/t/t_flag_hier0_bad.pl +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_hier_block.v"); - -lint( - fails => 1, - verilator_flags2 => ['--hierarchical-block', - 'modName,mangledName,param0,"paramValue0",param0,"paramValue1",param1,2,param3', - '--hierarchical-block', - 'modName', - '--hierarchical-block', - 'mod0,mod1,\'"str\\\'', # end with backslash - '--hierarchical-block', - 'mod2,mod3,\'"str\\a\'', # unexpected 'a' after backslash - '--hierarchical-block', - 'mod4,mod5,\'"str"abc\',', # not end with " - '--hierarchical-block', - 'mod6,mod7,\'"str"\',', # end with , - '--hierarchical-block', - 'mod8,mod9,\'s"tr"\',', # unexpected " - '--hierarchical-block', - 'modA,modB,param,', # end with , - ], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_hier0_bad.py b/test_regress/t/t_flag_hier0_bad.py new file mode 100755 index 000000000..9d9e638b4 --- /dev/null +++ b/test_regress/t/t_flag_hier0_bad.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_hier_block.v" + +test.lint( + fails=True, + verilator_flags2=[ + '--hierarchical-block', + 'modName,mangledName,param0,"paramValue0",param0,"paramValue1",param1,2,param3', + '--hierarchical-block', 'modName', + '--hierarchical-block', 'mod0,mod1,\'"str\\\'', # end with backslash + '--hierarchical-block', 'mod2,mod3,\'"str\\a\'', # unexpected 'a' after backslash + '--hierarchical-block', 'mod4,mod5,\'"str"abc\',', # not end with " + '--hierarchical-block', 'mod6,mod7,\'"str"\',', # end with , + '--hierarchical-block', 'mod8,mod9,\'s"tr"\',', # unexpected " + '--hierarchical-block', 'modA,modB,param,', # end with , + ], + expect_filename=test.golden_filename) # yapf:disable + +test.passes() diff --git a/test_regress/t/t_flag_hier1_bad.pl b/test_regress/t/t_flag_hier1_bad.pl deleted file mode 100755 index 8a3475533..000000000 --- a/test_regress/t/t_flag_hier1_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_hier_block.v"); - -lint( - fails => 1, - verilator_flags2 => ['--hierarchical', - '--hierarchical-child 1', - 'modName', - ], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_hier1_bad.py b/test_regress/t/t_flag_hier1_bad.py new file mode 100755 index 000000000..6c7b401a8 --- /dev/null +++ b/test_regress/t/t_flag_hier1_bad.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_hier_block.v" + +test.lint(fails=True, + verilator_flags2=[ + '--hierarchical', + '--hierarchical-child 1', + 'modName', + ], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_i_empty.pl b/test_regress/t/t_flag_i_empty.pl deleted file mode 100755 index 8cee660a7..000000000 --- a/test_regress/t/t_flag_i_empty.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-Wno-MODDUP -I t_flag_i_empty.v t_flag_i_empty.v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_i_empty.py b/test_regress/t/t_flag_i_empty.py new file mode 100755 index 000000000..885a35916 --- /dev/null +++ b/test_regress/t/t_flag_i_empty.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-Wno-MODDUP -I t_flag_i_empty.v t_flag_i_empty.v"]) + +test.passes() diff --git a/test_regress/t/t_flag_instr_count_dpi_bad.pl b/test_regress/t/t_flag_instr_count_dpi_bad.pl deleted file mode 100755 index ebc71f887..000000000 --- a/test_regress/t/t_flag_instr_count_dpi_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--instr-count-dpi -1"], - fails => 1, - expect => "%Error: --instr-count-dpi must be non-negative: -1" - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_instr_count_dpi_bad.py b/test_regress/t/t_flag_instr_count_dpi_bad.py new file mode 100755 index 000000000..b3e8df414 --- /dev/null +++ b/test_regress/t/t_flag_instr_count_dpi_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--instr-count-dpi -1"], fails=True) + +test.file_grep(test.compile_log_filename, "%Error: --instr-count-dpi must be non-negative: -1") + +test.passes() diff --git a/test_regress/t/t_flag_invalid2_bad.pl b/test_regress/t/t_flag_invalid2_bad.pl deleted file mode 100755 index 7aae03f4b..000000000 --- a/test_regress/t/t_flag_invalid2_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ['+invalid-plus'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_invalid2_bad.py b/test_regress/t/t_flag_invalid2_bad.py new file mode 100755 index 000000000..a91c4f34f --- /dev/null +++ b/test_regress/t/t_flag_invalid2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, verilator_flags2=['+invalid-plus'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_invalid_bad.pl b/test_regress/t/t_flag_invalid_bad.pl deleted file mode 100755 index ac8693b64..000000000 --- a/test_regress/t/t_flag_invalid_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ['--invalid-dash'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_invalid_bad.py b/test_regress/t/t_flag_invalid_bad.py new file mode 100755 index 000000000..139abb1ab --- /dev/null +++ b/test_regress/t/t_flag_invalid_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, verilator_flags2=['--invalid-dash'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_j_hier.py b/test_regress/t/t_flag_j_hier.py new file mode 100755 index 000000000..4c393789a --- /dev/null +++ b/test_regress/t/t_flag_j_hier.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--hierarchical -j --build-jobs 2']) + +test.passes() diff --git a/test_regress/t/t_flag_j_hier.v b/test_regress/t/t_flag_j_hier.v new file mode 100644 index 000000000..885f06437 --- /dev/null +++ b/test_regress/t/t_flag_j_hier.v @@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + logic a; + s u_s(.a(a)); +endmodule + +module s(output logic a); + /*verilator hier_block*/ +endmodule diff --git a/test_regress/t/t_flag_language.pl b/test_regress/t/t_flag_language.pl deleted file mode 100755 index b6ccf5eef..000000000 --- a/test_regress/t/t_flag_language.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--language 1364-2001'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_language.py b/test_regress/t/t_flag_language.py new file mode 100755 index 000000000..8ce75c418 --- /dev/null +++ b/test_regress/t/t_flag_language.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--language 1364-2001']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_language_bad.pl b/test_regress/t/t_flag_language_bad.pl deleted file mode 100755 index bfd78a9ab..000000000 --- a/test_regress/t/t_flag_language_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ['--language 1-2-3-4'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_language_bad.py b/test_regress/t/t_flag_language_bad.py new file mode 100755 index 000000000..fb255200c --- /dev/null +++ b/test_regress/t/t_flag_language_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--language 1-2-3-4'], fails=True) + +test.passes() diff --git a/test_regress/t/t_flag_ldflags.pl b/test_regress/t/t_flag_ldflags.pl deleted file mode 100755 index b68cea7ad..000000000 --- a/test_regress/t/t_flag_ldflags.pl +++ /dev/null @@ -1,50 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -run(cmd => ["cd $Self->{obj_dir}" - . " && $ENV{CXX} -c ../../t/t_flag_ldflags_a.cpp" - . " && ar -cr t_flag_ldflags_a.a t_flag_ldflags_a.o" - . " && ranlib t_flag_ldflags_a.a "], - check_finished => 0); -run(cmd => ["cd $Self->{obj_dir}" - . " && $ENV{CXX} -fPIC -c ../../t/t_flag_ldflags_so.cpp" - . " && $ENV{CXX} -shared -o t_flag_ldflags_so.so -lc t_flag_ldflags_so.o"], - check_finished => 0); - -compile( - # Pass multiple -D's so we check quoting works properly - v_flags2 => ["-CFLAGS '-DCFLAGS_FROM_CMDLINE -DCFLAGS2_FROM_CMDLINE' ", - "t/t_flag_ldflags_c.cpp", - "t_flag_ldflags_a.a", - "t_flag_ldflags_so.so",], - ); - - -# On OS X, LD_LIBRARY_PATH is ignored, so set rpath of the exe to find the .so -if ($^O eq "darwin") { - run(cmd => ["cd $Self->{obj_dir}" - . " && install_name_tool -add_rpath \@executable_path/." - . " $Self->{vm_prefix}"], - check_finished => 0); - run(cmd => ["cd $Self->{obj_dir}" - . " && install_name_tool -change t_flag_ldflags_so.so" - . " \@rpath/t_flag_ldflags_so.so $Self->{vm_prefix}"], - check_finished => 0); -} - -execute( - check_finished => 1, - run_env => "LD_LIBRARY_PATH=$Self->{obj_dir}:$ENV{LD_LIBRARY_PATH}", - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_ldflags.py b/test_regress/t/t_flag_ldflags.py new file mode 100755 index 000000000..661f2b1af --- /dev/null +++ b/test_regress/t/t_flag_ldflags.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import sys + +test.scenarios('vlt') + +CXX = os.environ["CXX"] + +test.run( + cmd=[ + "cd " + test.obj_dir # + + " && " + CXX + " -c ../../t/t_flag_ldflags_a.cpp" # + + " && ar -cr t_flag_ldflags_a.a t_flag_ldflags_a.o" # + + " && ranlib t_flag_ldflags_a.a " + ], + check_finished=False) + +test.run( + cmd=[ + "cd " + test.obj_dir # + + " && " + CXX + " -fPIC -c ../../t/t_flag_ldflags_so.cpp" # + + " && " + CXX + " -shared -o t_flag_ldflags_so.so -lc t_flag_ldflags_so.o" + ], + check_finished=False) + +test.compile( + # Pass multiple -D's so we check quoting works properly + v_flags2=[ + "-CFLAGS '-DCFLAGS_FROM_CMDLINE -DCFLAGS2_FROM_CMDLINE' ", "t/t_flag_ldflags_c.cpp", + "t_flag_ldflags_a.a", "t_flag_ldflags_so.so" + ]) + +# On OS X, LD_LIBRARY_PATH is ignored, so set rpath of the exe to find the .so +if sys.platform == "darwin": + test.run(cmd=[ + "cd " + test.obj_dir + " && install_name_tool -add_rpath @executable_path/.", + test.vm_prefix + ], + check_finished=False) + + test.run(cmd=[ + "cd " + test.obj_dir + " && install_name_tool -change t_flag_ldflags_so.so" + + " @rpath/t_flag_ldflags_so.so", test.vm_prefix + ], + check_finished=False) + +test.execute(run_env="LD_LIBRARY_PATH=" + test.obj_dir + ":" + + test.getenv_def("LD_LIBRARY_PATH", "")) + +test.passes() diff --git a/test_regress/t/t_flag_lib.pl b/test_regress/t/t_flag_lib.pl deleted file mode 100755 index d2c9d5c46..000000000 --- a/test_regress/t/t_flag_lib.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ['-v', 't/t_flag_libinc.v'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_lib.py b/test_regress/t/t_flag_lib.py new file mode 100755 index 000000000..59e45bab9 --- /dev/null +++ b/test_regress/t/t_flag_lib.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=['-v', 't/t_flag_libinc.v']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_lib_dpi.pl b/test_regress/t/t_flag_lib_dpi.pl deleted file mode 100755 index 9cb3e8bfb..000000000 --- a/test_regress/t/t_flag_lib_dpi.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2023 by Shupei Fan. -# SPDX-License-Identifier: CC0-1.0 - -scenarios(vlt => 1); - -run(logfile => "$Self->{obj_dir}/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - "-cc", - "--build", - '--no-timing', - "-Mdir", - "$Self->{obj_dir}", - "t/t_flag_lib_dpi.v", - "$Self->{t_dir}/t_flag_lib_dpi.cpp", - "$Self->{t_dir}/t_flag_lib_dpi_main.cpp"], - verilator_run => 1, - ); - -run(logfile => "$Self->{obj_dir}/cxx_compile.log", - cmd => ["cd $Self->{obj_dir}" - . " && cp $Self->{t_dir}/t_flag_lib_dpi.mk t_flag_lib_dpi.mk" - . " && $ENV{MAKE} -f t_flag_lib_dpi.mk t_flag_lib_dpi_test" - . " && ./t_flag_lib_dpi_test"], - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_lib_dpi.py b/test_regress/t/t_flag_lib_dpi.py new file mode 100755 index 000000000..225f73eb6 --- /dev/null +++ b/test_regress/t/t_flag_lib_dpi.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.run(logfile=test.obj_dir + "/vlt_compile.log", + cmd=[ + "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", "--build", + '--no-timing', "-Mdir", test.obj_dir, "t/t_flag_lib_dpi.v", + test.t_dir + "/t_flag_lib_dpi.cpp", test.t_dir + "/t_flag_lib_dpi_main.cpp" + ], + verilator_run=True) + +test.run( + logfile=test.obj_dir + "/cxx_compile.log", + cmd=[ + "cd " + test.obj_dir # + + " && cp " + test.t_dir + "/t_flag_lib_dpi.mk t_flag_lib_dpi.mk" # + + " && " + os.environ["MAKE"] + " -f t_flag_lib_dpi.mk t_flag_lib_dpi_test" # + + " && ./t_flag_lib_dpi_test" + ]) + +test.passes() diff --git a/test_regress/t/t_flag_main.pl b/test_regress/t/t_flag_main.pl deleted file mode 100755 index 2d1040ad8..000000000 --- a/test_regress/t/t_flag_main.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--exe --build --main'], - # Check that code --main produces uses only most modern API features - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_main.py b/test_regress/t/t_flag_main.py new file mode 100755 index 000000000..52df09333 --- /dev/null +++ b/test_regress/t/t_flag_main.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir " + test.obj_dir, "--debug-check" + ], + verilator_flags2=['--exe --build --main'], + # Check that code --main produces uses only most modern API features + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_main_sc_bad.pl b/test_regress/t/t_flag_main_sc_bad.pl deleted file mode 100755 index 75c182412..000000000 --- a/test_regress/t/t_flag_main_sc_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ['--exe --build --main --sc'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_main_sc_bad.py b/test_regress/t/t_flag_main_sc_bad.py new file mode 100755 index 000000000..08d370745 --- /dev/null +++ b/test_regress/t/t_flag_main_sc_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--exe --build --main --sc'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_main_top_name.pl b/test_regress/t/t_flag_main_top_name.pl deleted file mode 100755 index 027e13395..000000000 --- a/test_regress/t/t_flag_main_top_name.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Don Williamson and Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_main_top_name.v"); - -compile( - verilator_flags => ["-Mdir $Self->{obj_dir}", "--exe", "--build", "--main"], - verilator_flags2 => ["--top-module top", "--main-top-name ALTOP"], - make_main => 0, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_main_top_name.py b/test_regress/t/t_flag_main_top_name.py new file mode 100755 index 000000000..40d6b3d44 --- /dev/null +++ b/test_regress/t/t_flag_main_top_name.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_main_top_name.v" + +test.compile(verilator_flags=["-Mdir " + test.obj_dir, "--exe", "--build", "--main"], + verilator_flags2=["--top-module top", "--main-top-name ALTOP"], + make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_main_top_name_empty.pl b/test_regress/t/t_flag_main_top_name_empty.pl deleted file mode 100755 index 2f4bc41fb..000000000 --- a/test_regress/t/t_flag_main_top_name_empty.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Don Williamson and Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_main_top_name.v"); - -compile( - verilator_flags => ["-Mdir $Self->{obj_dir}", "--exe", "--build", "--main"], - verilator_flags2 => ["--top-module top", "--main-top-name -", "-DMAIN_TOP_NAME_EMPTY"], - make_main => 0, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_main_top_name_empty.py b/test_regress/t/t_flag_main_top_name_empty.py new file mode 100755 index 000000000..872d0f076 --- /dev/null +++ b/test_regress/t/t_flag_main_top_name_empty.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_main_top_name.v" + +test.compile(verilator_flags=["-Mdir " + test.obj_dir, "--exe", "--build", "--main"], + verilator_flags2=["--top-module top", "--main-top-name -", "-DMAIN_TOP_NAME_EMPTY"], + make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_make_bad.pl b/test_regress/t/t_flag_make_bad.pl deleted file mode 100755 index 1c6f23aec..000000000 --- a/test_regress/t/t_flag_make_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--make bad_one"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_make_bad.py b/test_regress/t/t_flag_make_bad.py new file mode 100755 index 000000000..39e7f80eb --- /dev/null +++ b/test_regress/t/t_flag_make_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--make bad_one"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_make_cmake.pl b/test_regress/t/t_flag_make_cmake.pl deleted file mode 100755 index 868582ff7..000000000 --- a/test_regress/t/t_flag_make_cmake.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_make_gmake => 0, - verilator_make_cmake => 1, - ); - -if (!$Self->have_cmake) { - skip("cmake is not installed"); -} else { - my $cmakecache = $Self->{obj_dir} . "/CMakeCache.txt"; - if (! -e $cmakecache) { - error("$cmakecache does not exist.") - } - - execute( - check_finished => 1, - ); -} -ok(1); -1; diff --git a/test_regress/t/t_flag_make_cmake.py b/test_regress/t/t_flag_make_cmake.py new file mode 100755 index 000000000..1802450e1 --- /dev/null +++ b/test_regress/t/t_flag_make_cmake.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_make_gmake=False, verilator_make_cmake=True) + +if not test.have_cmake: + test.skip("cmake is not installed") + +cmakecache = test.obj_dir + "/CMakeCache.txt" +if not os.path.exists(cmakecache): + test.error(cmakecache + " does not exist") + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_make_cmake_sc.pl b/test_regress/t/t_flag_make_cmake_sc.pl deleted file mode 100755 index c94d61d8c..000000000 --- a/test_regress/t/t_flag_make_cmake_sc.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# This test tests CMake support for SystemC - -scenarios(simulator => 1); - -compile( - verilator_make_gmake => 0, - verilator_make_cmake => 1, - verilator_flags2 => ["-sc"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_make_cmake_sc.py b/test_regress/t/t_flag_make_cmake_sc.py new file mode 100755 index 000000000..b32ca9667 --- /dev/null +++ b/test_regress/t/t_flag_make_cmake_sc.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# This test tests CMake support for SystemC + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_make_gmake=False, verilator_make_cmake=True, verilator_flags2=["-sc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_make_gmake.pl b/test_regress/t/t_flag_make_gmake.pl deleted file mode 100755 index b25888d6e..000000000 --- a/test_regress/t/t_flag_make_gmake.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_make_cmake.v"); - -compile( - verilator_flags2 => ['--make gmake'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_make_gmake.py b/test_regress/t/t_flag_make_gmake.py new file mode 100755 index 000000000..aa50772d8 --- /dev/null +++ b/test_regress/t/t_flag_make_gmake.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_make_cmake.v" + +test.compile(verilator_flags2=['--make gmake']) + +test.passes() diff --git a/test_regress/t/t_flag_mmd.pl b/test_regress/t/t_flag_mmd.pl deleted file mode 100755 index 7f2955642..000000000 --- a/test_regress/t/t_flag_mmd.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-MMD -MP"], - ); - -file_grep("$Self->{obj_dir}/Vt_flag_mmd__ver.d", qr!t/t_flag_mmd.v!x); - -ok(1); -1; diff --git a/test_regress/t/t_flag_mmd.py b/test_regress/t/t_flag_mmd.py new file mode 100755 index 000000000..4709521ae --- /dev/null +++ b/test_regress/t/t_flag_mmd.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-MMD -MP"]) + +test.file_grep(test.obj_dir + "/Vt_flag_mmd__ver.d", r't/t_flag_mmd.v') + +test.passes() diff --git a/test_regress/t/t_flag_names.pl b/test_regress/t/t_flag_names.pl deleted file mode 100755 index 4a878bda8..000000000 --- a/test_regress/t/t_flag_names.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--mod-prefix modPrefix --top-module t --l2-name l2Name"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_names.py b/test_regress/t/t_flag_names.py new file mode 100755 index 000000000..f4807c1bc --- /dev/null +++ b/test_regress/t/t_flag_names.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--mod-prefix modPrefix --top-module t --l2-name l2Name"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_no_unlimited_stack.pl b/test_regress/t/t_flag_no_unlimited_stack.pl deleted file mode 100755 index ef1a415a2..000000000 --- a/test_regress/t/t_flag_no_unlimited_stack.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# Just check whether the flag is recognized. -lint( - verilator_flags2 => ["--no-unlimited-stack"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_no_unlimited_stack.py b/test_regress/t/t_flag_no_unlimited_stack.py new file mode 100755 index 000000000..d414c3381 --- /dev/null +++ b/test_regress/t/t_flag_no_unlimited_stack.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# Just check whether the flag is recognized. +test.lint(verilator_flags2=["--no-unlimited-stack"]) + +test.passes() diff --git a/test_regress/t/t_flag_nofile_bad.pl b/test_regress/t/t_flag_nofile_bad.pl deleted file mode 100755 index 88e6198ba..000000000 --- a/test_regress/t/t_flag_nofile_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --lint-only"], - fails => 1, - logfile => "$Self->{obj_dir}/sim.log", - expect_filename => $Self->{golden_filename}, - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_nofile_bad.py b/test_regress/t/t_flag_nofile_bad.py new file mode 100755 index 000000000..15e3547bb --- /dev/null +++ b/test_regress/t/t_flag_nofile_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --lint-only"], + fails=True, + logfile=test.obj_dir + "/sim.log", + expect_filename=test.golden_filename, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_flag_nomod_bad.pl b/test_regress/t/t_flag_nomod_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_flag_nomod_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_nomod_bad.py b/test_regress/t/t_flag_nomod_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_flag_nomod_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_noop_bad.pl b/test_regress/t/t_flag_noop_bad.pl deleted file mode 100755 index 7f1db4900..000000000 --- a/test_regress/t/t_flag_noop_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator", - "t_flag_noop_bad.v"], - fails => 1, - logfile => "$Self->{obj_dir}/sim.log", - expect_filename => $Self->{golden_filename}, - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_noop_bad.py b/test_regress/t/t_flag_noop_bad.py new file mode 100755 index 000000000..8ac06d1a7 --- /dev/null +++ b/test_regress/t/t_flag_noop_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator", "t_flag_noop_bad.v"], + fails=True, + logfile=test.obj_dir + "/sim.log", + expect_filename=test.golden_filename, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_flag_only_bad.pl b/test_regress/t/t_flag_only_bad.pl deleted file mode 100755 index aa2276bc0..000000000 --- a/test_regress/t/t_flag_only_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_flag_main.v"); - -lint( - verilator_flags2 => ["--binary -E --dpi-hdr-only --lint-only --xml-only --json-only -Wall"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_only_bad.py b/test_regress/t/t_flag_only_bad.py new file mode 100755 index 000000000..be2835493 --- /dev/null +++ b/test_regress/t/t_flag_only_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_main.v" + +test.lint(verilator_flags2=["--binary -E --dpi-hdr-only --lint-only --xml-only --json-only -Wall"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_only_bad2.pl b/test_regress/t/t_flag_only_bad2.pl deleted file mode 100755 index 0d33fbf71..000000000 --- a/test_regress/t/t_flag_only_bad2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_flag_main.v"); - -lint( - verilator_flags2 => ["--build -E -Wno-fatal --dpi-hdr-only --lint-only --xml-only --json-only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_only_bad2.py b/test_regress/t/t_flag_only_bad2.py new file mode 100755 index 000000000..10fa26356 --- /dev/null +++ b/test_regress/t/t_flag_only_bad2.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_main.v" + +test.lint( + verilator_flags2=["--build -E -Wno-fatal --dpi-hdr-only --lint-only --xml-only --json-only"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_only_bad3.pl b/test_regress/t/t_flag_only_bad3.pl deleted file mode 100755 index d01fc2b88..000000000 --- a/test_regress/t/t_flag_only_bad3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_flag_main.v"); - -lint( - verilator_flags2 => ["-Wall --lint-only -Wno-fatal --dpi-hdr-only --xml-only --json-only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_only_bad3.py b/test_regress/t/t_flag_only_bad3.py new file mode 100755 index 000000000..7bd76ebe4 --- /dev/null +++ b/test_regress/t/t_flag_only_bad3.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_main.v" + +test.lint(verilator_flags2=["-Wall --lint-only -Wno-fatal --dpi-hdr-only --xml-only --json-only"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_output_groups_bad.out b/test_regress/t/t_flag_output_groups_bad.out new file mode 100644 index 000000000..a52d629fd --- /dev/null +++ b/test_regress/t/t_flag_output_groups_bad.out @@ -0,0 +1,2 @@ +%Error: --output-groups must be >= 0: -1 +%Error: Exiting due to diff --git a/test_regress/t/t_flag_output_groups_bad.py b/test_regress/t/t_flag_output_groups_bad.py new file mode 100755 index 000000000..1a3a5346b --- /dev/null +++ b/test_regress/t/t_flag_output_groups_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--output-groups -1'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_parameter.pl b/test_regress/t/t_flag_parameter.pl deleted file mode 100755 index fc20a6898..000000000 --- a/test_regress/t/t_flag_parameter.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # It is not possible to put them into the options file - v_flags2 => ['-f t/t_flag_parameter.vc'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_parameter.py b/test_regress/t/t_flag_parameter.py new file mode 100755 index 000000000..a0976af1a --- /dev/null +++ b/test_regress/t/t_flag_parameter.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # It is not possible to put them into the options file + v_flags2=['-f t/t_flag_parameter.vc']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_parameter_bad.pl b/test_regress/t/t_flag_parameter_bad.pl deleted file mode 100755 index ec91b7170..000000000 --- a/test_regress/t/t_flag_parameter_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_parameter.v"); - -lint( - fails => 1, - # It is not possible to put them into the options file - v_flags2 => ['-GPARAM_THAT_DOES_NON_EXIST=1'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_parameter_bad.py b/test_regress/t/t_flag_parameter_bad.py new file mode 100755 index 000000000..79a16fac7 --- /dev/null +++ b/test_regress/t/t_flag_parameter_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_parameter.v" + +test.lint( + fails=True, + # It is not possible to put them into the options file + v_flags2=['-GPARAM_THAT_DOES_NON_EXIST=1'], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_parameter_hier.pl b/test_regress/t/t_flag_parameter_hier.pl deleted file mode 100755 index 655ecf51b..000000000 --- a/test_regress/t/t_flag_parameter_hier.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # For Verilator, all PARAMs at all levels are overridden - # Error if parameter not found - #verilator_flags2 => ['-GPARAM=10 -Gtop.t.x.HIER=20'], # HIER would error - verilator_flags2 => ['-GPARAM=10'], - # For NC, always implies a hierarchy, only HIER will be set - # Warns if sets nothing - nc_flags2 => ['+defparam+PARAM=10 +defparam+top.t.x.HIER=20'], - # For VCS, all PARAMs at all levels are overridden. Hierarchy not allowed. - # Informational on all overrides - vcs_flags2 => ['-pvalue+PARAM=10 -px.HIER=20'], - # For icarus -P without hierarchy does nothing, only can ref into top - iv_flags2 => ['-PPARAM=10', '-Ptop.HIER=30', '-Ptop.t.x.HIER=20'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_parameter_hier.py b/test_regress/t/t_flag_parameter_hier.py new file mode 100755 index 000000000..b795ba12c --- /dev/null +++ b/test_regress/t/t_flag_parameter_hier.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # For Verilator, all PARAMs at all levels are overridden + # Error if parameter not found + #verilator_flags2 = ['-GPARAM=10 -Gtop.t.x.HIER=20'], # HIER would error + verilator_flags2=['-GPARAM=10'], + # For NC, always implies a hierarchy, only HIER will be set + # Warns if sets nothing + nc_flags2=['+defparam+PARAM=10 +defparam+top.t.x.HIER=20'], + # For VCS, all PARAMs at all levels are overridden. Hierarchy not allowed. + # Informational on all overrides + vcs_flags2=['-pvalue+PARAM=10 -px.HIER=20'], + # For icarus -P without hierarchy does nothing, only can ref into top + iv_flags2=['-PPARAM=10', '-Ptop.HIER=30', '-Ptop.t.x.HIER=20']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_parameter_pkg.pl b/test_regress/t/t_flag_parameter_pkg.pl deleted file mode 100755 index c0493da3e..000000000 --- a/test_regress/t/t_flag_parameter_pkg.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-GPARAM_A=1'], - ms_flags2 => ['-GPARAM_A=1'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_parameter_pkg.py b/test_regress/t/t_flag_parameter_pkg.py new file mode 100755 index 000000000..84bc7ac5a --- /dev/null +++ b/test_regress/t/t_flag_parameter_pkg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-GPARAM_A=1'], ms_flags2=['-GPARAM_A=1']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_parameter_pkg.v b/test_regress/t/t_flag_parameter_pkg.v index b5c67e4ff..a0187b7d6 100644 --- a/test_regress/t/t_flag_parameter_pkg.v +++ b/test_regress/t/t_flag_parameter_pkg.v @@ -9,12 +9,7 @@ package pack_a; endpackage : pack_a //module t; -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); parameter PARAM_A = 0; diff --git a/test_regress/t/t_flag_prefix.pl b/test_regress/t/t_flag_prefix.pl deleted file mode 100755 index 940ddc16b..000000000 --- a/test_regress/t/t_flag_prefix.pl +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--prefix t_flag_prefix", # should be overridden - "--prefix Vprefix", - "--exe", "--main", "--stats", "--build"], - verilator_make_cmake => 0, - verilator_make_gmake => 0, - ); - -execute( - check_finished => 1, - executable => "$Self->{obj_dir}/Vprefix", - ); - -sub check_files { - foreach my $path (glob("$Self->{obj_dir}/*")) { - my $filename = substr $path, ((length $Self->{obj_dir}) + 1); - next if ($filename =~ /^.*\.log$/); - if ($filename =~ /t_flag_prefix/) { - error("bad filename $filename"); - next; - } - next if ($filename =~ /^(.*\.(o|a)|Vprefix)$/); - my $fh = IO::File->new("<$path") or error("$! $filenme"); - while (defined(my $line = $fh->getline)) { - $line =~ s/--prefix V?t_flag_prefix//g; - $line =~ s/obj_vlt\/t_flag_prefix//g; - $line =~ s/t\/t_flag_prefix\.v//g; - error("bad line in $filename: $line") if $line =~ /t_flag_prefix/; - } - } -} - -check_files(); - -ok(1); -1; diff --git a/test_regress/t/t_flag_prefix.py b/test_regress/t/t_flag_prefix.py new file mode 100755 index 000000000..3e0ee470a --- /dev/null +++ b/test_regress/t/t_flag_prefix.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + verilator_flags2=[ + "--prefix t_flag_prefix", # should be overridden + "--prefix Vprefix", + "--exe", + "--main", + "--stats", + "--build" + ], + verilator_make_cmake=False, + verilator_make_gmake=False) + +test.execute(executable=test.obj_dir + "/Vprefix") + + +def check_files(): + for path in test.glob_some(test.obj_dir + "/*"): + filename = path[(len(test.obj_dir) + 1):] + if re.search(r'\.log$', filename): + continue + if re.search(r't_flag_prefix', filename): + test.error("bad filename '" + filename + "'") + continue + if re.search(r'^(.*\.(o|a)|Vprefix)$', filename): + continue + with open(path, 'r', encoding="utf8") as fh: + for line in fh: + line = re.sub(r'--prefix V?t_flag_prefix', '', line) + line = re.sub(r'obj_vlt\/t_flag_prefix', '', line) + line = re.sub(r't\/t_flag_prefix\.v', '', line) + if re.search(r't_flag_prefix', line): + test.error(filename + ": bad line: " + line) + + +check_files() + +test.passes() diff --git a/test_regress/t/t_flag_quiet_exit.pl b/test_regress/t/t_flag_quiet_exit.pl deleted file mode 100755 index cb3d6bedd..000000000 --- a/test_regress/t/t_flag_quiet_exit.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_file_does_not_exist.v"); - -# Tests for the error message and then the absence of the -# "Command Failed" line -compile( - v_flags2 => ["--quiet-exit"], - fails => 1, - ); - -file_grep_not("$Self->{obj_dir}/vlt_compile.log", qr/Exiting due to/); -file_grep_not("$Self->{obj_dir}/vlt_compile.log", qr/Command Failed/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_quiet_exit.py b/test_regress/t/t_flag_quiet_exit.py new file mode 100755 index 000000000..ad7e5791a --- /dev/null +++ b/test_regress/t/t_flag_quiet_exit.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_file_does_not_exist.v" + +# Tests for the error message and then the absence of the +# "Command Failed" line +test.compile(v_flags2=["--quiet-exit"], fails=True) + +test.file_grep_not(test.compile_log_filename, r'Exiting due to') +test.file_grep_not(test.compile_log_filename, r'Command Failed') + +test.passes() diff --git a/test_regress/t/t_flag_quiet_stats.pl b/test_regress/t/t_flag_quiet_stats.pl deleted file mode 100755 index eb7961c00..000000000 --- a/test_regress/t/t_flag_quiet_stats.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--quiet-stats'], - verilator_make_gcc => 0, - logfile => $Self->{run_log_filename}, - ); - -file_grep_not($Self->{obj_dir}.'/vlt_compile.log', qr/V e r i l a t/i,); - -ok(1); -1; diff --git a/test_regress/t/t_flag_quiet_stats.py b/test_regress/t/t_flag_quiet_stats.py new file mode 100755 index 000000000..03b230104 --- /dev/null +++ b/test_regress/t/t_flag_quiet_stats.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--quiet-stats'], + verilator_make_gcc=False, + logfile=test.run_log_filename) + +test.file_grep_not(test.compile_log_filename, r'V e r i l a t') + +test.passes() diff --git a/test_regress/t/t_flag_quiet_stats2.pl b/test_regress/t/t_flag_quiet_stats2.pl deleted file mode 100755 index 5a87e9df8..000000000 --- a/test_regress/t/t_flag_quiet_stats2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_quiet_stats.v"); - -compile( - verilator_flags2 => ['--quiet'], - verilator_make_gcc => 0, - logfile => $Self->{run_log_filename}, - ); - -file_grep_not($Self->{obj_dir}.'/vlt_compile.log', qr/V e r i l a t/i,); - -ok(1); -1; diff --git a/test_regress/t/t_flag_quiet_stats2.py b/test_regress/t/t_flag_quiet_stats2.py new file mode 100755 index 000000000..0e875e258 --- /dev/null +++ b/test_regress/t/t_flag_quiet_stats2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_quiet_stats.v" + +test.compile(verilator_flags2=['--quiet'], verilator_make_gcc=False, logfile=test.run_log_filename) + +test.file_grep_not(test.compile_log_filename, r'V e r i l a t') + +test.passes() diff --git a/test_regress/t/t_flag_quiet_stats3.pl b/test_regress/t/t_flag_quiet_stats3.pl deleted file mode 100755 index f7e7580a5..000000000 --- a/test_regress/t/t_flag_quiet_stats3.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_quiet_stats.v"); - -compile( - verilator_flags2 => ['--quiet --no-quiet-stats'], - verilator_make_gcc => 0, - logfile => $Self->{run_log_filename}, - ); - -file_grep($Self->{obj_dir}.'/vlt_compile.log', qr/V e r i l a t/i,); - -ok(1); -1; diff --git a/test_regress/t/t_flag_quiet_stats3.py b/test_regress/t/t_flag_quiet_stats3.py new file mode 100755 index 000000000..f7fb9b54b --- /dev/null +++ b/test_regress/t/t_flag_quiet_stats3.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_quiet_stats.v" + +test.compile(verilator_flags2=['--quiet --no-quiet-stats'], + verilator_make_gcc=False, + logfile=test.run_log_filename) + +test.file_grep(test.compile_log_filename, r'V e r i l a t') + +test.passes() diff --git a/test_regress/t/t_flag_relinc.pl b/test_regress/t/t_flag_relinc.pl deleted file mode 100755 index 38fc1bf91..000000000 --- a/test_regress/t/t_flag_relinc.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - v_flags2 => ["--relative-includes", - "--lint-only $Self->{t_dir}/t_flag_relinc_dir/chip/t_flag_relinc_sub.v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_relinc.py b/test_regress/t/t_flag_relinc.py new file mode 100755 index 000000000..af6f9fa75 --- /dev/null +++ b/test_regress/t/t_flag_relinc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(v_flags2=[ + "--relative-includes", "--lint-only", test.t_dir + + "/t_flag_relinc_dir/chip/t_flag_relinc_sub.v" +]) + +test.passes() diff --git a/test_regress/t/t_flag_runtime_debug.pl b/test_regress/t/t_flag_runtime_debug.pl deleted file mode 100755 index 7e26eb589..000000000 --- a/test_regress/t/t_flag_runtime_debug.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_main.v"); - -compile( - verilator_flags2 => ['--binary --runtime-debug'], - ); - -execute( - check_finished => 1, - aslr_off => 1, # Some GCC versions hit an address-sanitizer bug otherwise - ); - -file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.mk", qr/VL_DEBUG=1/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_runtime_debug.py b/test_regress/t/t_flag_runtime_debug.py new file mode 100755 index 000000000..aabbbc531 --- /dev/null +++ b/test_regress/t/t_flag_runtime_debug.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_main.v" + +test.compile(verilator_flags2=['--binary --runtime-debug']) + +test.execute( + # Some GCC versions hit an address-sanitizer bug otherwise + aslr_off=True) + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".mk", r'VL_DEBUG=1') + +test.passes() diff --git a/test_regress/t/t_flag_skipidentical.pl b/test_regress/t/t_flag_skipidentical.pl deleted file mode 100755 index 731515d06..000000000 --- a/test_regress/t/t_flag_skipidentical.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -{ - compile(); - - print "NOTE: use --debugi, as --debug in driver turns off skip-identical\n"; - - my $outfile = "$Self->{obj_dir}/V" . $Self->{name} . ".cpp"; - my @oldstats = stat($outfile); - print "Old mtime=", $oldstats[9], "\n"; - $oldstats[9] or error("No output file found: $outfile\n"); - - sleep(2); # Or else it might take < 1 second to compile and see no diff. - - setenv('VERILATOR_DEBUG_SKIP_IDENTICAL', 1); - compile(); - - my @newstats = stat($outfile); - print "New mtime=", $newstats[9], "\n"; - - ($oldstats[9] == $newstats[9]) - or error("--skip-identical was ignored -- recompiled\n"); -} - -ok(1); -1; diff --git a/test_regress/t/t_flag_skipidentical.py b/test_regress/t/t_flag_skipidentical.py new file mode 100755 index 000000000..5b20bd00b --- /dev/null +++ b/test_regress/t/t_flag_skipidentical.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import time + +test.scenarios('vlt') + +test.compile() + +print("NOTE: use --debugi, as --debug in driver turns off skip-identical") + +outfile = test.obj_dir + "/V" + test.name + ".cpp" +oldstats = os.path.getmtime(outfile) +if not oldstats: + test.error("No output file found: " + outfile) +print("Old mtime=", oldstats) + +time.sleep(2) # Or else it might take < 1 second to compile and see no diff. + +test.setenv('VERILATOR_DEBUG_SKIP_IDENTICAL', "1") +test.compile() + +newstats = os.path.getmtime(outfile) +print("New mtime=", newstats) + +if oldstats != newstats: + test.error("--skip-identical was ignored -- recompiled") + +test.passes() diff --git a/test_regress/t/t_flag_stats.pl b/test_regress/t/t_flag_stats.pl deleted file mode 100755 index 854fb2b62..000000000 --- a/test_regress/t/t_flag_stats.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats --stats-vars"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_stats.py b/test_regress/t/t_flag_stats.py new file mode 100755 index 000000000..e3ec064b6 --- /dev/null +++ b/test_regress/t/t_flag_stats.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats --stats-vars"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_structs_packed.pl b/test_regress/t/t_flag_structs_packed.pl deleted file mode 100755 index 4f0a79a43..000000000 --- a/test_regress/t/t_flag_structs_packed.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -compile( - verilator_flags2 => ['--structs-packed'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_structs_packed.py b/test_regress/t/t_flag_structs_packed.py new file mode 100755 index 000000000..77a354d22 --- /dev/null +++ b/test_regress/t/t_flag_structs_packed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.compile(verilator_flags2=['--structs-packed']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_structs_packed_bad.pl b/test_regress/t/t_flag_structs_packed_bad.pl deleted file mode 100755 index 2ac9f69e8..000000000 --- a/test_regress/t/t_flag_structs_packed_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_flag_structs_packed.v"); - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_structs_packed_bad.py b/test_regress/t/t_flag_structs_packed_bad.py new file mode 100755 index 000000000..002271397 --- /dev/null +++ b/test_regress/t/t_flag_structs_packed_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_flag_structs_packed.v" + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_suggest.pl b/test_regress/t/t_flag_suggest.pl deleted file mode 100755 index 1022af5ff..000000000 --- a/test_regress/t/t_flag_suggest.pl +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my @opts; -# Typo -push @opts, "-ccc"; -# Typo of an option that starts with "--" -push @opts, "--ccc"; -# Typo of an option that starts with "-no-" -push @opts, "-no-asserT"; -# Typo of an option that starts with "-no" -push @opts, "-noasserT"; -# Typo of an option that allows "-no" -push @opts, "-asserT"; -# Typo of an option that starts with '+' -push @opts, "+definE+A=B"; -# Typo that takes arg -push @opts, "-CFLAGs -ggdb"; -# Typo of an undocumented option -push @opts, "-debug-aborT"; -# Typo of "-Wno" for partial match -push @opts, "-Won-SPLITVAR"; -# Typo after -Wno- for partial match -push @opts, "-Wno-SPLITVER"; -# Typo of -language -push @opts, "-language 1364-1997"; - -my $cmd = ""; - -foreach my $var (@opts) { - $cmd = $cmd . $ENV{VERILATOR_ROOT} . "/bin/verilator ${var}; "; -} - -run(cmd => [$cmd], - verilator_run => 1, - logfile => "$Self->{obj_dir}/sim.log", - fails => 1, - expect_filename => $Self->{golden_filename}, -); - -ok(1); -1; diff --git a/test_regress/t/t_flag_suggest.py b/test_regress/t/t_flag_suggest.py new file mode 100755 index 000000000..baf7f8394 --- /dev/null +++ b/test_regress/t/t_flag_suggest.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +opts = [] +# Typo +opts += ["-ccc"] +# Typo of an option that starts with "--" +opts += ["--ccc"] +# Typo of an option that starts with "-no-" +opts += ["-no-asserT"] +# Typo of an option that starts with "-no" +opts += ["-noasserT"] +# Typo of an option that allows "-no" +opts += ["-asserT"] +# Typo of an option that starts with '+' +opts += ["+definE+A=B"] +# Typo that takes arg +opts += ["-CFLAGs -ggdb"] +# Typo of an undocumented option +opts += ["-debug-aborT"] +# Typo of "-Wno" for partial match +opts += ["-Won-SPLITVAR"] +# Typo after -Wno- for partial match +opts += ["-Wno-SPLITVER"] +# Typo of -language +opts += ["-language 1364-1997"] + +cmd = "" +for var in opts: + cmd += os.environ["VERILATOR_ROOT"] + "/bin/verilator " + var + "; " + +test.run(cmd=[cmd], + verilator_run=True, + logfile=test.obj_dir + "/sim.log", + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_supported.pl b/test_regress/t/t_flag_supported.pl deleted file mode 100755 index ae36a6645..000000000 --- a/test_regress/t/t_flag_supported.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if ($Self->have_coroutines) { - run( - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --get-supported COROUTINES"], - expect => '1 -', - logfile => "$Self->{obj_dir}/vlt_coroutines.log", - verilator_run => 1, - ); -} - -if ($Self->have_sc) { - run( - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --get-supported SYSTEMC"], - expect => '1 -', - logfile => "$Self->{obj_dir}/vlt_systemc.log", - verilator_run => 1, - ); -} - -run( - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --get-supported DOES_NOT_EXIST"], - expect => '', - logfile => "$Self->{obj_dir}/vlt_does_not_exist.log", - verilator_run => 1, - ); - - -ok(1); -1; diff --git a/test_regress/t/t_flag_supported.py b/test_regress/t/t_flag_supported.py new file mode 100755 index 000000000..56d4984b8 --- /dev/null +++ b/test_regress/t/t_flag_supported.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +if test.have_coroutines: + test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --get-supported COROUTINES"], + logfile=test.obj_dir + "/vlt_coroutines.log", + expect_filename="t/t_flag_supported_1.out", + verilator_run=True) + +if test.have_sc: + test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --get-supported SYSTEMC"], + logfile=test.obj_dir + "/vlt_systemc.log", + expect_filename="t/t_flag_supported_1.out", + verilator_run=True) + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --get-supported DOES_NOT_EXIST"], + logfile=test.obj_dir + "/vlt_does_not_exist.log", + expect_filename="t/t_flag_supported_empty.out", + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_flag_supported_1.out b/test_regress/t/t_flag_supported_1.out new file mode 100755 index 000000000..d00491fd7 --- /dev/null +++ b/test_regress/t/t_flag_supported_1.out @@ -0,0 +1 @@ +1 diff --git a/test_regress/t/t_flag_supported_empty.out b/test_regress/t/t_flag_supported_empty.out new file mode 100755 index 000000000..8b1378917 --- /dev/null +++ b/test_regress/t/t_flag_supported_empty.out @@ -0,0 +1 @@ + diff --git a/test_regress/t/t_flag_threads_dpi_bad.pl b/test_regress/t/t_flag_threads_dpi_bad.pl deleted file mode 100755 index 46cf0221c..000000000 --- a/test_regress/t/t_flag_threads_dpi_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--threads-dpi bad_one"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_threads_dpi_bad.py b/test_regress/t/t_flag_threads_dpi_bad.py new file mode 100755 index 000000000..e37bc99e3 --- /dev/null +++ b/test_regress/t/t_flag_threads_dpi_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--threads-dpi bad_one"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_timescale.pl b/test_regress/t/t_flag_timescale.pl deleted file mode 100755 index 98ff5cfe2..000000000 --- a/test_regress/t/t_flag_timescale.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-timescale 1ms/1us"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_timescale.py b/test_regress/t/t_flag_timescale.py new file mode 100755 index 000000000..0aee7a5b7 --- /dev/null +++ b/test_regress/t/t_flag_timescale.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-timescale 1ms/1us"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_timescale_override.pl b/test_regress/t/t_flag_timescale_override.pl deleted file mode 100755 index 1cb5ff133..000000000 --- a/test_regress/t/t_flag_timescale_override.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-timescale-override 1ms/1us"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_timescale_override.py b/test_regress/t/t_flag_timescale_override.py new file mode 100755 index 000000000..f3c33e6b1 --- /dev/null +++ b/test_regress/t/t_flag_timescale_override.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-timescale-override 1ms/1us"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_timescale_override2.pl b/test_regress/t/t_flag_timescale_override2.pl deleted file mode 100755 index 58b219698..000000000 --- a/test_regress/t/t_flag_timescale_override2.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_timescale_override.v"); - -compile( - verilator_flags2 => ["-timescale-override /1us"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_timescale_override2.py b/test_regress/t/t_flag_timescale_override2.py new file mode 100755 index 000000000..1403c4c24 --- /dev/null +++ b/test_regress/t/t_flag_timescale_override2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_timescale_override.v" + +test.compile(verilator_flags2=["-timescale-override /1us"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_topmodule.pl b/test_regress/t/t_flag_topmodule.pl deleted file mode 100755 index c8e5ea2a6..000000000 --- a/test_regress/t/t_flag_topmodule.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--top-module b "], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_topmodule.py b/test_regress/t/t_flag_topmodule.py new file mode 100755 index 000000000..3d54ce7d9 --- /dev/null +++ b/test_regress/t/t_flag_topmodule.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--top-module b "]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_topmodule_bad.pl b/test_regress/t/t_flag_topmodule_bad.pl deleted file mode 100755 index 856e31ae4..000000000 --- a/test_regress/t/t_flag_topmodule_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_topmodule.v"); - -lint( - fails => 1, - nc => 0, # Need to get it not to give the prompt - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_topmodule_bad.py b/test_regress/t/t_flag_topmodule_bad.py new file mode 100755 index 000000000..55e58e547 --- /dev/null +++ b/test_regress/t/t_flag_topmodule_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_topmodule.v" + +test.lint( + fails=True, + nc=False, # Need to get it not to give the prompt + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_topmodule_bad2.pl b/test_regress/t/t_flag_topmodule_bad2.pl deleted file mode 100755 index c3f6245ff..000000000 --- a/test_regress/t/t_flag_topmodule_bad2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_topmodule.v"); - -lint( - fails => 1, - v_flags2 => ["--top-module notfound"], - nc => 0, # Need to get it not to give the prompt - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_topmodule_bad2.py b/test_regress/t/t_flag_topmodule_bad2.py new file mode 100755 index 000000000..e78d43f39 --- /dev/null +++ b/test_regress/t/t_flag_topmodule_bad2.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_topmodule.v" + +test.lint( + fails=True, + v_flags2=["--top-module notfound"], + nc=False, # Need to get it not to give the prompt + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_topmodule_inline.pl b/test_regress/t/t_flag_topmodule_inline.pl deleted file mode 100755 index b6bfb1af9..000000000 --- a/test_regress/t/t_flag_topmodule_inline.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # This also tests --top as opposed to --top-module - v_flags2 => ["--top b"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_topmodule_inline.py b/test_regress/t/t_flag_topmodule_inline.py new file mode 100755 index 000000000..5738ae537 --- /dev/null +++ b/test_regress/t/t_flag_topmodule_inline.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # This also tests --top as opposed to --top-module + v_flags2=["--top b"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_values_bad.pl b/test_regress/t/t_flag_values_bad.pl deleted file mode 100755 index a5f3d7743..000000000 --- a/test_regress/t/t_flag_values_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--output-split-cfuncs -1", - "--output-split-ctrace -1", - "--reloop-limit -1",], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_values_bad.py b/test_regress/t/t_flag_values_bad.py new file mode 100755 index 000000000..ab8c8bb79 --- /dev/null +++ b/test_regress/t/t_flag_values_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + verilator_flags2=["--output-split-cfuncs -1", "--output-split-ctrace -1", "--reloop-limit -1"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_values_deprecated.pl b/test_regress/t/t_flag_values_deprecated.pl deleted file mode 100755 index a4d6ad3c2..000000000 --- a/test_regress/t/t_flag_values_deprecated.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Werror-DEPRECATED", "--no-threads"], - fails => 1, - threads => 0, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_values_deprecated.py b/test_regress/t/t_flag_values_deprecated.py new file mode 100755 index 000000000..8db5f897f --- /dev/null +++ b/test_regress/t/t_flag_values_deprecated.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Werror-DEPRECATED", "--no-threads"], + fails=True, + threads=0, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_verilate.pl b/test_regress/t/t_flag_verilate.pl deleted file mode 100755 index aa1ec0ef8..000000000 --- a/test_regress/t/t_flag_verilate.pl +++ /dev/null @@ -1,61 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_flag_make_cmake.v"); - -# We expect below that Vt_flag_verilate.mk and others are not in the build -# tree already when doing --no-verilate, so we must remove them when -# re-running the test. -clean_objs(); - -compile( # Don't call cmake nor gmake from driver.pl. Nothing should be done here. - verilator_make_cmake => 0, - verilator_make_gmake => 0, - verilator_flags2 => ['--exe --cc --no-verilate', - '../' . $Self->{main_filename}] - ); - -# --no-verilate should skip Verilation -if ( -e $Self->{obj_dir} . '/Vt_flag_verilate.mk' ) { - $Self->error('Vt_flag_verilate.mk is unexpectedly created'); -} - -# --verilate this time -compile( # Don't call cmake nor gmake from driver.pl. Just verilate here. - verilator_make_cmake => 0, - verilator_make_gmake => 0, - verilator_flags2 => ['--exe --cc --verilate', - '../' . $Self->{main_filename}] - ); - -# must be verilated this time -if ( ! -e $Self->{obj_dir} . '/Vt_flag_verilate.mk' ) { - $Self->error('Vt_flag_verilate.mk does not exist'); -} - -# Just build, no Verilation. .tree must not be saved even with --dump-tree option. -compile( # Don't call cmake nor gmake from driver.pl. Just build here - verilator_flags2 => ['--exe --cc --build --no-verilate', - '../' . $Self->{main_filename}, - '--debugi 1 --dump-tree --dump-tree-addrids'], - ); - -# The previous run must not verilated, only build is expected. -if (-e $Self->{obj_dir} . '/Vt_flag_verilate_990_final.tree') { - $Self->error('Unexpectedly verilated.'); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_verilate.py b/test_regress/t/t_flag_verilate.py new file mode 100755 index 000000000..38928e3db --- /dev/null +++ b/test_regress/t/t_flag_verilate.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_make_cmake.v" + +# We expect below that Vt_flag_verilate.mk and others are not in the build +# tree already when doing --no-verilate, so we must remove them when +# re-running the test. +test.clean_objs() + +test.compile( # Don't call cmake nor gmake from driver.py. Nothing should be done here. + verilator_make_cmake=False, + verilator_make_gmake=False, + verilator_flags2=['--exe --cc --no-verilate', '../' + test.main_filename]) + +# --no-verilate should skip Verilation +if os.path.exists(test.obj_dir + '/Vt_flag_verilate.mk'): + test.error('Vt_flag_verilate.mk is unexpectedly created') + +# --verilate this time +test.compile( # Don't call cmake nor gmake from driver.py. Just verilate here. + verilator_make_cmake=False, + verilator_make_gmake=False, + verilator_flags2=['--exe --cc --verilate', '../' + test.main_filename]) + +# must be verilated this time +if not os.path.exists(test.obj_dir + '/Vt_flag_verilate.mk'): + test.error('Vt_flag_verilate.mk does not exist') + +# Just build, no Verilation. .tree must not be saved even with --dump-tree option. +test.compile( # Don't call cmake nor gmake from driver.py. Just build here + verilator_flags2=[ + '--exe --cc --build --no-verilate', '../' + test.main_filename, + '--debugi 1 --dump-tree --dump-tree-addrids' + ]) + +# The previous run must not verilated, only build is expected. +if os.path.exists(test.obj_dir + '/Vt_flag_verilate_990_final.tree'): + test.error('Unexpectedly verilated.') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_verilate_threads_bad.pl b/test_regress/t/t_flag_verilate_threads_bad.pl deleted file mode 100755 index 8743294da..000000000 --- a/test_regress/t/t_flag_verilate_threads_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - verilator_flags => [qw(--verilate-jobs -1)], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_verilate_threads_bad.py b/test_regress/t/t_flag_verilate_threads_bad.py new file mode 100755 index 000000000..26f50c37b --- /dev/null +++ b/test_regress/t/t_flag_verilate_threads_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, verilator_flags=["--verilate-jobs -1"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_version.pl b/test_regress/t/t_flag_version.pl deleted file mode 100755 index 5e7c46a06..000000000 --- a/test_regress/t/t_flag_version.pl +++ /dev/null @@ -1,49 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -foreach my $prog ( - # See also t_flag_help.pl - "$ENV{VERILATOR_ROOT}/bin/verilator", - "$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - #"$ENV{VERILATOR_ROOT}/bin/verilator_difftree", - #"$ENV{VERILATOR_ROOT}/bin/verilator_gantt", - #"$ENV{VERILATOR_ROOT}/bin/verilator_profcfunc", - ) { - run(fails => 0, - cmd => ["perl", $prog, - "--version"], - tee => $self->{verbose}, - logfile => "$Self->{obj_dir}/t_help.log", - expect => qr/^Verilator/, - verilator_run => 1, - ); - - run(fails => 0, - cmd => ["perl", $prog, - "-V"], - tee => $self->{verbose}, - logfile => "$Self->{obj_dir}/t_help.log", - expect => qr/^Verilator/, - verilator_run => 1, - ); - - run(fails => 0, - cmd => ["perl", $prog, - "-V"], - logfile => "$Self->{obj_dir}/t_help.log", - expect => qr/^Verilator/, - verilator_run => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_flag_version.py b/test_regress/t/t_flag_version.py new file mode 100755 index 000000000..05b74a5da --- /dev/null +++ b/test_regress/t/t_flag_version.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +n = 0 + +for prog in [ + # See also t_flag_help.py + os.environ["VERILATOR_ROOT"] + "/bin/verilator", + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + #os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree", + #os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", + #os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc", +]: + n += 1 + log_filename = test.obj_dir + "/vlt_" + str(n) + ".log" + test.run(fails=False, + cmd=["perl", prog, "--version"], + tee=test.verbose, + logfile=log_filename, + verilator_run=True) + test.file_grep(log_filename, r'Verilator') + + n += 1 + log_filename = test.obj_dir + "/vlt_" + str(n) + ".log" + test.run(fails=False, + cmd=["perl", prog, "-V"], + tee=test.verbose, + logfile=log_filename, + verilator_run=True) + test.file_grep(log_filename, r'Verilator') + +test.passes() diff --git a/test_regress/t/t_flag_werror_bad1.pl b/test_regress/t/t_flag_werror_bad1.pl deleted file mode 100755 index c9a9614cc..000000000 --- a/test_regress/t/t_flag_werror_bad1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_werror_bad1.py b/test_regress/t/t_flag_werror_bad1.py new file mode 100755 index 000000000..61de16fab --- /dev/null +++ b/test_regress/t/t_flag_werror_bad1.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_werror_bad2.pl b/test_regress/t/t_flag_werror_bad2.pl deleted file mode 100755 index e3044056a..000000000 --- a/test_regress/t/t_flag_werror_bad2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - verilator_flags => [qw(-cc -Werror-WIDTH)], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_werror_bad2.py b/test_regress/t/t_flag_werror_bad2.py new file mode 100755 index 000000000..c960be889 --- /dev/null +++ b/test_regress/t/t_flag_werror_bad2.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, verilator_flags=["-cc -Werror-WIDTH"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_werror_bad3.pl b/test_regress/t/t_flag_werror_bad3.pl deleted file mode 100755 index d031c654f..000000000 --- a/test_regress/t/t_flag_werror_bad3.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - verilator_flags => [qw(-cc -Werror-NOSUCHERRORASTHIS)], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_werror_bad3.py b/test_regress/t/t_flag_werror_bad3.py new file mode 100755 index 000000000..7d2cd8587 --- /dev/null +++ b/test_regress/t/t_flag_werror_bad3.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, + verilator_flags=["-cc -Werror-NOSUCHERRORASTHIS"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_wfatal.pl b/test_regress/t/t_flag_wfatal.pl deleted file mode 100755 index 1fee4b430..000000000 --- a/test_regress/t/t_flag_wfatal.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_wfatal.v"); - -lint( - verilator_flags2 => ["--lint-only -Wno-fatal"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_wfatal.py b/test_regress/t/t_flag_wfatal.py new file mode 100755 index 000000000..a23be6d7a --- /dev/null +++ b/test_regress/t/t_flag_wfatal.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_wfatal.v" + +test.lint(verilator_flags2=["--lint-only -Wno-fatal"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_woff.pl b/test_regress/t/t_flag_woff.pl deleted file mode 100755 index 17c128753..000000000 --- a/test_regress/t/t_flag_woff.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wno-WIDTH"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_woff.py b/test_regress/t/t_flag_woff.py new file mode 100755 index 000000000..b31c5f049 --- /dev/null +++ b/test_regress/t/t_flag_woff.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wno-WIDTH"]) + +test.passes() diff --git a/test_regress/t/t_flag_woff_bad.pl b/test_regress/t/t_flag_woff_bad.pl deleted file mode 100755 index d1c151c64..000000000 --- a/test_regress/t/t_flag_woff_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wno-NOSUCHERRORASTHIS"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_woff_bad.py b/test_regress/t/t_flag_woff_bad.py new file mode 100755 index 000000000..10a2221a7 --- /dev/null +++ b/test_regress/t/t_flag_woff_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wno-NOSUCHERRORASTHIS"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_wpedantic_bad.out b/test_regress/t/t_flag_wpedantic_bad.out index 707d92b51..f6b196425 100644 --- a/test_regress/t/t_flag_wpedantic_bad.out +++ b/test_regress/t/t_flag_wpedantic_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_flag_wpedantic_bad.v:8:8: syntax error, unexpected global +%Error: t/t_flag_wpedantic_bad.v:8:8: syntax error, unexpected global, expecting IDENTIFIER or do or final or randomize 8 | reg global; | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_flag_wpedantic_bad.pl b/test_regress/t/t_flag_wpedantic_bad.pl deleted file mode 100755 index 9de6b85ee..000000000 --- a/test_regress/t/t_flag_wpedantic_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Wpedantic"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_wpedantic_bad.py b/test_regress/t/t_flag_wpedantic_bad.py new file mode 100755 index 000000000..4cc015636 --- /dev/null +++ b/test_regress/t/t_flag_wpedantic_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Wpedantic"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_wwarn_bad.pl b/test_regress/t/t_flag_wwarn_bad.pl deleted file mode 100755 index 541ce84cf..000000000 --- a/test_regress/t/t_flag_wwarn_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - verilator_flags => [qw(-cc -Wwarn-NOSUCHERRORASTHIS)], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_wwarn_bad.py b/test_regress/t/t_flag_wwarn_bad.py new file mode 100755 index 000000000..ec10e44d4 --- /dev/null +++ b/test_regress/t/t_flag_wwarn_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, + verilator_flags=["-cc -Wwarn-NOSUCHERRORASTHIS"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_x_assign_bad.pl b/test_regress/t/t_flag_x_assign_bad.pl deleted file mode 100755 index af3b0a78c..000000000 --- a/test_regress/t/t_flag_x_assign_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--x-assign bad_one"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_x_assign_bad.py b/test_regress/t/t_flag_x_assign_bad.py new file mode 100755 index 000000000..a800d4eb2 --- /dev/null +++ b/test_regress/t/t_flag_x_assign_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--x-assign bad_one"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_x_initial_bad.pl b/test_regress/t/t_flag_x_initial_bad.pl deleted file mode 100755 index 88423465e..000000000 --- a/test_regress/t/t_flag_x_initial_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--x-initial bad_one"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_x_initial_bad.py b/test_regress/t/t_flag_x_initial_bad.py new file mode 100755 index 000000000..98cc57a39 --- /dev/null +++ b/test_regress/t/t_flag_x_initial_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--x-initial bad_one"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_xinitial_0.pl b/test_regress/t/t_flag_xinitial_0.pl deleted file mode 100755 index 937f65c98..000000000 --- a/test_regress/t/t_flag_xinitial_0.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--x-initial 0"], - ); - -execute( - check_finished => 1, - ); - -file_grep_not("$Self->{obj_dir}/$Self->{vm_prefix}___024root__Slow.cpp", qr/VL_RAND_RESET/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_xinitial_0.py b/test_regress/t/t_flag_xinitial_0.py new file mode 100755 index 000000000..a5c7efa68 --- /dev/null +++ b/test_regress/t/t_flag_xinitial_0.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--x-initial 0"]) + +test.execute() + +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "___024root__Slow.cpp", r'VL_RAND_RESET') + +test.passes() diff --git a/test_regress/t/t_flag_xinitial_unique.pl b/test_regress/t/t_flag_xinitial_unique.pl deleted file mode 100755 index 961fb9756..000000000 --- a/test_regress/t/t_flag_xinitial_unique.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--x-initial unique"], - ); - -execute( - check_finished => 1, - ); - -my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root__DepSet_*__Slow.cpp"); -file_grep_any(\@files, qr/VL_RAND_RESET/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_xinitial_unique.py b/test_regress/t/t_flag_xinitial_unique.py new file mode 100755 index 000000000..64ac07036 --- /dev/null +++ b/test_regress/t/t_flag_xinitial_unique.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--x-initial unique"]) + +test.execute() + +files = glob.glob(test.obj_dir + "/" + test.vm_prefix + "___024root__DepSet_*__Slow.cpp") +test.file_grep_any(files, r'VL_RAND_RESET') + +test.passes() diff --git a/test_regress/t/t_for_assign.pl b/test_regress/t/t_for_assign.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_for_assign.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_assign.py b/test_regress/t/t_for_assign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_for_break.pl b/test_regress/t/t_for_break.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_for_break.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_break.py b/test_regress/t/t_for_break.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_break.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_for_comma.pl b/test_regress/t/t_for_comma.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_for_comma.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_comma.py b/test_regress/t/t_for_comma.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_comma.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_for_count.pl b/test_regress/t/t_for_count.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_for_count.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_count.py b/test_regress/t/t_for_count.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_count.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_for_disable_dot.pl b/test_regress/t/t_for_disable_dot.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_for_disable_dot.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_disable_dot.py b/test_regress/t/t_for_disable_dot.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_for_disable_dot.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_for_funcbound.pl b/test_regress/t/t_for_funcbound.pl deleted file mode 100755 index 06c985de2..000000000 --- a/test_regress/t/t_for_funcbound.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect => -'[10] hello -[20] world -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_funcbound.py b/test_regress/t/t_for_funcbound.py new file mode 100755 index 000000000..f4b1881d1 --- /dev/null +++ b/test_regress/t/t_for_funcbound.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.file_grep(test.run_log_filename, r"\[10\] hello") +test.file_grep(test.run_log_filename, r"\[20\] world") + +test.passes() diff --git a/test_regress/t/t_for_init_bug.pl b/test_regress/t/t_for_init_bug.pl deleted file mode 100755 index 300cb0b09..000000000 --- a/test_regress/t/t_for_init_bug.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -#execute() - -ok(1); -1; diff --git a/test_regress/t/t_for_init_bug.py b/test_regress/t/t_for_init_bug.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_for_init_bug.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_for_local.pl b/test_regress/t/t_for_local.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_for_local.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_local.py b/test_regress/t/t_for_local.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_for_loop.pl b/test_regress/t/t_for_loop.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_for_loop.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_loop.py b/test_regress/t/t_for_loop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_loop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force.pl b/test_regress/t/t_force.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_force.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force.py b/test_regress/t/t_force.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_bad_rw.pl b/test_regress/t/t_force_bad_rw.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_force_bad_rw.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_bad_rw.py b/test_regress/t/t_force_bad_rw.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_force_bad_rw.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_force_mid.pl b/test_regress/t/t_force_mid.pl deleted file mode 100755 index 52a0affb5..000000000 --- a/test_regress/t/t_force_mid.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_force_mid.cpp"] - ); - -execute( - check_finised => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_mid.py b/test_regress/t/t_force_mid.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_force_mid.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_multi.pl b/test_regress/t/t_force_multi.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_force_multi.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_multi.py b/test_regress/t/t_force_multi.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force_multi.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_port_alias.pl b/test_regress/t/t_force_port_alias.pl deleted file mode 100755 index 3b16dd5a3..000000000 --- a/test_regress/t/t_force_port_alias.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_port_alias.py b/test_regress/t/t_force_port_alias.py new file mode 100755 index 000000000..cacc314ab --- /dev/null +++ b/test_regress/t/t_force_port_alias.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_release_net.pl b/test_regress/t/t_force_release_net.pl deleted file mode 100755 index 7b483d32e..000000000 --- a/test_regress/t/t_force_release_net.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_net.py b/test_regress/t/t_force_release_net.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force_release_net.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_release_net_reverse.pl b/test_regress/t/t_force_release_net_reverse.pl deleted file mode 100755 index 709491b91..000000000 --- a/test_regress/t/t_force_release_net_reverse.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_force_release_net.v"); - -compile( - verilator_flags2 => ['+define+REVERSE'] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_net_reverse.py b/test_regress/t/t_force_release_net_reverse.py new file mode 100755 index 000000000..eee5aeb88 --- /dev/null +++ b/test_regress/t/t_force_release_net_reverse.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_force_release_net.v" + +test.compile(verilator_flags2=['+define+REVERSE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_release_net_trace.pl b/test_regress/t/t_force_release_net_trace.pl deleted file mode 100755 index 6a0f17b04..000000000 --- a/test_regress/t/t_force_release_net_trace.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_force_release_net.v"); - -compile( - verilator_flags2 => ['--trace'] - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_net_trace.py b/test_regress/t/t_force_release_net_trace.py new file mode 100755 index 000000000..721b7b0e4 --- /dev/null +++ b/test_regress/t/t_force_release_net_trace.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_force_release_net.v" + +test.compile(verilator_flags2=['--trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_force_release_var.pl b/test_regress/t/t_force_release_var.pl deleted file mode 100755 index 7b483d32e..000000000 --- a/test_regress/t/t_force_release_var.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_var.py b/test_regress/t/t_force_release_var.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force_release_var.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_release_var_reverse.pl b/test_regress/t/t_force_release_var_reverse.pl deleted file mode 100755 index 7b31629df..000000000 --- a/test_regress/t/t_force_release_var_reverse.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_force_release_var.v"); - -compile( - verilator_flags2 => ['+define+REVERSE'] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_var_reverse.py b/test_regress/t/t_force_release_var_reverse.py new file mode 100755 index 000000000..624ccbc3b --- /dev/null +++ b/test_regress/t/t_force_release_var_reverse.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_force_release_var.v" + +test.compile(verilator_flags2=['+define+REVERSE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_release_var_trace.pl b/test_regress/t/t_force_release_var_trace.pl deleted file mode 100755 index 2e7da6c27..000000000 --- a/test_regress/t/t_force_release_var_trace.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_force_release_var.v"); - -compile( - verilator_flags2 => ['--trace'] - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_var_trace.py b/test_regress/t/t_force_release_var_trace.py new file mode 100755 index 000000000..d8f366168 --- /dev/null +++ b/test_regress/t/t_force_release_var_trace.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_force_release_var.v" + +test.compile(verilator_flags2=['--trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_force_subnet.pl b/test_regress/t/t_force_subnet.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_force_subnet.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_subnet.py b/test_regress/t/t_force_subnet.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force_subnet.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_subvar.pl b/test_regress/t/t_force_subvar.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_force_subvar.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_subvar.py b/test_regress/t/t_force_subvar.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force_subvar.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_tri.pl b/test_regress/t/t_force_tri.pl deleted file mode 100755 index c213189c1..000000000 --- a/test_regress/t/t_force_tri.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_tri.py b/test_regress/t/t_force_tri.py new file mode 100755 index 000000000..6038b562c --- /dev/null +++ b/test_regress/t/t_force_tri.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_forceable_net_cmt.pl b/test_regress/t/t_forceable_net_cmt.pl deleted file mode 100755 index ff2553af1..000000000 --- a/test_regress/t/t_forceable_net_cmt.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_net.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '-DCMT=1', - '--exe', - "$Self->{t_dir}/t_forceable_net.cpp" - ], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_net_cmt.py b/test_regress/t/t_forceable_net_cmt.py new file mode 100755 index 000000000..041bb0c49 --- /dev/null +++ b/test_regress/t/t_forceable_net_cmt.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_net.cpp" +test.top_filename = "t/t_forceable_net.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['-DCMT=1', '--exe', test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_forceable_net_cmt_trace.pl b/test_regress/t/t_forceable_net_cmt_trace.pl deleted file mode 100755 index af5581da8..000000000 --- a/test_regress/t/t_forceable_net_cmt_trace.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_net.v"); -golden_filename("t/t_forceable_net_trace.vcd"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '-DCMT=1', - '--exe', - '--trace', - "$Self->{t_dir}/t_forceable_net.cpp" - ], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_net_cmt_trace.py b/test_regress/t/t_forceable_net_cmt_trace.py new file mode 100755 index 000000000..bed940206 --- /dev/null +++ b/test_regress/t/t_forceable_net_cmt_trace.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_net.cpp" +test.top_filename = "t/t_forceable_net.v" +test.golden_filename = "t/t_forceable_net_trace.vcd" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['-DCMT=1', '--exe', '--trace', test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_forceable_net_vlt.pl b/test_regress/t/t_forceable_net_vlt.pl deleted file mode 100755 index 595b70dc8..000000000 --- a/test_regress/t/t_forceable_net_vlt.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_net.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '--exe', - "$Self->{t_dir}/t_forceable_net.cpp", - "$Self->{t_dir}/t_forceable_net.vlt" - ], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_net_vlt.py b/test_regress/t/t_forceable_net_vlt.py new file mode 100755 index 000000000..5d9d78291 --- /dev/null +++ b/test_regress/t/t_forceable_net_vlt.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_net.cpp" +test.top_filename = "t/t_forceable_net.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['--exe', test.pli_filename, test.t_dir + "/t_forceable_net.vlt"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_forceable_net_vlt_trace.pl b/test_regress/t/t_forceable_net_vlt_trace.pl deleted file mode 100755 index eb0d52d78..000000000 --- a/test_regress/t/t_forceable_net_vlt_trace.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_net.v"); -golden_filename("t/t_forceable_net_trace.vcd"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '--exe', - '--trace', - "$Self->{t_dir}/t_forceable_net.cpp", - "$Self->{t_dir}/t_forceable_net.vlt" - ], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_net_vlt_trace.py b/test_regress/t/t_forceable_net_vlt_trace.py new file mode 100755 index 000000000..59b55a74e --- /dev/null +++ b/test_regress/t/t_forceable_net_vlt_trace.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_net.cpp" +test.top_filename = "t/t_forceable_net.v" +test.golden_filename = "t/t_forceable_net_trace.vcd" + +test.compile( + make_top_shell=False, + make_main=False, + verilator_flags2=['--exe', '--trace', test.pli_filename, test.t_dir + "/t_forceable_net.vlt"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_forceable_var_cmt.pl b/test_regress/t/t_forceable_var_cmt.pl deleted file mode 100755 index ba21c8b9b..000000000 --- a/test_regress/t/t_forceable_var_cmt.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_var.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '-DCMT=1', - '--exe', - "$Self->{t_dir}/t_forceable_var.cpp" - ], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_var_cmt.py b/test_regress/t/t_forceable_var_cmt.py new file mode 100755 index 000000000..c79bd38ef --- /dev/null +++ b/test_regress/t/t_forceable_var_cmt.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_var.cpp" +test.top_filename = "t/t_forceable_var.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['-DCMT=1', '--exe', test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_forceable_var_cmt_trace.pl b/test_regress/t/t_forceable_var_cmt_trace.pl deleted file mode 100755 index 51443e81c..000000000 --- a/test_regress/t/t_forceable_var_cmt_trace.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_var.v"); -golden_filename("t/t_forceable_var_trace.vcd"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '-DCMT=1', - '--exe', - '--trace', - "$Self->{t_dir}/t_forceable_var.cpp" - ], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_var_cmt_trace.py b/test_regress/t/t_forceable_var_cmt_trace.py new file mode 100755 index 000000000..a59d2e6c5 --- /dev/null +++ b/test_regress/t/t_forceable_var_cmt_trace.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_var.cpp" +test.top_filename = "t/t_forceable_var.v" +test.golden_filename = "t/t_forceable_var_trace.vcd" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['-DCMT=1', '--exe', '--trace', test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_forceable_var_vlt.pl b/test_regress/t/t_forceable_var_vlt.pl deleted file mode 100755 index c0b9f7b79..000000000 --- a/test_regress/t/t_forceable_var_vlt.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_var.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '--exe', - "$Self->{t_dir}/t_forceable_var.cpp", - "$Self->{t_dir}/t_forceable_var.vlt" - ], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_var_vlt.py b/test_regress/t/t_forceable_var_vlt.py new file mode 100755 index 000000000..83033dff9 --- /dev/null +++ b/test_regress/t/t_forceable_var_vlt.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_var.cpp" +test.top_filename = "t/t_forceable_var.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['--exe', test.pli_filename, test.t_dir + "/t_forceable_var.vlt"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_forceable_var_vlt_trace.pl b/test_regress/t/t_forceable_var_vlt_trace.pl deleted file mode 100755 index 932307bb5..000000000 --- a/test_regress/t/t_forceable_var_vlt_trace.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_var.v"); -golden_filename("t/t_forceable_var_trace.vcd"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '--exe', - '--trace', - "$Self->{t_dir}/t_forceable_var.cpp", - "$Self->{t_dir}/t_forceable_var.vlt" - ], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_var_vlt_trace.py b/test_regress/t/t_forceable_var_vlt_trace.py new file mode 100755 index 000000000..fad62ca60 --- /dev/null +++ b/test_regress/t/t_forceable_var_vlt_trace.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_var.cpp" +test.top_filename = "t/t_forceable_var.v" +test.golden_filename = "t/t_forceable_var_trace.vcd" + +test.compile( + make_top_shell=False, + make_main=False, + verilator_flags2=['--exe', '--trace', test.pli_filename, test.t_dir + "/t_forceable_var.vlt"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_foreach.pl b/test_regress/t/t_foreach.pl deleted file mode 100755 index 6a69d589f..000000000 --- a/test_regress/t/t_foreach.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'] - ); - -execute( - check_finished => 1, - ); - -# We expect all loops should be unrolled by verilator, -# none of the loop variables should exist in the output: -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp")) { - file_grep_not($file, qr/index_/); -} - -# Further, we expect that all logic within the loop should -# have been evaluated inside the compiler. So there should be -# no references to 'sum' in the .cpp. -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp")) { - file_grep_not($file, qr/[^a-zA-Z]sum[^a-zA-Z]/); -} - -ok(1); -1; diff --git a/test_regress/t/t_foreach.py b/test_regress/t/t_foreach.py new file mode 100755 index 000000000..7a4bc150c --- /dev/null +++ b/test_regress/t/t_foreach.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +# We expect all loops should be unrolled by verilator, +# none of the loop variables should exist in the output: +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp"): + test.file_grep_not(filename, r'index_') + +# Further, we expect that all logic within the loop should +# have been evaluated inside the compiler. So there should be +# no references to 'sum' in the .cpp. +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp"): + test.file_grep_not(filename, r'[^a-zA-Z]sum[^a-zA-Z]') + +test.passes() diff --git a/test_regress/t/t_foreach.v b/test_regress/t/t_foreach.v index b700d5bb6..22035e4cd 100644 --- a/test_regress/t/t_foreach.v +++ b/test_regress/t/t_foreach.v @@ -37,7 +37,7 @@ module t (/*AUTOARG*/); initial begin sum = 0; // We use 'index_' as the prefix for all loop vars, - // this allows t_foreach.pl to confirm that all loops + // this allows t_foreach.py to confirm that all loops // have been unrolled and flattened away and no loop vars // remain in the generated .cpp foreach (depth1_array[index_a]) begin diff --git a/test_regress/t/t_foreach_array.py b/test_regress/t/t_foreach_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_foreach_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_foreach_array.v b/test_regress/t/t_foreach_array.v new file mode 100755 index 000000000..7b4a8eca6 --- /dev/null +++ b/test_regress/t/t_foreach_array.v @@ -0,0 +1,94 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by PlanV GmbH. +// SPDX-License-Identifier: CC0-1.0 + +module t_foreach_array; + + int dyn_arr[][]; + int queue[$][$]; + int unpacked_arr [3:1][9:8]; + int associative_array_3d[string][string][string]; + + int count_que; + int exp_count_que; + int count_dyn; + int exp_count_dyn; + int count_unp; + int exp_count_unp; + int count_assoc; + + string k1, k2, k3; + + initial begin + // Initialize + queue = '{'{1, 2, 3}, '{4, 5}, '{6}}; + dyn_arr = '{'{1, 2, 3}, '{4, 5, 6, 0, 10}, '{6, 7, 8, 9}}; + associative_array_3d["key1"]["subkey1"]["subsubkey1"] = 1; + associative_array_3d["key1"]["subkey1"]["subsubkey2"] = 2; + associative_array_3d["key1"]["subkey2"]["subsubkey1"] = 3; + associative_array_3d["key1"]["subkey3"]["subsubkey1"] = 4; + associative_array_3d["key1"]["subkey3"]["subsubkey2"] = 5; + associative_array_3d["key1"]["subkey3"]["subsubkey3"] = 6; + associative_array_3d["key2"]["subkey1"]["subsubkey1"] = 7; + associative_array_3d["key2"]["subkey1"]["subsubkey2"] = 8; + associative_array_3d["key2"]["subkey3"]["subsubkey1"] = 9; + + count_que = 0; + + foreach(queue[i, j]) begin + count_que++; + end + + exp_count_que = 0; + foreach(queue[i]) begin + foreach(queue[i][j]) begin + exp_count_que++; + end + end + + count_dyn = 0; + + foreach(dyn_arr[i, j]) begin + count_dyn++; + end + + exp_count_dyn = 0; + + foreach(dyn_arr[i]) begin + foreach(dyn_arr[i][j]) begin + exp_count_dyn++; + end + end + + count_unp = 0; + + foreach(unpacked_arr[i, j]) begin + count_unp++; + end + + exp_count_unp = 0; + + foreach(unpacked_arr[i]) begin + foreach(unpacked_arr[i][j]) begin + exp_count_unp++; + end + end + + count_assoc = 0; + + foreach(associative_array_3d[k1, k2, k3]) begin + count_assoc++; + end + + if (count_que != 6 || count_que != exp_count_que) $stop; + if (count_dyn != 12 || count_dyn != exp_count_dyn) $stop; + if (count_unp != 6 || count_unp != exp_count_unp) $stop; + if (count_assoc != 9) $stop; + + $write("*-* All Finished *-*\\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_foreach_bad.pl b/test_regress/t/t_foreach_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_foreach_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_bad.py b/test_regress/t/t_foreach_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_foreach_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_foreach_blkname.pl b/test_regress/t/t_foreach_blkname.pl deleted file mode 100755 index 13587bf85..000000000 --- a/test_regress/t/t_foreach_blkname.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_blkname.py b/test_regress/t/t_foreach_blkname.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_foreach_blkname.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_foreach_class.pl b/test_regress/t/t_foreach_class.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_foreach_class.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_class.py b/test_regress/t/t_foreach_class.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_foreach_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_foreach_const.pl b/test_regress/t/t_foreach_const.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_foreach_const.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_const.py b/test_regress/t/t_foreach_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_foreach_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_foreach_const.v b/test_regress/t/t_foreach_const.v index 999ca69e1..08e95917c 100644 --- a/test_regress/t/t_foreach_const.v +++ b/test_regress/t/t_foreach_const.v @@ -34,7 +34,7 @@ module t (/*AUTOARG*/); function [63:0] test1; test1 = 0; // We use 'index_' as the prefix for all loop vars, - // this allows t_foreach.pl to confirm that all loops + // this allows t_foreach.py to confirm that all loops // have been unrolled and flattened away and no loop vars // remain in the generated .cpp foreach (depth1_array[index_a]) begin diff --git a/test_regress/t/t_foreach_iface.pl b/test_regress/t/t_foreach_iface.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_foreach_iface.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_iface.py b/test_regress/t/t_foreach_iface.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_foreach_iface.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_foreach_nindex_bad.pl b/test_regress/t/t_foreach_nindex_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_foreach_nindex_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_nindex_bad.py b/test_regress/t/t_foreach_nindex_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_foreach_nindex_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_foreach_type_bad.pl b/test_regress/t/t_foreach_type_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_foreach_type_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_type_bad.py b/test_regress/t/t_foreach_type_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_foreach_type_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fork.pl b/test_regress/t/t_fork.pl deleted file mode 100755 index 9459580d1..000000000 --- a/test_regress/t/t_fork.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ['--no-timing'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork.py b/test_regress/t/t_fork.py new file mode 100755 index 000000000..bb6e45319 --- /dev/null +++ b/test_regress/t/t_fork.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--no-timing'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fork_bbox.pl b/test_regress/t/t_fork_bbox.pl deleted file mode 100755 index 72f18add1..000000000 --- a/test_regress/t/t_fork_bbox.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ['--lint-only --no-timing --bbox-unsup'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_bbox.py b/test_regress/t/t_fork_bbox.py new file mode 100755 index 000000000..7a642a939 --- /dev/null +++ b/test_regress/t/t_fork_bbox.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--lint-only --no-timing --bbox-unsup']) + +test.passes() diff --git a/test_regress/t/t_fork_block_item_declaration.pl b/test_regress/t/t_fork_block_item_declaration.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_fork_block_item_declaration.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_block_item_declaration.py b/test_regress/t/t_fork_block_item_declaration.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_block_item_declaration.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_dynscope.pl b/test_regress/t/t_fork_dynscope.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_fork_dynscope.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_dynscope.py b/test_regress/t/t_fork_dynscope.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_dynscope.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_dynscope_out.pl b/test_regress/t/t_fork_dynscope_out.pl deleted file mode 100755 index 320872684..000000000 --- a/test_regress/t/t_fork_dynscope_out.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary -Wno-INITIALDLY"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_dynscope_out.py b/test_regress/t/t_fork_dynscope_out.py new file mode 100755 index 000000000..e555ab909 --- /dev/null +++ b/test_regress/t/t_fork_dynscope_out.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary -Wno-INITIALDLY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_dynscope_unsup.pl b/test_regress/t/t_fork_dynscope_unsup.pl deleted file mode 100755 index 4bc2cbf36..000000000 --- a/test_regress/t/t_fork_dynscope_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_dynscope_unsup.py b/test_regress/t/t_fork_dynscope_unsup.py new file mode 100755 index 000000000..27ba50a31 --- /dev/null +++ b/test_regress/t/t_fork_dynscope_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fork_func2_bad.pl b/test_regress/t/t_fork_func2_bad.pl deleted file mode 100755 index 89ffd046b..000000000 --- a/test_regress/t/t_fork_func2_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--lint-only'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_func2_bad.py b/test_regress/t/t_fork_func2_bad.py new file mode 100755 index 000000000..d6dde1012 --- /dev/null +++ b/test_regress/t/t_fork_func2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fork_func_bad.pl b/test_regress/t/t_fork_func_bad.pl deleted file mode 100755 index 89ffd046b..000000000 --- a/test_regress/t/t_fork_func_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--lint-only'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_func_bad.py b/test_regress/t/t_fork_func_bad.py new file mode 100755 index 000000000..d6dde1012 --- /dev/null +++ b/test_regress/t/t_fork_func_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fork_initial.pl b/test_regress/t/t_fork_initial.pl deleted file mode 100755 index 7751e4fe8..000000000 --- a/test_regress/t/t_fork_initial.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - # issue #4471 - remove this - verilator_make_gmake => 0, - ); - -# issue #4471 - add this -#execute( -# check_finished => 1, -# ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_initial.py b/test_regress/t/t_fork_initial.py new file mode 100755 index 000000000..8dbd20354 --- /dev/null +++ b/test_regress/t/t_fork_initial.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + verilator_flags2=["--exe --main --timing"], + # issue #4471 - remove this + verilator_make_gmake=False) + +# issue #4471 - add this +#test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_join_none_any_nested.pl b/test_regress/t/t_fork_join_none_any_nested.pl deleted file mode 100755 index fec4c2942..000000000 --- a/test_regress/t/t_fork_join_none_any_nested.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_join_none_any_nested.py b/test_regress/t/t_fork_join_none_any_nested.py new file mode 100755 index 000000000..7bd93561b --- /dev/null +++ b/test_regress/t/t_fork_join_none_any_nested.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_join_none_class_cap.pl b/test_regress/t/t_fork_join_none_class_cap.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_fork_join_none_class_cap.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_join_none_class_cap.py b/test_regress/t/t_fork_join_none_class_cap.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_join_none_class_cap.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_join_none_virtual.pl b/test_regress/t/t_fork_join_none_virtual.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_fork_join_none_virtual.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_join_none_virtual.py b/test_regress/t/t_fork_join_none_virtual.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_join_none_virtual.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_jumpblock.pl b/test_regress/t/t_fork_jumpblock.pl deleted file mode 100755 index a1cdcff37..000000000 --- a/test_regress/t/t_fork_jumpblock.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_jumpblock.py b/test_regress/t/t_fork_jumpblock.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_jumpblock.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_label.pl b/test_regress/t/t_fork_label.pl deleted file mode 100755 index dc3cfd898..000000000 --- a/test_regress/t/t_fork_label.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --no-timing'], - ); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_fork_label.py b/test_regress/t/t_fork_label.py new file mode 100755 index 000000000..46560bc9c --- /dev/null +++ b/test_regress/t/t_fork_label.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --no-timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_label_timing.pl b/test_regress/t/t_fork_label_timing.pl deleted file mode 100755 index da97b37e2..000000000 --- a/test_regress/t/t_fork_label_timing.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_fork_label.v"); - -compile( - verilator_flags2 => ["--exe --main --timing"], - make_main => 0, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_label_timing.py b/test_regress/t/t_fork_label_timing.py new file mode 100755 index 000000000..21739800c --- /dev/null +++ b/test_regress/t/t_fork_label_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_fork_label.v" + +test.compile(verilator_flags2=["--exe --main --timing"], make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_none_var.pl b/test_regress/t/t_fork_none_var.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_fork_none_var.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_none_var.py b/test_regress/t/t_fork_none_var.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_none_var.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_output_arg.pl b/test_regress/t/t_fork_output_arg.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_fork_output_arg.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_output_arg.py b/test_regress/t/t_fork_output_arg.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_output_arg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_port.pl b/test_regress/t/t_fork_port.pl deleted file mode 100755 index 3a7d44569..000000000 --- a/test_regress/t/t_fork_port.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_port.py b/test_regress/t/t_fork_port.py new file mode 100755 index 000000000..664ad3bec --- /dev/null +++ b/test_regress/t/t_fork_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_repeat.py b/test_regress/t/t_fork_repeat.py new file mode 100755 index 000000000..c53b55262 --- /dev/null +++ b/test_regress/t/t_fork_repeat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_repeat.v b/test_regress/t/t_fork_repeat.v new file mode 100644 index 000000000..388584070 --- /dev/null +++ b/test_regress/t/t_fork_repeat.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/); + bit clk; + + // Gen Clock + always #10 + clk = ~clk; + + initial begin + fork + begin + forever + @(posedge clk); + end + begin + repeat(10) + @(posedge clk); + end + begin + for(int i=0; i < 6; ++i) + @(posedge clk); + end + join_any + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_fork_timing.pl b/test_regress/t/t_fork_timing.pl deleted file mode 100755 index b62f5837f..000000000 --- a/test_regress/t/t_fork_timing.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_fork.v"); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_timing.py b/test_regress/t/t_fork_timing.py new file mode 100755 index 000000000..b8512ba82 --- /dev/null +++ b/test_regress/t/t_fork_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_fork.v" + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_format_wide_decimal.pl b/test_regress/t/t_format_wide_decimal.pl deleted file mode 100755 index b949e06e1..000000000 --- a/test_regress/t/t_format_wide_decimal.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wall"] - ); - - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_format_wide_decimal.py b/test_regress/t/t_format_wide_decimal.py new file mode 100755 index 000000000..957f7bb4c --- /dev/null +++ b/test_regress/t/t_format_wide_decimal.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wall"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func.pl b/test_regress/t/t_func.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func.py b/test_regress/t/t_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_arg_complex.pl b/test_regress/t/t_func_arg_complex.pl deleted file mode 100755 index 433693b72..000000000 --- a/test_regress/t/t_func_arg_complex.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["-Wno-PKGNODECL -Wno-UNPACKED -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT", - "--error-limit 200"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_arg_complex.py b/test_regress/t/t_func_arg_complex.py new file mode 100755 index 000000000..b9135448f --- /dev/null +++ b/test_regress/t/t_func_arg_complex.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=[ + "-Wno-PKGNODECL -Wno-UNPACKED -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT", + "--error-limit 200" +]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_bad.pl b/test_regress/t/t_func_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_func_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_bad.py b/test_regress/t/t_func_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_bad_width.pl b/test_regress/t/t_func_bad_width.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_func_bad_width.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_bad_width.py b/test_regress/t/t_func_bad_width.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_func_bad_width.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_begin2.pl b/test_regress/t/t_func_begin2.pl deleted file mode 100755 index 0f2fb4862..000000000 --- a/test_regress/t/t_func_begin2.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --inline-mult 1"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_begin2.py b/test_regress/t/t_func_begin2.py new file mode 100755 index 000000000..713453910 --- /dev/null +++ b/test_regress/t/t_func_begin2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --inline-mult 1"]) + +test.passes() diff --git a/test_regress/t/t_func_call_order.pl b/test_regress/t/t_func_call_order.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_func_call_order.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_call_order.py b/test_regress/t/t_func_call_order.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_call_order.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_check.pl b/test_regress/t/t_func_check.pl deleted file mode 100755 index db885e46d..000000000 --- a/test_regress/t/t_func_check.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{verilated_randReset} = 1; - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_check.py b/test_regress/t/t_func_check.py new file mode 100755 index 000000000..629441927 --- /dev/null +++ b/test_regress/t/t_func_check.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.verilated_randReset = 1 + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_complex.pl b/test_regress/t/t_func_complex.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_complex.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_complex.py b/test_regress/t/t_func_complex.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_complex.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_complex_noinl.pl b/test_regress/t/t_func_complex_noinl.pl deleted file mode 100755 index e7a493593..000000000 --- a/test_regress/t/t_func_complex_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_func_complex.v"); - -scenarios(simulator => 1); - -compile( - v_flags2 => ["+define+TEST_NOINLINE"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_complex_noinl.py b/test_regress/t/t_func_complex_noinl.py new file mode 100755 index 000000000..b5ec76840 --- /dev/null +++ b/test_regress/t/t_func_complex_noinl.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +test.top_filename = "t/t_func_complex.v" + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["+define+TEST_NOINLINE"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_cond.pl b/test_regress/t/t_func_cond.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_func_cond.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_cond.py b/test_regress/t/t_func_cond.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_cond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_const.pl b/test_regress/t/t_func_const.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_const.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const.py b/test_regress/t/t_func_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_const2_bad.pl b/test_regress/t/t_func_const2_bad.pl deleted file mode 100755 index 0fd907991..000000000 --- a/test_regress/t/t_func_const2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const2_bad.py b/test_regress/t/t_func_const2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const2_bad.v b/test_regress/t/t_func_const2_bad.v index c90343878..f4515b317 100644 --- a/test_regress/t/t_func_const2_bad.v +++ b/test_regress/t/t_func_const2_bad.v @@ -29,7 +29,7 @@ module b8 c9 #(.A (A), .B (8)) - c9; + c9(); endmodule @@ -39,9 +39,9 @@ module t; localparam P14 = f_add2(2, 3, f_add(4, 5)); //localparam P24 = f_add2(7, 8, 9); - b8 b8; - b8 #(.A (6)) b8_a6; - b8 #(.A (7)) b8_a7; + b8 b8(); + b8 #(.A (6)) b8_a6(); + b8 #(.A (7)) b8_a7(); initial begin // Should never get here diff --git a/test_regress/t/t_func_const3_bad.pl b/test_regress/t/t_func_const3_bad.pl deleted file mode 100755 index 5ece32e17..000000000 --- a/test_regress/t/t_func_const3_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const3_bad.py b/test_regress/t/t_func_const3_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_func_const3_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const3_bad.v b/test_regress/t/t_func_const3_bad.v index 9d6d7fe32..9d45b03a9 100644 --- a/test_regress/t/t_func_const3_bad.v +++ b/test_regress/t/t_func_const3_bad.v @@ -19,15 +19,15 @@ module b9 c9 #(.A (A), .B (9)) - c9; + c9(); endmodule module t; - b9 b9; - b9 #(.A (100)) b900; - b9 #(.A (1000)) b9k; + b9 b9(); + b9 #(.A (100)) b900(); + b9 #(.A (1000)) b9k(); initial begin // Should never get here diff --git a/test_regress/t/t_func_const_bad.pl b/test_regress/t/t_func_const_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_func_const_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const_bad.py b/test_regress/t/t_func_const_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const_packed_array_bad.pl b/test_regress/t/t_func_const_packed_array_bad.pl deleted file mode 100755 index 0fd907991..000000000 --- a/test_regress/t/t_func_const_packed_array_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const_packed_array_bad.py b/test_regress/t/t_func_const_packed_array_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const_packed_array_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const_packed_struct_bad.pl b/test_regress/t/t_func_const_packed_struct_bad.pl deleted file mode 100755 index 0fd907991..000000000 --- a/test_regress/t/t_func_const_packed_struct_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const_packed_struct_bad.py b/test_regress/t/t_func_const_packed_struct_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const_packed_struct_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const_packed_struct_bad2.pl b/test_regress/t/t_func_const_packed_struct_bad2.pl deleted file mode 100755 index 0fd907991..000000000 --- a/test_regress/t/t_func_const_packed_struct_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const_packed_struct_bad2.py b/test_regress/t/t_func_const_packed_struct_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const_packed_struct_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const_struct_bad.pl b/test_regress/t/t_func_const_struct_bad.pl deleted file mode 100755 index 0fd907991..000000000 --- a/test_regress/t/t_func_const_struct_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const_struct_bad.py b/test_regress/t/t_func_const_struct_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const_struct_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_crc.pl b/test_regress/t/t_func_crc.pl deleted file mode 100755 index 6549284aa..000000000 --- a/test_regress/t/t_func_crc.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc", "--stats"], # We have deep expressions we want to test - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 3888); -} - -ok(1); -1; diff --git a/test_regress/t/t_func_crc.py b/test_regress/t/t_func_crc.py new file mode 100755 index 000000000..0304e7ed5 --- /dev/null +++ b/test_regress/t/t_func_crc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test + verilator_flags2=["--compiler msvc", "--stats"]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 3888) + +test.passes() diff --git a/test_regress/t/t_func_default_warn.pl b/test_regress/t/t_func_default_warn.pl deleted file mode 100755 index e355c477c..000000000 --- a/test_regress/t/t_func_default_warn.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-WIDTH"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_default_warn.py b/test_regress/t/t_func_default_warn.py new file mode 100755 index 000000000..78d425f95 --- /dev/null +++ b/test_regress/t/t_func_default_warn.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-WIDTH"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_defaults.pl b/test_regress/t/t_func_defaults.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_defaults.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_defaults.py b/test_regress/t/t_func_defaults.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_defaults.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted.v b/test_regress/t/t_func_dotted.v index e858b2ef8..17653192b 100644 --- a/test_regress/t/t_func_dotted.v +++ b/test_regress/t/t_func_dotted.v @@ -156,4 +156,4 @@ module b; endmodule : b -bind ma b u_b[0:1]; +bind ma b u_b[0:1](); diff --git a/test_regress/t/t_func_dotted_inl0.pl b/test_regress/t/t_func_dotted_inl0.pl deleted file mode 100755 index 488f844c4..000000000 --- a/test_regress/t/t_func_dotted_inl0.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ['--no-json-edit-nums', '+define+ATTRIBUTES', '+define+NOUSE_INLINE',], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"MODULE","name":"ma",.*"loc":"e,84:[^"]*","origName":"ma",.*,"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mb",.*"loc":"e,99:[^"]*","origName":"mb",.*"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mc","addr":"[^"]*","loc":"e,127:[^"]*","origName":"mc",.*"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mc__PB1","addr":"[^"]*","loc":"e,127:[^"]*","origName":"mc",.*"modPublic":true/); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl0.py b/test_regress/t/t_func_dotted_inl0.py new file mode 100755 index 000000000..ac6c72de4 --- /dev/null +++ b/test_regress/t/t_func_dotted_inl0.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=['--no-json-edit-nums', '+define+ATTRIBUTES', '+define+NOUSE_INLINE']) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"ma",.*"loc":"e,84:[^"]*","origName":"ma",.*,"modPublic":true') + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mb",.*"loc":"e,99:[^"]*","origName":"mb",.*"modPublic":true') + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mc","addr":"[^"]*","loc":"e,127:[^"]*","origName":"mc",.*"modPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mc__PB1","addr":"[^"]*","loc":"e,127:[^"]*","origName":"mc",.*"modPublic":true' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted_inl0_vlt.pl b/test_regress/t/t_func_dotted_inl0_vlt.pl deleted file mode 100755 index 8818d3996..000000000 --- a/test_regress/t/t_func_dotted_inl0_vlt.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "$Self->{t_dir}/t_func_dotted_inl0.vlt"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"MODULE","name":"ma",.*"loc":"f,84:[^"]*",.*"origName":"ma",.*"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mb",.*"loc":"f,99:[^"]*",.*"origName":"mb",.*"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mc",.*"loc":"f,127:[^"]*",.*"origName":"mc",.*"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mc__PB1",.*"loc":"f,127:[^"]*",.*"origName":"mc",.*"modPublic":true/); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl0_vlt.py b/test_regress/t/t_func_dotted_inl0_vlt.py new file mode 100755 index 000000000..dd12a7af4 --- /dev/null +++ b/test_regress/t/t_func_dotted_inl0_vlt.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", test.t_dir + "/t_func_dotted_inl0.vlt"]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"ma",.*"loc":"f,84:[^"]*",.*"origName":"ma",.*"modPublic":true') + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mb",.*"loc":"f,99:[^"]*",.*"origName":"mb",.*"modPublic":true') + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mc",.*"loc":"f,127:[^"]*",.*"origName":"mc",.*"modPublic":true') + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mc__PB1",.*"loc":"f,127:[^"]*",.*"origName":"mc",.*"modPublic":true' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted_inl1.pl b/test_regress/t/t_func_dotted_inl1.pl deleted file mode 100755 index ca0ff2614..000000000 --- a/test_regress/t/t_func_dotted_inl1.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", '+define+ATTRIBUTES', '+define+USE_INLINE',], - ); - -if ($Self->{vlt_all}) { - file_grep_not("$out_filename", qr/"ma0"/i); - file_grep_not("$out_filename", qr/"mb0"/i); - file_grep_not("$out_filename", qr/"mc0"/i); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl1.py b/test_regress/t/t_func_dotted_inl1.py new file mode 100755 index 000000000..a60a34cb4 --- /dev/null +++ b/test_regress/t/t_func_dotted_inl1.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", '+define+ATTRIBUTES', '+define+USE_INLINE']) + +if test.vlt_all: + test.file_grep_not(out_filename, r'"ma0"') + test.file_grep_not(out_filename, r'"mb0"') + test.file_grep_not(out_filename, r'"mc0"') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted_inl1_vlt.pl b/test_regress/t/t_func_dotted_inl1_vlt.pl deleted file mode 100755 index 794527a9d..000000000 --- a/test_regress/t/t_func_dotted_inl1_vlt.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "t/t_func_dotted_inl1.vlt",], - ); - -if ($Self->{vlt_all}) { - file_grep_not("$out_filename", qr/"ma0"/i); - file_grep_not("$out_filename", qr/"mb0"/i); - file_grep_not("$out_filename", qr/"mc0"/i); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl1_vlt.py b/test_regress/t/t_func_dotted_inl1_vlt.py new file mode 100755 index 000000000..bd48a7f96 --- /dev/null +++ b/test_regress/t/t_func_dotted_inl1_vlt.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", "t/t_func_dotted_inl1.vlt"]) + +if test.vlt_all: + test.file_grep_not(out_filename, r'"ma0"') + test.file_grep_not(out_filename, r'"mb0"') + test.file_grep_not(out_filename, r'"mc0"') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted_inl2.pl b/test_regress/t/t_func_dotted_inl2.pl deleted file mode 100755 index f68e21290..000000000 --- a/test_regress/t/t_func_dotted_inl2.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", '+define+ATTRIBUTES', '+define+USE_INLINE_MID',], - ); - -if ($Self->{vlt_all}) { - my $modp = (file_grep("$out_filename", qr/{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"e,99:[^"]*",.*"origName":"mb"/))[0]; - file_grep("$out_filename", qr/{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"e,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"/, $modp); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl2.py b/test_regress/t/t_func_dotted_inl2.py new file mode 100755 index 000000000..1ab47172d --- /dev/null +++ b/test_regress/t/t_func_dotted_inl2.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", '+define+ATTRIBUTES', '+define+USE_INLINE_MID']) + +if test.vlt_all: + modps = test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"e,99:[^"]*",.*"origName":"mb"') + modp = modps[0][0] + test.file_grep( + out_filename, + r'{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"e,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"', + modp) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted_inl2_vlt.pl b/test_regress/t/t_func_dotted_inl2_vlt.pl deleted file mode 100755 index 10d0a48cd..000000000 --- a/test_regress/t/t_func_dotted_inl2_vlt.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "t/t_func_dotted_inl2.vlt",], - ); - -if ($Self->{vlt_all}) { - my $modp = (file_grep("$out_filename", qr/{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"f,99:[^"]*",.*"origName":"mb"/))[0]; - file_grep("$out_filename", qr/{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"f,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"/, $modp); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl2_vlt.py b/test_regress/t/t_func_dotted_inl2_vlt.py new file mode 100755 index 000000000..76860999e --- /dev/null +++ b/test_regress/t/t_func_dotted_inl2_vlt.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", "t/t_func_dotted_inl2.vlt"]) + +if test.vlt_all: + modps = test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"f,99:[^"]*",.*"origName":"mb"') + modp = modps[0][0] + test.file_grep( + out_filename, + r'{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"f,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"', + modp) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_endian.pl b/test_regress/t/t_func_endian.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_endian.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_endian.py b/test_regress/t/t_func_endian.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_endian.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_first.pl b/test_regress/t/t_func_first.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_first.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_first.py b/test_regress/t/t_func_first.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_flip.pl b/test_regress/t/t_func_flip.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_flip.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_flip.py b/test_regress/t/t_func_flip.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_flip.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_gen.pl b/test_regress/t/t_func_gen.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_gen.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_gen.py b/test_regress/t/t_func_gen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_gen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_graphcirc.pl b/test_regress/t/t_func_graphcirc.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_graphcirc.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_graphcirc.py b/test_regress/t/t_func_graphcirc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_graphcirc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_grey.pl b/test_regress/t/t_func_grey.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_grey.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_grey.py b/test_regress/t/t_func_grey.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_grey.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_impure_bad.pl b/test_regress/t/t_func_impure_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_func_impure_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_impure_bad.py b/test_regress/t/t_func_impure_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_func_impure_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_inconly.pl b/test_regress/t/t_func_inconly.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_func_inconly.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_inconly.py b/test_regress/t/t_func_inconly.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_inconly.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_inout_bit_sel.pl b/test_regress/t/t_func_inout_bit_sel.pl deleted file mode 100755 index beaa2ca59..000000000 --- a/test_regress/t/t_func_inout_bit_sel.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_inout_bit_sel.py b/test_regress/t/t_func_inout_bit_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_inout_bit_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_io_order.pl b/test_regress/t/t_func_io_order.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_func_io_order.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_io_order.py b/test_regress/t/t_func_io_order.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_io_order.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_io_order.v b/test_regress/t/t_func_io_order.v index 97c5d514d..c7b90d5c5 100644 --- a/test_regress/t/t_func_io_order.v +++ b/test_regress/t/t_func_io_order.v @@ -31,7 +31,7 @@ module t(/*AUTOARG*/ // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; diff --git a/test_regress/t/t_func_lib.pl b/test_regress/t/t_func_lib.pl deleted file mode 100755 index 3f293390f..000000000 --- a/test_regress/t/t_func_lib.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['-v', 't/t_func_lib_sub.v'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_lib.py b/test_regress/t/t_func_lib.py new file mode 100755 index 000000000..1b870040f --- /dev/null +++ b/test_regress/t/t_func_lib.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['-v', 't/t_func_lib_sub.v']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_lib_sub.pl b/test_regress/t/t_func_lib_sub.pl deleted file mode 100755 index 8651e4fd4..000000000 --- a/test_regress/t/t_func_lib_sub.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ['--no-timing'], - ); -# No execute -ok(1); -1; diff --git a/test_regress/t/t_func_lib_sub.py b/test_regress/t/t_func_lib_sub.py new file mode 100755 index 000000000..de97f6118 --- /dev/null +++ b/test_regress/t/t_func_lib_sub.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=['--no-timing']) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_func_lib_sub_timing.pl b/test_regress/t/t_func_lib_sub_timing.pl deleted file mode 100755 index 6101d0fa0..000000000 --- a/test_regress/t/t_func_lib_sub_timing.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); # UNOPTTHREADS in vltmt - -top_filename("t/t_func_lib_sub.v"); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -# No execute -ok(1); -1; diff --git a/test_regress/t/t_func_lib_sub_timing.py b/test_regress/t/t_func_lib_sub_timing.py new file mode 100755 index 000000000..b882e9cc6 --- /dev/null +++ b/test_regress/t/t_func_lib_sub_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') # UNOPTTHREADS in vltmt +test.top_filename = "t/t_func_lib_sub.v" + +test.compile(verilator_flags2=["--binary --timing"]) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_func_link.pl b/test_regress/t/t_func_link.pl deleted file mode 100755 index a65ad0e19..000000000 --- a/test_regress/t/t_func_link.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_link.py b/test_regress/t/t_func_link.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_link.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_many_return.pl b/test_regress/t/t_func_many_return.pl deleted file mode 100755 index b51fe33a6..000000000 --- a/test_regress/t/t_func_many_return.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--comp-limit-blocks 100"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_many_return.py b/test_regress/t/t_func_many_return.py new file mode 100755 index 000000000..5b582e767 --- /dev/null +++ b/test_regress/t/t_func_many_return.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--comp-limit-blocks 100"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_mlog2.pl b/test_regress/t/t_func_mlog2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_mlog2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_mlog2.py b/test_regress/t/t_func_mlog2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_mlog2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_modify_input.pl b/test_regress/t/t_func_modify_input.pl deleted file mode 100755 index 32bdf873d..000000000 --- a/test_regress/t/t_func_modify_input.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_func_modify_input.py b/test_regress/t/t_func_modify_input.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_func_modify_input.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_func_named.pl b/test_regress/t/t_func_named.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_named.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_named.py b/test_regress/t/t_func_named.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_named.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_no_lifetime_bad.out b/test_regress/t/t_func_no_lifetime_bad.out index bc145b029..b4e8bb538 100644 --- a/test_regress/t/t_func_no_lifetime_bad.out +++ b/test_regress/t/t_func_no_lifetime_bad.out @@ -1,19 +1,19 @@ -%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:29:17: Function/task's lifetime implicitly set to static +%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:26:17: Function/task's lifetime implicitly set to static : ... Suggest use 'function automatic' or 'function static' - 29 | function int f_implicit_static(); + 26 | function int f_implicit_static(); | ^~~~~~~~~~~~~~~~~ - t/t_func_no_lifetime_bad.v:30:11: ... Location of implicit static variable - 30 | int cnt = 0; + t/t_func_no_lifetime_bad.v:27:11: ... Location of implicit static variable + 27 | int cnt = 0; | ^~~ ... Suggest use 'function automatic' or 'function static' ... For warning description see https://verilator.org/warn/IMPLICITSTATIC?v=latest ... Use "/* verilator lint_off IMPLICITSTATIC */" and lint_on around source to disable this message. -%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:34:9: Function/task's lifetime implicitly set to static +%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:31:9: Function/task's lifetime implicitly set to static : ... Suggest use 'function automatic' or 'function static' - 34 | task t_implicit_static(); + 31 | task t_implicit_static(); | ^~~~~~~~~~~~~~~~~ - t/t_func_no_lifetime_bad.v:35:11: ... Location of implicit static variable - 35 | int cnt = 0; + t/t_func_no_lifetime_bad.v:32:11: ... Location of implicit static variable + 32 | int cnt = 0; | ^~~ ... Suggest use 'function automatic' or 'function static' %Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:9:8: Variable's lifetime implicitly set to static diff --git a/test_regress/t/t_func_no_lifetime_bad.pl b/test_regress/t/t_func_no_lifetime_bad.pl deleted file mode 100755 index bd07fc421..000000000 --- a/test_regress/t/t_func_no_lifetime_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_func_no_lifetime_bad.py b/test_regress/t/t_func_no_lifetime_bad.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_func_no_lifetime_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_func_no_lifetime_bad.v b/test_regress/t/t_func_no_lifetime_bad.v index 1c2fe0c2d..160d40c02 100644 --- a/test_regress/t/t_func_no_lifetime_bad.v +++ b/test_regress/t/t_func_no_lifetime_bad.v @@ -21,10 +21,7 @@ task t_dunit_static_ok(input int in_ok = 1); $display("%d", ++cnt_ok); endtask -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t (/*AUTOARG*/); function int f_implicit_static(); int cnt = 0; @@ -42,8 +39,6 @@ module t (/*AUTOARG*/ return ++cnt; endfunction - input clk; - int a, b; initial begin a = f_dunit_static(); diff --git a/test_regress/t/t_func_no_parentheses_bad.out b/test_regress/t/t_func_no_parentheses_bad.out index e5c42c647..c1c6cd176 100644 --- a/test_regress/t/t_func_no_parentheses_bad.out +++ b/test_regress/t/t_func_no_parentheses_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_func_no_parentheses_bad.v:21:11: Found definition of 'func' as a FUNC but expected a variable - 21 | a = func; +%Error: t/t_func_no_parentheses_bad.v:16:11: Found definition of 'func' as a FUNC but expected a variable + 16 | a = func; | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_no_parentheses_bad.pl b/test_regress/t/t_func_no_parentheses_bad.pl deleted file mode 100755 index bd07fc421..000000000 --- a/test_regress/t/t_func_no_parentheses_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_func_no_parentheses_bad.py b/test_regress/t/t_func_no_parentheses_bad.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_func_no_parentheses_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_func_no_parentheses_bad.v b/test_regress/t/t_func_no_parentheses_bad.v index a23810fdf..f8587c71c 100644 --- a/test_regress/t/t_func_no_parentheses_bad.v +++ b/test_regress/t/t_func_no_parentheses_bad.v @@ -9,12 +9,7 @@ function static int func(); return ++cnt; endfunction -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); int a; initial begin diff --git a/test_regress/t/t_func_noinl.pl b/test_regress/t/t_func_noinl.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_noinl.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_noinl.py b/test_regress/t/t_func_noinl.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_noinl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_numones.pl b/test_regress/t/t_func_numones.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_numones.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_numones.py b/test_regress/t/t_func_numones.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_numones.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_outfirst.pl b/test_regress/t/t_func_outfirst.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_outfirst.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_outfirst.py b/test_regress/t/t_func_outfirst.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_outfirst.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_outp.pl b/test_regress/t/t_func_outp.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_outp.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_outp.py b/test_regress/t/t_func_outp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_outp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_paramed.pl b/test_regress/t/t_func_paramed.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_paramed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_paramed.py b/test_regress/t/t_func_paramed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_paramed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_plog.pl b/test_regress/t/t_func_plog.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_plog.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_plog.py b/test_regress/t/t_func_plog.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_plog.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_public.pl b/test_regress/t/t_func_public.pl deleted file mode 100755 index cb925f76f..000000000 --- a/test_regress/t/t_func_public.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['+define+VERILATOR_PUBLIC_TASKS'], - fails => $fail, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_public.py b/test_regress/t/t_func_public.py new file mode 100755 index 000000000..8c9c746dc --- /dev/null +++ b/test_regress/t/t_func_public.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['+define+VERILATOR_PUBLIC_TASKS']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_public_trace.pl b/test_regress/t/t_func_public_trace.pl deleted file mode 100755 index a8afb6674..000000000 --- a/test_regress/t/t_func_public_trace.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_public.v"); - -compile( - verilator_flags2 => ["--trace"], - fails => $fail, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_public_trace.py b/test_regress/t/t_func_public_trace.py new file mode 100755 index 000000000..296e9f1cf --- /dev/null +++ b/test_regress/t/t_func_public_trace.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_public.v" + +test.compile(verilator_flags2=["--trace"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_rand.pl b/test_regress/t/t_func_rand.pl deleted file mode 100755 index 32375a0ef..000000000 --- a/test_regress/t/t_func_rand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp", "--no-timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_rand.py b/test_regress/t/t_func_rand.py new file mode 100755 index 000000000..7b94250d8 --- /dev/null +++ b/test_regress/t/t_func_rand.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "--no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_range.pl b/test_regress/t/t_func_range.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_range.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_range.py b/test_regress/t/t_func_range.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_range.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_real_abs.pl b/test_regress/t/t_func_real_abs.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_real_abs.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_real_abs.py b/test_regress/t/t_func_real_abs.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_real_abs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_real_exprstmt.pl b/test_regress/t/t_func_real_exprstmt.pl deleted file mode 100755 index e8d0aa63b..000000000 --- a/test_regress/t/t_func_real_exprstmt.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - # Check no EXPRSTMTs in final output - should get optimized away - file_grep_not($Self->{stats}, qr/Node count, EXPRSTMT/i); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_real_exprstmt.py b/test_regress/t/t_func_real_exprstmt.py new file mode 100755 index 000000000..f8d9a4ad0 --- /dev/null +++ b/test_regress/t/t_func_real_exprstmt.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + # Check no EXPRSTMTs in final output - should get optimized away + test.file_grep_not(test.stats, r'Node count, EXPRSTMT') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_real_param.pl b/test_regress/t/t_func_real_param.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_real_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_real_param.py b/test_regress/t/t_func_real_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_real_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_recurse.pl b/test_regress/t/t_func_recurse.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_recurse.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_recurse.py b/test_regress/t/t_func_recurse.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_recurse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_recurse2.pl b/test_regress/t/t_func_recurse2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_recurse2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_recurse2.py b/test_regress/t/t_func_recurse2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_recurse2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_recurse_param.pl b/test_regress/t/t_func_recurse_param.pl deleted file mode 100755 index be66c40e6..000000000 --- a/test_regress/t/t_func_recurse_param.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_func_recurse_param.py b/test_regress/t/t_func_recurse_param.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_func_recurse_param.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_func_recurse_param_bad.pl b/test_regress/t/t_func_recurse_param_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_func_recurse_param_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_recurse_param_bad.py b/test_regress/t/t_func_recurse_param_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_func_recurse_param_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_redef.pl b/test_regress/t/t_func_redef.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_func_redef.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_redef.py b/test_regress/t/t_func_redef.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_func_redef.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_func_ref.pl b/test_regress/t/t_func_ref.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_func_ref.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_ref.py b/test_regress/t/t_func_ref.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_ref.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_ref_arg.pl b/test_regress/t/t_func_ref_arg.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_func_ref_arg.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_ref_arg.py b/test_regress/t/t_func_ref_arg.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_ref_arg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_ref_bad.pl b/test_regress/t/t_func_ref_bad.pl deleted file mode 100755 index 23eda8f99..000000000 --- a/test_regress/t/t_func_ref_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_ref_bad.py b/test_regress/t/t_func_ref_bad.py new file mode 100755 index 000000000..07fc79e8e --- /dev/null +++ b/test_regress/t/t_func_ref_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_refio_bad.pl b/test_regress/t/t_func_refio_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_func_refio_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_refio_bad.py b/test_regress/t/t_func_refio_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_func_refio_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_regfirst.pl b/test_regress/t/t_func_regfirst.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_regfirst.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_regfirst.py b/test_regress/t/t_func_regfirst.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_regfirst.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_return.pl b/test_regress/t/t_func_return.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_return.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_return.py b/test_regress/t/t_func_return.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_return.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_return_bad.pl b/test_regress/t/t_func_return_bad.pl deleted file mode 100755 index 0c0e3ac70..000000000 --- a/test_regress/t/t_func_return_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_return_bad.py b/test_regress/t/t_func_return_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_return_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_sel.pl b/test_regress/t/t_func_sel.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_func_sel.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_sel.py b/test_regress/t/t_func_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_sum.pl b/test_regress/t/t_func_sum.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_sum.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_sum.py b/test_regress/t/t_func_sum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_sum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_task_bad.pl b/test_regress/t/t_func_task_bad.pl deleted file mode 100755 index 0c0e3ac70..000000000 --- a/test_regress/t/t_func_task_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_task_bad.py b/test_regress/t/t_func_task_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_task_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_tie_bad.pl b/test_regress/t/t_func_tie_bad.pl deleted file mode 100755 index 0c0e3ac70..000000000 --- a/test_regress/t/t_func_tie_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_tie_bad.py b/test_regress/t/t_func_tie_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_tie_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_twocall.pl b/test_regress/t/t_func_twocall.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_twocall.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_twocall.py b/test_regress/t/t_func_twocall.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_twocall.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_twocall_noexpand.pl b/test_regress/t/t_func_twocall_noexpand.pl deleted file mode 100755 index 452d4b37a..000000000 --- a/test_regress/t/t_func_twocall_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_func_twocall.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_twocall_noexpand.py b/test_regress/t/t_func_twocall_noexpand.py new file mode 100755 index 000000000..995ad7526 --- /dev/null +++ b/test_regress/t/t_func_twocall_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_func_twocall.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_types.pl b/test_regress/t/t_func_types.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_types.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_types.py b/test_regress/t/t_func_types.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_types.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_under.pl b/test_regress/t/t_func_under.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_under.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_under.py b/test_regress/t/t_func_under.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_under.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_under2.pl b/test_regress/t/t_func_under2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_under2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_under2.py b/test_regress/t/t_func_under2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_under2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_uninit.pl b/test_regress/t/t_func_uninit.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_func_uninit.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_uninit.py b/test_regress/t/t_func_uninit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_uninit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_unit.pl b/test_regress/t/t_func_unit.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_func_unit.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_unit.py b/test_regress/t/t_func_unit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_unit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_v.pl b/test_regress/t/t_func_v.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_v.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_v.py b/test_regress/t/t_func_v.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_v.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_v_noinl.pl b/test_regress/t/t_func_v_noinl.pl deleted file mode 100755 index 818d754c1..000000000 --- a/test_regress/t/t_func_v_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_v.v"); - -compile( - v_flags2 => ['+define+T_FUNC_V_NOINL',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_v_noinl.py b/test_regress/t/t_func_v_noinl.py new file mode 100755 index 000000000..eb69b64b8 --- /dev/null +++ b/test_regress/t/t_func_v_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_v.v" + +test.compile(v_flags2=['+define+T_FUNC_V_NOINL']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_void.pl b/test_regress/t/t_func_void.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_void.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_void.py b/test_regress/t/t_func_void.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_void.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_void_bad.out b/test_regress/t/t_func_void_bad.out index a2ccc177d..e14223a08 100644 --- a/test_regress/t/t_func_void_bad.out +++ b/test_regress/t/t_func_void_bad.out @@ -1,6 +1,9 @@ -%Warning-IGNOREDRETURN: t/t_func_void_bad.v:26:7: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) - 26 | f1(20); +%Warning-IGNOREDRETURN: t/t_func_void_bad.v:21:7: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) + 21 | f1(); | ^~ ... For warning description see https://verilator.org/warn/IGNOREDRETURN?v=latest ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message. +%Warning-IGNOREDRETURN: t/t_func_void_bad.v:24:9: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) + 24 | c.fi(); + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_func_void_bad.pl b/test_regress/t/t_func_void_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_func_void_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_void_bad.py b/test_regress/t/t_func_void_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_void_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_void_bad.v b/test_regress/t/t_func_void_bad.v index 3cea6abc8..837595812 100644 --- a/test_regress/t/t_func_void_bad.v +++ b/test_regress/t/t_func_void_bad.v @@ -4,30 +4,24 @@ // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; - - int side_effect; +class Cls; + function int fi(); + return 10; + endfunction +endclass +module t; function int f1; - input int in; - f1 = in + 1; - side_effect += in + 1; + return 20; endfunction initial begin - int got; - side_effect = 1; + Cls c; // - got = f1(10); - if (got != 11) $stop; - if (side_effect != 12) $stop; + f1(); // Bad - ignored result // - f1(20); - if (side_effect != 33) $stop; - // -// void'f1(30); -// if (side_effect != 64) $stop; + c = new; + c.fi(); // Bad - ignored result // $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_func_while.pl b/test_regress/t/t_func_while.pl deleted file mode 100755 index 886645acd..000000000 --- a/test_regress/t/t_func_while.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--trace"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_while.py b/test_regress/t/t_func_while.py new file mode 100755 index 000000000..320934d1d --- /dev/null +++ b/test_regress/t/t_func_while.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--trace"]) + +test.passes() diff --git a/test_regress/t/t_func_wide.pl b/test_regress/t/t_func_wide.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_func_wide.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_wide.py b/test_regress/t/t_func_wide.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_wide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_wide_out.pl b/test_regress/t/t_func_wide_out.pl deleted file mode 100755 index bdc7b0a29..000000000 --- a/test_regress/t/t_func_wide_out.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-WIDTHTRUNC"], - v_flags2 => ["+define+T_FUNC_WIDE_OUT t/t_func_wide_out_c.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_wide_out.py b/test_regress/t/t_func_wide_out.py new file mode 100755 index 000000000..a4ec64568 --- /dev/null +++ b/test_regress/t/t_func_wide_out.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-WIDTHTRUNC"], + v_flags2=["+define+T_FUNC_WIDE_OUT t/t_func_wide_out_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_wide_out_bad.pl b/test_regress/t/t_func_wide_out_bad.pl deleted file mode 100755 index 15b164f6a..000000000 --- a/test_regress/t/t_func_wide_out_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_func_wide_out.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_wide_out_bad.py b/test_regress/t/t_func_wide_out_bad.py new file mode 100755 index 000000000..f2623d634 --- /dev/null +++ b/test_regress/t/t_func_wide_out_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_func_wide_out.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_wide_out_noinl.pl b/test_regress/t/t_func_wide_out_noinl.pl deleted file mode 100755 index cfdf588bf..000000000 --- a/test_regress/t/t_func_wide_out_noinl.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t_func_wide_out.v"); - -compile( - verilator_flags2 => ["-Wno-WIDTHTRUNC"], - v_flags2 => ["+define+T_FUNC_WIDE_OUT_NOINL +define+TEST_NOINLINE t/t_func_wide_out_c.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_wide_out_noinl.py b/test_regress/t/t_func_wide_out_noinl.py new file mode 100755 index 000000000..a27b30540 --- /dev/null +++ b/test_regress/t/t_func_wide_out_noinl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t_func_wide_out.v" + +test.compile( + verilator_flags2=["-Wno-WIDTHTRUNC"], + v_flags2=["+define+T_FUNC_WIDE_OUT_NOINL +define+TEST_NOINLINE t/t_func_wide_out_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fuzz_always_bad.pl b/test_regress/t/t_fuzz_always_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_fuzz_always_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_always_bad.py b/test_regress/t/t_fuzz_always_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fuzz_always_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fuzz_eof_bad.pl b/test_regress/t/t_fuzz_eof_bad.pl deleted file mode 100755 index 3be843059..000000000 --- a/test_regress/t/t_fuzz_eof_bad.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_eof_bad.py b/test_regress/t/t_fuzz_eof_bad.py new file mode 100755 index 000000000..d14db8ce3 --- /dev/null +++ b/test_regress/t/t_fuzz_eof_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True) + +test.passes() diff --git a/test_regress/t/t_fuzz_eqne_bad.pl b/test_regress/t/t_fuzz_eqne_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_fuzz_eqne_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_eqne_bad.py b/test_regress/t/t_fuzz_eqne_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fuzz_eqne_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fuzz_genintf_bad.pl b/test_regress/t/t_fuzz_genintf_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_fuzz_genintf_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_genintf_bad.py b/test_regress/t/t_fuzz_genintf_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fuzz_genintf_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fuzz_negwidth_bad.pl b/test_regress/t/t_fuzz_negwidth_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_fuzz_negwidth_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_negwidth_bad.py b/test_regress/t/t_fuzz_negwidth_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fuzz_negwidth_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fuzz_triand_bad.pl b/test_regress/t/t_fuzz_triand_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_fuzz_triand_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_triand_bad.py b/test_regress/t/t_fuzz_triand_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fuzz_triand_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gantt.pl b/test_regress/t/t_gantt.pl deleted file mode 100755 index 917ede8fe..000000000 --- a/test_regress/t/t_gantt.pl +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test for bin/verilator_gantt, - -scenarios(vlt_all => 1); - -# It doesn't really matter what test -# we use, so long as it runs several cycles, -# enough for the profiling to happen: -top_filename("t/t_gen_alw.v"); - -compile( - v_flags2 => ["--prof-exec"], - # Checks below care about thread count, so use 2 (minimum reasonable) - threads => $Self->{vltmt} ? 2 : 1 - ); - -execute( - all_run_flags => ["+verilator+prof+exec+start+2", - " +verilator+prof+exec+window+2", - " +verilator+prof+exec+file+$Self->{obj_dir}/profile_exec.dat", - " +verilator+prof+vlt+file+$Self->{obj_dir}/profile.vlt", - ], - check_finished => 1, - ); - -# For now, verilator_gantt still reads from STDIN -# (probably it should take a file, gantt.dat like verilator_profcfunc) -# The profiling data still goes direct to the runtime's STDOUT -# (maybe that should go to a separate file - gantt.dat?) -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_gantt", - "$Self->{obj_dir}/profile_exec.dat", - "--vcd $Self->{obj_dir}/profile_exec.vcd", - "| tee $Self->{obj_dir}/gantt.log"], - ); - -if ($Self->{vltmt}) { - file_grep("$Self->{obj_dir}/gantt.log", qr/Total threads += 2/i); - file_grep("$Self->{obj_dir}/gantt.log", qr/Total mtasks += 7/i); - # Predicted thread utilization should be less than 100% - file_grep_not("$Self->{obj_dir}/gantt.log", qr/Thread utilization =\s*\d\d\d+\.\d+%/i); -} else { - file_grep("$Self->{obj_dir}/gantt.log", qr/Total threads += 1/i); - file_grep("$Self->{obj_dir}/gantt.log", qr/Total mtasks += 0/i); -} -file_grep("$Self->{obj_dir}/gantt.log", qr/\|\s+2\s+\|\s+2\.0+\s+\|\s+eval/i); - -# Diff to itself, just to check parsing -vcd_identical("$Self->{obj_dir}/profile_exec.vcd", "$Self->{obj_dir}/profile_exec.vcd"); - -ok(1); -1; diff --git a/test_regress/t/t_gantt.py b/test_regress/t/t_gantt.py new file mode 100755 index 000000000..2217faff4 --- /dev/null +++ b/test_regress/t/t_gantt.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test for bin/verilator_gantt, + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_gen_alw.v" # Any, as long as runs a few cycles + +test.compile( + v_flags2=["--prof-exec"], + # Checks below care about thread count, so use 2 (minimum reasonable) + threads=(2 if test.vltmt else 1)) + +test.execute(all_run_flags=[ + "+verilator+prof+exec+start+2", + " +verilator+prof+exec+window+2", + " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", + " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable + +# For now, verilator_gantt still reads from STDIN +# (probably it should take a file, gantt.dat like verilator_profcfunc) +# The profiling data still goes direct to the runtime's STDOUT +# (maybe that should go to a separate file - gantt.dat?) +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", test.obj_dir + + "/profile_exec.dat", "--vcd " + test.obj_dir + "/profile_exec.vcd", "| tee " + test.obj_dir + + "/gantt.log" +]) + +if test.vltmt: + test.file_grep(test.obj_dir + "/gantt.log", r'Total threads += 2') + test.file_grep(test.obj_dir + "/gantt.log", r'Total mtasks += 7') + # Predicted thread utilization should be less than 100% + test.file_grep_not(test.obj_dir + "/gantt.log", r'Thread utilization =\s*\d\d\d+\.\d+%') +else: + test.file_grep(test.obj_dir + "/gantt.log", r'Total threads += 1') + test.file_grep(test.obj_dir + "/gantt.log", r'Total mtasks += 0') + +test.file_grep(test.obj_dir + "/gantt.log", r'\|\s+2\s+\|\s+2\.0+\s+\|\s+eval') + +# Diff to itself, just to check parsing +test.vcd_identical(test.obj_dir + "/profile_exec.vcd", test.obj_dir + "/profile_exec.vcd") + +test.passes() diff --git a/test_regress/t/t_gantt_io.pl b/test_regress/t/t_gantt_io.pl deleted file mode 100755 index d3ba7df5c..000000000 --- a/test_regress/t/t_gantt_io.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_gantt" - . " $Self->{t_dir}/$Self->{name}.dat > gantt.log"], - check_finished => 0); - -files_identical("$Self->{obj_dir}/gantt.log", $Self->{golden_filename}); - -vcd_identical("$Self->{obj_dir}/profile_exec.vcd", "$Self->{t_dir}/$Self->{name}.vcd.out"); - -ok(1); -1; diff --git a/test_regress/t/t_gantt_io.py b/test_regress/t/t_gantt_io.py new file mode 100755 index 000000000..03f00fd52 --- /dev/null +++ b/test_regress/t/t_gantt_io.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt" + " " + + test.t_dir + "/" + test.name + ".dat > gantt.log" +], + check_finished=False) + +test.files_identical(test.obj_dir + "/gantt.log", test.golden_filename) +test.vcd_identical(test.obj_dir + "/profile_exec.vcd", test.t_dir + "/" + test.name + ".vcd.out") + +test.passes() diff --git a/test_regress/t/t_gantt_io_arm.pl b/test_regress/t/t_gantt_io_arm.pl deleted file mode 100755 index 7eac146d9..000000000 --- a/test_regress/t/t_gantt_io_arm.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_gantt" - . " $Self->{t_dir}/$Self->{name}.dat > gantt.log"], - check_finished => 0); - -files_identical("$Self->{obj_dir}/gantt.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_gantt_io_arm.py b/test_regress/t/t_gantt_io_arm.py new file mode 100755 index 000000000..99cb09f47 --- /dev/null +++ b/test_regress/t/t_gantt_io_arm.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt" + " " + + test.t_dir + "/" + test.name + ".dat > gantt.log" +], + check_finished=False) + +test.files_identical(test.obj_dir + "/gantt.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gantt_io_noproc.pl b/test_regress/t/t_gantt_io_noproc.pl deleted file mode 100755 index f3011e1ff..000000000 --- a/test_regress/t/t_gantt_io_noproc.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_gantt" - . " --no-vcd $Self->{t_dir}/$Self->{name}.dat > gantt.log"], - check_finished => 0); - -files_identical("$Self->{obj_dir}/gantt.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_gantt_io_noproc.py b/test_regress/t/t_gantt_io_noproc.py new file mode 100755 index 000000000..d5270ebae --- /dev/null +++ b/test_regress/t/t_gantt_io_noproc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt" + + " --no-vcd", test.t_dir + "/" + test.name + ".dat > gantt.log" +], + check_finished=False) + +test.files_identical(test.obj_dir + "/gantt.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gantt_two.cpp b/test_regress/t/t_gantt_two.cpp index 50a30b88b..484fd4072 100644 --- a/test_regress/t/t_gantt_two.cpp +++ b/test_regress/t/t_gantt_two.cpp @@ -16,7 +16,7 @@ int main(int argc, char** argv) { srand48(5); const std::unique_ptr contextp{new VerilatedContext}; - // VL_USE_THREADS define is set in t_gantt_two.pl + // VL_USE_THREADS define is set in t_gantt_two.py contextp->threads(TEST_USE_THREADS); contextp->debug(0); contextp->commandArgs(argc, argv); diff --git a/test_regress/t/t_gantt_two.pl b/test_regress/t/t_gantt_two.pl deleted file mode 100755 index 895a24c85..000000000 --- a/test_regress/t/t_gantt_two.pl +++ /dev/null @@ -1,63 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test for bin/verilator_gantt, - -scenarios(vlt_all => 1); - -# It doesn't really matter what test -# we use, so long as it runs several cycles, -# enough for the profiling to happen: -top_filename("t/t_gen_alw.v"); - -my $threads_num = $Self->{vltmt} ? 2 : 1; - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--prof-exec --exe $Self->{t_dir}/$Self->{name}.cpp"], - # Checks below care about thread count, so use 2 (minimum reasonable) - threads => $threads_num, - make_flags => "CPPFLAGS_ADD=\"-DVL_NO_LEGACY -DTEST_USE_THREADS=$threads_num\"", - ); - -execute( - all_run_flags => ["+verilator+prof+exec+start+4", - " +verilator+prof+exec+window+4", - " +verilator+prof+exec+file+$Self->{obj_dir}/profile_exec.dat", - " +verilator+prof+vlt+file+$Self->{obj_dir}/profile.vlt", - ], - check_finished => 1, - ); - -# For now, verilator_gantt still reads from STDIN -# (probably it should take a file, gantt.dat like verilator_profcfunc) -# The profiling data still goes direct to the runtime's STDOUT -# (maybe that should go to a separate file - gantt.dat?) -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_gantt", - "$Self->{obj_dir}/profile_exec.dat", - "--vcd $Self->{obj_dir}/profile_exec.vcd", - "| tee $Self->{obj_dir}/gantt.log"], - ); - -if ($Self->{vltmt}) { - file_grep("$Self->{obj_dir}/gantt.log", qr/Total threads += 2/i); - file_grep("$Self->{obj_dir}/gantt.log", qr/Total mtasks += 7/i); -} else { - file_grep("$Self->{obj_dir}/gantt.log", qr/Total threads += 1/i); - file_grep("$Self->{obj_dir}/gantt.log", qr/Total mtasks += 0/i); -} -file_grep("$Self->{obj_dir}/gantt.log", qr/\|\s+4\s+\|\s+4\.0+\s+\|\s+eval/i); - -# Diff to itself, just to check parsing -vcd_identical("$Self->{obj_dir}/profile_exec.vcd", "$Self->{obj_dir}/profile_exec.vcd"); - -ok(1); -1; diff --git a/test_regress/t/t_gantt_two.py b/test_regress/t/t_gantt_two.py new file mode 100755 index 000000000..e9a61e566 --- /dev/null +++ b/test_regress/t/t_gantt_two.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test for bin/verilator_gantt, + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_gen_alw.v" # Any, as long as runs a few cycles + +threads_num = (2 if test.vltmt else 1) + +test.compile( + make_top_shell=False, + make_main=False, + v_flags2=["--prof-exec --exe", test.pli_filename], + # Checks below care about thread count, so use 2 (minimum reasonable) + threads=threads_num, + make_flags=["CPPFLAGS_ADD=\"-DVL_NO_LEGACY -DTEST_USE_THREADS=" + str(threads_num) + "\""]) + +test.execute(all_run_flags=[ + "+verilator+prof+exec+start+4", + " +verilator+prof+exec+window+4", + " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", + " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable + +# For now, verilator_gantt still reads from STDIN +# (probably it should take a file, gantt.dat like verilator_profcfunc) +# The profiling data still goes direct to the runtime's STDOUT +# (maybe that should go to a separate file - gantt.dat?) +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", + test.obj_dir + "/profile_exec.dat", + "--vcd " + test.obj_dir + "/profile_exec.vcd", + "| tee " + test.obj_dir + "/gantt.log"]) # yapf:disable + +if test.vltmt: + test.file_grep(test.obj_dir + "/gantt.log", r'Total threads += 2') + test.file_grep(test.obj_dir + "/gantt.log", r'Total mtasks += 7') +else: + test.file_grep(test.obj_dir + "/gantt.log", r'Total threads += 1') + test.file_grep(test.obj_dir + "/gantt.log", r'Total mtasks += 0') + +test.file_grep(test.obj_dir + "/gantt.log", r'\|\s+4\s+\|\s+4\.0+\s+\|\s+eval') + +# Diff to itself, just to check parsing +test.vcd_identical(test.obj_dir + "/profile_exec.vcd", test.obj_dir + "/profile_exec.vcd") + +test.passes() diff --git a/test_regress/t/t_gate_array.pl b/test_regress/t/t_gate_array.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_gate_array.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_array.py b/test_regress/t/t_gate_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gate_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_basic.pl b/test_regress/t/t_gate_basic.pl deleted file mode 100755 index b56aa9309..000000000 --- a/test_regress/t/t_gate_basic.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--no-timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_basic.py b/test_regress/t/t_gate_basic.py new file mode 100755 index 000000000..e5667d0d0 --- /dev/null +++ b/test_regress/t/t_gate_basic.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_basic_timing.pl b/test_regress/t/t_gate_basic_timing.pl deleted file mode 100755 index efbe15374..000000000 --- a/test_regress/t/t_gate_basic_timing.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 10e-7 / 10e-9; - -top_filename("t/t_gate_basic.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing --timescale 10ns/1ns -Wno-RISEFALLDLY"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_basic_timing.py b/test_regress/t/t_gate_basic_timing.py new file mode 100755 index 000000000..cfcba0b42 --- /dev/null +++ b/test_regress/t/t_gate_basic_timing.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_gate_basic.v" +test.main_time_multiplier = 10e-7 / 10e-9 + +test.compile(timing_loop=True, verilator_flags2=["--timing --timescale 10ns/1ns -Wno-RISEFALLDLY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_chained.pl b/test_regress/t/t_gate_chained.pl deleted file mode 100755 index ebaff169c..000000000 --- a/test_regress/t/t_gate_chained.pl +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; - -scenarios(simulator => 1); - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_gate_chained.pl\n"); - $fh->print("module t (clk,i,sel,o);\n"); - $fh->print(" input clk;\n"); - $fh->print(" input [63:0] i;\n"); - $fh->print(" input [15:0] sel;\n"); - $fh->print(" output [63:0] o;\n"); - $fh->print("\n"); - my $prev = "i"; - my $n = 9000; - for (my $i = 1; $i < $n; ++$i) { - $fh->printf(" wire [63:0] ass%04x = (sel == 16'h%04x) ? 64'h0 : $prev;\n", $i, $i); - $prev = sprintf("ass%04x", $i); - } - - $fh->print("\n"); - $fh->print(" wire [63:0] o = $prev;\n"); - - $fh->print("\n"); - $fh->print(" always @ (posedge clk) begin\n"); - $fh->print(' $write("*-* All Finished *-*\n");', "\n"); - $fh->print(' $finish;', "\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_gate_chained.v"); - -gen($Self->{top_filename}); - -compile( - verilator_flags2 => ["--stats --x-assign fast --x-initial fast", - "-Wno-UNOPTTHREADS -fno-dfg"], - ); - -execute( - check_finished => 1, - ); - -# Must be <<9000 above to prove this worked -file_grep($Self->{stats}, qr/Optimizations, Gate sigs deleted\s+(\d+)/i, 8575); - -ok(1); -1; diff --git a/test_regress/t/t_gate_chained.py b/test_regress/t/t_gate_chained.py new file mode 100755 index 000000000..37a8dd6d4 --- /dev/null +++ b/test_regress/t/t_gate_chained.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = test.obj_dir + "/t_gate_chained.v" + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_gate_chained.py\n") + fh.write("module t (clk,i,sel,o);\n") + fh.write(" input clk;\n") + fh.write(" input [63:0] i;\n") + fh.write(" input [15:0] sel;\n") + fh.write(" output [63:0] o;\n") + fh.write("\n") + prev = "i" + n = 9000 + for i in range(1, n): + fh.write( + (" wire [63:0] ass%04x = (sel == 16'h%04x) ? 64'h0 : " + prev + ";\n") % (i, i)) + prev = "ass%04x" % i + + fh.write("\n") + fh.write(" wire [63:0] o = " + prev + ";\n") + + fh.write("\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(' $write("*-* All Finished *-*\\n");' + "\n") + fh.write(' $finish;' + "\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen(test.top_filename) + +test.compile( + verilator_flags2=["--stats --x-assign fast --x-initial fast", "-Wno-UNOPTTHREADS -fno-dfg"]) + +test.execute() + +# Must be <<9000 above to prove this worked +test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 8575) + +test.passes() diff --git a/test_regress/t/t_gate_delay_unsup.pl b/test_regress/t/t_gate_delay_unsup.pl deleted file mode 100755 index ecb0ab324..000000000 --- a/test_regress/t/t_gate_delay_unsup.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_gate_basic.v"); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME -Wno-UNUSED --timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_delay_unsup.py b/test_regress/t/t_gate_delay_unsup.py new file mode 100755 index 000000000..3e0229f9a --- /dev/null +++ b/test_regress/t/t_gate_delay_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_gate_basic.v" + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME -Wno-UNUSED --timing"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gate_delref.pl b/test_regress/t/t_gate_delref.pl deleted file mode 100755 index 2eb6a63bc..000000000 --- a/test_regress/t/t_gate_delref.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_delref.py b/test_regress/t/t_gate_delref.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_gate_delref.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_gate_elim.pl b/test_regress/t/t_gate_elim.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_gate_elim.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_elim.py b/test_regress/t/t_gate_elim.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gate_elim.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_fdup.pl b/test_regress/t/t_gate_fdup.pl deleted file mode 100755 index d2f13f637..000000000 --- a/test_regress/t/t_gate_fdup.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -lint( - verilator_flags2 => ["--language 1364-2005"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_fdup.py b/test_regress/t/t_gate_fdup.py new file mode 100755 index 000000000..648df1761 --- /dev/null +++ b/test_regress/t/t_gate_fdup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.lint(verilator_flags2=["--language 1364-2005"]) + +test.passes() diff --git a/test_regress/t/t_gate_implicit.pl b/test_regress/t/t_gate_implicit.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gate_implicit.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_implicit.py b/test_regress/t/t_gate_implicit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gate_implicit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_loop.pl b/test_regress/t/t_gate_loop.pl deleted file mode 100755 index 1d9caab1c..000000000 --- a/test_regress/t/t_gate_loop.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_loop.py b/test_regress/t/t_gate_loop.py new file mode 100755 index 000000000..8e15ef2eb --- /dev/null +++ b/test_regress/t/t_gate_loop.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.passes() diff --git a/test_regress/t/t_gate_lvalue_const.pl b/test_regress/t/t_gate_lvalue_const.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_gate_lvalue_const.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_lvalue_const.py b/test_regress/t/t_gate_lvalue_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gate_lvalue_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_opt.pl b/test_regress/t/t_gate_opt.pl deleted file mode 100755 index 68e7b55e1..000000000 --- a/test_regress/t/t_gate_opt.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_opt.py b/test_regress/t/t_gate_opt.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gate_opt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_ormux.pl b/test_regress/t/t_gate_ormux.pl deleted file mode 100755 index 3f5118673..000000000 --- a/test_regress/t/t_gate_ormux.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{cycles} = ($Self->{benchmark} ? 100_000_000 : 100); -$Self->{sim_time} = $Self->{cycles} * 10 + 1000; - -compile( - v_flags2 => ["+define+SIM_CYCLES=$Self->{cycles}",], - verilator_flags2 => ["-Wno-UNOPTTHREADS", "--stats", "-fno-dfg"], - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 1058); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_ormux.py b/test_regress/t/t_gate_ormux.py new file mode 100755 index 000000000..3fb514208 --- /dev/null +++ b/test_regress/t/t_gate_ormux.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.cycles = (100000000 if test.benchmark else 100) +test.sim_time = test.cycles * 10 + 1000 + +test.compile(v_flags2=["+define+SIM_CYCLES=" + str(test.cycles)], + verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", "-fno-dfg"]) + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 1058) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_primitives_implicit_net.pl b/test_regress/t/t_gate_primitives_implicit_net.pl deleted file mode 100755 index 922c66457..000000000 --- a/test_regress/t/t_gate_primitives_implicit_net.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-Wno-fatal --no-skip-identical"], - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_primitives_implicit_net.py b/test_regress/t/t_gate_primitives_implicit_net.py new file mode 100755 index 000000000..30e8dbdb0 --- /dev/null +++ b/test_regress/t/t_gate_primitives_implicit_net.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-Wno-fatal --no-skip-identical"], + expect_filename=test.golden_filename) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_strength.pl b/test_regress/t/t_gate_strength.pl deleted file mode 100755 index dd8b670e0..000000000 --- a/test_regress/t/t_gate_strength.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-bbox-unsup'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_strength.py b/test_regress/t/t_gate_strength.py new file mode 100755 index 000000000..e838b9b8f --- /dev/null +++ b/test_regress/t/t_gate_strength.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-bbox-unsup']) + +test.passes() diff --git a/test_regress/t/t_gate_tree.pl b/test_regress/t/t_gate_tree.pl deleted file mode 100755 index 0eb5101e5..000000000 --- a/test_regress/t/t_gate_tree.pl +++ /dev/null @@ -1,130 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; -#use Data::Dumper; -use strict; -use vars qw($Self); - -scenarios(simulator => 1); - -my $width = 64 * ($ENV{VERILATOR_TEST_WIDTH} || 4); -my $vars = 64; - -$Self->{cycles} = ($Self->{benchmark} ? 1_000_000 : 100); -$Self->{sim_time} = $Self->{cycles} * 10 + 1000; - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_gate_tree.pl\n"); - $fh->print("module t (clk);\n"); - $fh->print(" input clk;\n"); - $fh->print("\n"); - $fh->print(" integer cyc=0;\n"); - $fh->print(" reg reset;\n"); - $fh->print("\n"); - - my %tree; - my $fanin = 8; - my $stages = int(log($vars) / log($fanin) + 0.99999) + 1; - my $result = 0; - for (my $n = 0; $n < $vars; $n++) { - $result += ($n || 1); - $tree{0}{$n}{$n} = 1; - my $nl = $n; - for (my $stage=1; $stage < $stages; $stage++) { - my $lastn = $nl; - $nl = int($nl / $fanin); - $tree{$stage}{$nl}{$lastn} = 1; - } - } - #print Dumper(\%tree); - - $fh->print("\n"); - my $workingset = 0; - foreach my $stage (sort { $a <=> $b} keys %tree) { - foreach my $n (sort { $a <=> $b} keys %{$tree{$stage}}) { - $fh->print( " reg [" . ($width - 1) . ":0] v${stage}_${n};\n"); - $workingset += int($width/8 + 7); - } - } - - $fh->print("\n"); - $fh->print(" always @ (posedge clk) begin\n"); - $fh->print(" cyc <= cyc + 1;\n"); - $fh->print("`ifdef TEST_VERBOSE\n"); - $fh->print(" \$write(\"[%0t] rst=%0x v0_0=%0x v1_0=%0x result=%0x\\n\"" - .", \$time, reset, v0_0, v1_0, v" . ($stages - 1) . "_0);\n"); - $fh->print("`endif\n"); - $fh->print(" if (cyc==0) begin\n"); - $fh->print(" reset <= 1;\n"); - $fh->print(" end\n"); - $fh->print(" else if (cyc==10) begin\n"); - $fh->print(" reset <= 0;\n"); - $fh->print(" end\n"); - $fh->print("`ifndef SIM_CYCLES\n"); - $fh->print(" `define SIM_CYCLES 99\n"); - $fh->print("`endif\n"); - $fh->print(" else if (cyc==`SIM_CYCLES) begin\n"); - $fh->print(" if (v" . ($stages - 1) . "_0 != ${width}'d${result}) \$stop;\n"); - $fh->print(" \$write(\"VARS=${vars} WIDTH=${width}" - ." WORKINGSET=" . (int($workingset / 1024)) . "KB\\n\");\n"); - $fh->print(' $write("*-* All Finished *-*\n");', "\n"); - $fh->print(' $finish;', "\n"); - $fh->print(" end\n"); - $fh->print(" end\n"); - - $fh->print("\n"); - for (my $n=0; $n<$vars; $n++) { - $fh->print(" always @ (posedge clk)" - . " v0_${n} <= reset ? ${width}'d" . (${n} || 1) . " : v0_" - . ((int($n / $fanin) * $fanin) + (($n + 1) % $fanin)) . ";\n"); - } - - foreach my $stage (sort {$a<=>$b} keys %tree) { - next if $stage == 0; - $fh->print("\n"); - foreach my $n (sort {$a<=>$b} keys %{$tree{$stage}}) { - $fh->print(" always @ (posedge clk)" - . " v${stage}_${n} <="); - my $op = ""; - foreach my $ni (sort {$a<=>$b} keys %{$tree{$stage}{$n}}) { - $fh->print($op . " v" . (${stage} - 1) . "_${ni}"); - $op = " +"; - } - $fh->print(";\n"); - } - } - - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_gate_tree.v"); - -gen($Self->{top_filename}); - -compile( - v_flags2 => ["+define+SIM_CYCLES=$Self->{cycles}",], - verilator_flags2=>["--stats --x-assign fast --x-initial fast", - "-Wno-UNOPTTHREADS"], - ); - -execute( - all_run_flags => ["+verilator+prof+exec+start+100", - " +verilator+prof+exec+window+2", - " +verilator+prof+exec+file+$Self->{obj_dir}/profile_exec.dat", - " +verilator+prof+vlt+file+$Self->{obj_dir}/profile.vlt", - ], - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_tree.py b/test_regress/t/t_gate_tree.py new file mode 100755 index 000000000..49fa92260 --- /dev/null +++ b/test_regress/t/t_gate_tree.py @@ -0,0 +1,121 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import collections +import math + +test.scenarios('simulator') +test.top_filename = test.obj_dir + "/t_gate_tree.v" +test.cycles = (1000000 if test.benchmark else 100) +test.sim_time = test.cycles * 10 + 1000 + +width = 64 * int(test.getenv_def("VERILATOR_TEST_WIDTH", "4")) +nvars = 64 + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_gate_tree.py\n") + fh.write("module t (clk);\n") + fh.write(" input clk;\n") + fh.write("\n") + fh.write(" integer cyc=0;\n") + fh.write(" reg reset;\n") + fh.write("\n") + + tree = collections.defaultdict(dict) + fanin = 8 + stages = int(math.log(nvars) / math.log(fanin) + 0.99999) + 1 + result = 0 + for n in range(0, nvars): + result += max(n, 1) + if 0 not in tree: + tree[0] = {} + if n not in tree[0]: + tree[0][n] = {} + tree[0][n][n] = True + nl = n + for stage in range(1, stages): + lastn = nl + nl = int(nl / fanin) + if stage not in tree: + tree[stage] = {} + if nl not in tree[stage]: + tree[stage][nl] = {} + tree[stage][nl][lastn] = True + + # pprint(tree) + + fh.write("\n") + workingset = 0 + for stage in sorted(tree.keys()): + for n in sorted(tree[stage].keys()): + fh.write(" reg [" + str(width - 1) + ":0] v" + str(stage) + "_" + str(n) + ";\n") + workingset += int(width / 8 + 7) + + fh.write("\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(" cyc <= cyc + 1;\n") + fh.write("`ifdef TEST_VERBOSE\n") + fh.write(" $write(\"[%0t] rst=%0x v0_0=%0x v1_0=%0x result=%0x\\n\"" + ", $time, reset, v0_0, v1_0, v" + str(stages - 1) + "_0);\n") + fh.write("`endif\n") + fh.write(" if (cyc==0) begin\n") + fh.write(" reset <= 1;\n") + fh.write(" end\n") + fh.write(" else if (cyc==10) begin\n") + fh.write(" reset <= 0;\n") + fh.write(" end\n") + fh.write("`ifndef SIM_CYCLES\n") + fh.write(" `define SIM_CYCLES 99\n") + fh.write("`endif\n") + fh.write(" else if (cyc==`SIM_CYCLES) begin\n") + fh.write(" if (v" + str(stages - 1) + "_0 != " + str(width) + "'d" + str(result) + + ") $stop;\n") + fh.write(" $write(\"VARS=" + str(nvars) + " WIDTH=" + str(width) + " WORKINGSET=" + + str(int(workingset / 1024)) + "KB\\n\");\n") + fh.write(' $write("*-* All Finished *-*\\n");' + "\n") + fh.write(' $finish;' + "\n") + fh.write(" end\n") + fh.write(" end\n") + + fh.write("\n") + for n in range(0, nvars): + fh.write(" always @ (posedge clk)" + " v0_" + str(n) + " <= reset ? " + str(width) + + "'d" + str(max(n, 1)) + " : v0_" + str((int(n / fanin) * fanin) + + ((n + 1) % fanin)) + ";\n") + + for stage in sorted(tree.keys()): + if stage == 0: + continue + fh.write("\n") + for n in sorted(tree[stage].keys()): + fh.write(" always @ (posedge clk) v" + str(stage) + "_" + str(n) + " <=") + op = "" + for ni in sorted(tree[stage][n].keys()): + fh.write(op + " v" + str(stage - 1) + "_" + str(ni)) + op = " +" + fh.write(";\n") + + fh.write("endmodule\n") + + +gen(test.top_filename) + +test.compile(v_flags2=["+define+SIM_CYCLES=" + str(test.cycles)], + verilator_flags2=["--stats --x-assign fast --x-initial fast", "-Wno-UNOPTTHREADS"]) + +test.execute(all_run_flags=[ + "+verilator+prof+exec+start+100", + " +verilator+prof+exec+window+2", + " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", + " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable + +test.passes() diff --git a/test_regress/t/t_gate_unsup.pl b/test_regress/t/t_gate_unsup.pl deleted file mode 100755 index f32089412..000000000 --- a/test_regress/t/t_gate_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - # Unsupported: UDP Tables - verilator_flags2 => ["--lint-only --bbox-unsup"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_unsup.py b/test_regress/t/t_gate_unsup.py new file mode 100755 index 000000000..fcdfcc6f4 --- /dev/null +++ b/test_regress/t/t_gate_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + # Unsupported: UDP Tables + verilator_flags2=["--lint-only --bbox-unsup"]) + +test.passes() diff --git a/test_regress/t/t_gated_clk_1.pl b/test_regress/t/t_gated_clk_1.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gated_clk_1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gated_clk_1.py b/test_regress/t/t_gated_clk_1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gated_clk_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_alw.pl b/test_regress/t/t_gen_alw.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_alw.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_alw.py b/test_regress/t/t_gen_alw.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_alw.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_assign.pl b/test_regress/t/t_gen_assign.pl deleted file mode 100755 index 7c611fc4c..000000000 --- a/test_regress/t/t_gen_assign.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_assign.py b/test_regress/t/t_gen_assign.py new file mode 100755 index 000000000..3527cdb06 --- /dev/null +++ b/test_regress/t/t_gen_assign.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_gen_cond_bitrange.pl b/test_regress/t/t_gen_cond_bitrange.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_cond_bitrange.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_cond_bitrange.py b/test_regress/t/t_gen_cond_bitrange.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_cond_bitrange.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_cond_bitrange_bad.pl b/test_regress/t/t_gen_cond_bitrange_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_gen_cond_bitrange_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_cond_bitrange_bad.py b/test_regress/t/t_gen_cond_bitrange_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_gen_cond_bitrange_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_cond_const.pl b/test_regress/t/t_gen_cond_const.pl deleted file mode 100755 index 680071db4..000000000 --- a/test_regress/t/t_gen_cond_const.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--language 1364-2001"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_cond_const.py b/test_regress/t/t_gen_cond_const.py new file mode 100755 index 000000000..4aa451103 --- /dev/null +++ b/test_regress/t/t_gen_cond_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--language 1364-2001"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_defparam.pl b/test_regress/t/t_gen_defparam.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_defparam.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_defparam.py b/test_regress/t/t_gen_defparam.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_defparam.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_defparam_bad.out b/test_regress/t/t_gen_defparam_bad.out new file mode 100644 index 000000000..2cf6e7073 --- /dev/null +++ b/test_regress/t/t_gen_defparam_bad.out @@ -0,0 +1,11 @@ +%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:9:12: Unsupported: defparam with no dot + 9 | id_15 = id_14; + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:11:18: Unsupported: defparam with no dot + 11 | defparam id_8 = 1, id_9 = 1; + | ^ +%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:11:28: Unsupported: defparam with no dot + 11 | defparam id_8 = 1, id_9 = 1; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_gen_defparam_bad.py b/test_regress/t/t_gen_defparam_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_gen_defparam_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_defparam_bad.v b/test_regress/t/t_gen_defparam_bad.v new file mode 100644 index 000000000..ec0e08d44 --- /dev/null +++ b/test_regress/t/t_gen_defparam_bad.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/); + defparam id_13.id_14 = -id_13, + id_15 = id_14; + + defparam id_8 = 1, id_9 = 1; +endmodule diff --git a/test_regress/t/t_gen_defparam_multi.pl b/test_regress/t/t_gen_defparam_multi.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_gen_defparam_multi.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_defparam_multi.py b/test_regress/t/t_gen_defparam_multi.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_gen_defparam_multi.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_defparam_nfound_bad.pl b/test_regress/t/t_gen_defparam_nfound_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_gen_defparam_nfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_defparam_nfound_bad.py b/test_regress/t/t_gen_defparam_nfound_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_gen_defparam_nfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_div0.pl b/test_regress/t/t_gen_div0.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_div0.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_div0.py b/test_regress/t/t_gen_div0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_div0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for.pl b/test_regress/t/t_gen_for.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_for.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for.py b/test_regress/t/t_gen_for.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for0.pl b/test_regress/t/t_gen_for0.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_for0.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for0.py b/test_regress/t/t_gen_for0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for1.pl b/test_regress/t/t_gen_for1.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_for1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for1.py b/test_regress/t/t_gen_for1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for_interface.pl b/test_regress/t/t_gen_for_interface.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_for_interface.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for_interface.py b/test_regress/t/t_gen_for_interface.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for_interface.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for_overlap.pl b/test_regress/t/t_gen_for_overlap.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_for_overlap.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for_overlap.py b/test_regress/t/t_gen_for_overlap.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for_overlap.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for_shuffle.pl b/test_regress/t/t_gen_for_shuffle.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_for_shuffle.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for_shuffle.py b/test_regress/t/t_gen_for_shuffle.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for_shuffle.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_forif.pl b/test_regress/t/t_gen_forif.pl deleted file mode 100755 index 4017016a5..000000000 --- a/test_regress/t/t_gen_forif.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - nc_flags2 => ['+access+r'], - verilator_flags2 => ["--no-timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_forif.py b/test_regress/t/t_gen_forif.py new file mode 100755 index 000000000..c8913bea4 --- /dev/null +++ b/test_regress/t/t_gen_forif.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(nc_flags2=['+access+r'], verilator_flags2=["--no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_genblk.pl b/test_regress/t/t_gen_genblk.pl deleted file mode 100755 index e86489964..000000000 --- a/test_regress/t/t_gen_genblk.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{sim_time} = 11000; - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_genblk.py b/test_regress/t/t_gen_genblk.py new file mode 100755 index 000000000..b89e72146 --- /dev/null +++ b/test_regress/t/t_gen_genblk.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.sim_time = 11000 + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_genblk_noinl.pl b/test_regress/t/t_gen_genblk_noinl.pl deleted file mode 100755 index ef537cd4d..000000000 --- a/test_regress/t/t_gen_genblk_noinl.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t_gen_genblk.v"); -golden_filename("t/t_gen_genblk.out"); - -scenarios(simulator => 1); - -$Self->{sim_time} = 11000; - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_genblk_noinl.py b/test_regress/t/t_gen_genblk_noinl.py new file mode 100755 index 000000000..0b6136eb6 --- /dev/null +++ b/test_regress/t/t_gen_genblk_noinl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t_gen_genblk.v" +test.golden_filename = "t/t_gen_genblk.out" +test.sim_time = 11000 + +test.compile(v_flags2=["-fno-inline"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_if.pl b/test_regress/t/t_gen_if.pl deleted file mode 100755 index 1f3b9a577..000000000 --- a/test_regress/t/t_gen_if.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_if.py b/test_regress/t/t_gen_if.py new file mode 100755 index 000000000..3527cdb06 --- /dev/null +++ b/test_regress/t/t_gen_if.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_gen_ifelse.pl b/test_regress/t/t_gen_ifelse.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_gen_ifelse.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_ifelse.py b/test_regress/t/t_gen_ifelse.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_ifelse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_inc.pl b/test_regress/t/t_gen_inc.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_inc.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_inc.py b/test_regress/t/t_gen_inc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_inc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_index.pl b/test_regress/t/t_gen_index.pl deleted file mode 100755 index 6d131b585..000000000 --- a/test_regress/t/t_gen_index.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile time only test -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_index.py b/test_regress/t/t_gen_index.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_gen_index.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_gen_intdot.pl b/test_regress/t/t_gen_intdot.pl deleted file mode 100755 index e245a66a7..000000000 --- a/test_regress/t/t_gen_intdot.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--no-timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_intdot.py b/test_regress/t/t_gen_intdot.py new file mode 100755 index 000000000..e5667d0d0 --- /dev/null +++ b/test_regress/t/t_gen_intdot.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_intdot2.pl b/test_regress/t/t_gen_intdot2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_intdot2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_intdot2.py b/test_regress/t/t_gen_intdot2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_intdot2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_local.pl b/test_regress/t/t_gen_local.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_local.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_local.py b/test_regress/t/t_gen_local.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_lsb.pl b/test_regress/t/t_gen_lsb.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_lsb.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_lsb.py b/test_regress/t/t_gen_lsb.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_lsb.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_mislevel.pl b/test_regress/t/t_gen_mislevel.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_gen_mislevel.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_mislevel.py b/test_regress/t/t_gen_mislevel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_mislevel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_missing.pl b/test_regress/t/t_gen_missing.pl deleted file mode 100755 index 5b0c42469..000000000 --- a/test_regress/t/t_gen_missing.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['+define+T_GEN_MISSING'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_missing.py b/test_regress/t/t_gen_missing.py new file mode 100755 index 000000000..1421dc553 --- /dev/null +++ b/test_regress/t/t_gen_missing.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['+define+T_GEN_MISSING']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_missing.v b/test_regress/t/t_gen_missing.v index 44dad55f1..459c7fb65 100644 --- a/test_regress/t/t_gen_missing.v +++ b/test_regress/t/t_gen_missing.v @@ -7,9 +7,9 @@ module t; // verilator lint_off PINMISSING `ifdef T_GEN_MISSING_BAD - foobar #(.FOO_TYPE(1)) foobar; // This means we should instatiate missing module + foobar #(.FOO_TYPE(1)) foobar(); // This means we should instatiate missing module `elsif T_GEN_MISSING - foobar #(.FOO_TYPE(0)) foobar; // This means we should instatiate foo0 + foobar #(.FOO_TYPE(0)) foobar(); // This means we should instatiate foo0 `else `error "Bad Test" `endif diff --git a/test_regress/t/t_gen_missing_bad.pl b/test_regress/t/t_gen_missing_bad.pl deleted file mode 100755 index 7cd5ea1e5..000000000 --- a/test_regress/t/t_gen_missing_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_gen_missing.v"); - -lint( - v_flags2 => ['+define+T_GEN_MISSING_BAD'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_missing_bad.py b/test_regress/t/t_gen_missing_bad.py new file mode 100755 index 000000000..8be012ec5 --- /dev/null +++ b/test_regress/t/t_gen_missing_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_gen_missing.v" + +test.lint(v_flags2=['+define+T_GEN_MISSING_BAD'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_missing_bad2.pl b/test_regress/t/t_gen_missing_bad2.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_gen_missing_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_missing_bad2.py b/test_regress/t/t_gen_missing_bad2.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_gen_missing_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_nonconst_bad.pl b/test_regress/t/t_gen_nonconst_bad.pl deleted file mode 100755 index d9066a317..000000000 --- a/test_regress/t/t_gen_nonconst_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - v_flags => [], # To avoid -I - v_flags2 => [], # To avoid -I - verilator_flags => ["--lint-only"], # To avoid -I - verilator_flags2 => [], # To avoid -I - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_nonconst_bad.py b/test_regress/t/t_gen_nonconst_bad.py new file mode 100755 index 000000000..a3ece0800 --- /dev/null +++ b/test_regress/t/t_gen_nonconst_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + v_flags=[], # To avoid -I + v_flags2=[], # To avoid -I + verilator_flags=["--lint-only"], # To avoid -I + verilator_flags2=[], # To avoid -I + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_self_return.pl b/test_regress/t/t_gen_self_return.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_gen_self_return.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_self_return.py b/test_regress/t/t_gen_self_return.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_self_return.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_upscope.pl b/test_regress/t/t_gen_upscope.pl deleted file mode 100755 index 1576259ea..000000000 --- a/test_regress/t/t_gen_upscope.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_upscope.py b/test_regress/t/t_gen_upscope.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_gen_upscope.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_var_bad.pl b/test_regress/t/t_gen_var_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_gen_var_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_var_bad.py b/test_regress/t/t_gen_var_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_gen_var_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_generate_fatal_bad.pl b/test_regress/t/t_generate_fatal_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_generate_fatal_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_generate_fatal_bad.py b/test_regress/t/t_generate_fatal_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_generate_fatal_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_genfor_hier.pl b/test_regress/t/t_genfor_hier.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_genfor_hier.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_genfor_hier.py b/test_regress/t/t_genfor_hier.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_genfor_hier.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_genfor_init_o0.pl b/test_regress/t/t_genfor_init_o0.pl deleted file mode 100755 index 60b075c18..000000000 --- a/test_regress/t/t_genfor_init_o0.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['-O0'], - make_main => 0, - verilator_make_gmake => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_genfor_init_o0.py b/test_regress/t/t_genfor_init_o0.py new file mode 100755 index 000000000..3eb087ae6 --- /dev/null +++ b/test_regress/t/t_genfor_init_o0.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['-O0'], make_main=False, verilator_make_gmake=False) + +test.passes() diff --git a/test_regress/t/t_genfor_signed.pl b/test_regress/t/t_genfor_signed.pl deleted file mode 100755 index c6a015747..000000000 --- a/test_regress/t/t_genfor_signed.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_genfor_signed.py b/test_regress/t/t_genfor_signed.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_genfor_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_genvar_for_bad.out b/test_regress/t/t_genvar_for_bad.out index 5088dc104..0ecb3be58 100644 --- a/test_regress/t/t_genvar_for_bad.out +++ b/test_regress/t/t_genvar_for_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_genvar_for_bad.v:23:10: Genvar not legal in non-generate for (IEEE 1800-2023 27.4): 't.i' +%Error: t/t_genvar_for_bad.v:25:13: Genvar not legal in non-generate for (IEEE 1800-2023 27.4): 't.i' : ... Suggest move for loop upwards to generate-level scope. - 23 | for (i=0; i 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_genvar_for_bad.py b/test_regress/t/t_genvar_for_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_genvar_for_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_genvar_for_bad.v b/test_regress/t/t_genvar_for_bad.v index 7dab4cafb..c90da5b15 100644 --- a/test_regress/t/t_genvar_for_bad.v +++ b/test_regress/t/t_genvar_for_bad.v @@ -17,11 +17,14 @@ module t (/*AUTOARG*/ input [63:0] iv[N-1:0]; output logic [63:0] ov[N-1:0]; + genvar j; // Bypass first genvar check genvar i; generate - always @(posedge clk) begin - for (i=0; i 1); - -lint( - # Should fail, but bug408, Verilator unsupported - fails => !$Self->{vlt}, - # expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_genvar_misuse_bad.py b/test_regress/t/t_genvar_misuse_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_genvar_misuse_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block.pl b/test_regress/t/t_hier_block.pl deleted file mode 100755 index 4253963ee..000000000 --- a/test_regress/t/t_hier_block.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -scenarios(vlt_all => 1); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--stats', - '--hierarchical', - '--Wno-TIMESCALEMOD', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", qr/^\s+\/\/\s+timeprecision\s+(\d+)ps;/mi, 1); -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block.py b/test_regress/t/t_hier_block.py new file mode 100755 index 000000000..c2cac597b --- /dev/null +++ b/test_regress/t/t_hier_block.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--stats', '--hierarchical', '--Wno-TIMESCALEMOD', '--CFLAGS', + '"-pipe -DCPP_MACRO=cplusplus"' + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^\s+\/\/\s+timeprecision\s+(\d+)ps;', 1) +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_block0_bad.pl b/test_regress/t/t_hier_block0_bad.pl deleted file mode 100755 index 39bf8dbac..000000000 --- a/test_regress/t/t_hier_block0_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ['--hierarchical'], - expect_filename => $Self->{golden_filename}, -); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block0_bad.py b/test_regress/t/t_hier_block0_bad.py new file mode 100755 index 000000000..c80415ffe --- /dev/null +++ b/test_regress/t/t_hier_block0_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, verilator_flags2=['--hierarchical'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block1_bad.pl b/test_regress/t/t_hier_block1_bad.pl deleted file mode 100755 index 39bf8dbac..000000000 --- a/test_regress/t/t_hier_block1_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ['--hierarchical'], - expect_filename => $Self->{golden_filename}, -); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block1_bad.py b/test_regress/t/t_hier_block1_bad.py new file mode 100755 index 000000000..c80415ffe --- /dev/null +++ b/test_regress/t/t_hier_block1_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, verilator_flags2=['--hierarchical'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_cmake.pl b/test_regress/t/t_hier_block_cmake.pl deleted file mode 100755 index c815fb6c9..000000000 --- a/test_regress/t/t_hier_block_cmake.pl +++ /dev/null @@ -1,44 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# If a test fails, broken .cmake may disturb the next run -clean_objs(); - -scenarios(simulator => 1); -top_filename("t/t_hier_block.v"); - -my $threads = ($Self->{vltmt} ? '-DTEST_THREADS=6' : '-DTEST_THREADS=1'); - -if (!$Self->have_cmake) { - $Self->skip("Test requires CMake; ignore error since not available or version too old\n"); -} else { - run(logfile => "$Self->{obj_dir}/cmake.log", - cmd => ['cd "' . $Self->{obj_dir} . '" && cmake ' . $Self->{t_dir} . '/t_hier_block_cmake', - "-DCMAKE_PREFIX_PATH=$ENV{VERILATOR_ROOT}", - $threads - ]); - - run(logfile => "$Self->{obj_dir}/build.log", - cmd => ['cd "' . $Self->{obj_dir} . '" && cmake --build', '.', '--', "CXX_FLAGS=$threads"] - ); - - run(logfile => "$Self->{obj_dir}/run.log", - cmd => ['cd "' . $Self->{obj_dir} . '" && ./t_hier_block_cmake', '.'] - ); - my $target_dir = $Self->{obj_dir} . '/CMakeFiles/t_hier_block_cmake.dir/Vt_hier_block.dir/'; - file_grep($target_dir . 'Vsub0/sub0.sv', /^module\s+(\S+)\s+/, "sub0"); - file_grep($target_dir . 'Vsub1/sub1.sv', /^module\s+(\S+)\s+/, "sub1"); - file_grep($target_dir . 'Vsub2/sub2.sv', /^module\s+(\S+)\s+/, "sub2"); - file_grep($target_dir . 'Vt_hier_block__stats.txt', qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); - file_grep($Self->{obj_dir} . '/run.log', qr/MACRO:(\S+) is defined/i, "cplusplus"); -} - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_cmake/main.cpp b/test_regress/t/t_hier_block_cmake/main.cpp index beebaabff..731237b88 100644 --- a/test_regress/t/t_hier_block_cmake/main.cpp +++ b/test_regress/t/t_hier_block_cmake/main.cpp @@ -14,7 +14,7 @@ int main(int argc, char *argv[]) { const std::unique_ptr contextp{new VerilatedContext}; - // TEST_THREADS is set in t_hier_block_cmake.pl + // TEST_THREADS is set in t_hier_block_cmake.py contextp->threads(TEST_THREADS); contextp->commandArgs(argc, argv); std::unique_ptr top{new Vt_hier_block{contextp.get(), "top"}}; diff --git a/test_regress/t/t_hier_block_libmod.pl b/test_regress/t/t_hier_block_libmod.pl deleted file mode 100755 index 4f6d583d9..000000000 --- a/test_regress/t/t_hier_block_libmod.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ['--hierarchical', - '-y', $Self->{t_dir} . '/t_flag_relinc_dir/chip', - '+incdir+'. $Self->{t_dir} . '/t_flag_relinc_dir/include'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_libmod.py b/test_regress/t/t_hier_block_libmod.py new file mode 100755 index 000000000..7b78daf9c --- /dev/null +++ b/test_regress/t/t_hier_block_libmod.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=[ + '--hierarchical', '-y', test.t_dir + '/t_flag_relinc_dir/chip', '+incdir+' + test.t_dir + + '/t_flag_relinc_dir/include' +]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_block_nohier.pl b/test_regress/t/t_hier_block_nohier.pl deleted file mode 100755 index 9b5be406b..000000000 --- a/test_regress/t/t_hier_block_nohier.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# This test makes sure that the internal check of t_hier_block.v is correct. -# --hierarchical option is not set intentionally. - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -scenarios(vlt_all => 1); -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--stats', - '+define+USE_VLT', 't/t_hier_block_vlt.vlt', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"'], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -file_grep_not($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_nohier.py b/test_regress/t/t_hier_block_nohier.py new file mode 100755 index 000000000..514491950 --- /dev/null +++ b/test_regress/t/t_hier_block_nohier.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# This test makes sure that the internal check of t_hier_block.v is correct. +# --hierarchical option is not set intentionally. + +import vltest_bootstrap + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--stats', '+define+USE_VLT', 't/t_hier_block_vlt.vlt', '--CFLAGS', + '"-pipe -DCPP_MACRO=cplusplus"' + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep_not(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)') +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_block_prot_lib.pl b/test_regress/t/t_hier_block_prot_lib.pl deleted file mode 100755 index 13cf91c7a..000000000 --- a/test_regress/t/t_hier_block_prot_lib.pl +++ /dev/null @@ -1,66 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_hier_block.v"); - -scenarios(vlt_all => 1, xsim => 1); - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - "-cc", - "--hierarchical", - "-Mdir", - $secret_dir, - "--protect-lib", - $secret_prefix, - "--protect-key", - "PROTECT_KEY", - "t/t_hier_block.v", - "-DAS_PROT_LIB", - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - $Self->{vltmt} ? ' --threads 1' : '', - "--build"], - verilator_run => 1, - ); - last if $Self->{errors}; - - compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ["$secret_dir/secret.sv", - "-DPROTLIB_TOP", - "--top-module t", - "-LDFLAGS", - "'$secret_prefix/libsecret.a'"], - ); - - execute( - check_finished => 1, - ); - - - ok(1); - last; -} - -file_grep($secret_dir . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($secret_dir . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($secret_dir . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_prot_lib.py b/test_regress/t/t_hier_block_prot_lib.py new file mode 100755 index 000000000..d8f4103ee --- /dev/null +++ b/test_regress/t/t_hier_block_prot_lib.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all', 'xsim') +test.top_filename = "t/t_hier_block.v" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run(logfile=secret_dir + "/vlt_compile.log", + cmd=[ + "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", "--hierarchical", + "-Mdir", secret_dir, "--protect-lib", secret_prefix, "--protect-key", "PROTECT_KEY", + "t/t_hier_block.v", "-DAS_PROT_LIB", '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', + (' --threads 1' if test.vltmt else ''), "--build" + ], + verilator_run=True) + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + secret_dir + "/secret.sv", "-DPROTLIB_TOP", "--top-module t", "-LDFLAGS", + "'" + secret_prefix + "/libsecret.a'" + ]) + +test.execute() + +test.passes() + +test.file_grep(secret_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(secret_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(secret_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_block_prot_lib_shared.pl b/test_regress/t/t_hier_block_prot_lib_shared.pl deleted file mode 100755 index 0e5239345..000000000 --- a/test_regress/t/t_hier_block_prot_lib_shared.pl +++ /dev/null @@ -1,68 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_hier_block.v"); - -scenarios(vlt_all => 1, xsim => 1); - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; -my $abs_secret_dir = File::Spec->rel2abs($secret_dir); - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - "-cc", - "--hierarchical", - "-Mdir", - $secret_dir, - "--protect-lib", - $secret_prefix, - "--protect-key", - "PROTECT_KEY", - "t/t_hier_block.v", - "-DAS_PROT_LIB", - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - $Self->{vltmt} ? ' --threads 1' : '', - "--build"], - verilator_run => 1, - ); - last if $Self->{errors}; - - compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ["$secret_dir/secret.sv", - "-DPROTLIB_TOP", - "--top-module t", - "-LDFLAGS", - "'-Wl,-rpath,$abs_secret_dir -L$abs_secret_dir -l$secret_prefix'"], - ); - - execute( - check_finished => 1, - run_env => "DYLD_FALLBACK_LIBRARY_PATH=$abs_secret_dir" - ); - - - ok(1); - last; -} - -file_grep($secret_dir . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($secret_dir . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($secret_dir . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_prot_lib_shared.py b/test_regress/t/t_hier_block_prot_lib_shared.py new file mode 100755 index 000000000..1f073834c --- /dev/null +++ b/test_regress/t/t_hier_block_prot_lib_shared.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all', 'xsim') +test.top_filename = "t/t_hier_block.v" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) +abs_secret_dir = os.path.abspath(secret_dir) + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run(logfile=secret_dir + "/vlt_compile.log", + cmd=[ + "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", "--hierarchical", + "-Mdir", secret_dir, "--protect-lib", secret_prefix, "--protect-key", "PROTECT_KEY", + "t/t_hier_block.v", "-DAS_PROT_LIB", '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', + (' --threads 1' if test.vltmt else ''), "--build" + ], + verilator_run=True) + +test.compile( + v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + secret_dir + "/secret.sv", "-DPROTLIB_TOP", "--top-module t", "-LDFLAGS", + "'-Wl,-rpath," + abs_secret_dir + " -L" + abs_secret_dir + " -l" + secret_prefix + "'" + ]) + +test.execute(run_env="DYLD_FALLBACK_LIBRARY_PATH=" + abs_secret_dir) + +test.file_grep(secret_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(secret_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(secret_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_block_sc.pl b/test_regress/t/t_hier_block_sc.pl deleted file mode 100755 index 8fa8cc912..000000000 --- a/test_regress/t/t_hier_block_sc.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -scenarios(vlt_all => 1); - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--sc', - '--stats', - '--hierarchical', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_sc.py b/test_regress/t/t_hier_block_sc.py new file mode 100755 index 000000000..ee03f4602 --- /dev/null +++ b/test_regress/t/t_hier_block_sc.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_block_sc_trace_fst.pl b/test_regress/t/t_hier_block_sc_trace_fst.pl deleted file mode 100755 index f95c37ec9..000000000 --- a/test_regress/t/t_hier_block_sc_trace_fst.pl +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -scenarios(vlt_all => 1); - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--sc', - '--stats', - '--hierarchical', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - "--CFLAGS", '"-O0 -ggdb"', - "--trace-fst" - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); -ok(1); -1; diff --git a/test_regress/t/t_hier_block_sc_trace_fst.py b/test_regress/t/t_hier_block_sc_trace_fst.py new file mode 100755 index 000000000..5dbe51557 --- /dev/null +++ b/test_regress/t/t_hier_block_sc_trace_fst.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', + "--CFLAGS", '"-O0 -ggdb"', "--trace-fst" + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.pl b/test_regress/t/t_hier_block_sc_trace_vcd.pl deleted file mode 100755 index 57b99c8dc..000000000 --- a/test_regress/t/t_hier_block_sc_trace_vcd.pl +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -scenarios(vlt_all => 1); - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--sc', - '--stats', - '--hierarchical', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - "--CFLAGS", '"-O0 -ggdb"', - "--trace" - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); -ok(1); -1; diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.py b/test_regress/t/t_hier_block_sc_trace_vcd.py new file mode 100755 index 000000000..a2b2d0353 --- /dev/null +++ b/test_regress/t/t_hier_block_sc_trace_vcd.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', + "--CFLAGS", '"-O0 -ggdb"', "--trace" + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_signed_logic.pl b/test_regress/t/t_hier_block_signed_logic.pl deleted file mode 100755 index 824dfb8ea..000000000 --- a/test_regress/t/t_hier_block_signed_logic.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--stats', '--hierarchical'] - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{obj_dir} . "/Vsub/sub.sv", /^module\s+(\S+)\s+/, "sub"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 1); - -ok(1); diff --git a/test_regress/t/t_hier_block_signed_logic.py b/test_regress/t/t_hier_block_signed_logic.py new file mode 100755 index 000000000..7bba1f55e --- /dev/null +++ b/test_regress/t/t_hier_block_signed_logic.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--stats', '--hierarchical']) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub/sub.sv", r'^module\s+(\S+)\s+', "sub") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_hier_block_struct.pl b/test_regress/t/t_hier_block_struct.pl deleted file mode 100755 index 0bce0213b..000000000 --- a/test_regress/t/t_hier_block_struct.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--hierarchical'] - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{obj_dir} . "/VTest/Test.sv", /^module\s+(\S+)\s+/, "Test"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_struct.py b/test_regress/t/t_hier_block_struct.py new file mode 100755 index 000000000..1f3ee62cc --- /dev/null +++ b/test_regress/t/t_hier_block_struct.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--hierarchical']) + +test.execute() + +test.file_grep(test.obj_dir + "/VTest/Test.sv", r'^module\s+(\S+)\s+', "Test") + +test.passes() diff --git a/test_regress/t/t_hier_block_trace_fst.pl b/test_regress/t/t_hier_block_trace_fst.pl deleted file mode 100755 index f5e8a33c1..000000000 --- a/test_regress/t/t_hier_block_trace_fst.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--hierarchical', - '--Wno-TIMESCALEMOD', - '--trace-fst', - '--no-trace-underscore', # To avoid handle mismatches - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_trace_fst.py b/test_regress/t/t_hier_block_trace_fst.py new file mode 100755 index 000000000..f6b26d0f5 --- /dev/null +++ b/test_regress/t/t_hier_block_trace_fst.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile( + v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--hierarchical', + '--Wno-TIMESCALEMOD', + '--trace-fst', + '--no-trace-underscore', # To avoid handle mismatches + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_trace_vcd.pl b/test_regress/t/t_hier_block_trace_vcd.pl deleted file mode 100755 index 1dc8b71cf..000000000 --- a/test_regress/t/t_hier_block_trace_vcd.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--hierarchical', - '--Wno-TIMESCALEMOD', - '--trace', - '--no-trace-underscore', # To avoid handle mismatches - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_trace_vcd.py b/test_regress/t/t_hier_block_trace_vcd.py new file mode 100755 index 000000000..8952878f4 --- /dev/null +++ b/test_regress/t/t_hier_block_trace_vcd.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile( + v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--hierarchical', + '--Wno-TIMESCALEMOD', + '--trace', + '--no-trace-underscore', # To avoid handle mismatches + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_type_param.pl b/test_regress/t/t_hier_block_type_param.pl deleted file mode 100755 index 283cb4e4d..000000000 --- a/test_regress/t/t_hier_block_type_param.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--hierarchical'] - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{obj_dir} . "/VTest_1/Test_1.sv", /^module\s+(\S+)\s+/, "Test"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_type_param.py b/test_regress/t/t_hier_block_type_param.py new file mode 100755 index 000000000..96ef0646c --- /dev/null +++ b/test_regress/t/t_hier_block_type_param.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--hierarchical']) + +test.execute() + +test.file_grep(test.obj_dir + "/VTest_1/Test_1.sv", r'^module\s+(\S+)\s+', "Test_1") + +test.passes() diff --git a/test_regress/t/t_hier_block_type_param_multiple.pl b/test_regress/t/t_hier_block_type_param_multiple.pl deleted file mode 100755 index 0d22e8fea..000000000 --- a/test_regress/t/t_hier_block_type_param_multiple.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--hierarchical'] - ); - -execute( - check_finished => 1, - ); -ok(1); -1; diff --git a/test_regress/t/t_hier_block_type_param_multiple.py b/test_regress/t/t_hier_block_type_param_multiple.py new file mode 100755 index 000000000..a5474d2ec --- /dev/null +++ b/test_regress/t/t_hier_block_type_param_multiple.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--hierarchical']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_block_type_param_multiple_instances.pl b/test_regress/t/t_hier_block_type_param_multiple_instances.pl deleted file mode 100755 index 0d22e8fea..000000000 --- a/test_regress/t/t_hier_block_type_param_multiple_instances.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--hierarchical'] - ); - -execute( - check_finished => 1, - ); -ok(1); -1; diff --git a/test_regress/t/t_hier_block_type_param_multiple_instances.py b/test_regress/t/t_hier_block_type_param_multiple_instances.py new file mode 100755 index 000000000..a5474d2ec --- /dev/null +++ b/test_regress/t/t_hier_block_type_param_multiple_instances.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--hierarchical']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_block_type_param_nested.pl b/test_regress/t/t_hier_block_type_param_nested.pl deleted file mode 100755 index c608808f4..000000000 --- a/test_regress/t/t_hier_block_type_param_nested.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--hierarchical'], - ); - -execute( - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_type_param_nested.py b/test_regress/t/t_hier_block_type_param_nested.py new file mode 100755 index 000000000..a5474d2ec --- /dev/null +++ b/test_regress/t/t_hier_block_type_param_nested.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--hierarchical']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_block_type_param_notfound_bad.pl b/test_regress/t/t_hier_block_type_param_notfound_bad.pl deleted file mode 100755 index 253e975ef..000000000 --- a/test_regress/t/t_hier_block_type_param_notfound_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_hier_block_type_param.v"); - -compile ( - verilator_flags2 => ["--hierarchical-params-file", "/does-not-exist"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_type_param_notfound_bad.py b/test_regress/t/t_hier_block_type_param_notfound_bad.py new file mode 100755 index 000000000..7eae3e24a --- /dev/null +++ b/test_regress/t/t_hier_block_type_param_notfound_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_hier_block_type_param.v" + +test.compile(verilator_flags2=["--hierarchical-params-file", "/does-not-exist"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_typedef_param.pl b/test_regress/t/t_hier_block_typedef_param.pl deleted file mode 100755 index 6cf1d198e..000000000 --- a/test_regress/t/t_hier_block_typedef_param.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_typedef_param.v"); - -compile( - verilator_flags2 => ["--hierarchical"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_typedef_param.py b/test_regress/t/t_hier_block_typedef_param.py new file mode 100755 index 000000000..43ec2591b --- /dev/null +++ b/test_regress/t/t_hier_block_typedef_param.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_typedef_param.v" + +test.compile(verilator_flags2=["--hierarchical"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_block_vlt.pl b/test_regress/t/t_hier_block_vlt.pl deleted file mode 100755 index b86c9be41..000000000 --- a/test_regress/t/t_hier_block_vlt.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -scenarios(vlt_all => 1); -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--stats', - '--hierarchical', - '+define+SHOW_TIMESCALE', - '+define+USE_VLT', 't/t_hier_block_vlt.vlt', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"'], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", qr/^\s+timeprecision\s+(\d+)ps;/mi, 1); -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_vlt.py b/test_regress/t/t_hier_block_vlt.py new file mode 100755 index 000000000..0d1643704 --- /dev/null +++ b/test_regress/t/t_hier_block_vlt.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--stats', '--hierarchical', '+define+SHOW_TIMESCALE', '+define+USE_VLT', + 't/t_hier_block_vlt.vlt', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^\s+timeprecision\s+(\d+)ps;', 1) +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_bynum.pl b/test_regress/t/t_hier_bynum.pl deleted file mode 100755 index 4e314adef..000000000 --- a/test_regress/t/t_hier_bynum.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--hierarchical'], - verilator_make_gmake => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_bynum.py b/test_regress/t/t_hier_bynum.py new file mode 100755 index 000000000..c2db19e11 --- /dev/null +++ b/test_regress/t/t_hier_bynum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=['--hierarchical'], + verilator_make_gmake=False) + +test.passes() diff --git a/test_regress/t/t_hier_task.pl b/test_regress/t/t_hier_task.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_hier_task.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_task.py b/test_regress/t/t_hier_task.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_hier_task.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_task.v b/test_regress/t/t_hier_task.v index 42fe3eff2..ec20d1d63 100644 --- a/test_regress/t/t_hier_task.v +++ b/test_regress/t/t_hier_task.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module mod_a; - mod_inner u_inner; - mod_a_mon u_a_mon; + mod_inner u_inner(); + mod_a_mon u_a_mon(); initial begin bit x; diff --git a/test_regress/t/t_hier_trace.pl b/test_regress/t/t_hier_trace.pl deleted file mode 100755 index 64fcc5912..000000000 --- a/test_regress/t/t_hier_trace.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--trace', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', '-F t/t_hier_trace_sub/top.F'], - ); - -execute( - all_run_flags => ['-j 4'], - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_hier_trace.py b/test_regress/t/t_hier_trace.py new file mode 100755 index 000000000..4da2102bc --- /dev/null +++ b/test_regress/t/t_hier_trace.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=[ + '--trace', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', + '-F t/t_hier_trace_sub/top.F' +]) + +test.execute(all_run_flags=['-j 4']) + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_trace_noinl.pl b/test_regress/t/t_hier_trace_noinl.pl deleted file mode 100755 index 77ba5b40c..000000000 --- a/test_regress/t/t_hier_trace_noinl.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_hier_trace.v"); - -compile( - verilator_flags2 => ['--trace', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', '--fno-inline', '-F t/t_hier_trace_sub/top.F'], - ); - -execute( - all_run_flags => ['-j 4'], - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_hier_trace_noinl.py b/test_regress/t/t_hier_trace_noinl.py new file mode 100755 index 000000000..890644b91 --- /dev/null +++ b/test_regress/t/t_hier_trace_noinl.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_hier_trace.v" + +test.compile(verilator_flags2=[ + '--trace', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', + '--fno-inline', '-F t/t_hier_trace_sub/top.F' +]) + +test.execute(all_run_flags=['-j 4']) + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hierarchy_identifier.pl b/test_regress/t/t_hierarchy_identifier.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_hierarchy_identifier.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_hierarchy_identifier.py b/test_regress/t/t_hierarchy_identifier.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_hierarchy_identifier.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hierarchy_identifier_bad.pl b/test_regress/t/t_hierarchy_identifier_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_hierarchy_identifier_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_hierarchy_identifier_bad.py b/test_regress/t/t_hierarchy_identifier_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_hierarchy_identifier_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hierarchy_unnamed.pl b/test_regress/t/t_hierarchy_unnamed.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_hierarchy_unnamed.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_hierarchy_unnamed.py b/test_regress/t/t_hierarchy_unnamed.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_hierarchy_unnamed.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_if_deep.pl b/test_regress/t/t_if_deep.pl deleted file mode 100755 index 7d49cd2cd..000000000 --- a/test_regress/t/t_if_deep.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_if_deep.py b/test_regress/t/t_if_deep.py new file mode 100755 index 000000000..539f320b1 --- /dev/null +++ b/test_regress/t/t_if_deep.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test) + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_if_same_bad.pl b/test_regress/t/t_if_same_bad.pl deleted file mode 100755 index fa67e585c..000000000 --- a/test_regress/t/t_if_same_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 0, # bug3806 - this test should fail but does not - # expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_if_same_bad.py b/test_regress/t/t_if_same_bad.py new file mode 100755 index 000000000..f206d9126 --- /dev/null +++ b/test_regress/t/t_if_same_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # expect_filename = test.golden_filename + fails=False) # bug3806 - this test should fail but does not + +test.passes() diff --git a/test_regress/t/t_if_swap.pl b/test_regress/t/t_if_swap.pl deleted file mode 100755 index da2e37bda..000000000 --- a/test_regress/t/t_if_swap.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_if_swap.py b/test_regress/t/t_if_swap.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_if_swap.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_iff.pl b/test_regress/t/t_iff.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_iff.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_iff.py b/test_regress/t/t_iff.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_iff.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_implements.pl b/test_regress/t/t_implements.pl deleted file mode 100755 index da2e37bda..000000000 --- a/test_regress/t/t_implements.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements.py b/test_regress/t/t_implements.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_implements.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_implements_collision.pl b/test_regress/t/t_implements_collision.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_implements_collision.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_collision.py b/test_regress/t/t_implements_collision.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_implements_collision.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_implements_collision_bad.pl b/test_regress/t/t_implements_collision_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_collision_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_collision_bad.py b/test_regress/t/t_implements_collision_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_collision_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_contents_bad.pl b/test_regress/t/t_implements_contents_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_contents_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_contents_bad.py b/test_regress/t/t_implements_contents_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_contents_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_missing_bad.pl b/test_regress/t/t_implements_missing_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_missing_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_missing_bad.py b/test_regress/t/t_implements_missing_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_missing_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_nested_bad.pl b/test_regress/t/t_implements_nested_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_nested_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_nested_bad.py b/test_regress/t/t_implements_nested_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_nested_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_new_bad.pl b/test_regress/t/t_implements_new_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_new_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_new_bad.py b/test_regress/t/t_implements_new_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_new_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_noinherit_bad.pl b/test_regress/t/t_implements_noinherit_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_noinherit_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_noinherit_bad.py b/test_regress/t/t_implements_noinherit_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_noinherit_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_noninterface_bad.pl b/test_regress/t/t_implements_noninterface_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_noninterface_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_noninterface_bad.py b/test_regress/t/t_implements_noninterface_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_noninterface_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_noninterface_bad.v b/test_regress/t/t_implements_noninterface_bad.v index 95ff76301..51c036928 100644 --- a/test_regress/t/t_implements_noninterface_bad.v +++ b/test_regress/t/t_implements_noninterface_bad.v @@ -17,5 +17,5 @@ class ClsBad2 extends Icls; endclass module t (/*AUTOARG*/); - Cls c; + ClsBad2 c; endmodule diff --git a/test_regress/t/t_implements_notfound_bad.pl b/test_regress/t/t_implements_notfound_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_notfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_notfound_bad.py b/test_regress/t/t_implements_notfound_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_notfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_typed.pl b/test_regress/t/t_implements_typed.pl deleted file mode 100755 index da2e37bda..000000000 --- a/test_regress/t/t_implements_typed.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_typed.py b/test_regress/t/t_implements_typed.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_implements_typed.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_impure_cond_empty_if.pl b/test_regress/t/t_impure_cond_empty_if.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_impure_cond_empty_if.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_impure_cond_empty_if.py b/test_regress/t/t_impure_cond_empty_if.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_impure_cond_empty_if.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inc_relink.pl b/test_regress/t/t_inc_relink.pl deleted file mode 100755 index 92b300018..000000000 --- a/test_regress/t/t_inc_relink.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-WIDTHTRUNC"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_inc_relink.py b/test_regress/t/t_inc_relink.py new file mode 100755 index 000000000..754bdeefc --- /dev/null +++ b/test_regress/t/t_inc_relink.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-WIDTHTRUNC"]) + +test.passes() diff --git a/test_regress/t/t_inc_relink.v b/test_regress/t/t_inc_relink.v index fcaf80289..089f1cf34 100644 --- a/test_regress/t/t_inc_relink.v +++ b/test_regress/t/t_inc_relink.v @@ -28,7 +28,7 @@ module C; // Like above but in a module endmodule module t; // Actually use those to test relinking - C c; + C c(); initial begin A::t(); diff --git a/test_regress/t/t_incorrect_multi_driven.pl b/test_regress/t/t_incorrect_multi_driven.pl deleted file mode 100755 index 0fc71f8e9..000000000 --- a/test_regress/t/t_incorrect_multi_driven.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_incorrect_multi_driven.v"); - -lint( - fails => 0 - ); - -ok(1); -1; diff --git a/test_regress/t/t_incorrect_multi_driven.py b/test_regress/t/t_incorrect_multi_driven.py new file mode 100755 index 000000000..f51428711 --- /dev/null +++ b/test_regress/t/t_incorrect_multi_driven.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 + +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_incorrect_multi_driven.v" + +test.lint(fails=False) + +test.passes() diff --git a/test_regress/t/t_incr_void.pl b/test_regress/t/t_incr_void.pl deleted file mode 100755 index e7d3e18e3..000000000 --- a/test_regress/t/t_incr_void.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--fno-split -x-assign 0"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_incr_void.py b/test_regress/t/t_incr_void.py new file mode 100755 index 000000000..487255781 --- /dev/null +++ b/test_regress/t/t_incr_void.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--fno-split -x-assign 0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_increment_bad.pl b/test_regress/t/t_increment_bad.pl deleted file mode 100755 index 23eda8f99..000000000 --- a/test_regress/t/t_increment_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_increment_bad.py b/test_regress/t/t_increment_bad.py new file mode 100755 index 000000000..07fc79e8e --- /dev/null +++ b/test_regress/t/t_increment_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_infinite_recursion.py b/test_regress/t/t_infinite_recursion.py new file mode 100755 index 000000000..d789a829e --- /dev/null +++ b/test_regress/t/t_infinite_recursion.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--no-unlimited-stack"]) + +test.passes() diff --git a/test_regress/t/t_infinite_recursion.v b/test_regress/t/t_infinite_recursion.v new file mode 100644 index 000000000..9bacc5bd2 --- /dev/null +++ b/test_regress/t/t_infinite_recursion.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +class cls; + task t; t; endtask + task pre_randomize; + t; + endtask +endclass +module t; + cls obj; + task static t; + int _ = obj.randomize() with {1 == 1;}; + endtask +endmodule diff --git a/test_regress/t/t_init_concat.pl b/test_regress/t/t_init_concat.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_init_concat.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_init_concat.py b/test_regress/t/t_init_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_init_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initarray_nonarray.pl b/test_regress/t/t_initarray_nonarray.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_initarray_nonarray.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_initarray_nonarray.py b/test_regress/t/t_initarray_nonarray.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_initarray_nonarray.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_initarray_nonarray.v b/test_regress/t/t_initarray_nonarray.v index 3eb518264..16cb697da 100644 --- a/test_regress/t/t_initarray_nonarray.v +++ b/test_regress/t/t_initarray_nonarray.v @@ -13,11 +13,7 @@ typedef logic [7:0] mask_t [7:0]; parameter mask_t IMP_MASK = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8'h37}; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); mask_t a; //logic [7:0] a[7:0]; diff --git a/test_regress/t/t_initial.pl b/test_regress/t/t_initial.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_initial.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial.py b/test_regress/t/t_initial.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_initial.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initial_assign_sformatf.py b/test_regress/t/t_initial_assign_sformatf.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_initial_assign_sformatf.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initial_assign_sformatf.v b/test_regress/t/t_initial_assign_sformatf.v new file mode 100644 index 000000000..7ff94eaba --- /dev/null +++ b/test_regress/t/t_initial_assign_sformatf.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: SystemVerilog interface test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 + +interface intf(); + + function automatic string get_scope; + string the_scope = $sformatf("%m"); + return the_scope; + endfunction + + initial $display(get_scope()); +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // finish report + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + intf the_intf(); + +endmodule diff --git a/test_regress/t/t_initial_assign_sformatf_debug.py b/test_regress/t/t_initial_assign_sformatf_debug.py new file mode 100755 index 000000000..4679bcd8c --- /dev/null +++ b/test_regress/t/t_initial_assign_sformatf_debug.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_initial_assign_sformatf.v" + +test.compile(verilator_flags2=['--debug']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initial_dlyass.pl b/test_regress/t/t_initial_dlyass.pl deleted file mode 100755 index b15591906..000000000 --- a/test_regress/t/t_initial_dlyass.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wno-INITIALDLY'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial_dlyass.py b/test_regress/t/t_initial_dlyass.py new file mode 100755 index 000000000..49c67d3a1 --- /dev/null +++ b/test_regress/t/t_initial_dlyass.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wno-INITIALDLY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initial_dlyass_bad.pl b/test_regress/t/t_initial_dlyass_bad.pl deleted file mode 100755 index e9702830c..000000000 --- a/test_regress/t/t_initial_dlyass_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_initial_dlyass.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial_dlyass_bad.py b/test_regress/t/t_initial_dlyass_bad.py new file mode 100755 index 000000000..883aebe62 --- /dev/null +++ b/test_regress/t/t_initial_dlyass_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_initial_dlyass.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_initial_edge.pl b/test_regress/t/t_initial_edge.pl deleted file mode 100755 index 3c491f443..000000000 --- a/test_regress/t/t_initial_edge.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--x-initial-edge"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial_edge.py b/test_regress/t/t_initial_edge.py new file mode 100755 index 000000000..989bc8776 --- /dev/null +++ b/test_regress/t/t_initial_edge.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-initial-edge"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initial_edge_bad.pl b/test_regress/t/t_initial_edge_bad.pl deleted file mode 100755 index 8d882c587..000000000 --- a/test_regress/t/t_initial_edge_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# This works with other vlt_alls, we we don't run it for them. It should -# fail with Verilator if --x-initial-edge is not specified. - -scenarios(vlt_all => 1); - -top_filename("t/t_initial_edge.v"); - -compile( - ); - -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial_edge_bad.py b/test_regress/t/t_initial_edge_bad.py new file mode 100755 index 000000000..2182cc77c --- /dev/null +++ b/test_regress/t/t_initial_edge_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# This works with other vlt_alls, we we don't run it for them. It should +# fail with Verilator if --x-initial-edge is not specified. + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_initial_edge.v" + +test.compile() + +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_initialstatic_circ.pl b/test_regress/t/t_initialstatic_circ.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_initialstatic_circ.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_initialstatic_circ.py b/test_regress/t/t_initialstatic_circ.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_initialstatic_circ.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside.pl b/test_regress/t/t_inside.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inside.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside.py b/test_regress/t/t_inside.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inside.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside2.pl b/test_regress/t/t_inside2.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_inside2.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside2.py b/test_regress/t/t_inside2.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_inside2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_inside_assoc_unsup.pl b/test_regress/t/t_inside_assoc_unsup.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_inside_assoc_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside_assoc_unsup.py b/test_regress/t/t_inside_assoc_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inside_assoc_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inside_dyn.pl b/test_regress/t/t_inside_dyn.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_inside_dyn.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside_dyn.py b/test_regress/t/t_inside_dyn.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inside_dyn.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside_nonint.pl b/test_regress/t/t_inside_nonint.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_inside_nonint.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside_nonint.py b/test_regress/t/t_inside_nonint.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inside_nonint.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside_unpacked.pl b/test_regress/t/t_inside_unpacked.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_inside_unpacked.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside_unpacked.py b/test_regress/t/t_inside_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inside_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside_unpacked_param.pl b/test_regress/t/t_inside_unpacked_param.pl deleted file mode 100755 index 40f69d41d..000000000 --- a/test_regress/t/t_inside_unpacked_param.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_inside_unpacked_param.py b/test_regress/t/t_inside_unpacked_param.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_inside_unpacked_param.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_inside_wild.pl b/test_regress/t/t_inside_wild.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inside_wild.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside_wild.py b/test_regress/t/t_inside_wild.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inside_wild.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_2star_bad.pl b/test_regress/t/t_inst_2star_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_inst_2star_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_2star_bad.py b/test_regress/t/t_inst_2star_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_2star_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_array_bad.out b/test_regress/t/t_inst_array_bad.out index 7e9897d64..7e3b4234e 100644 --- a/test_regress/t/t_inst_array_bad.out +++ b/test_regress/t/t_inst_array_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_inst_array_bad.v:19:28: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. (IEEE 1800-2023 23.3.3) +%Error: t/t_inst_array_bad.v:14:28: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. (IEEE 1800-2023 23.3.3) : ... note: In instance 't' - 19 | sub sub [7:0] (allbits, onebitbad, bitout); + 14 | sub sub [7:0] (allbits, onebitbad, bitout); | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_array_bad.pl b/test_regress/t/t_inst_array_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_inst_array_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_bad.py b/test_regress/t/t_inst_array_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_array_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_array_bad.v b/test_regress/t/t_inst_array_bad.v index c0261f9e3..669d2e92d 100644 --- a/test_regress/t/t_inst_array_bad.v +++ b/test_regress/t/t_inst_array_bad.v @@ -4,12 +4,7 @@ // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); wire [7:0] bitout; reg [7:0] allbits; diff --git a/test_regress/t/t_inst_array_connect.pl b/test_regress/t/t_inst_array_connect.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_inst_array_connect.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_connect.py b/test_regress/t/t_inst_array_connect.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_array_connect.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_array_inl0.pl b/test_regress/t/t_inst_array_inl0.pl deleted file mode 100755 index 98f84bb24..000000000 --- a/test_regress/t/t_inst_array_inl0.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_array.v"); - -compile( - v_flags2 => ['+define+NOUSE_INLINE',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_inl0.py b/test_regress/t/t_inst_array_inl0.py new file mode 100755 index 000000000..38c939c11 --- /dev/null +++ b/test_regress/t/t_inst_array_inl0.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_array.v" + +test.compile(v_flags2=['+define+NOUSE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_array_inl1.pl b/test_regress/t/t_inst_array_inl1.pl deleted file mode 100755 index 024282cc4..000000000 --- a/test_regress/t/t_inst_array_inl1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_array.v"); - -compile( - v_flags2 => ['+define+USE_INLINE',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_inl1.py b/test_regress/t/t_inst_array_inl1.py new file mode 100755 index 000000000..588df37a9 --- /dev/null +++ b/test_regress/t/t_inst_array_inl1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_array.v" + +test.compile(v_flags2=['+define+USE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_array_partial.pl b/test_regress/t/t_inst_array_partial.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inst_array_partial.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_partial.py b/test_regress/t/t_inst_array_partial.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_array_partial.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_array_struct.pl b/test_regress/t/t_inst_array_struct.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_inst_array_struct.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_struct.py b/test_regress/t/t_inst_array_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_array_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_ccall.pl b/test_regress/t/t_inst_ccall.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inst_ccall.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_ccall.py b/test_regress/t/t_inst_ccall.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_ccall.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_comma_inl0.pl b/test_regress/t/t_inst_comma_inl0.pl deleted file mode 100755 index 9e566919a..000000000 --- a/test_regress/t/t_inst_comma_inl0.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_comma.v"); - -compile( - v_flags2 => ['+define+NOUSE_INLINE',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_comma_inl0.py b/test_regress/t/t_inst_comma_inl0.py new file mode 100755 index 000000000..03cf930d4 --- /dev/null +++ b/test_regress/t/t_inst_comma_inl0.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_comma.v" + +test.compile(v_flags2=['+define+NOUSE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_comma_inl1.pl b/test_regress/t/t_inst_comma_inl1.pl deleted file mode 100755 index a083d104c..000000000 --- a/test_regress/t/t_inst_comma_inl1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_comma.v"); - -compile( - v_flags2 => ['+define+USE_INLINE',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_comma_inl1.py b/test_regress/t/t_inst_comma_inl1.py new file mode 100755 index 000000000..02a41e5a1 --- /dev/null +++ b/test_regress/t/t_inst_comma_inl1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_comma.v" + +test.compile(v_flags2=['+define+USE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_darray.pl b/test_regress/t/t_inst_darray.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inst_darray.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_darray.py b/test_regress/t/t_inst_darray.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_darray.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dearray_slice.pl b/test_regress/t/t_inst_dearray_slice.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_inst_dearray_slice.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dearray_slice.py b/test_regress/t/t_inst_dearray_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_dearray_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dff.pl b/test_regress/t/t_inst_dff.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_inst_dff.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dff.py b/test_regress/t/t_inst_dff.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_dff.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inla.pl b/test_regress/t/t_inst_dtree_inla.pl deleted file mode 100755 index 01bccbe35..000000000 --- a/test_regress/t/t_inst_dtree_inla.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_A'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inla.py b/test_regress/t/t_inst_dtree_inla.py new file mode 100755 index 000000000..0c74e5b29 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inla.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_A'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlab.pl b/test_regress/t/t_inst_dtree_inlab.pl deleted file mode 100755 index b12d4ee12..000000000 --- a/test_regress/t/t_inst_dtree_inlab.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_B'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlab.py b/test_regress/t/t_inst_dtree_inlab.py new file mode 100755 index 000000000..2e47b5491 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlab.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_B'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlac.pl b/test_regress/t/t_inst_dtree_inlac.pl deleted file mode 100755 index 717db06d6..000000000 --- a/test_regress/t/t_inst_dtree_inlac.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlac.py b/test_regress/t/t_inst_dtree_inlac.py new file mode 100755 index 000000000..af4e087f5 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlac.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlad.pl b/test_regress/t/t_inst_dtree_inlad.pl deleted file mode 100755 index 49cf78d93..000000000 --- a/test_regress/t/t_inst_dtree_inlad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlad.py b/test_regress/t/t_inst_dtree_inlad.py new file mode 100755 index 000000000..f8d8a945a --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlb.pl b/test_regress/t/t_inst_dtree_inlb.pl deleted file mode 100755 index 5db311cbc..000000000 --- a/test_regress/t/t_inst_dtree_inlb.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_B'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlb.py b/test_regress/t/t_inst_dtree_inlb.py new file mode 100755 index 000000000..ff392eb7a --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlb.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_B'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlbc.pl b/test_regress/t/t_inst_dtree_inlbc.pl deleted file mode 100755 index 935883d92..000000000 --- a/test_regress/t/t_inst_dtree_inlbc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_B +define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlbc.py b/test_regress/t/t_inst_dtree_inlbc.py new file mode 100755 index 000000000..2bf440d42 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlbc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_B +define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlbd.pl b/test_regress/t/t_inst_dtree_inlbd.pl deleted file mode 100755 index 381918f5c..000000000 --- a/test_regress/t/t_inst_dtree_inlbd.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_B +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlbd.py b/test_regress/t/t_inst_dtree_inlbd.py new file mode 100755 index 000000000..9b9abcd5c --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlbd.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_B +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlc.pl b/test_regress/t/t_inst_dtree_inlc.pl deleted file mode 100755 index f86b44eef..000000000 --- a/test_regress/t/t_inst_dtree_inlc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlc.py b/test_regress/t/t_inst_dtree_inlc.py new file mode 100755 index 000000000..3310eff69 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlcd.pl b/test_regress/t/t_inst_dtree_inlcd.pl deleted file mode 100755 index 67ad049e5..000000000 --- a/test_regress/t/t_inst_dtree_inlcd.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_C +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlcd.py b/test_regress/t/t_inst_dtree_inlcd.py new file mode 100755 index 000000000..2ba7663b0 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlcd.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_C +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inld.pl b/test_regress/t/t_inst_dtree_inld.pl deleted file mode 100755 index f61782a04..000000000 --- a/test_regress/t/t_inst_dtree_inld.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inld.py b/test_regress/t/t_inst_dtree_inld.py new file mode 100755 index 000000000..304292305 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inld.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_first.pl b/test_regress/t/t_inst_first.pl deleted file mode 100755 index 987de13d5..000000000 --- a/test_regress/t/t_inst_first.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => [$Self->wno_unopthreads_for_few_cores()] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_first.py b/test_regress/t/t_inst_first.py new file mode 100755 index 000000000..a06492309 --- /dev/null +++ b/test_regress/t/t_inst_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=[test.wno_unopthreads_for_few_cores]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_implicit.pl b/test_regress/t/t_inst_implicit.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inst_implicit.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_implicit.py b/test_regress/t/t_inst_implicit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_implicit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_long.pl b/test_regress/t/t_inst_long.pl deleted file mode 100755 index 425516114..000000000 --- a/test_regress/t/t_inst_long.pl +++ /dev/null @@ -1,58 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(vlt => 1); - -my $length = 200; -my $long = "long_" x (($length + 4) / 5); - -sub gen_top { - my $filename = shift; - - my $fh = IO::File->new(">$filename") - or $Self->error("Can't write $filename"); - $fh->print("// Generated by t_inst_long.pl\n"); - $fh->print("module t;\n"); - $fh->print("\n"); - $fh->print(" ${long} inst ();\n"); - $fh->print("\n"); - $fh->print("endmodule\n"); - $fh->close; -} - -sub gen_sub { - my $filename = shift; - - my $fh = IO::File->new(">$filename") - or $Self->error("Can't write $filename"); - $fh->print("// Generated by t_inst_long.pl\n"); - $fh->print("module ${long};\n"); - $fh->print("\n"); - $fh->print(" initial begin\n"); - $fh->print(" \$write(\"*-* All Finished *-*\\n\");\n"); - $fh->print(" \$finish;\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); - $fh->close; -} - -top_filename("$Self->{obj_dir}/t_inst_long.v", $long); - -gen_top($Self->{top_filename}); -gen_sub("$Self->{obj_dir}/${long}.v"); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_inst_long.py b/test_regress/t/t_inst_long.py new file mode 100755 index 000000000..a34888c88 --- /dev/null +++ b/test_regress/t/t_inst_long.py @@ -0,0 +1,46 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = os.path.join(test.obj_dir, "t_inst_long.v") + +length = 200 +longname = "long_" * int((length + 4) / 5) + + +def gen_top(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_inst_long.py\n") + fh.write("module t;\n") + fh.write("\n") + fh.write(" " + longname + " inst ();\n") + fh.write("\n") + fh.write("endmodule\n") + + +def gen_sub(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_inst_long.py\n") + fh.write("module " + longname + ";\n") + fh.write("\n") + fh.write(" initial begin\n") + fh.write(" $write(\"*-* All Finished *-*\\n\");\n") + fh.write(" $finish;\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen_top(test.top_filename) +gen_sub(os.path.join(test.obj_dir, longname + ".v")) + +test.compile() + +test.passes() diff --git a/test_regress/t/t_inst_long_bad.pl b/test_regress/t/t_inst_long_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_inst_long_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_long_bad.py b/test_regress/t/t_inst_long_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_long_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_misarray2_bad.pl b/test_regress/t/t_inst_misarray2_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_inst_misarray2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_misarray2_bad.py b/test_regress/t/t_inst_misarray2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_misarray2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_misarray_bad.pl b/test_regress/t/t_inst_misarray_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_inst_misarray_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_misarray_bad.py b/test_regress/t/t_inst_misarray_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_misarray_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_mism.pl b/test_regress/t/t_inst_mism.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inst_mism.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_mism.py b/test_regress/t/t_inst_mism.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_mism.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_missing.pl b/test_regress/t/t_inst_missing.pl deleted file mode 100755 index 47e83b415..000000000 --- a/test_regress/t/t_inst_missing.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --Wall -Wno-DECLFILENAME"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_missing.py b/test_regress/t/t_inst_missing.py new file mode 100755 index 000000000..eed023f4a --- /dev/null +++ b/test_regress/t/t_inst_missing.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --Wall -Wno-DECLFILENAME"]) + +test.passes() diff --git a/test_regress/t/t_inst_missing_bad.pl b/test_regress/t/t_inst_missing_bad.pl deleted file mode 100755 index ebce1e9f0..000000000 --- a/test_regress/t/t_inst_missing_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_missing_bad.py b/test_regress/t/t_inst_missing_bad.py new file mode 100755 index 000000000..af59f8be9 --- /dev/null +++ b/test_regress/t/t_inst_missing_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_missing_dot_bad.pl b/test_regress/t/t_inst_missing_dot_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_inst_missing_dot_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_missing_dot_bad.py b/test_regress/t/t_inst_missing_dot_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_missing_dot_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_mnpipe.pl b/test_regress/t/t_inst_mnpipe.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_inst_mnpipe.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_mnpipe.py b/test_regress/t/t_inst_mnpipe.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_mnpipe.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_name_long.pl b/test_regress/t/t_inst_name_long.pl deleted file mode 100755 index b65c35c81..000000000 --- a/test_regress/t/t_inst_name_long.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_inst_name_long.py b/test_regress/t/t_inst_name_long.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_inst_name_long.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_inst_noname_bad.pl b/test_regress/t/t_inst_noname_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_inst_noname_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_noname_bad.py b/test_regress/t/t_inst_noname_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_noname_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_notunsized.pl b/test_regress/t/t_inst_notunsized.pl deleted file mode 100755 index fa437f2fe..000000000 --- a/test_regress/t/t_inst_notunsized.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-IMPLICIT"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_notunsized.py b/test_regress/t/t_inst_notunsized.py new file mode 100755 index 000000000..46c86aaf4 --- /dev/null +++ b/test_regress/t/t_inst_notunsized.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-IMPLICIT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_overwide.pl b/test_regress/t/t_inst_overwide.pl deleted file mode 100755 index 741f0f044..000000000 --- a/test_regress/t/t_inst_overwide.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => [qw(-sc -Wno-WIDTH)], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -#No execute() - -ok(1); -1; diff --git a/test_regress/t/t_inst_overwide.py b/test_regress/t/t_inst_overwide.py new file mode 100755 index 000000000..9acf5a62b --- /dev/null +++ b/test_regress/t/t_inst_overwide.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-sc -Wno-WIDTH"], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_overwide_bad.pl b/test_regress/t/t_inst_overwide_bad.pl deleted file mode 100755 index 9bb70c819..000000000 --- a/test_regress/t/t_inst_overwide_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_inst_overwide.v"); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_overwide_bad.py b/test_regress/t/t_inst_overwide_bad.py new file mode 100755 index 000000000..3133e885c --- /dev/null +++ b/test_regress/t/t_inst_overwide_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_inst_overwide.v" + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_param_comma_bad.pl b/test_regress/t/t_inst_param_comma_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_inst_param_comma_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_param_comma_bad.py b/test_regress/t/t_inst_param_comma_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_param_comma_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_param_override_bad.pl b/test_regress/t/t_inst_param_override_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_inst_param_override_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_param_override_bad.py b/test_regress/t/t_inst_param_override_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_param_override_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_paren_bad.out b/test_regress/t/t_inst_paren_bad.out new file mode 100644 index 000000000..e19bc13b5 --- /dev/null +++ b/test_regress/t/t_inst_paren_bad.out @@ -0,0 +1,5 @@ +%Error: t/t_inst_paren_bad.v:11:8: Instantiation 'sub_inst' requires parenthesis (IEEE 1800-2023 23.3.2) + : ... Suggest use 'sub_inst()' + 11 | sub sub_inst; + | ^~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_inst_paren_bad.py b/test_regress/t/t_inst_paren_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_paren_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_paren_bad.v b/test_regress/t/t_inst_paren_bad.v new file mode 100644 index 000000000..c7f6c7775 --- /dev/null +++ b/test_regress/t/t_inst_paren_bad.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module sub; +endmodule + +module t(/*AUTOARG*/); + sub sub_inst; // No () +endmodule diff --git a/test_regress/t/t_inst_pin_place_bad.pl b/test_regress/t/t_inst_pin_place_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_inst_pin_place_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_pin_place_bad.py b/test_regress/t/t_inst_pin_place_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_pin_place_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_pin_realnreal.pl b/test_regress/t/t_inst_pin_realnreal.pl deleted file mode 100755 index 40f69d41d..000000000 --- a/test_regress/t/t_inst_pin_realnreal.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_inst_pin_realnreal.py b/test_regress/t/t_inst_pin_realnreal.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_inst_pin_realnreal.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_port_array.pl b/test_regress/t/t_inst_port_array.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inst_port_array.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_port_array.py b/test_regress/t/t_inst_port_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_port_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_prepost.pl b/test_regress/t/t_inst_prepost.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_inst_prepost.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_prepost.py b/test_regress/t/t_inst_prepost.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_inst_prepost.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_inst_recurse2_bad.out b/test_regress/t/t_inst_recurse2_bad.out index 024193f31..1bbb101cb 100644 --- a/test_regress/t/t_inst_recurse2_bad.out +++ b/test_regress/t/t_inst_recurse2_bad.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_inst_recurse2_bad.v:18:8: Unsupported: Identically recursive module (module instantiates itself, without changing parameters): 'looped' - : ... note: In instance 't.looped.looped' - 18 | module looped ( ); +%Error-UNSUPPORTED: t/t_inst_recurse2_bad.v:13:8: Unsupported: Identically recursive module (module instantiates itself, without changing parameters): 'looped' + : ... note: In instance 't.looped.looped.looped' + 13 | module looped ( ); | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_inst_recurse2_bad.pl b/test_regress/t/t_inst_recurse2_bad.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_inst_recurse2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_recurse2_bad.py b/test_regress/t/t_inst_recurse2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_recurse2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_recurse2_bad.v b/test_regress/t/t_inst_recurse2_bad.v index 2cba45e12..08713ef5d 100644 --- a/test_regress/t/t_inst_recurse2_bad.v +++ b/test_regress/t/t_inst_recurse2_bad.v @@ -4,12 +4,7 @@ // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); looped looped (); diff --git a/test_regress/t/t_inst_recurse_bad.out b/test_regress/t/t_inst_recurse_bad.out index eb83d4b29..43e9442f1 100644 --- a/test_regress/t/t_inst_recurse_bad.out +++ b/test_regress/t/t_inst_recurse_bad.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_inst_recurse_bad.v:18:8: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): 'looped' +%Error-UNSUPPORTED: t/t_inst_recurse_bad.v:13:8: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): 'looped' : ... note: self-recursion (module instantiating itself directly) is supported. - 18 | module looped ( ); + 13 | module looped ( ); | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_inst_recurse_bad.pl b/test_regress/t/t_inst_recurse_bad.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_inst_recurse_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_recurse_bad.py b/test_regress/t/t_inst_recurse_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_recurse_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_recurse_bad.v b/test_regress/t/t_inst_recurse_bad.v index 9a1048fa2..b525e8902 100644 --- a/test_regress/t/t_inst_recurse_bad.v +++ b/test_regress/t/t_inst_recurse_bad.v @@ -4,12 +4,7 @@ // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); looped looped (); diff --git a/test_regress/t/t_inst_signed.pl b/test_regress/t/t_inst_signed.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inst_signed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_signed.py b/test_regress/t/t_inst_signed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_signed1.pl b/test_regress/t/t_inst_signed1.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inst_signed1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_signed1.py b/test_regress/t/t_inst_signed1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_signed1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_slice.pl b/test_regress/t/t_inst_slice.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inst_slice.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_slice.py b/test_regress/t/t_inst_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_slice_noinl.pl b/test_regress/t/t_inst_slice_noinl.pl deleted file mode 100755 index aa56e6155..000000000 --- a/test_regress/t/t_inst_slice_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_slice.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_slice_noinl.py b/test_regress/t/t_inst_slice_noinl.py new file mode 100755 index 000000000..bd7bcdff5 --- /dev/null +++ b/test_regress/t/t_inst_slice_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_slice.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_slice_part_select.pl b/test_regress/t/t_inst_slice_part_select.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_inst_slice_part_select.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_slice_part_select.py b/test_regress/t/t_inst_slice_part_select.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_slice_part_select.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_sv.pl b/test_regress/t/t_inst_sv.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_inst_sv.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_sv.py b/test_regress/t/t_inst_sv.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_sv.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_tree_inl0_pub0.pl b/test_regress/t/t_inst_tree_inl0_pub0.pl deleted file mode 100755 index 51465fca4..000000000 --- a/test_regress/t/t_inst_tree_inl0_pub0.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_tree.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "$Self->{t_dir}/$Self->{name}.vlt"], -); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"MODULE","name":"l1",.*"loc":"f,56:[^"]*",.*"origName":"l1"/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"l2",.*"loc":"f,62:[^"]*",.*"origName":"l2"/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"l3",.*"loc":"f,69:[^"]*",.*"origName":"l3"/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"l4",.*"loc":"f,76:[^"]*",.*"origName":"l4"/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"l5__P1",.*"loc":"f,83:[^"]*",.*"origName":"l5"/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"l5__P2",.*"loc":"f,83:[^"]*",.*"origName":"l5"/); -} - -execute( - check_finished => 1, - expect => -'\] (%m|.*t\.ps): Clocked -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_tree_inl0_pub0.py b/test_regress/t/t_inst_tree_inl0_pub0.py new file mode 100755 index 000000000..25514c89e --- /dev/null +++ b/test_regress/t/t_inst_tree_inl0_pub0.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_tree.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", test.t_dir + "/" + test.name + ".vlt"]) + +if test.vlt_all: + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l1",.*"loc":"f,56:[^"]*",.*"origName":"l1"') + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l2",.*"loc":"f,62:[^"]*",.*"origName":"l2"') + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l3",.*"loc":"f,69:[^"]*",.*"origName":"l3"') + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l4",.*"loc":"f,76:[^"]*",.*"origName":"l4"') + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l5__P1",.*"loc":"f,83:[^"]*",.*"origName":"l5"') + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l5__P2",.*"loc":"f,83:[^"]*",.*"origName":"l5"') + +test.execute() +test.file_grep(test.run_log_filename, r"\] (%m|.*t\.ps): Clocked") + +test.passes() diff --git a/test_regress/t/t_inst_tree_inl0_pub1.pl b/test_regress/t/t_inst_tree_inl0_pub1.pl deleted file mode 100755 index 5979621aa..000000000 --- a/test_regress/t/t_inst_tree_inl0_pub1.pl +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_tree.v"); - -my $default_vltmt_threads = $Self->get_default_vltmt_threads(); -compile( - verilator_flags2 => ['--stats', "$Self->{t_dir}/$Self->{name}.vlt"], - # Force 3 threads even if we have fewer cores - threads => $Self->{vltmt} ? $default_vltmt_threads : 1 - ); - -sub checkRelativeRefs { - my ($mod, $expect_relative) = @_; - my $found_relative = 0; - - foreach my $file (glob_all("$Self->{obj_dir}/V$Self->{name}_${mod}*.cpp")) { - my $text = file_contents($file); - - if ($text =~ m/this->/ || $text =~ m/vlSelf->/) { - $found_relative = 1; - } - - if ($found_relative != $expect_relative) { - error("$file " - . ($found_relative ? "has" : "does not have") - . " relative variable references."); - } - } -} - -if ($Self->{vlt_all}) { - # We expect to combine sequent functions across multiple instances of - # l2, l3, l4, l5. If this number drops, please confirm this has not broken. - file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, - ($Self->{vltmt} ? 85 : 67)); - - # Everything should use relative references - checkRelativeRefs("t", 1); - checkRelativeRefs("l1", 1); - checkRelativeRefs("l2", 1); - checkRelativeRefs("l3", 1); - checkRelativeRefs("l4", 1); - checkRelativeRefs("l5__P1", 1); - checkRelativeRefs("l5__P2", 1); -} - -execute( - check_finished => 1, - expect => -'\] (%m|.*t\.ps): Clocked -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_tree_inl0_pub1.py b/test_regress/t/t_inst_tree_inl0_pub1.py new file mode 100755 index 000000000..3fa932f0e --- /dev/null +++ b/test_regress/t/t_inst_tree_inl0_pub1.py @@ -0,0 +1,59 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_tree.v" + +default_vltmt_threads = test.get_default_vltmt_threads +test.compile( + verilator_flags2=['--stats', test.t_dir + "/" + test.name + ".vlt"], + # Force 3 threads even if we have fewer cores + threads=(default_vltmt_threads if test.vltmt else 1)) + + +def check_relative_refs(mod, expect_relative): + found_relative = False + for filename in test.glob_some(test.obj_dir + "/V" + test.name + "_" + mod + "*.cpp"): + if test.verbose: + print("FILE " + filename) + text = test.file_contents(filename) + + if re.search(r'this->', text) or re.search(r'vlSelf->', text): + if test.verbose: + print(" REL " + filename) + found_relative = True + + if found_relative != expect_relative: + test.error(filename + " " + + ("has 'relative'" if found_relative else "has 'non-relative'") + + " variable references but expected " + + ("'relative'" if expect_relative else "'non-relative'")) + + +if test.vlt_all: + # We expect to combine sequent functions across multiple instances of + # l2, l3, l4, l5. If this number drops, please confirm this has not broken. + test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', + (85 if test.vltmt else 67)) + + # Everything should use relative references + check_relative_refs("t", True) + check_relative_refs("l1", True) + check_relative_refs("l2", True) + check_relative_refs("l3", True) + check_relative_refs("l4", True) + check_relative_refs("l5__P1", True) + check_relative_refs("l5__P2", True) + +test.execute() +test.file_grep(test.run_log_filename, r"\] (%m|.*t\.ps): Clocked") + +test.passes() diff --git a/test_regress/t/t_inst_tree_inl1_pub0.pl b/test_regress/t/t_inst_tree_inl1_pub0.pl deleted file mode 100755 index 74309894b..000000000 --- a/test_regress/t/t_inst_tree_inl1_pub0.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_tree.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "-fno-dfg-post-inline", "$Self->{t_dir}/t_inst_tree_inl1_pub0.vlt"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"t.u.u0.u0.z1",.*"loc":"f,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.u.u0.u1.z1",.*"loc":"f,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.u.u1.u0.z0",.*"loc":"f,70:[^"]*",.*"origName":"z0",.*"dtypeName":"logic"/); -} - -execute( - check_finished => 1, - expect => -'\] (%m|.*t\.ps): Clocked -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_tree_inl1_pub0.py b/test_regress/t/t_inst_tree_inl1_pub0.py new file mode 100755 index 000000000..c3ddf6de9 --- /dev/null +++ b/test_regress/t/t_inst_tree_inl1_pub0.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_tree.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=[ + "--no-json-edit-nums", "-fno-dfg-post-inline", test.t_dir + "/t_inst_tree_inl1_pub0.vlt" +]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.u.u0.u0.z1",.*"loc":"f,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.u.u0.u1.z1",.*"loc":"f,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.u.u1.u0.z0",.*"loc":"f,70:[^"]*",.*"origName":"z0",.*"dtypeName":"logic"' + ) + +test.execute() +test.file_grep(test.run_log_filename, r"\] (%m|.*t\.ps): Clocked") + +test.passes() diff --git a/test_regress/t/t_inst_tree_inl1_pub1.pl b/test_regress/t/t_inst_tree_inl1_pub1.pl deleted file mode 100755 index 23ec04b64..000000000 --- a/test_regress/t/t_inst_tree_inl1_pub1.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_tree.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "-fno-dfg-post-inline", "t/$Self->{name}.vlt", - $Self->wno_unopthreads_for_few_cores()] - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"u.u0.u0.z0",.*"loc":"f,70:[^"]*",.*"origName":"z0",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true.*"isSigUserRWPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"u.u0.u0.u0.u0.z1",.*"loc":"f,85:[^"]*",.*"origName":"z1",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"u.u0.u1.u0.u0.z",.*"loc":"f,83:[^"]*",.*"origName":"z",.*,"isSigPublic":true,.*dtypeName":"logic",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); -} - -execute( - check_finished => 1, - expect => -'\] (%m|.*t\.ps): Clocked -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_tree_inl1_pub1.py b/test_regress/t/t_inst_tree_inl1_pub1.py new file mode 100755 index 000000000..0a61713b5 --- /dev/null +++ b/test_regress/t/t_inst_tree_inl1_pub1.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_tree.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=[ + "--no-json-edit-nums", "-fno-dfg-post-inline", "t/" + test.name + + ".vlt", test.wno_unopthreads_for_few_cores +]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"u.u0.u0.z0",.*"loc":"f,70:[^"]*",.*"origName":"z0",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true.*"isSigUserRWPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"u.u0.u0.u0.u0.z1",.*"loc":"f,85:[^"]*",.*"origName":"z1",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"u.u0.u1.u0.u0.z",.*"loc":"f,83:[^"]*",.*"origName":"z",.*,"isSigPublic":true,.*dtypeName":"logic",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + +test.execute() +test.file_grep(test.run_log_filename, r"\] (%m|.*t\.ps): Clocked") + +test.passes() diff --git a/test_regress/t/t_inst_v2k.pl b/test_regress/t/t_inst_v2k.pl deleted file mode 100755 index 377bc93b2..000000000 --- a/test_regress/t/t_inst_v2k.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['+libext+.vi+.extranoneed'], - nc => 0, # Error: Multiple +libext flags found - vcs => 0, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_v2k.py b/test_regress/t/t_inst_v2k.py new file mode 100755 index 000000000..a791c097a --- /dev/null +++ b/test_regress/t/t_inst_v2k.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + v_flags2=['+libext+.vi+.extranoneed'], + nc=False, # Error: Multiple +libext flags found + vcs=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_wideconst.pl b/test_regress/t/t_inst_wideconst.pl deleted file mode 100755 index 83fe0eda2..000000000 --- a/test_regress/t/t_inst_wideconst.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-public'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_wideconst.py b/test_regress/t/t_inst_wideconst.py new file mode 100755 index 000000000..54297fbe0 --- /dev/null +++ b/test_regress/t/t_inst_wideconst.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-public']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interconnect.pl b/test_regress/t/t_interconnect.pl deleted file mode 100755 index 7cb28e364..000000000 --- a/test_regress/t/t_interconnect.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interconnect.py b/test_regress/t/t_interconnect.py new file mode 100755 index 000000000..186787928 --- /dev/null +++ b/test_regress/t/t_interconnect.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interconnect_bad.pl b/test_regress/t/t_interconnect_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interconnect_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interconnect_bad.py b/test_regress/t/t_interconnect_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interconnect_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface.pl b/test_regress/t/t_interface.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_interface.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface.py b/test_regress/t/t_interface.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1.pl b/test_regress/t/t_interface1.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1.py b/test_regress/t/t_interface1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1_modport.pl b/test_regress/t/t_interface1_modport.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface1_modport.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1_modport.py b/test_regress/t/t_interface1_modport.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface1_modport.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1_modport_nansi.pl b/test_regress/t/t_interface1_modport_nansi.pl deleted file mode 100755 index 3f71acf60..000000000 --- a/test_regress/t/t_interface1_modport_nansi.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface1_modport.v"); - -compile( - v_flags2 => ['+define+NANSI'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1_modport_nansi.py b/test_regress/t/t_interface1_modport_nansi.py new file mode 100755 index 000000000..83abc3d48 --- /dev/null +++ b/test_regress/t/t_interface1_modport_nansi.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface1_modport.v" + +test.compile(v_flags2=['+define+NANSI']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1_modport_noinl.pl b/test_regress/t/t_interface1_modport_noinl.pl deleted file mode 100755 index 4f4b314ae..000000000 --- a/test_regress/t/t_interface1_modport_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface1_modport.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1_modport_noinl.py b/test_regress/t/t_interface1_modport_noinl.py new file mode 100755 index 000000000..39ec887e7 --- /dev/null +++ b/test_regress/t/t_interface1_modport_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface1_modport.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1_modport_trace.pl b/test_regress/t/t_interface1_modport_trace.pl deleted file mode 100755 index cb728321b..000000000 --- a/test_regress/t/t_interface1_modport_trace.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface1_modport.v"); - -compile( - verilator_flags2 => ['--trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1_modport_trace.py b/test_regress/t/t_interface1_modport_trace.py new file mode 100755 index 000000000..c16b2aa0e --- /dev/null +++ b/test_regress/t/t_interface1_modport_trace.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface1_modport.v" + +test.compile(verilator_flags2=['--trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1_noinl.pl b/test_regress/t/t_interface1_noinl.pl deleted file mode 100755 index 867b1e993..000000000 --- a/test_regress/t/t_interface1_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface1.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1_noinl.py b/test_regress/t/t_interface1_noinl.py new file mode 100755 index 000000000..f38117e8e --- /dev/null +++ b/test_regress/t/t_interface1_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface1.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface2.pl b/test_regress/t/t_interface2.pl deleted file mode 100755 index c2f17b6ac..000000000 --- a/test_regress/t/t_interface2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--top-module t"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface2.py b/test_regress/t/t_interface2.py new file mode 100755 index 000000000..fd9bd7244 --- /dev/null +++ b/test_regress/t/t_interface2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--top-module t"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface2_noinl.pl b/test_regress/t/t_interface2_noinl.pl deleted file mode 100755 index cad1b6e3d..000000000 --- a/test_regress/t/t_interface2_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface2.v"); - -compile( - verilator_flags2 => ["--top-module t -fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface2_noinl.py b/test_regress/t/t_interface2_noinl.py new file mode 100755 index 000000000..b231b4c73 --- /dev/null +++ b/test_regress/t/t_interface2_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface2.v" + +test.compile(verilator_flags2=["--top-module t -fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_ar2a.pl b/test_regress/t/t_interface_ar2a.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_interface_ar2a.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ar2a.py b/test_regress/t/t_interface_ar2a.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_interface_ar2a.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_interface_ar2b.pl b/test_regress/t/t_interface_ar2b.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_interface_ar2b.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ar2b.py b/test_regress/t/t_interface_ar2b.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_interface_ar2b.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_interface_ar3.pl b/test_regress/t/t_interface_ar3.pl deleted file mode 100755 index 8d48ddb75..000000000 --- a/test_regress/t/t_interface_ar3.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, # Verilator unsupported, bug546 - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_interface_ar3.py b/test_regress/t/t_interface_ar3.py new file mode 100755 index 000000000..b0a6b1891 --- /dev/null +++ b/test_regress/t/t_interface_ar3.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + fails=test.vlt_all, # Verilator unsupported, bug546 + expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array.pl b/test_regress/t/t_interface_array.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_interface_array.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array.py b/test_regress/t/t_interface_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array2.pl b/test_regress/t/t_interface_array2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_interface_array2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array2.py b/test_regress/t/t_interface_array2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_array2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array2_coverage.pl b/test_regress/t/t_interface_array2_coverage.pl deleted file mode 100755 index 184f7f8bb..000000000 --- a/test_regress/t/t_interface_array2_coverage.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_array2.v"); - -compile( - v_flags2 => ["--coverage"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array2_coverage.py b/test_regress/t/t_interface_array2_coverage.py new file mode 100755 index 000000000..4b8df9ff0 --- /dev/null +++ b/test_regress/t/t_interface_array2_coverage.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_array2.v" + +test.compile(v_flags2=["--coverage"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array2_noinl.pl b/test_regress/t/t_interface_array2_noinl.pl deleted file mode 100755 index 7bf1518f5..000000000 --- a/test_regress/t/t_interface_array2_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_array2.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array2_noinl.py b/test_regress/t/t_interface_array2_noinl.py new file mode 100755 index 000000000..2c6d02725 --- /dev/null +++ b/test_regress/t/t_interface_array2_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_array2.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array_bad.pl b/test_regress/t/t_interface_array_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_array_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array_bad.py b/test_regress/t/t_interface_array_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_array_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_array_modport.pl b/test_regress/t/t_interface_array_modport.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_interface_array_modport.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array_modport.py b/test_regress/t/t_interface_array_modport.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_array_modport.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array_nocolon.pl b/test_regress/t/t_interface_array_nocolon.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_interface_array_nocolon.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array_nocolon.py b/test_regress/t/t_interface_array_nocolon.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_array_nocolon.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array_nocolon_bad.pl b/test_regress/t/t_interface_array_nocolon_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_interface_array_nocolon_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array_nocolon_bad.py b/test_regress/t/t_interface_array_nocolon_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_interface_array_nocolon_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_array_noinl.pl b/test_regress/t/t_interface_array_noinl.pl deleted file mode 100755 index df71f77e9..000000000 --- a/test_regress/t/t_interface_array_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_array.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array_noinl.py b/test_regress/t/t_interface_array_noinl.py new file mode 100755 index 000000000..e4b1e7a2d --- /dev/null +++ b/test_regress/t/t_interface_array_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_array.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_arraymux.pl b/test_regress/t/t_interface_arraymux.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_interface_arraymux.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_interface_arraymux.py b/test_regress/t/t_interface_arraymux.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_interface_arraymux.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_interface_asvar_bad.pl b/test_regress/t/t_interface_asvar_bad.pl deleted file mode 100755 index df9afd1d4..000000000 --- a/test_regress/t/t_interface_asvar_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_asvar_bad.py b/test_regress/t/t_interface_asvar_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_asvar_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_bind_public.pl b/test_regress/t/t_interface_bind_public.pl deleted file mode 100755 index 83fe0eda2..000000000 --- a/test_regress/t/t_interface_bind_public.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-public'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_bind_public.py b/test_regress/t/t_interface_bind_public.py new file mode 100755 index 000000000..54297fbe0 --- /dev/null +++ b/test_regress/t/t_interface_bind_public.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-public']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_derived_type.py b/test_regress/t/t_interface_derived_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_derived_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_derived_type.v b/test_regress/t/t_interface_derived_type.v new file mode 100644 index 000000000..cee8559bc --- /dev/null +++ b/test_regress/t/t_interface_derived_type.v @@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: SystemVerilog interface test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 + +interface intf #( + parameter type data_t = bit, + parameter int arr[2][4] +) (); + data_t data; + // TODO -- some kind of issue with multi-dimensional array constness: + // %Error: t/t_interface_derived_type.v:12:12: Expecting expression to be constant, but variable isn't const: 'arr' + // : ... note: In instance 't.sub16' + // 19 | logic [arr[0][0]-1:0] other_data; + // | ^~~ + // `define SHOW_2D_BUG + `ifdef SHOW_2D_BUG + logic [arr[0][0]-1:0] other_data; + `else + logic [$bits(data)-1:0] other_data; + `endif +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // finish report + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); + sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 (); + +endmodule + +module sub #( + parameter int width, + parameter int arr[2][4] +) (); + typedef struct packed { + logic [3:3] [0:0] [width-1:0] field; + } user_type_t; + + intf #( + .data_t(user_type_t), + .arr(arr) + ) the_intf (); + + logic [width-1:0] signal; + + always_comb begin + the_intf.data.field = signal; + the_intf.other_data = signal; + end +endmodule diff --git a/test_regress/t/t_interface_down.pl b/test_regress/t/t_interface_down.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_down.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down.py b/test_regress/t/t_interface_down.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_down.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inla.pl b/test_regress/t/t_interface_down_inla.pl deleted file mode 100755 index 9a06eafa5..000000000 --- a/test_regress/t/t_interface_down_inla.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_A'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inla.py b/test_regress/t/t_interface_down_inla.py new file mode 100755 index 000000000..1782f7d1b --- /dev/null +++ b/test_regress/t/t_interface_down_inla.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_A'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlab.pl b/test_regress/t/t_interface_down_inlab.pl deleted file mode 100755 index 9ea954b1b..000000000 --- a/test_regress/t/t_interface_down_inlab.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_B'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlab.py b/test_regress/t/t_interface_down_inlab.py new file mode 100755 index 000000000..d65a7085d --- /dev/null +++ b/test_regress/t/t_interface_down_inlab.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_B'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlac.pl b/test_regress/t/t_interface_down_inlac.pl deleted file mode 100755 index 4ca7f2496..000000000 --- a/test_regress/t/t_interface_down_inlac.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlac.py b/test_regress/t/t_interface_down_inlac.py new file mode 100755 index 000000000..6cc094f25 --- /dev/null +++ b/test_regress/t/t_interface_down_inlac.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlad.pl b/test_regress/t/t_interface_down_inlad.pl deleted file mode 100755 index 0071e1864..000000000 --- a/test_regress/t/t_interface_down_inlad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlad.py b/test_regress/t/t_interface_down_inlad.py new file mode 100755 index 000000000..d7d413259 --- /dev/null +++ b/test_regress/t/t_interface_down_inlad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlb.pl b/test_regress/t/t_interface_down_inlb.pl deleted file mode 100755 index ef94ea94f..000000000 --- a/test_regress/t/t_interface_down_inlb.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_B'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlb.py b/test_regress/t/t_interface_down_inlb.py new file mode 100755 index 000000000..daf398a11 --- /dev/null +++ b/test_regress/t/t_interface_down_inlb.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_B'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlbc.pl b/test_regress/t/t_interface_down_inlbc.pl deleted file mode 100755 index a2a12be41..000000000 --- a/test_regress/t/t_interface_down_inlbc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_B +define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlbc.py b/test_regress/t/t_interface_down_inlbc.py new file mode 100755 index 000000000..5a4620498 --- /dev/null +++ b/test_regress/t/t_interface_down_inlbc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_B +define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlbd.pl b/test_regress/t/t_interface_down_inlbd.pl deleted file mode 100755 index 609238c88..000000000 --- a/test_regress/t/t_interface_down_inlbd.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_B +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlbd.py b/test_regress/t/t_interface_down_inlbd.py new file mode 100755 index 000000000..7b3bdf8c9 --- /dev/null +++ b/test_regress/t/t_interface_down_inlbd.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_B +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlc.pl b/test_regress/t/t_interface_down_inlc.pl deleted file mode 100755 index d7f77f2c9..000000000 --- a/test_regress/t/t_interface_down_inlc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlc.py b/test_regress/t/t_interface_down_inlc.py new file mode 100755 index 000000000..f0d83ee04 --- /dev/null +++ b/test_regress/t/t_interface_down_inlc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlcd.pl b/test_regress/t/t_interface_down_inlcd.pl deleted file mode 100755 index 22d785305..000000000 --- a/test_regress/t/t_interface_down_inlcd.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_C +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlcd.py b/test_regress/t/t_interface_down_inlcd.py new file mode 100755 index 000000000..bc2c3a4ff --- /dev/null +++ b/test_regress/t/t_interface_down_inlcd.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_C +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inld.pl b/test_regress/t/t_interface_down_inld.pl deleted file mode 100755 index b484ee157..000000000 --- a/test_regress/t/t_interface_down_inld.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inld.py b/test_regress/t/t_interface_down_inld.py new file mode 100755 index 000000000..aa706ba17 --- /dev/null +++ b/test_regress/t/t_interface_down_inld.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_noinl.pl b/test_regress/t/t_interface_down_noinl.pl deleted file mode 100755 index 34ce5cb69..000000000 --- a/test_regress/t/t_interface_down_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_noinl.py b/test_regress/t/t_interface_down_noinl.py new file mode 100755 index 000000000..d1aa7ab2b --- /dev/null +++ b/test_regress/t/t_interface_down_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_dups.pl b/test_regress/t/t_interface_dups.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_dups.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_dups.py b/test_regress/t/t_interface_dups.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_dups.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen.pl b/test_regress/t/t_interface_gen.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen.py b/test_regress/t/t_interface_gen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen.v b/test_regress/t/t_interface_gen.v index 6c7b88b66..e4dbedad5 100644 --- a/test_regress/t/t_interface_gen.v +++ b/test_regress/t/t_interface_gen.v @@ -6,13 +6,6 @@ // Very simple test for interface pathclearing -`ifdef VCS - `define UNSUPPORTED_MOD_IN_GENS -`endif -`ifdef VERILATOR - `define UNSUPPORTED_MOD_IN_GENS -`endif - module t (/*AUTOARG*/ // Inputs clk @@ -51,38 +44,22 @@ module sub input integer i_value ); -`ifdef UNSUPPORTED_MOD_IN_GENS always @* isub.value = i_value; -`else - generate if (MODE == 1) begin - always @* isub.valuea = i_value; - end - else if (MODE == 2) begin - always @* isub.valueb = i_value; - end - endgenerate -`endif endmodule interface ifc; parameter MODE = 0; // Modports under generates not supported by all commercial simulators -`ifdef UNSUPPORTED_MOD_IN_GENS + integer value; modport out_modport (output value); function integer get_value(); return value; endfunction -`else - generate if (MODE == 0) begin - integer valuea; - modport out_modport (output valuea); - function integer get_valuea(); return valuea; endfunction - end - else begin - integer valueb; - modport out_modport (output valueb); - function integer get_valueb(); return valueb; endfunction - end - endgenerate -`endif + + // IEEE 1800-2017 deprecated alowing modports inside generates + // generate if (MODE == 0) begin + // integer valuea; + // modport out_modport (output valuea); + // function integer get_valuea(); return valuea; endfunction + // end endinterface diff --git a/test_regress/t/t_interface_gen10.pl b/test_regress/t/t_interface_gen10.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen10.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen10.py b/test_regress/t/t_interface_gen10.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen10.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen10_noinl.pl b/test_regress/t/t_interface_gen10_noinl.pl deleted file mode 100755 index f691c6d0a..000000000 --- a/test_regress/t/t_interface_gen10_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen10.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen10_noinl.py b/test_regress/t/t_interface_gen10_noinl.py new file mode 100755 index 000000000..b75c3971f --- /dev/null +++ b/test_regress/t/t_interface_gen10_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen10.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen11.pl b/test_regress/t/t_interface_gen11.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen11.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen11.py b/test_regress/t/t_interface_gen11.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen11.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen11_noinl.pl b/test_regress/t/t_interface_gen11_noinl.pl deleted file mode 100755 index d1e7dd3c0..000000000 --- a/test_regress/t/t_interface_gen11_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen11.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen11_noinl.py b/test_regress/t/t_interface_gen11_noinl.py new file mode 100755 index 000000000..0c8f41ceb --- /dev/null +++ b/test_regress/t/t_interface_gen11_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen11.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen12.pl b/test_regress/t/t_interface_gen12.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen12.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen12.py b/test_regress/t/t_interface_gen12.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen12.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen12_noinl.pl b/test_regress/t/t_interface_gen12_noinl.pl deleted file mode 100755 index 8ebecd448..000000000 --- a/test_regress/t/t_interface_gen12_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen12.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen12_noinl.py b/test_regress/t/t_interface_gen12_noinl.py new file mode 100755 index 000000000..343c709d0 --- /dev/null +++ b/test_regress/t/t_interface_gen12_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen12.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen13.pl b/test_regress/t/t_interface_gen13.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen13.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen13.py b/test_regress/t/t_interface_gen13.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen13.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen2.pl b/test_regress/t/t_interface_gen2.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen2.py b/test_regress/t/t_interface_gen2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen2_collision.pl b/test_regress/t/t_interface_gen2_collision.pl deleted file mode 100755 index 93d1979f9..000000000 --- a/test_regress/t/t_interface_gen2_collision.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen2.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen2_collision.py b/test_regress/t/t_interface_gen2_collision.py new file mode 100755 index 000000000..132e5efc8 --- /dev/null +++ b/test_regress/t/t_interface_gen2_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen2.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen2_noinl.pl b/test_regress/t/t_interface_gen2_noinl.pl deleted file mode 100755 index eb772bab6..000000000 --- a/test_regress/t/t_interface_gen2_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen2.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen2_noinl.py b/test_regress/t/t_interface_gen2_noinl.py new file mode 100755 index 000000000..a58e9c947 --- /dev/null +++ b/test_regress/t/t_interface_gen2_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen2.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen3.pl b/test_regress/t/t_interface_gen3.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen3.py b/test_regress/t/t_interface_gen3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen3_collision.pl b/test_regress/t/t_interface_gen3_collision.pl deleted file mode 100755 index 9a52345e3..000000000 --- a/test_regress/t/t_interface_gen3_collision.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen3.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen3_collision.py b/test_regress/t/t_interface_gen3_collision.py new file mode 100755 index 000000000..90c0230e2 --- /dev/null +++ b/test_regress/t/t_interface_gen3_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen3.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen3_noinl.pl b/test_regress/t/t_interface_gen3_noinl.pl deleted file mode 100755 index b63c72eb9..000000000 --- a/test_regress/t/t_interface_gen3_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen3.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen3_noinl.py b/test_regress/t/t_interface_gen3_noinl.py new file mode 100755 index 000000000..a3c907564 --- /dev/null +++ b/test_regress/t/t_interface_gen3_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen3.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen4.pl b/test_regress/t/t_interface_gen4.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen4.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen4.py b/test_regress/t/t_interface_gen4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen4_noinl.pl b/test_regress/t/t_interface_gen4_noinl.pl deleted file mode 100755 index e724c2859..000000000 --- a/test_regress/t/t_interface_gen4_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen4.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen4_noinl.py b/test_regress/t/t_interface_gen4_noinl.py new file mode 100755 index 000000000..4309bc821 --- /dev/null +++ b/test_regress/t/t_interface_gen4_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen4.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen5.pl b/test_regress/t/t_interface_gen5.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen5.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen5.py b/test_regress/t/t_interface_gen5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen5_noinl.pl b/test_regress/t/t_interface_gen5_noinl.pl deleted file mode 100755 index 5b4852691..000000000 --- a/test_regress/t/t_interface_gen5_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen5.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen5_noinl.py b/test_regress/t/t_interface_gen5_noinl.py new file mode 100755 index 000000000..6408c8ce9 --- /dev/null +++ b/test_regress/t/t_interface_gen5_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen5.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen6.pl b/test_regress/t/t_interface_gen6.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen6.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen6.py b/test_regress/t/t_interface_gen6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen6_noinl.pl b/test_regress/t/t_interface_gen6_noinl.pl deleted file mode 100755 index e43d9460a..000000000 --- a/test_regress/t/t_interface_gen6_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen6.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen6_noinl.py b/test_regress/t/t_interface_gen6_noinl.py new file mode 100755 index 000000000..1130f060e --- /dev/null +++ b/test_regress/t/t_interface_gen6_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen6.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen7.pl b/test_regress/t/t_interface_gen7.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen7.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen7.py b/test_regress/t/t_interface_gen7.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen7_noinl.pl b/test_regress/t/t_interface_gen7_noinl.pl deleted file mode 100755 index 458c5f0f6..000000000 --- a/test_regress/t/t_interface_gen7_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen7.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen7_noinl.py b/test_regress/t/t_interface_gen7_noinl.py new file mode 100755 index 000000000..5f3047e6d --- /dev/null +++ b/test_regress/t/t_interface_gen7_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen7.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen8.pl b/test_regress/t/t_interface_gen8.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen8.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen8.py b/test_regress/t/t_interface_gen8.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen8.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen8_noinl.pl b/test_regress/t/t_interface_gen8_noinl.pl deleted file mode 100755 index 644d9a10e..000000000 --- a/test_regress/t/t_interface_gen8_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen8.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen8_noinl.py b/test_regress/t/t_interface_gen8_noinl.py new file mode 100755 index 000000000..a436079e9 --- /dev/null +++ b/test_regress/t/t_interface_gen8_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen8.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen9.pl b/test_regress/t/t_interface_gen9.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_gen9.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen9.py b/test_regress/t/t_interface_gen9.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen9.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen9_noinl.pl b/test_regress/t/t_interface_gen9_noinl.pl deleted file mode 100755 index 6ac0d6296..000000000 --- a/test_regress/t/t_interface_gen9_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen9.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen9_noinl.py b/test_regress/t/t_interface_gen9_noinl.py new file mode 100755 index 000000000..a4c47ac50 --- /dev/null +++ b/test_regress/t/t_interface_gen9_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen9.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen_noinl.pl b/test_regress/t/t_interface_gen_noinl.pl deleted file mode 100755 index 17273106f..000000000 --- a/test_regress/t/t_interface_gen_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen_noinl.py b/test_regress/t/t_interface_gen_noinl.py new file mode 100755 index 000000000..510c52a8b --- /dev/null +++ b/test_regress/t/t_interface_gen_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_import_param.pl b/test_regress/t/t_interface_import_param.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_interface_import_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_import_param.py b/test_regress/t/t_interface_import_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_import_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_inl.pl b/test_regress/t/t_interface_inl.pl deleted file mode 100755 index 08dfa385c..000000000 --- a/test_regress/t/t_interface_inl.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface.v"); - -compile( - # Avoid inlining so we find bugs in the non-inliner connection code - verilator_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_inl.py b/test_regress/t/t_interface_inl.py new file mode 100755 index 000000000..e5a851161 --- /dev/null +++ b/test_regress/t/t_interface_inl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface.v" + +test.compile( + # Avoid inlining so we find bugs in the non-inliner connection code + verilator_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_localparam.pl b/test_regress/t/t_interface_localparam.pl deleted file mode 100755 index 762975c8b..000000000 --- a/test_regress/t/t_interface_localparam.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, -); - -ok(1); -1; diff --git a/test_regress/t/t_interface_localparam.py b/test_regress/t/t_interface_localparam.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_localparam.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_mismodport_bad.out b/test_regress/t/t_interface_mismodport_bad.out index a46bee788..ae7743b8b 100644 --- a/test_regress/t/t_interface_mismodport_bad.out +++ b/test_regress/t/t_interface_mismodport_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_interface_mismodport_bad.v:36:12: Can't find definition of 'bad' in dotted signal: 'isub.bad' - 36 | isub.bad = i_value; +%Error: t/t_interface_mismodport_bad.v:32:12: Can't find definition of 'bad' in dotted signal: 'isub.bad' + 32 | isub.bad = i_value; | ^~~ ... Known scopes under 'bad': %Error: Exiting due to diff --git a/test_regress/t/t_interface_mismodport_bad.pl b/test_regress/t/t_interface_mismodport_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_mismodport_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_mismodport_bad.py b/test_regress/t/t_interface_mismodport_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_mismodport_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_mismodport_bad.v b/test_regress/t/t_interface_mismodport_bad.v index 1b5f656fc..0b45e53d8 100644 --- a/test_regress/t/t_interface_mismodport_bad.v +++ b/test_regress/t/t_interface_mismodport_bad.v @@ -10,12 +10,8 @@ interface ifc; modport out_modport (output ok); endinterface -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t (/*AUTOARG*/); - input clk; integer cyc=1; ifc itop(); diff --git a/test_regress/t/t_interface_missing_bad.pl b/test_regress/t/t_interface_missing_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_missing_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_missing_bad.py b/test_regress/t/t_interface_missing_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_missing_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_modport.pl b/test_regress/t/t_interface_modport.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_modport.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport.py b/test_regress/t/t_interface_modport.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_modport.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_bad.pl b/test_regress/t/t_interface_modport_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_modport_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_bad.py b/test_regress/t/t_interface_modport_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_modport_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_modport_coverage.pl b/test_regress/t/t_interface_modport_coverage.pl deleted file mode 100755 index 2b42c5830..000000000 --- a/test_regress/t/t_interface_modport_coverage.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_modport.v"); - -compile( - verilator_flags2 => ["-fno-inline --coverage"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_coverage.py b/test_regress/t/t_interface_modport_coverage.py new file mode 100755 index 000000000..76d179c19 --- /dev/null +++ b/test_regress/t/t_interface_modport_coverage.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport.v" + +test.compile(verilator_flags2=["-fno-inline --coverage"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_dir_bad.pl b/test_regress/t/t_interface_modport_dir_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_interface_modport_dir_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_dir_bad.py b/test_regress/t/t_interface_modport_dir_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_modport_dir_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_modport_export.pl b/test_regress/t/t_interface_modport_export.pl deleted file mode 100755 index be66c40e6..000000000 --- a/test_regress/t/t_interface_modport_export.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_export.py b/test_regress/t/t_interface_modport_export.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_interface_modport_export.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_import.pl b/test_regress/t/t_interface_modport_import.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_interface_modport_import.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_import.py b/test_regress/t/t_interface_modport_import.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_modport_import.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_import_export_list.pl b/test_regress/t/t_interface_modport_import_export_list.pl deleted file mode 100755 index c74d44be5..000000000 --- a/test_regress/t/t_interface_modport_import_export_list.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_import_export_list.py b/test_regress/t/t_interface_modport_import_export_list.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_interface_modport_import_export_list.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_interface_modport_import_noinl.pl b/test_regress/t/t_interface_modport_import_noinl.pl deleted file mode 100755 index a9e97bee1..000000000 --- a/test_regress/t/t_interface_modport_import_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_modport_import.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_import_noinl.py b/test_regress/t/t_interface_modport_import_noinl.py new file mode 100755 index 000000000..799af8f28 --- /dev/null +++ b/test_regress/t/t_interface_modport_import_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport_import.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_inl.pl b/test_regress/t/t_interface_modport_inl.pl deleted file mode 100755 index eb2ca2181..000000000 --- a/test_regress/t/t_interface_modport_inl.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_modport.v"); - -compile( - # Avoid inlining so we find bugs in the non-inliner connection code - verilator_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_inl.py b/test_regress/t/t_interface_modport_inl.py new file mode 100755 index 000000000..06444df8c --- /dev/null +++ b/test_regress/t/t_interface_modport_inl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport.v" + +test.compile( + # Avoid inlining so we find bugs in the non-inliner connection code + verilator_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_noinl.pl b/test_regress/t/t_interface_modport_noinl.pl deleted file mode 100755 index 7f1015d23..000000000 --- a/test_regress/t/t_interface_modport_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_modport.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_noinl.py b/test_regress/t/t_interface_modport_noinl.py new file mode 100755 index 000000000..cd95c2a08 --- /dev/null +++ b/test_regress/t/t_interface_modport_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modportlist.pl b/test_regress/t/t_interface_modportlist.pl deleted file mode 100755 index 78cb97ce0..000000000 --- a/test_regress/t/t_interface_modportlist.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modportlist.py b/test_regress/t/t_interface_modportlist.py new file mode 100755 index 000000000..69ecdb152 --- /dev/null +++ b/test_regress/t/t_interface_modportlist.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_make_gmake=False, make_top_shell=False, make_main=False) + +test.passes() diff --git a/test_regress/t/t_interface_mp_func.pl b/test_regress/t/t_interface_mp_func.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_interface_mp_func.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_mp_func.py b/test_regress/t/t_interface_mp_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_mp_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_mp_func_noinl.pl b/test_regress/t/t_interface_mp_func_noinl.pl deleted file mode 100755 index 89f4835b5..000000000 --- a/test_regress/t/t_interface_mp_func_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_mp_func.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_mp_func_noinl.py b/test_regress/t/t_interface_mp_func_noinl.py new file mode 100755 index 000000000..eaddfaae9 --- /dev/null +++ b/test_regress/t/t_interface_mp_func_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_mp_func.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_nansi.pl b/test_regress/t/t_interface_nansi.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_nansi.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_nansi.py b/test_regress/t/t_interface_nansi.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_nansi.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_nest.pl b/test_regress/t/t_interface_nest.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_interface_nest.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_nest.py b/test_regress/t/t_interface_nest.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_nest.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_nest_noinl.pl b/test_regress/t/t_interface_nest_noinl.pl deleted file mode 100755 index e042d33c1..000000000 --- a/test_regress/t/t_interface_nest_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_nest.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_nest_noinl.py b/test_regress/t/t_interface_nest_noinl.py new file mode 100755 index 000000000..bd3c559ac --- /dev/null +++ b/test_regress/t/t_interface_nest_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_nest.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_noinl.pl b/test_regress/t/t_interface_noinl.pl deleted file mode 100755 index 7be6235ad..000000000 --- a/test_regress/t/t_interface_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_noinl.py b/test_regress/t/t_interface_noinl.py new file mode 100755 index 000000000..626af0d7c --- /dev/null +++ b/test_regress/t/t_interface_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_param1.pl b/test_regress/t/t_interface_param1.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_interface_param1.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_interface_param1.py b/test_regress/t/t_interface_param1.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_interface_param1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_interface_param2.pl b/test_regress/t/t_interface_param2.pl deleted file mode 100755 index b5f2e4dd2..000000000 --- a/test_regress/t/t_interface_param2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Verilator unsupported, bug1104 - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_interface_param2.py b/test_regress/t/t_interface_param2.py new file mode 100755 index 000000000..fb4c87343 --- /dev/null +++ b/test_regress/t/t_interface_param2.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # Verilator unsupported, bug1104 + fails=test.vlt_all, + expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_param_acc_bits.pl b/test_regress/t/t_interface_param_acc_bits.pl deleted file mode 100755 index 1c9cd303c..000000000 --- a/test_regress/t/t_interface_param_acc_bits.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, # Unsupported bug1523 - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_param_acc_bits.py b/test_regress/t/t_interface_param_acc_bits.py new file mode 100755 index 000000000..ac60e9122 --- /dev/null +++ b/test_regress/t/t_interface_param_acc_bits.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + fails=test.vlt_all, # Unsupported bug1523 + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_param_another_bad.pl b/test_regress/t/t_interface_param_another_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_param_another_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_param_another_bad.py b/test_regress/t/t_interface_param_another_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_param_another_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_param_genblk.pl b/test_regress/t/t_interface_param_genblk.pl deleted file mode 100755 index d1ed9a923..000000000 --- a/test_regress/t/t_interface_param_genblk.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_param_genblk.py b/test_regress/t/t_interface_param_genblk.py new file mode 100755 index 000000000..ccec64024 --- /dev/null +++ b/test_regress/t/t_interface_param_genblk.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_param_loop_bad.pl b/test_regress/t/t_interface_param_loop_bad.pl deleted file mode 100755 index 485e44130..000000000 --- a/test_regress/t/t_interface_param_loop_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - # Should fail, Verilator unsupported, bug1626"); - fails => !$Self->{vlt}, - # expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_param_loop_bad.py b/test_regress/t/t_interface_param_loop_bad.py new file mode 100755 index 000000000..564f2a1d8 --- /dev/null +++ b/test_regress/t/t_interface_param_loop_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + # Should fail, Verilator unsupported, bug1626 + # expect_filename = test.golden_filename, + fails=not test.vlt) + +test.passes() diff --git a/test_regress/t/t_interface_parameter_access.pl b/test_regress/t/t_interface_parameter_access.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_interface_parameter_access.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_parameter_access.py b/test_regress/t/t_interface_parameter_access.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_parameter_access.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_paren_missing_bad.out b/test_regress/t/t_interface_paren_missing_bad.out index 161dad3fc..70a167b83 100644 --- a/test_regress/t/t_interface_paren_missing_bad.out +++ b/test_regress/t/t_interface_paren_missing_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_interface_paren_missing_bad.v:13:9: Interface instantiation 'intf_i' requires parenthesis +%Error: t/t_interface_paren_missing_bad.v:13:9: Instantiation 'intf_i' requires parenthesis (IEEE 1800-2023 23.3.2) : ... Suggest use 'intf_i()' 13 | intf intf_i; | ^~~~~~ diff --git a/test_regress/t/t_interface_paren_missing_bad.pl b/test_regress/t/t_interface_paren_missing_bad.pl deleted file mode 100755 index b564041ff..000000000 --- a/test_regress/t/t_interface_paren_missing_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_paren_missing_bad.py b/test_regress/t/t_interface_paren_missing_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_interface_paren_missing_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_parent_scope_bad.pl b/test_regress/t/t_interface_parent_scope_bad.pl deleted file mode 100755 index 2d88dbd1b..000000000 --- a/test_regress/t/t_interface_parent_scope_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - # Should fail, Verilator unsupported, bug1623 - fails => !$Self->{vlt}, - # expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_parent_scope_bad.py b/test_regress/t/t_interface_parent_scope_bad.py new file mode 100755 index 000000000..96a59e345 --- /dev/null +++ b/test_regress/t/t_interface_parent_scope_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + # Should fail, Verilator unsupported, bug1623 + # expect_filename = test.golden_filename, + fails=not test.vlt) + +test.passes() diff --git a/test_regress/t/t_interface_parent_scope_bad.v b/test_regress/t/t_interface_parent_scope_bad.v index b8b17f7a8..029f7e6cd 100644 --- a/test_regress/t/t_interface_parent_scope_bad.v +++ b/test_regress/t/t_interface_parent_scope_bad.v @@ -17,12 +17,7 @@ module Baz(); Bar bar(); endmodule -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); Baz baz(); diff --git a/test_regress/t/t_interface_ref_trace.pl b/test_regress/t/t_interface_ref_trace.pl deleted file mode 100755 index 8d5e2c07a..000000000 --- a/test_regress/t/t_interface_ref_trace.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--trace-structs --trace'], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace.py b/test_regress/t/t_interface_ref_trace.py new file mode 100755 index 000000000..b62c5c728 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--trace-structs --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_fst.pl b/test_regress/t/t_interface_ref_trace_fst.pl deleted file mode 100755 index 69b5cc2a3..000000000 --- a/test_regress/t/t_interface_ref_trace_fst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); - -compile( - verilator_flags2 => ['--trace-structs --trace-fst'], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_fst.py b/test_regress/t/t_interface_ref_trace_fst.py new file mode 100755 index 000000000..fef2fad52 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" + +test.compile(verilator_flags2=['--trace-structs --trace-fst']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.pl b/test_regress/t/t_interface_ref_trace_fst_sc.pl deleted file mode 100755 index 4f2137308..000000000 --- a/test_regress/t/t_interface_ref_trace_fst_sc.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_interface_ref_trace.v"); - - compile( - verilator_flags2 => ['--trace-structs --trace-fst --sc'], - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.py b/test_regress/t/t_interface_ref_trace_fst_sc.py new file mode 100755 index 000000000..a45926d74 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_fst_sc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--trace-structs --trace-fst --sc']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_inla.pl b/test_regress/t/t_interface_ref_trace_inla.pl deleted file mode 100755 index 60ba35eb9..000000000 --- a/test_regress/t/t_interface_ref_trace_inla.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); -golden_filename("t/t_interface_ref_trace.out"); - -compile( - v_flags2 => ['+define+NO_INLINE_A'], - verilator_flags2 => ['--trace-structs --trace'], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_inla.py b/test_regress/t/t_interface_ref_trace_inla.py new file mode 100755 index 000000000..cef0f6ce1 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_inla.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" +test.golden_filename = "t/t_interface_ref_trace.out" + +test.compile(v_flags2=['+define+NO_INLINE_A'], verilator_flags2=['--trace-structs --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_inlab.pl b/test_regress/t/t_interface_ref_trace_inlab.pl deleted file mode 100755 index 68d5d7a0e..000000000 --- a/test_regress/t/t_interface_ref_trace_inlab.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); -golden_filename("t/t_interface_ref_trace.out"); - -compile( - v_flags2 => ['+define+NO_INLINE_A +define+NO_INLINE_B'], - verilator_flags2 => ['--trace-structs --trace'], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_inlab.py b/test_regress/t/t_interface_ref_trace_inlab.py new file mode 100755 index 000000000..b0eece321 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_inlab.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" +test.golden_filename = "t/t_interface_ref_trace.out" + +test.compile(v_flags2=['+define+NO_INLINE_A +define+NO_INLINE_B'], + verilator_flags2=['--trace-structs --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_inlb.pl b/test_regress/t/t_interface_ref_trace_inlb.pl deleted file mode 100755 index 10e5c5036..000000000 --- a/test_regress/t/t_interface_ref_trace_inlb.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); -golden_filename("t/t_interface_ref_trace.out"); - -compile( - v_flags2 => ['+define+NO_INLINE_B'], - verilator_flags2 => ['--trace-structs --trace'], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_inlb.py b/test_regress/t/t_interface_ref_trace_inlb.py new file mode 100755 index 000000000..946cc2ece --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_inlb.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" +test.golden_filename = "t/t_interface_ref_trace.out" + +test.compile(v_flags2=['+define+NO_INLINE_B'], verilator_flags2=['--trace-structs --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_noinl.pl b/test_regress/t/t_interface_ref_trace_noinl.pl deleted file mode 100755 index 5a6d2ef82..000000000 --- a/test_regress/t/t_interface_ref_trace_noinl.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); -# Should be the same as the inlined version, but might have declarations -# in a different order. Sadly vcddiff can't check equivalence -# golden_filename("t/t_interface_ref_trace.out"); - -compile( - verilator_flags2 => ['-fno-inline --trace-structs --trace'], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_noinl.py b/test_regress/t/t_interface_ref_trace_noinl.py new file mode 100755 index 000000000..aff9b32b8 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_noinl.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" +# Should be the same as the inlined version, but might have declarations +# in a different order. Sadly vcddiff can't check equivalence +# test.golden_filename = "t/t_interface_ref_trace.out" + +test.compile(verilator_flags2=['-fno-inline --trace-structs --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_noinl_notrace.pl b/test_regress/t/t_interface_ref_trace_noinl_notrace.pl deleted file mode 100755 index b41a3654b..000000000 --- a/test_regress/t/t_interface_ref_trace_noinl_notrace.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); - -compile( - verilator_flags2 => ['-fno-inline'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_noinl_notrace.py b/test_regress/t/t_interface_ref_trace_noinl_notrace.py new file mode 100755 index 000000000..d646cb61b --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_noinl_notrace.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" + +test.compile(verilator_flags2=['-fno-inline']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_size_bad.pl b/test_regress/t/t_interface_size_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_size_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_size_bad.py b/test_regress/t/t_interface_size_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_size_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_star.pl b/test_regress/t/t_interface_star.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_star.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_star.py b/test_regress/t/t_interface_star.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_star.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_top_bad.pl b/test_regress/t/t_interface_top_bad.pl deleted file mode 100755 index 8eda3a219..000000000 --- a/test_regress/t/t_interface_top_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_top_bad.py b/test_regress/t/t_interface_top_bad.py new file mode 100755 index 000000000..3def97587 --- /dev/null +++ b/test_regress/t/t_interface_top_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_twod.pl b/test_regress/t/t_interface_twod.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_interface_twod.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_twod.py b/test_regress/t/t_interface_twod.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_twod.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_twod_noinl.pl b/test_regress/t/t_interface_twod_noinl.pl deleted file mode 100755 index e77089cb0..000000000 --- a/test_regress/t/t_interface_twod_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_twod.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_twod_noinl.py b/test_regress/t/t_interface_twod_noinl.py new file mode 100755 index 000000000..2c5b11cf0 --- /dev/null +++ b/test_regress/t/t_interface_twod_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_twod.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_typedef.pl b/test_regress/t/t_interface_typedef.pl deleted file mode 100755 index 3a6c0a6d3..000000000 --- a/test_regress/t/t_interface_typedef.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_interface_typedef.py b/test_regress/t/t_interface_typedef.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_interface_typedef.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_typo_bad.out b/test_regress/t/t_interface_typo_bad.out index 3f80ecf61..f2efc97e3 100644 --- a/test_regress/t/t_interface_typo_bad.out +++ b/test_regress/t/t_interface_typo_bad.out @@ -2,7 +2,7 @@ 14 | foo_intf foo | ^~~~~~~~ %Error: t/t_interface_typo_bad.v:22:4: Cannot find file containing interface: 'fo_intf' - 22 | fo_intf the_foo; + 22 | fo_intf the_foo(); | ^~~~~~~ %Error: t/t_interface_typo_bad.v:27:15: Found definition of 'the_foo' as a CELL but expected a variable 27 | .foo (the_foo) diff --git a/test_regress/t/t_interface_typo_bad.pl b/test_regress/t/t_interface_typo_bad.pl deleted file mode 100755 index e30ce1ac9..000000000 --- a/test_regress/t/t_interface_typo_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. - # However we no longer gate optimize this - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_typo_bad.py b/test_regress/t/t_interface_typo_bad.py new file mode 100755 index 000000000..9047bac40 --- /dev/null +++ b/test_regress/t/t_interface_typo_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + fails=True, + # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. + # However we no longer gate optimize this + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_typo_bad.v b/test_regress/t/t_interface_typo_bad.v index f684ba85c..542715b91 100644 --- a/test_regress/t/t_interface_typo_bad.v +++ b/test_regress/t/t_interface_typo_bad.v @@ -19,7 +19,7 @@ endmodule module t (/*AUTOARG*/); // Intentional typo, compiler should point this out, or that fo_intf does // not match foo_intf on the submod port map - fo_intf the_foo; + fo_intf the_foo(); submod submod_inst diff --git a/test_regress/t/t_interface_virtual.pl b/test_regress/t/t_interface_virtual.pl deleted file mode 100755 index 6247bd126..000000000 --- a/test_regress/t/t_interface_virtual.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual.py b/test_regress/t/t_interface_virtual.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_interface_virtual.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_bad.pl b/test_regress/t/t_interface_virtual_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_interface_virtual_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_bad.py b/test_regress/t/t_interface_virtual_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_virtual_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_controlflow.pl b/test_regress/t/t_interface_virtual_controlflow.pl deleted file mode 100755 index 3b4aae630..000000000 --- a/test_regress/t/t_interface_virtual_controlflow.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-fno-reorder"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_controlflow.py b/test_regress/t/t_interface_virtual_controlflow.py new file mode 100755 index 000000000..7aedd7b28 --- /dev/null +++ b/test_regress/t/t_interface_virtual_controlflow.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-fno-reorder"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_inl.pl b/test_regress/t/t_interface_virtual_inl.pl deleted file mode 100755 index b342b7b3a..000000000 --- a/test_regress/t/t_interface_virtual_inl.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_virtual.v"); -golden_filename("t/t_interface_virtual.out"); - -compile( - # Avoid inlining so we find bugs in the non-inliner connection code - verilator_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_inl.py b/test_regress/t/t_interface_virtual_inl.py new file mode 100755 index 000000000..0276a9140 --- /dev/null +++ b/test_regress/t/t_interface_virtual_inl.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_virtual.v" +test.golden_filename = "t/t_interface_virtual.out" + +test.compile( + # Avoid inlining so we find bugs in the non-inliner connection code + verilator_flags2=["-fno-inline"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_opt.pl b/test_regress/t/t_interface_virtual_opt.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_interface_virtual_opt.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_opt.py b/test_regress/t/t_interface_virtual_opt.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_virtual_opt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_virtual_param.pl b/test_regress/t/t_interface_virtual_param.pl deleted file mode 100755 index f45fe82b3..000000000 --- a/test_regress/t/t_interface_virtual_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_param.py b/test_regress/t/t_interface_virtual_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_virtual_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_virtual_sched_act.pl b/test_regress/t/t_interface_virtual_sched_act.pl deleted file mode 100755 index 6247bd126..000000000 --- a/test_regress/t/t_interface_virtual_sched_act.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_sched_act.py b/test_regress/t/t_interface_virtual_sched_act.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_act.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_sched_ico.pl b/test_regress/t/t_interface_virtual_sched_ico.pl deleted file mode 100755 index 1f4f8b7ca..000000000 --- a/test_regress/t/t_interface_virtual_sched_ico.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_main => 0, - v_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_sched_ico.py b/test_regress/t/t_interface_virtual_sched_ico.py new file mode 100755 index 000000000..5f13c2aee --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_ico.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_main=False, v_flags2=["--exe", test.pli_filename]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_sched_nba.pl b/test_regress/t/t_interface_virtual_sched_nba.pl deleted file mode 100755 index 6247bd126..000000000 --- a/test_regress/t/t_interface_virtual_sched_nba.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_sched_nba.py b/test_regress/t/t_interface_virtual_sched_nba.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_nba.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_timing.pl b/test_regress/t/t_interface_virtual_timing.pl deleted file mode 100755 index 30ef08a9e..000000000 --- a/test_regress/t/t_interface_virtual_timing.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_timing.py b/test_regress/t/t_interface_virtual_timing.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_interface_virtual_timing.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_unsup.pl b/test_regress/t/t_interface_virtual_unsup.pl deleted file mode 100755 index bd07fc421..000000000 --- a/test_regress/t/t_interface_virtual_unsup.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_unsup.py b/test_regress/t/t_interface_virtual_unsup.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_interface_virtual_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_virtual_unused_bad.pl b/test_regress/t/t_interface_virtual_unused_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_interface_virtual_unused_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_unused_bad.py b/test_regress/t/t_interface_virtual_unused_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_virtual_unused_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_wrong_bad.pl b/test_regress/t/t_interface_wrong_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_wrong_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_wrong_bad.py b/test_regress/t/t_interface_wrong_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_wrong_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_begin_hier.pl b/test_regress/t/t_json_only_begin_hier.pl deleted file mode 100755 index d6d231360..000000000 --- a/test_regress/t/t_json_only_begin_hier.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_begin_hier.py b/test_regress/t/t_json_only_begin_hier.py new file mode 100755 index 000000000..5fa0ddc00 --- /dev/null +++ b/test_regress/t/t_json_only_begin_hier.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_debugcheck.out b/test_regress/t/t_json_only_debugcheck.out index 14c9c7cdf..2cc666c9a 100644 --- a/test_regress/t/t_json_only_debugcheck.out +++ b/test_regress/t/t_json_only_debugcheck.out @@ -58,7 +58,7 @@ "varrefp": [ {"type":"VARREF","name":"t.unnamedblk1.e","addr":"(XB)","loc":"d,52:17,52:18","dtypep":"(VB)","access":"WR","varp":"(UB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"VAR","name":"__Vtemp_1","addr":"(YB)","loc":"d,49:123,49:127","dtypep":"(RB)","origName":"__Vtemp_1","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"__Vtemp_1","addr":"(YB)","loc":"d,49:120,49:121","dtypep":"(RB)","origName":"__Vtemp_1","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(ZB)","loc":"d,32:9,32:10","dtypep":"(AC)", @@ -75,14 +75,14 @@ {"type":"CONST","name":"4'h4","addr":"(FC)","loc":"d,38:31,38:34","dtypep":"(AC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(GC)","loc":"d,38:17,38:21","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(GC)","loc":"d,38:15,38:16","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(HC)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(HC)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(KC)","loc":"d,38:17,38:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(KC)","loc":"d,38:15,38:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(MC)","loc":"d,38:17,38:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(MC)","loc":"d,38:15,38:16","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(OC)","loc":"d,38:15,38:16","dtypep":"(LC)","size":32, @@ -98,14 +98,14 @@ "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:38: got='h%x exp='h4\\n","addr":"(RC)","loc":"d,38:43,38:49","dtypep":"(RB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(SC)","loc":"d,38:124,38:128","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(SC)","loc":"d,38:122,38:123","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(TC)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(TC)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(UC)","loc":"d,38:124,38:128","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(UC)","loc":"d,38:122,38:123","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(VC)","loc":"d,38:124,38:128","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(VC)","loc":"d,38:122,38:123","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(WC)","loc":"d,38:122,38:123","dtypep":"(LC)","size":32, @@ -116,7 +116,7 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(YC)","loc":"d,38:142,38:147"} + {"type":"STOP","name":"","addr":"(YC)","loc":"d,38:142,38:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(ZC)","loc":"d,39:10,39:12", "condp": [ @@ -125,24 +125,24 @@ {"type":"CONST","name":"4'h1","addr":"(BD)","loc":"d,39:39,39:42","dtypep":"(AC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(CD)","loc":"d,39:25,39:29","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(CD)","loc":"d,39:15,39:16","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(DD)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(DD)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(ED)","loc":"d,39:25,39:29","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(ED)","loc":"d,39:15,39:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(FD)","loc":"d,39:25,39:29","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(FD)","loc":"d,39:15,39:16","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(GD)","loc":"d,39:17,39:21","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(GD)","loc":"d,39:15,39:16","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(HD)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(HD)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(ID)","loc":"d,39:17,39:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(ID)","loc":"d,39:15,39:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(JD)","loc":"d,39:17,39:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(JD)","loc":"d,39:15,39:16","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(KD)","loc":"d,39:15,39:16","dtypep":"(LC)","size":32, @@ -160,24 +160,24 @@ "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:39: got='h%x exp='h1\\n","addr":"(ND)","loc":"d,39:51,39:57","dtypep":"(RB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(OD)","loc":"d,39:140,39:144","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(OD)","loc":"d,39:130,39:131","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(PD)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(PD)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(QD)","loc":"d,39:140,39:144","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(QD)","loc":"d,39:130,39:131","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(RD)","loc":"d,39:140,39:144","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(RD)","loc":"d,39:130,39:131","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(SD)","loc":"d,39:132,39:136","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(SD)","loc":"d,39:130,39:131","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(TD)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(TD)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(UD)","loc":"d,39:132,39:136","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(UD)","loc":"d,39:130,39:131","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(VD)","loc":"d,39:132,39:136","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(VD)","loc":"d,39:130,39:131","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(WD)","loc":"d,39:130,39:131","dtypep":"(LC)","size":32, @@ -190,7 +190,7 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(YD)","loc":"d,39:158,39:163"} + {"type":"STOP","name":"","addr":"(YD)","loc":"d,39:158,39:163","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(ZD)","loc":"d,40:10,40:12", "condp": [ @@ -199,24 +199,24 @@ {"type":"CONST","name":"4'h1","addr":"(BE)","loc":"d,40:31,40:34","dtypep":"(AC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(CE)","loc":"d,40:17,40:21","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(CE)","loc":"d,40:15,40:16","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(DE)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(DE)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(EE)","loc":"d,40:17,40:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(EE)","loc":"d,40:15,40:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(FE)","loc":"d,40:17,40:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(FE)","loc":"d,40:15,40:16","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(GE)","loc":"d,40:17,40:21","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(GE)","loc":"d,40:15,40:16","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(HE)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(HE)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(IE)","loc":"d,40:17,40:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(IE)","loc":"d,40:15,40:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(JE)","loc":"d,40:17,40:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(JE)","loc":"d,40:15,40:16","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(KE)","loc":"d,40:15,40:16","dtypep":"(LC)","size":32, @@ -234,24 +234,24 @@ "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:40: got='h%x exp='h1\\n","addr":"(NE)","loc":"d,40:43,40:49","dtypep":"(RB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(OE)","loc":"d,40:124,40:128","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(OE)","loc":"d,40:122,40:123","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(PE)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(PE)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(QE)","loc":"d,40:124,40:128","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(QE)","loc":"d,40:122,40:123","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(RE)","loc":"d,40:124,40:128","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(RE)","loc":"d,40:122,40:123","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(SE)","loc":"d,40:124,40:128","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(SE)","loc":"d,40:122,40:123","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(TE)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(TE)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(UE)","loc":"d,40:124,40:128","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(UE)","loc":"d,40:122,40:123","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(VE)","loc":"d,40:124,40:128","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(VE)","loc":"d,40:122,40:123","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(WE)","loc":"d,40:122,40:123","dtypep":"(LC)","size":32, @@ -264,7 +264,7 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(YE)","loc":"d,40:142,40:147"} + {"type":"STOP","name":"","addr":"(YE)","loc":"d,40:142,40:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(ZE)","loc":"d,41:10,41:12", "condp": [ @@ -273,34 +273,34 @@ {"type":"CONST","name":"4'h3","addr":"(BF)","loc":"d,41:47,41:50","dtypep":"(AC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(CF)","loc":"d,41:33,41:37","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(CF)","loc":"d,41:15,41:16","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(DF)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(DF)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(EF)","loc":"d,41:33,41:37","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(EF)","loc":"d,41:15,41:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(FF)","loc":"d,41:33,41:37","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(FF)","loc":"d,41:15,41:16","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(GF)","loc":"d,41:25,41:29","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(GF)","loc":"d,41:15,41:16","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(HF)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(HF)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(IF)","loc":"d,41:25,41:29","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(IF)","loc":"d,41:15,41:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(JF)","loc":"d,41:25,41:29","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(JF)","loc":"d,41:15,41:16","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(KF)","loc":"d,41:17,41:21","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(KF)","loc":"d,41:15,41:16","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(LF)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(LF)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(MF)","loc":"d,41:17,41:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(MF)","loc":"d,41:15,41:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(NF)","loc":"d,41:17,41:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(NF)","loc":"d,41:15,41:16","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(OF)","loc":"d,41:15,41:16","dtypep":"(LC)","size":32, @@ -320,34 +320,34 @@ "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:41: got='h%x exp='h3\\n","addr":"(RF)","loc":"d,41:59,41:65","dtypep":"(RB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(SF)","loc":"d,41:156,41:160","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(SF)","loc":"d,41:138,41:139","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(TF)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(TF)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(UF)","loc":"d,41:156,41:160","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(UF)","loc":"d,41:138,41:139","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(VF)","loc":"d,41:156,41:160","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(VF)","loc":"d,41:138,41:139","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(WF)","loc":"d,41:148,41:152","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(WF)","loc":"d,41:138,41:139","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(XF)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(XF)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(YF)","loc":"d,41:148,41:152","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(YF)","loc":"d,41:138,41:139","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(ZF)","loc":"d,41:148,41:152","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(ZF)","loc":"d,41:138,41:139","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(AG)","loc":"d,41:140,41:144","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(AG)","loc":"d,41:138,41:139","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(BG)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(BG)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(CG)","loc":"d,41:140,41:144","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(CG)","loc":"d,41:138,41:139","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(DG)","loc":"d,41:140,41:144","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(DG)","loc":"d,41:138,41:139","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(EG)","loc":"d,41:138,41:139","dtypep":"(LC)","size":32, @@ -362,7 +362,7 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(GG)","loc":"d,41:174,41:179"} + {"type":"STOP","name":"","addr":"(GG)","loc":"d,41:174,41:179","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(HG)","loc":"d,42:10,42:12", "condp": [ @@ -371,34 +371,34 @@ {"type":"CONST","name":"4'h3","addr":"(JG)","loc":"d,42:39,42:42","dtypep":"(AC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(KG)","loc":"d,42:25,42:29","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(KG)","loc":"d,42:15,42:16","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(LG)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(LG)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(MG)","loc":"d,42:25,42:29","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(MG)","loc":"d,42:15,42:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(NG)","loc":"d,42:25,42:29","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(NG)","loc":"d,42:15,42:16","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(OG)","loc":"d,42:25,42:29","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(OG)","loc":"d,42:15,42:16","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(PG)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(PG)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(QG)","loc":"d,42:25,42:29","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(QG)","loc":"d,42:15,42:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(RG)","loc":"d,42:25,42:29","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(RG)","loc":"d,42:15,42:16","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(SG)","loc":"d,42:17,42:21","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(SG)","loc":"d,42:15,42:16","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(TG)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(TG)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(UG)","loc":"d,42:17,42:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(UG)","loc":"d,42:15,42:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(VG)","loc":"d,42:17,42:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(VG)","loc":"d,42:15,42:16","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(WG)","loc":"d,42:15,42:16","dtypep":"(LC)","size":32, @@ -418,34 +418,34 @@ "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:42: got='h%x exp='h3\\n","addr":"(ZG)","loc":"d,42:51,42:57","dtypep":"(RB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(AH)","loc":"d,42:140,42:144","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(AH)","loc":"d,42:130,42:131","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(BH)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(BH)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(CH)","loc":"d,42:140,42:144","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(CH)","loc":"d,42:130,42:131","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(DH)","loc":"d,42:140,42:144","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(DH)","loc":"d,42:130,42:131","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(EH)","loc":"d,42:140,42:144","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(EH)","loc":"d,42:130,42:131","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(FH)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(FH)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(GH)","loc":"d,42:140,42:144","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(GH)","loc":"d,42:130,42:131","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(HH)","loc":"d,42:140,42:144","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(HH)","loc":"d,42:130,42:131","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(IH)","loc":"d,42:132,42:136","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(IH)","loc":"d,42:130,42:131","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(JH)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(JH)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(KH)","loc":"d,42:132,42:136","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(KH)","loc":"d,42:130,42:131","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(LH)","loc":"d,42:132,42:136","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(LH)","loc":"d,42:130,42:131","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(MH)","loc":"d,42:130,42:131","dtypep":"(LC)","size":32, @@ -460,7 +460,7 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(OH)","loc":"d,42:158,42:163"} + {"type":"STOP","name":"","addr":"(OH)","loc":"d,42:158,42:163","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(PH)","loc":"d,43:10,43:12", "condp": [ @@ -469,34 +469,34 @@ {"type":"CONST","name":"4'h3","addr":"(RH)","loc":"d,43:31,43:34","dtypep":"(AC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(SH)","loc":"d,43:17,43:21","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(SH)","loc":"d,43:15,43:16","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(TH)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(TH)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(UH)","loc":"d,43:17,43:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(UH)","loc":"d,43:15,43:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(VH)","loc":"d,43:17,43:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(VH)","loc":"d,43:15,43:16","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(WH)","loc":"d,43:17,43:21","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(WH)","loc":"d,43:15,43:16","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(XH)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(XH)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(YH)","loc":"d,43:17,43:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(YH)","loc":"d,43:15,43:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(ZH)","loc":"d,43:17,43:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(ZH)","loc":"d,43:15,43:16","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(AI)","loc":"d,43:17,43:21","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(AI)","loc":"d,43:15,43:16","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(BI)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(BI)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(CI)","loc":"d,43:17,43:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(CI)","loc":"d,43:15,43:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(DI)","loc":"d,43:17,43:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(DI)","loc":"d,43:15,43:16","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(EI)","loc":"d,43:15,43:16","dtypep":"(LC)","size":32, @@ -516,34 +516,34 @@ "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:43: got='h%x exp='h3\\n","addr":"(HI)","loc":"d,43:43,43:49","dtypep":"(RB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(II)","loc":"d,43:124,43:128","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(II)","loc":"d,43:122,43:123","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(JI)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(JI)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(KI)","loc":"d,43:124,43:128","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(KI)","loc":"d,43:122,43:123","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(LI)","loc":"d,43:124,43:128","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(LI)","loc":"d,43:122,43:123","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(MI)","loc":"d,43:124,43:128","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(MI)","loc":"d,43:122,43:123","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(NI)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(NI)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(OI)","loc":"d,43:124,43:128","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(OI)","loc":"d,43:122,43:123","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(PI)","loc":"d,43:124,43:128","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(PI)","loc":"d,43:122,43:123","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(QI)","loc":"d,43:124,43:128","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(QI)","loc":"d,43:122,43:123","dtypep":"(LC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(RI)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(RI)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(SI)","loc":"d,43:124,43:128","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(SI)","loc":"d,43:122,43:123","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(TI)","loc":"d,43:124,43:128","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(TI)","loc":"d,43:122,43:123","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(UI)","loc":"d,43:122,43:123","dtypep":"(LC)","size":32, @@ -558,7 +558,7 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(WI)","loc":"d,43:142,43:147"} + {"type":"STOP","name":"","addr":"(WI)","loc":"d,43:142,43:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(XI)","loc":"d,44:10,44:12", "condp": [ @@ -567,14 +567,14 @@ {"type":"CONST","name":"4'h1","addr":"(ZI)","loc":"d,44:28,44:31","dtypep":"(AC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(AJ)","loc":"d,44:17,44:21","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(AJ)","loc":"d,44:15,44:16","dtypep":"(AC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(BJ)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(EJ)","loc":"d,44:17,44:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(EJ)","loc":"d,44:15,44:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(FJ)","loc":"d,44:17,44:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(FJ)","loc":"d,44:15,44:16","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(GJ)","loc":"d,44:15,44:16","dtypep":"(LC)","size":32, @@ -590,14 +590,14 @@ "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:44: got='h%x exp='h1\\n","addr":"(JJ)","loc":"d,44:40,44:46","dtypep":"(RB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(KJ)","loc":"d,44:121,44:125","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(KJ)","loc":"d,44:119,44:120","dtypep":"(AC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(LJ)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(MJ)","loc":"d,44:121,44:125","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(MJ)","loc":"d,44:119,44:120","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(NJ)","loc":"d,44:121,44:125","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(NJ)","loc":"d,44:119,44:120","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(OJ)","loc":"d,44:119,44:120","dtypep":"(LC)","size":32, @@ -608,7 +608,7 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(QJ)","loc":"d,44:136,44:141"} + {"type":"STOP","name":"","addr":"(QJ)","loc":"d,44:136,44:141","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(RJ)","loc":"d,45:10,45:12", "condp": [ @@ -617,14 +617,14 @@ {"type":"CONST","name":"4'h1","addr":"(TJ)","loc":"d,45:31,45:34","dtypep":"(AC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(UJ)","loc":"d,45:17,45:21","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(UJ)","loc":"d,45:15,45:16","dtypep":"(AC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(VJ)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(WJ)","loc":"d,45:17,45:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(WJ)","loc":"d,45:15,45:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(XJ)","loc":"d,45:17,45:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(XJ)","loc":"d,45:15,45:16","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(YJ)","loc":"d,45:15,45:16","dtypep":"(LC)","size":32, @@ -640,14 +640,14 @@ "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:45: got='h%x exp='h1\\n","addr":"(BK)","loc":"d,45:43,45:49","dtypep":"(RB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(CK)","loc":"d,45:124,45:128","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(CK)","loc":"d,45:122,45:123","dtypep":"(AC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(DK)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(EK)","loc":"d,45:124,45:128","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(EK)","loc":"d,45:122,45:123","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(FK)","loc":"d,45:124,45:128","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(FK)","loc":"d,45:122,45:123","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(GK)","loc":"d,45:122,45:123","dtypep":"(LC)","size":32, @@ -658,7 +658,7 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(IK)","loc":"d,45:142,45:147"} + {"type":"STOP","name":"","addr":"(IK)","loc":"d,45:142,45:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(JK)","loc":"d,46:10,46:12", "condp": [ @@ -667,24 +667,24 @@ {"type":"CONST","name":"4'h4","addr":"(LK)","loc":"d,46:39,46:42","dtypep":"(AC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(MK)","loc":"d,46:25,46:29","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(MK)","loc":"d,46:15,46:16","dtypep":"(AC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(NK)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(OK)","loc":"d,46:25,46:29","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(OK)","loc":"d,46:15,46:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(PK)","loc":"d,46:25,46:29","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(PK)","loc":"d,46:15,46:16","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(QK)","loc":"d,46:17,46:21","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(QK)","loc":"d,46:15,46:16","dtypep":"(LC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(RK)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(SK)","loc":"d,46:17,46:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(SK)","loc":"d,46:15,46:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(TK)","loc":"d,46:17,46:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(TK)","loc":"d,46:15,46:16","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(UK)","loc":"d,46:15,46:16","dtypep":"(LC)","size":32, @@ -702,24 +702,24 @@ "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:46: got='h%x exp='h4\\n","addr":"(XK)","loc":"d,46:51,46:57","dtypep":"(RB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(YK)","loc":"d,46:140,46:144","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(YK)","loc":"d,46:130,46:131","dtypep":"(AC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(ZK)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(AL)","loc":"d,46:140,46:144","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(AL)","loc":"d,46:130,46:131","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(BL)","loc":"d,46:140,46:144","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(BL)","loc":"d,46:130,46:131","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(CL)","loc":"d,46:132,46:136","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(CL)","loc":"d,46:130,46:131","dtypep":"(LC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(DL)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(EL)","loc":"d,46:132,46:136","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(EL)","loc":"d,46:130,46:131","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(FL)","loc":"d,46:132,46:136","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(FL)","loc":"d,46:130,46:131","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(GL)","loc":"d,46:130,46:131","dtypep":"(LC)","size":32, @@ -732,7 +732,7 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(IL)","loc":"d,46:158,46:163"} + {"type":"STOP","name":"","addr":"(IL)","loc":"d,46:158,46:163","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(JL)","loc":"d,47:10,47:12", "condp": [ @@ -741,24 +741,24 @@ {"type":"CONST","name":"4'h4","addr":"(LL)","loc":"d,47:31,47:34","dtypep":"(AC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(ML)","loc":"d,47:17,47:21","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(ML)","loc":"d,47:15,47:16","dtypep":"(AC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(NL)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(OL)","loc":"d,47:17,47:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(OL)","loc":"d,47:15,47:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(PL)","loc":"d,47:17,47:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(PL)","loc":"d,47:15,47:16","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(QL)","loc":"d,47:17,47:21","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(QL)","loc":"d,47:15,47:16","dtypep":"(LC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(RL)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(SL)","loc":"d,47:17,47:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(SL)","loc":"d,47:15,47:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(TL)","loc":"d,47:17,47:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(TL)","loc":"d,47:15,47:16","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(UL)","loc":"d,47:15,47:16","dtypep":"(LC)","size":32, @@ -776,24 +776,24 @@ "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:47: got='h%x exp='h4\\n","addr":"(XL)","loc":"d,47:43,47:49","dtypep":"(RB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(YL)","loc":"d,47:124,47:128","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(YL)","loc":"d,47:122,47:123","dtypep":"(AC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(ZL)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(AM)","loc":"d,47:124,47:128","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(AM)","loc":"d,47:122,47:123","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(BM)","loc":"d,47:124,47:128","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(BM)","loc":"d,47:122,47:123","dtypep":"(NC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(CM)","loc":"d,47:124,47:128","dtypep":"(LC)", + {"type":"ARRAYSEL","name":"","addr":"(CM)","loc":"d,47:122,47:123","dtypep":"(LC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(DM)","loc":"d,17:12,17:16","dtypep":"(CJ)","access":"RD","varp":"(DJ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(EM)","loc":"d,47:124,47:128","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(EM)","loc":"d,47:122,47:123","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(FM)","loc":"d,47:124,47:128","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(FM)","loc":"d,47:122,47:123","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(GM)","loc":"d,47:122,47:123","dtypep":"(LC)","size":32, @@ -806,23 +806,23 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(IM)","loc":"d,47:142,47:147"} + {"type":"STOP","name":"","addr":"(IM)","loc":"d,47:142,47:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(JM)","loc":"d,49:10,49:12", "condp": [ - {"type":"NEQN","name":"","addr":"(KM)","loc":"d,49:23,49:26","dtypep":"(NB)", + {"type":"NEQN","name":"","addr":"(KM)","loc":"d,49:23,49:25","dtypep":"(NB)", "lhsp": [ - {"type":"CONST","name":"\\\"E03\\\"","addr":"(LM)","loc":"d,49:28,49:33","dtypep":"(RB)"} + {"type":"CONST","name":"\\\"E03\\\"","addr":"(LM)","loc":"d,49:27,49:32","dtypep":"(RB)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(MM)","loc":"d,49:17,49:21","dtypep":"(RB)", + {"type":"ARRAYSEL","name":"","addr":"(MM)","loc":"d,49:15,49:16","dtypep":"(RB)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_name2","addr":"(NM)","loc":"d,17:12,17:16","dtypep":"(OM)","access":"RD","varp":"(PM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(NM)","loc":"d,17:12,17:16","dtypep":"(OM)","access":"RD","varp":"(PM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(QM)","loc":"d,49:17,49:21","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(QM)","loc":"d,49:15,49:16","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(RM)","loc":"d,49:17,49:21","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(RM)","loc":"d,49:15,49:16","dtypep":"(NC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(SM)","loc":"d,49:15,49:16","dtypep":"(LC)","size":32, @@ -834,36 +834,36 @@ ]} ], "thensp": [ - {"type":"ASSIGN","name":"","addr":"(UM)","loc":"d,49:123,49:127","dtypep":"(RB)", + {"type":"ASSIGN","name":"","addr":"(UM)","loc":"d,49:120,49:121","dtypep":"(RB)", "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(VM)","loc":"d,49:123,49:127","dtypep":"(RB)", + {"type":"ARRAYSEL","name":"","addr":"(VM)","loc":"d,49:120,49:121","dtypep":"(RB)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_name2","addr":"(WM)","loc":"d,17:12,17:16","dtypep":"(OM)","access":"RD","varp":"(PM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(WM)","loc":"d,17:12,17:16","dtypep":"(OM)","access":"RD","varp":"(PM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(XM)","loc":"d,49:123,49:127","dtypep":"(LC)", + {"type":"AND","name":"","addr":"(XM)","loc":"d,49:120,49:121","dtypep":"(LC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(YM)","loc":"d,49:123,49:127","dtypep":"(NC)"} + {"type":"CONST","name":"32'h7","addr":"(YM)","loc":"d,49:120,49:121","dtypep":"(NC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(ZM)","loc":"d,49:121,49:122","dtypep":"(LC)","size":32, + {"type":"CCAST","name":"","addr":"(ZM)","loc":"d,49:120,49:121","dtypep":"(LC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(AN)","loc":"d,49:121,49:122","dtypep":"(LC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(AN)","loc":"d,49:120,49:121","dtypep":"(LC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ], "lhsp": [ - {"type":"VARREF","name":"__Vtemp_1","addr":"(BN)","loc":"d,49:123,49:127","dtypep":"(RB)","access":"WR","varp":"(YB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Vtemp_1","addr":"(BN)","loc":"d,49:120,49:121","dtypep":"(RB)","access":"WR","varp":"(YB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, - {"type":"DISPLAY","name":"","addr":"(CN)","loc":"d,49:42,49:48", + {"type":"DISPLAY","name":"","addr":"(CN)","loc":"d,49:41,49:47", "fmtp": [ - {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:49: got='%@' exp='E03'\\n","addr":"(DN)","loc":"d,49:42,49:48","dtypep":"(RB)", + {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:49: got='%@' exp='E03'\\n","addr":"(DN)","loc":"d,49:41,49:47","dtypep":"(RB)", "exprsp": [ - {"type":"VARREF","name":"__Vtemp_1","addr":"(EN)","loc":"d,49:123,49:127","dtypep":"(RB)","access":"RD","varp":"(YB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Vtemp_1","addr":"(EN)","loc":"d,49:120,49:121","dtypep":"(RB)","access":"RD","varp":"(YB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(FN)","loc":"d,49:140,49:145"} + {"type":"STOP","name":"","addr":"(FN)","loc":"d,49:139,49:144","isFatal":false} ],"elsesp": []}, {"type":"ASSIGN","name":"","addr":"(GN)","loc":"d,51:11,51:12","dtypep":"(RB)", "rhsp": [ @@ -895,529 +895,520 @@ "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(RN)","loc":"d,53:14,53:15","dtypep":"(RB)", "rhsp": [ - {"type":"CVTPACKSTRING","name":"","addr":"(SN)","loc":"d,53:20,53:21","dtypep":"(RB)", + {"type":"CONCATN","name":"","addr":"(SN)","loc":"d,53:20,53:21","dtypep":"(RB)", "lhsp": [ - {"type":"CONCATN","name":"","addr":"(TN)","loc":"d,53:20,53:21","dtypep":"(RB)", - "lhsp": [ - {"type":"VARREF","name":"t.all","addr":"(UN)","loc":"d,53:17,53:20","dtypep":"(RB)","access":"RD","varp":"(QB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.all","addr":"(TN)","loc":"d,53:17,53:20","dtypep":"(RB)","access":"RD","varp":"(QB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + ], + "rhsp": [ + {"type":"ARRAYSEL","name":"","addr":"(UN)","loc":"d,53:22,53:23","dtypep":"(RB)", + "fromp": [ + {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(VN)","loc":"d,17:12,17:16","dtypep":"(OM)","access":"RD","varp":"(PM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], - "rhsp": [ - {"type":"CVTPACKSTRING","name":"","addr":"(VN)","loc":"d,53:24,53:28","dtypep":"(RB)", + "bitp": [ + {"type":"AND","name":"","addr":"(WN)","loc":"d,53:22,53:23","dtypep":"(LC)", "lhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(WN)","loc":"d,53:24,53:28","dtypep":"(RB)", - "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_name2","addr":"(XN)","loc":"d,17:12,17:16","dtypep":"(OM)","access":"RD","varp":"(PM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} - ], - "bitp": [ - {"type":"AND","name":"","addr":"(YN)","loc":"d,53:24,53:28","dtypep":"(LC)", - "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(ZN)","loc":"d,53:24,53:28","dtypep":"(NC)"} - ], - "rhsp": [ - {"type":"CCAST","name":"","addr":"(AO)","loc":"d,53:22,53:23","dtypep":"(LC)","size":32, - "lhsp": [ - {"type":"VARREF","name":"t.unnamedblk1.e","addr":"(BO)","loc":"d,53:22,53:23","dtypep":"(LC)","access":"RD","varp":"(UB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} - ]} - ]} + {"type":"CONST","name":"32'h7","addr":"(XN)","loc":"d,53:22,53:23","dtypep":"(NC)"} + ], + "rhsp": [ + {"type":"CCAST","name":"","addr":"(YN)","loc":"d,53:22,53:23","dtypep":"(LC)","size":32, + "lhsp": [ + {"type":"VARREF","name":"t.unnamedblk1.e","addr":"(ZN)","loc":"d,53:22,53:23","dtypep":"(LC)","access":"RD","varp":"(UB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "lhsp": [ - {"type":"VARREF","name":"t.all","addr":"(CO)","loc":"d,53:10,53:13","dtypep":"(RB)","access":"WR","varp":"(QB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.all","addr":"(AO)","loc":"d,53:10,53:13","dtypep":"(RB)","access":"WR","varp":"(QB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ], "incsp": [ - {"type":"ASSIGN","name":"","addr":"(DO)","loc":"d,52:45,52:46","dtypep":"(AC)", + {"type":"ASSIGN","name":"","addr":"(BO)","loc":"d,52:45,52:46","dtypep":"(AC)", "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(EO)","loc":"d,52:49,52:53","dtypep":"(AC)", + {"type":"ARRAYSEL","name":"","addr":"(CO)","loc":"d,52:47,52:48","dtypep":"(AC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next0","addr":"(FO)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(DO)","loc":"d,17:12,17:16","dtypep":"(IC)","access":"RD","varp":"(JC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - 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{"type":"UNPACKARRAYDTYPE","name":"","addr":"(CJ)","loc":"d,17:12,17:16","dtypep":"(CJ)","isCompound":false,"declRange":"[7:0]","generic":false,"refDTypep":"(HRB)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(OM)","loc":"d,17:12,17:16","dtypep":"(OM)","isCompound":true,"declRange":"[7:0]","generic":false,"refDTypep":"(RB)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(RRB)","loc":"d,17:12,17:16","ascending":false, "leftp": [ @@ -2971,34 +2972,24 @@ {"type":"CONST","name":"32'h0","addr":"(TRB)","loc":"d,17:12,17:16","dtypep":"(NC)"} ]} ]}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(OM)","loc":"d,17:12,17:16","dtypep":"(OM)","isCompound":true,"declRange":"[7:0]","generic":false,"refDTypep":"(RB)","childDTypep": [], - "rangep": [ - {"type":"RANGE","name":"","addr":"(URB)","loc":"d,17:12,17:16","ascending":false, - "leftp": [ - {"type":"CONST","name":"32'h7","addr":"(VRB)","loc":"d,17:12,17:16","dtypep":"(NC)"} - ], - "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(WRB)","loc":"d,17:12,17:16","dtypep":"(NC)"} - ]} - ]}, - {"type":"REFDTYPE","name":"my_t","addr":"(VB)","loc":"d,52:12,52:16","dtypep":"(HRB)","generic":false,"typedefp":"UNLINKED","refDTypep":"(HRB)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, + {"type":"REFDTYPE","name":"my_t","addr":"(VB)","loc":"d,52:12,52:16","dtypep":"(ERB)","generic":false,"typedefp":"UNLINKED","refDTypep":"(ERB)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, {"type":"BASICDTYPE","name":"logic","addr":"(GB)","loc":"d,23:23,23:24","dtypep":"(GB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(CB)","loc":"d,11:8,11:9","dtypep":"(CB)","generic":false}, {"type":"BASICDTYPE","name":"VlTriggerVec","addr":"(V)","loc":"d,11:8,11:9","dtypep":"(V)","keyword":"VlTriggerVec","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"QData","addr":"(MQ)","loc":"d,11:8,11:9","dtypep":"(MQ)","keyword":"QData","range":"63:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(JQ)","loc":"d,11:8,11:9","dtypep":"(JQ)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"QData","addr":"(JQ)","loc":"d,11:8,11:9","dtypep":"(JQ)","keyword":"QData","range":"63:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(GQ)","loc":"d,11:8,11:9","dtypep":"(GQ)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"bit","addr":"(P)","loc":"d,11:8,11:9","dtypep":"(P)","keyword":"bit","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"bit","addr":"(T)","loc":"d,11:8,11:9","dtypep":"(T)","keyword":"bit","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(NB)","loc":"d,61:22,61:25","dtypep":"(NB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(AC)","loc":"d,32:11,32:14","dtypep":"(AC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(LC)","loc":"d,38:17,38:21","dtypep":"(LC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(APB)","loc":"d,15:10,15:13","dtypep":"(APB)","keyword":"logic","range":"7:0","generic":true,"rangep": []} + {"type":"BASICDTYPE","name":"logic","addr":"(LC)","loc":"d,38:15,38:16","dtypep":"(LC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(XOB)","loc":"d,15:10,15:13","dtypep":"(XOB)","keyword":"logic","range":"7:0","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(XRB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(URB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ - {"type":"SCOPE","name":"TOP","addr":"(YRB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(XRB)","varsp": [],"blocksp": [],"inlinesp": []} + {"type":"SCOPE","name":"TOP","addr":"(VRB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(URB)","varsp": [],"blocksp": [],"inlinesp": []} ],"activesp": []} ]} ]} diff --git a/test_regress/t/t_json_only_debugcheck.pl b/test_regress/t/t_json_only_debugcheck.pl deleted file mode 100755 index 9eb18a787..000000000 --- a/test_regress/t/t_json_only_debugcheck.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -top_filename("t/t_enum_type_methods.v"); - -compile( - verilator_flags2 => ['--no-std', '--debug-check', '--no-json-edit-nums', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}, 'logfile'); - - -ok(1); -1; diff --git a/test_regress/t/t_json_only_debugcheck.py b/test_regress/t/t_json_only_debugcheck.py new file mode 100755 index 000000000..810a93a19 --- /dev/null +++ b/test_regress/t/t_json_only_debugcheck.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_enum_type_methods.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--debug-check', '--no-json-edit-nums', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename, 'logfile') + +test.passes() diff --git a/test_regress/t/t_json_only_first.pl b/test_regress/t/t_json_only_first.pl deleted file mode 100755 index d6d231360..000000000 --- a/test_regress/t/t_json_only_first.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_first.py b/test_regress/t/t_json_only_first.py new file mode 100755 index 000000000..5fa0ddc00 --- /dev/null +++ b/test_regress/t/t_json_only_first.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_flat.pl b/test_regress/t/t_json_only_flat.pl deleted file mode 100755 index 339b4b5a3..000000000 --- a/test_regress/t/t_json_only_flat.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -top_filename("t/t_json_only_first.v"); - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_flat.py b/test_regress/t/t_json_only_flat.py new file mode 100755 index 000000000..0c8fa3240 --- /dev/null +++ b/test_regress/t/t_json_only_flat.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_json_only_first.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_flat_no_inline_mod.pl b/test_regress/t/t_json_only_flat_no_inline_mod.pl deleted file mode 100755 index 4ae513fb6..000000000 --- a/test_regress/t/t_json_only_flat_no_inline_mod.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_flat_no_inline_mod.py b/test_regress/t/t_json_only_flat_no_inline_mod.py new file mode 100755 index 000000000..9903be780 --- /dev/null +++ b/test_regress/t/t_json_only_flat_no_inline_mod.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_flat_pub_mod.pl b/test_regress/t/t_json_only_flat_pub_mod.pl deleted file mode 100755 index 4ae513fb6..000000000 --- a/test_regress/t/t_json_only_flat_pub_mod.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_flat_pub_mod.py b/test_regress/t/t_json_only_flat_pub_mod.py new file mode 100755 index 000000000..9903be780 --- /dev/null +++ b/test_regress/t/t_json_only_flat_pub_mod.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_flat_vlvbound.pl b/test_regress/t/t_json_only_flat_vlvbound.pl deleted file mode 100755 index 4ae513fb6..000000000 --- a/test_regress/t/t_json_only_flat_vlvbound.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_flat_vlvbound.py b/test_regress/t/t_json_only_flat_vlvbound.py new file mode 100755 index 000000000..9903be780 --- /dev/null +++ b/test_regress/t/t_json_only_flat_vlvbound.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_output.pl b/test_regress/t/t_json_only_output.pl deleted file mode 100755 index 81baf48b0..000000000 --- a/test_regress/t/t_json_only_output.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/renamed-$Self->{name}.tree.json"; -my $meta_filename = "$Self->{obj_dir}/renamed-$Self->{name}.tree.meta.json"; - -compile( - verilator_flags2 => ["--no-std", "--json-only", "--json-only-output", "$out_filename", "--json-only-meta-output", "$meta_filename", '--no-json-edit-nums'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -foreach my $file (glob("$Self->{obj_dir}/*")) { - next if $file =~ /\.log/; # Made by driver.pl, not Verilator - next if $file =~ /\.status/; # Made by driver.pl, not Verilator - next if $file =~ /renamed-/; # Requested output - error("%Error: Created $file, but --json-only shouldn't create files"); -} - -ok(1); -1; diff --git a/test_regress/t/t_json_only_output.py b/test_regress/t/t_json_only_output.py new file mode 100755 index 000000000..8f6c3b581 --- /dev/null +++ b/test_regress/t/t_json_only_output.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/renamed-" + test.name + ".tree.json" +meta_filename = test.obj_dir + "/renamed-" + test.name + ".tree.meta.json" + +test.compile(verilator_flags2=[ + "--no-std", "--json-only", "--json-only-output", out_filename, "--json-only-meta-output", + meta_filename, '--no-json-edit-nums' +], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +for filename in glob.glob(test.obj_dir + "/*"): + if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources + or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources + or re.search(r'renamed-', filename)): # Requested output + continue + test.error("%Error: Created '" + filename + "', but --json-only shouldn't create files") + +test.passes() diff --git a/test_regress/t/t_json_only_tag.pl b/test_regress/t/t_json_only_tag.pl deleted file mode 100755 index d6d231360..000000000 --- a/test_regress/t/t_json_only_tag.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_tag.py b/test_regress/t/t_json_only_tag.py new file mode 100755 index 000000000..5fa0ddc00 --- /dev/null +++ b/test_regress/t/t_json_only_tag.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_jumps_do_while.pl b/test_regress/t/t_jumps_do_while.pl deleted file mode 100755 index a86f4c404..000000000 --- a/test_regress/t/t_jumps_do_while.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_jumps_do_while.py b/test_regress/t/t_jumps_do_while.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_jumps_do_while.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_jumps_uninit_destructor_call.pl b/test_regress/t/t_jumps_uninit_destructor_call.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_jumps_uninit_destructor_call.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_jumps_uninit_destructor_call.py b/test_regress/t/t_jumps_uninit_destructor_call.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_jumps_uninit_destructor_call.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_langext_1.pl b/test_regress/t/t_langext_1.pl deleted file mode 100755 index 98a9e0a4a..000000000 --- a/test_regress/t/t_langext_1.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# This is a compile only test. -compile( - v_flags2 => ["+verilog2001ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_1.py b/test_regress/t/t_langext_1.py new file mode 100755 index 000000000..e87ec43cc --- /dev/null +++ b/test_regress/t/t_langext_1.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# This is a compile only test. +test.compile(v_flags2=["+verilog2001ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_1_bad.pl b/test_regress/t/t_langext_1_bad.pl deleted file mode 100755 index 9929990a7..000000000 --- a/test_regress/t/t_langext_1_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_langext_1.v"); - -# This is a lint only test. -lint( - v_flags2 => ["+verilog1995ext+v"], - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_1_bad.py b/test_regress/t/t_langext_1_bad.py new file mode 100755 index 000000000..f09919252 --- /dev/null +++ b/test_regress/t/t_langext_1_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_langext_1.v" + +# This is a lint only test. +test.lint(v_flags2=["+verilog1995ext+v"], fails=True) + +test.passes() diff --git a/test_regress/t/t_langext_2.pl b/test_regress/t/t_langext_2.pl deleted file mode 100755 index 9cade2ddb..000000000 --- a/test_regress/t/t_langext_2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# This is a compile only test. -compile( - v_flags2 => ["+systemverilogext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_2.py b/test_regress/t/t_langext_2.py new file mode 100755 index 000000000..76841dd5e --- /dev/null +++ b/test_regress/t/t_langext_2.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# This is a compile only test. +test.compile(v_flags2=["+systemverilogext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_2012ext.pl b/test_regress/t/t_langext_2012ext.pl deleted file mode 100755 index cbf040cde..000000000 --- a/test_regress/t/t_langext_2012ext.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_langext_2.v"); - -# This is a compile only test. -compile( - v_flags2 => ["+1800-2012ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_2012ext.py b/test_regress/t/t_langext_2012ext.py new file mode 100755 index 000000000..bdc9b832b --- /dev/null +++ b/test_regress/t/t_langext_2012ext.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_langext_2.v" + +# This is a compile only test. +test.compile(v_flags2=["+1800-2012ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_2017ext.pl b/test_regress/t/t_langext_2017ext.pl deleted file mode 100755 index 7aa0a8c5f..000000000 --- a/test_regress/t/t_langext_2017ext.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_langext_2.v"); - -# This is a compile only test. -compile( - v_flags2 => ["+1800-2017ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_2017ext.py b/test_regress/t/t_langext_2017ext.py new file mode 100755 index 000000000..0c7fffebf --- /dev/null +++ b/test_regress/t/t_langext_2017ext.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_langext_2.v" + +# This is a compile only test. +test.compile(v_flags2=["+1800-2017ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_2023ext.pl b/test_regress/t/t_langext_2023ext.pl deleted file mode 100755 index 6badad6e3..000000000 --- a/test_regress/t/t_langext_2023ext.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_langext_2.v"); - -# This is a compile only test. -compile( - v_flags2 => ["+1800-2023ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_2023ext.py b/test_regress/t/t_langext_2023ext.py new file mode 100755 index 000000000..2fb9f6909 --- /dev/null +++ b/test_regress/t/t_langext_2023ext.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_langext_2.v" + +# This is a compile only test. +test.compile(v_flags2=["+1800-2023ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_2_bad.pl b/test_regress/t/t_langext_2_bad.pl deleted file mode 100755 index 4e8700380..000000000 --- a/test_regress/t/t_langext_2_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_langext_2.v"); - -# This is a lint only test. -lint( - v_flags2 => ["+1364-1995ext+v"], - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_2_bad.py b/test_regress/t/t_langext_2_bad.py new file mode 100755 index 000000000..2c8cce718 --- /dev/null +++ b/test_regress/t/t_langext_2_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_langext_2.v" + +# This is a lint only test. +test.lint(v_flags2=["+1364-1995ext+v"], fails=True) + +test.passes() diff --git a/test_regress/t/t_langext_3.pl b/test_regress/t/t_langext_3.pl deleted file mode 100755 index 6286db1d6..000000000 --- a/test_regress/t/t_langext_3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# This is a compile only test. -compile( - v_flags2 => ["+1364-2005ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_3.py b/test_regress/t/t_langext_3.py new file mode 100755 index 000000000..d2e142d8b --- /dev/null +++ b/test_regress/t/t_langext_3.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# This is a compile only test. +test.compile(v_flags2=["+1364-2005ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_3_bad.pl b/test_regress/t/t_langext_3_bad.pl deleted file mode 100755 index f6e5e2b52..000000000 --- a/test_regress/t/t_langext_3_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_langext_3.v"); - -# This is a lint only test. -lint( - v_flags2 => ["+1364-2001ext+v"], - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_3_bad.py b/test_regress/t/t_langext_3_bad.py new file mode 100755 index 000000000..b0cb8ed8e --- /dev/null +++ b/test_regress/t/t_langext_3_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_langext_3.v" + +# This is a lint only test. +test.lint(v_flags2=["+1364-2001ext+v"], fails=True) + +test.passes() diff --git a/test_regress/t/t_langext_4.pl b/test_regress/t/t_langext_4.pl deleted file mode 100755 index dc5b8030c..000000000 --- a/test_regress/t/t_langext_4.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_langext_2.v"); - -# This is a compile only test. -compile( - v_flags2 => ["+1800-2009ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_4.py b/test_regress/t/t_langext_4.py new file mode 100755 index 000000000..829a07706 --- /dev/null +++ b/test_regress/t/t_langext_4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_langext_2.v" + +# This is a compile only test. +test.compile(v_flags2=["+1800-2009ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_4_bad.pl b/test_regress/t/t_langext_4_bad.pl deleted file mode 100755 index ed58832e3..000000000 --- a/test_regress/t/t_langext_4_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_langext_2.v"); - -# This is a lint only test. -lint( - v_flags2 => ["+1800-2005ext+v"], - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_4_bad.py b/test_regress/t/t_langext_4_bad.py new file mode 100755 index 000000000..fa9e4431d --- /dev/null +++ b/test_regress/t/t_langext_4_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_langext_2.v" + +# This is a lint only test. +test.lint(v_flags2=["+1800-2005ext+v"], fails=True) + +test.passes() diff --git a/test_regress/t/t_langext_order.pl b/test_regress/t/t_langext_order.pl deleted file mode 100755 index 6286db1d6..000000000 --- a/test_regress/t/t_langext_order.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# This is a compile only test. -compile( - v_flags2 => ["+1364-2005ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_order.py b/test_regress/t/t_langext_order.py new file mode 100755 index 000000000..d2e142d8b --- /dev/null +++ b/test_regress/t/t_langext_order.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# This is a compile only test. +test.compile(v_flags2=["+1364-2005ext+v"]) + +test.passes() diff --git a/test_regress/t/t_leak.pl b/test_regress/t/t_leak.pl deleted file mode 100755 index 39a931540..000000000 --- a/test_regress/t/t_leak.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if ($Self->{vltmt} && exists $ENV{TRAVIS_DIST} && - $ENV{TRAVIS_DIST} eq "trusty") -{ - skip("Multithreaded test does not work under CI w/ Ubuntu Trusty"); -} - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_leak.py b/test_regress/t/t_leak.py new file mode 100755 index 000000000..a743e049c --- /dev/null +++ b/test_regress/t/t_leak.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +if test.vltmt and test.getenv_def('TRAVIS_DIST', "None") == "trusty": + test.skip("Multithreaded test does not work under CI w/ Ubuntu Trusty") + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename], + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_let.pl b/test_regress/t/t_let.pl deleted file mode 100755 index 97d8dcc12..000000000 --- a/test_regress/t/t_let.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_let.py b/test_regress/t/t_let.py new file mode 100755 index 000000000..fc5a55e3f --- /dev/null +++ b/test_regress/t/t_let.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_let_arg_bad.pl b/test_regress/t/t_let_arg_bad.pl deleted file mode 100755 index d85145f99..000000000 --- a/test_regress/t/t_let_arg_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_let_arg_bad.py b/test_regress/t/t_let_arg_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_let_arg_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_let_recurse_bad.pl b/test_regress/t/t_let_recurse_bad.pl deleted file mode 100755 index d85145f99..000000000 --- a/test_regress/t/t_let_recurse_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_let_recurse_bad.py b/test_regress/t/t_let_recurse_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_let_recurse_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_let_unsup.pl b/test_regress/t/t_let_unsup.pl deleted file mode 100755 index d85145f99..000000000 --- a/test_regress/t/t_let_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_let_unsup.py b/test_regress/t/t_let_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_let_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lib.pl b/test_regress/t/t_lib.pl deleted file mode 100755 index de31f55b6..000000000 --- a/test_regress/t/t_lib.pl +++ /dev/null @@ -1,69 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1, xsim => 1); - -top_filename("t/t_lib_prot.v"); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - '--no-timing', - "--prefix", - "Vt_lib_prot_secret", - "-cc", - "-Mdir", - $secret_dir, - "--lib-create", - $secret_prefix, - "t/t_lib_prot_secret.v"], - verilator_run => 1, - ); - last if $Self->{errors}; - - run(logfile => "$secret_dir/secret_gcc.log", - cmd=>[$ENV{MAKE}, - "-C", - $secret_dir, - "-f", - "Vt_lib_prot_secret.mk"]); - last if $Self->{errors}; - - compile( - verilator_flags2 => ["$secret_dir/secret.sv", - '--no-timing', - "-LDFLAGS", - "$secret_prefix/libsecret.a"], - xsim_flags2 => ["$secret_dir/secret.sv"], - ); - - execute( - check_finished => 1, - xsim_run_flags2 => ["--sv_lib", - "$secret_dir/libsecret", - "--dpi_absolute"], - ); - - ok(1); - last; -} -1; diff --git a/test_regress/t/t_lib.py b/test_regress/t/t_lib.py new file mode 100755 index 000000000..ddd055e11 --- /dev/null +++ b/test_regress/t/t_lib.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt', 'xsim') +test.top_filename = "t/t_lib_prot.v" +if test.benchmark: + test.sim_time = test.benchmark * 100 + +trace_opt = "" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) + +while True: + # Always compile the secret file with Verilator no matter what simulator + # we are testing with + test.run(logfile=secret_dir + "/vlt_compile.log", + cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + '--no-timing', + trace_opt, + "--prefix", "Vt_lib_prot_secret", + "-cc", + "-Mdir", secret_dir, + "--lib-create", secret_prefix, + "t/t_lib_prot_secret.v"], + verilator_run=True) # yapf:disable + + test.run(logfile=secret_dir + "/secret_gcc.log", + cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) + + test.compile(verilator_flags2=['--no-timing', + trace_opt, + "-LDFLAGS", secret_prefix + "/libsecret.a", + secret_dir + "/secret.sv"], + xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable + + test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) + + test.passes() + break diff --git a/test_regress/t/t_lib_nolib.pl b/test_regress/t/t_lib_nolib.pl deleted file mode 100755 index b463b16b6..000000000 --- a/test_regress/t/t_lib_nolib.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1, xsim => 1); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; -top_filename("t/t_lib_prot.v"); - -# Tests the same code as t_lib_prot.pl but without --protect-lib -compile( - verilator_flags2 => ["t/t_lib_prot_secret.v", '--no-timing'], - xsim_flags2 => ["t/t_lib_prot_secret.v"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt} && $Self->{trace}) { - # We can see the ports of the secret module - file_grep("$Self->{obj_dir}/simx.vcd", qr/accum_in/); - # and we can see what's inside (because we didn't use --protect-lib) - file_grep("$Self->{obj_dir}/simx.vcd", qr/secret_/); -} - -ok(1); -1; diff --git a/test_regress/t/t_lib_nolib.py b/test_regress/t/t_lib_nolib.py new file mode 100755 index 000000000..3c4e861ab --- /dev/null +++ b/test_regress/t/t_lib_nolib.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all', 'xsim') +test.top_filename = "t/t_lib_prot.v" + +if test.benchmark: + test.sim_time = test.benchmark * 100 + +trace_opt = ("" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace") + +# Tests the same code as t_lib_prot.py but without --protect-lib +test.compile(verilator_flags2=['--no-timing', trace_opt, "t/t_lib_prot_secret.v"], + xsim_flags2=["t/t_lib_prot_secret.v"]) + +test.execute() + +if test.vlt and test.trace: + # We can see the ports of the secret module + test.file_grep(test.trace_filename, r'accum_in') + # and we can see what's inside (because we didn't use --protect-lib) + test.file_grep(test.trace_filename, r'secret_') + +test.passes() diff --git a/test_regress/t/t_lib_prot.pl b/test_regress/t/t_lib_prot.pl deleted file mode 100755 index dddc68012..000000000 --- a/test_regress/t/t_lib_prot.pl +++ /dev/null @@ -1,76 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1, xsim => 1); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - '--no-timing', - "--prefix", - "Vt_lib_prot_secret", - "-cc", - "-Mdir", - $secret_dir, - "--protect-lib", - $secret_prefix, - "--protect-key", - "secret-key", - "t/t_lib_prot_secret.v"], - verilator_run => 1, - ); - last if $Self->{errors}; - - run(logfile => "$secret_dir/secret_gcc.log", - cmd=>[$ENV{MAKE}, - "-C", - $secret_dir, - "-f", - "Vt_lib_prot_secret.mk"]); - last if $Self->{errors}; - - compile( - verilator_flags2 => ["$secret_dir/secret.sv", - '--no-timing', - "-LDFLAGS", - "$secret_prefix/libsecret.a"], - xsim_flags2 => ["$secret_dir/secret.sv"], - ); - - execute( - check_finished => 1, - xsim_run_flags2 => ["--sv_lib", - "$secret_dir/libsecret", - "--dpi_absolute"], - ); - - if ($Self->{vlt} && $Self->{trace}) { - # We can see the ports of the secret module - file_grep("$Self->{obj_dir}/simx.vcd", qr/accum_in/); - # but we can't see what's inside - file_grep_not("$Self->{obj_dir}/simx.vcd", qr/secret_/); - } - - ok(1); - last; -} -1; diff --git a/test_regress/t/t_lib_prot.py b/test_regress/t/t_lib_prot.py new file mode 100755 index 000000000..fdec419c3 --- /dev/null +++ b/test_regress/t/t_lib_prot.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt', 'xsim') + +if test.benchmark: + test.sim_time = test.benchmark * 100 + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) +trace_opt = "" + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run(logfile=secret_dir + "/vlt_compile.log", + cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + '--no-timing', + trace_opt, + "--prefix", "Vt_lib_prot_secret", + "-cc", + "-Mdir", secret_dir, + "--protect-lib", secret_prefix, + "--protect-key", "secret-key", + "t/t_lib_prot_secret.v"], + verilator_run=True) # yapf:disable + +test.run(logfile=secret_dir + "/secret_gcc.log", + cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) + +test.compile(verilator_flags2=['--no-timing', + trace_opt, + "-LDFLAGS", secret_prefix + "/libsecret.a", + secret_dir + "/secret.sv"], + xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable + +test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) + +if test.vlt and test.trace: + # We can see the ports of the secret module + test.file_grep(test.trace_filename, r'accum_in') + # but we can't see what's inside + test.file_grep_not(test.trace_filename, r'secret_') + +test.passes() diff --git a/test_regress/t/t_lib_prot_clk_gated.pl b/test_regress/t/t_lib_prot_clk_gated.pl deleted file mode 100755 index 787f69ad9..000000000 --- a/test_regress/t/t_lib_prot_clk_gated.pl +++ /dev/null @@ -1,79 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1, xsim => 1); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; - -top_filename("t/t_lib_prot.v"); -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - '--no-timing', - "--prefix", - "Vt_lib_prot_secret", - "-cc", - "-Mdir", - $secret_dir, - "-GGATED_CLK=1", - "--protect-lib", - $secret_prefix, - "--protect-key", - "secret-key", - "t/t_lib_prot_secret.v"], - verilator_run => 1, - ); - last if $Self->{errors}; - - run(logfile => "$secret_dir/secret_gcc.log", - cmd=>[$ENV{MAKE}, - "-C", - $secret_dir, - "-f", - "Vt_lib_prot_secret.mk"]); - last if $Self->{errors}; - - compile( - verilator_flags2 => ["$secret_dir/secret.sv", - '--no-timing', - "-GGATED_CLK=1", - "-LDFLAGS", - "$secret_prefix/libsecret.a"], - xsim_flags2 => ["$secret_dir/secret.sv"], - ); - - execute( - check_finished => 1, - xsim_run_flags2 => ["--sv_lib", - "$secret_dir/libsecret", - "--dpi_absolute"], - ); - - if ($Self->{vlt} && $Self->{trace}) { - # We can see the ports of the secret module - file_grep("$Self->{obj_dir}/simx.vcd", qr/accum_in/); - # but we can't see what's inside - file_grep_not("$Self->{obj_dir}/simx.vcd", qr/secret_/); - } - - ok(1); - last; -} -1; diff --git a/test_regress/t/t_lib_prot_clk_gated.py b/test_regress/t/t_lib_prot_clk_gated.py new file mode 100755 index 000000000..c7e7c897f --- /dev/null +++ b/test_regress/t/t_lib_prot_clk_gated.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt', 'xsim') +test.top_filename = "t/t_lib_prot.v" + +if test.benchmark: + test.sim_time = test.benchmark * 100 + +trace_opt = "" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run( + logfile=secret_dir + "/vlt_compile.log", + cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + '--no-timing', + trace_opt, + "--prefix", "Vt_lib_prot_secret", + "-cc", + "-Mdir", secret_dir, + "-GGATED_CLK=1", + "--protect-lib", secret_prefix, + "--protect-key", "secret-key", + "t/t_lib_prot_secret.v"], + verilator_run=True) # yapf:disable + +test.run(logfile=secret_dir + "/secret_gcc.log", + cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) + +test.compile(verilator_flags2=['--no-timing', + trace_opt, + "-GGATED_CLK=1", + "-LDFLAGS", secret_prefix + "/libsecret.a", + secret_dir + "/secret.sv"], + xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable + +test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) + +if test.vlt and test.trace: + # We can see the ports of the secret module + test.file_grep(test.trace_filename, r'accum_in') + # but we can't see what's inside + test.file_grep_not(test.trace_filename, r'secret_') + +test.passes() diff --git a/test_regress/t/t_lib_prot_comb.pl b/test_regress/t/t_lib_prot_comb.pl deleted file mode 100755 index 961af3799..000000000 --- a/test_regress/t/t_lib_prot_comb.pl +++ /dev/null @@ -1,68 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1, xsim => 1); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - "--prefix", - "Vt_lib_prot_secret", - "-cc", - "-Mdir", - $secret_dir, - "--protect-lib", - $secret_prefix, - "--protect-key", - "secret-key", - "t/t_lib_prot_comb.v"], - verilator_run => 1, - ); - last if $Self->{errors}; - - run(logfile => "$secret_dir/secret_gcc.log", - cmd=>[$ENV{MAKE}, - "-C", - $secret_dir, - "-f", - "Vt_lib_prot_secret.mk"]); - last if $Self->{errors}; - - compile( - verilator_flags2 => ["$secret_dir/secret.sv", - "+define+PROCESS_TOP", - "-LDFLAGS", - "$secret_prefix/libsecret.a"], - xsim_flags2 => ["$secret_dir/secret.sv"], - ); - - execute( - check_finished => 1, - xsim_run_flags2 => ["--sv_lib", - "$secret_dir/libsecret", - "--dpi_absolute"], - ); - - ok(1); - last; -} -1; diff --git a/test_regress/t/t_lib_prot_comb.py b/test_regress/t/t_lib_prot_comb.py new file mode 100755 index 000000000..4a314fcbd --- /dev/null +++ b/test_regress/t/t_lib_prot_comb.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all', 'xsim') + +if test.benchmark: + test.sim_time = test.benchmark * 100 + +trace_opt = "" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run( + logfile=secret_dir + "/vlt_compile.log", + cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + "-cc", + trace_opt, + "--prefix", "Vt_lib_prot_secret", + "-Mdir", secret_dir, + "--protect-lib", secret_prefix, + "--protect-key", "secret-key", + "t/t_lib_prot_comb.v"], + verilator_run=True) # yapf:disable + +test.run(logfile=secret_dir + "/secret_gcc.log", + cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) + +test.compile( + verilator_flags2=[ + secret_dir + "/secret.sv", + "+define+PROCESS_TOP", + "-LDFLAGS",secret_prefix + "/libsecret.a"], + xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable + +test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) + +test.passes() diff --git a/test_regress/t/t_lib_prot_delay_bad.pl b/test_regress/t/t_lib_prot_delay_bad.pl deleted file mode 100755 index 802270587..000000000 --- a/test_regress/t/t_lib_prot_delay_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile ( - verilator_flags2 => ["--protect-lib", - "secret", - "--protect-key", - "secret-key", - "--timing", - ], - verilator_make_gcc => 0, - make_main => 0, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lib_prot_delay_bad.py b/test_regress/t/t_lib_prot_delay_bad.py new file mode 100755 index 000000000..edbc0bdc5 --- /dev/null +++ b/test_regress/t/t_lib_prot_delay_bad.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=[ + "--protect-lib", + "secret", + "--protect-key", + "secret-key", + "--timing", +], + verilator_make_gcc=False, + make_main=False, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lib_prot_exe_bad.pl b/test_regress/t/t_lib_prot_exe_bad.pl deleted file mode 100755 index 9700f4120..000000000 --- a/test_regress/t/t_lib_prot_exe_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile ( - verilator_flags2 => ["--protect-lib", - "secret", - "--protect-key", - "secret-key", - ], - verilator_make_gcc => 0, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lib_prot_exe_bad.py b/test_regress/t/t_lib_prot_exe_bad.py new file mode 100755 index 000000000..236b2a27a --- /dev/null +++ b/test_regress/t/t_lib_prot_exe_bad.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=[ + "--protect-lib", + "secret", + "--protect-key", + "secret-key", +], + verilator_make_gcc=False, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lib_prot_inout_bad.pl b/test_regress/t/t_lib_prot_inout_bad.pl deleted file mode 100755 index 375b280ce..000000000 --- a/test_regress/t/t_lib_prot_inout_bad.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile ( - verilator_flags2 => ["--protect-lib", - "secret", - "--protect-key", - "secret-key" - ], - verilator_make_gcc => 0, - make_main => 0, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -#run(cmd=>["make", -# "-C", -# "$Self->{obj_dir}", -# "-f", -# "V$Self->{name}.mk"]); - -ok(1); -1; diff --git a/test_regress/t/t_lib_prot_inout_bad.py b/test_regress/t/t_lib_prot_inout_bad.py new file mode 100755 index 000000000..4ca020c38 --- /dev/null +++ b/test_regress/t/t_lib_prot_inout_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--protect-lib", "secret", "--protect-key", "secret-key"], + verilator_make_gcc=False, + make_main=False, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lib_prot_secret.pl b/test_regress/t/t_lib_prot_secret.pl deleted file mode 100755 index 18efa9ff7..000000000 --- a/test_regress/t/t_lib_prot_secret.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile ( - verilator_flags2 => ["--protect-lib", - "secret", - "--protect-key", - "SECRET_FAKE_KEY"], - verilator_make_gcc => 0, - verilator_make_gmake => 0, - make_main => 0, - make_top_shell => 0, - ); - -run(cmd=>[$ENV{MAKE}, - "-C", - "$Self->{obj_dir}", - "-f", - "V$Self->{name}.mk"]); - -ok(1); -1; diff --git a/test_regress/t/t_lib_prot_secret.py b/test_regress/t/t_lib_prot_secret.py new file mode 100755 index 000000000..d0e834c5a --- /dev/null +++ b/test_regress/t/t_lib_prot_secret.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--protect-lib", "secret", "--protect-key", "SECRET_FAKE_KEY"], + verilator_make_gcc=False, + verilator_make_gmake=False, + make_main=False, + make_top_shell=False) + +test.run(cmd=[os.environ["MAKE"], "-C", test.obj_dir, "-f", "V" + test.name + ".mk"]) + +test.passes() diff --git a/test_regress/t/t_lib_prot_shared.pl b/test_regress/t/t_lib_prot_shared.pl deleted file mode 100755 index 02d95a9e7..000000000 --- a/test_regress/t/t_lib_prot_shared.pl +++ /dev/null @@ -1,82 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1, xsim => 1); -top_filename("t/t_lib_prot.v"); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -my $abs_secret_dir = File::Spec->rel2abs($secret_dir); -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - ($Self->{vltmt} ? ' --threads 6' : ''), - '--no-timing', - "--prefix", - "Vt_lib_prot_secret", - "-cc", - "-Mdir", - $secret_dir, - "--protect-lib", - $secret_prefix, - "--protect-key", - "secret-key", - "t/t_lib_prot_secret.v"], - verilator_run => 1, - ); - last if $Self->{errors}; - - run(logfile => "$secret_dir/secret_gcc.log", - cmd=>[$ENV{MAKE}, - "-C", - $secret_dir, - "-f", - "Vt_lib_prot_secret.mk"]); - last if $Self->{errors}; - - compile( - verilator_flags2 => ["$secret_dir/secret.sv", - '--no-timing', - "-LDFLAGS", - "'-Wl,-rpath,$abs_secret_dir -L$abs_secret_dir -l$secret_prefix'"], - xsim_flags2 => ["$secret_dir/secret.sv"], - threads => 1, - context_threads => $Self->{vltmt} ? 6 : 1 - ); - - execute( - check_finished => 1, - run_env => "DYLD_FALLBACK_LIBRARY_PATH=$abs_secret_dir", - xsim_run_flags2 => ["--sv_lib", - "$secret_dir/libsecret", - "--dpi_absolute"], - ); - - if ($Self->{vlt} && $Self->{trace}) { - # We can see the ports of the secret module - file_grep("$Self->{obj_dir}/simx.vcd", qr/accum_in/); - # but we can't see what's inside - file_grep_not("$Self->{obj_dir}/simx.vcd", qr/secret_/); - } - - ok(1); - last; -} -1; diff --git a/test_regress/t/t_lib_prot_shared.py b/test_regress/t/t_lib_prot_shared.py new file mode 100755 index 000000000..17f750203 --- /dev/null +++ b/test_regress/t/t_lib_prot_shared.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all', 'xsim') +test.top_filename = "t/t_lib_prot.v" + +if test.benchmark: + test.sim_time = test.benchmark * 100 + +trace_opt = "" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +abs_secret_dir = os.path.abspath(secret_dir) +test.mkdir_ok(secret_dir) + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run(logfile=secret_dir + "/vlt_compile.log", + cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + (' --threads 6' if test.vltmt else ''), + '--no-timing', + "--prefix", "Vt_lib_prot_secret", + "-cc", + "-Mdir", secret_dir, + "--protect-lib", secret_prefix, + "--protect-key", "secret-key", + "t/t_lib_prot_secret.v"], + verilator_run=True) # yapf:disable + +test.run(logfile=secret_dir + "/secret_gcc.log", + cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) + +test.compile(verilator_flags2=['--no-timing', + "-LDFLAGS", "'-Wl,-rpath," + abs_secret_dir + " -L" + abs_secret_dir + " -l" + secret_prefix + "'", + secret_dir + "/secret.sv"], + xsim_flags2=[secret_dir + "/secret.sv"], + threads=1, + context_threads=(6 if test.vltmt else 1)) # yapf:disable + +test.execute(run_env="DYLD_FALLBACK_LIBRARY_PATH=" + abs_secret_dir, + xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) + +if test.vlt and test.trace: + # We can see the ports of the secret module + test.file_grep(test.trace_filename, r'accum_in') + # but we can't see what's inside + test.file_grep_not(test.trace_filename, r'secret_') + +test.passes() diff --git a/test_regress/t/t_lint_always_comb_bad.pl b/test_regress/t/t_lint_always_comb_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_always_comb_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_always_comb_bad.py b/test_regress/t/t_lint_always_comb_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_always_comb_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_always_comb_iface.pl b/test_regress/t/t_lint_always_comb_iface.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_always_comb_iface.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_always_comb_iface.py b/test_regress/t/t_lint_always_comb_iface.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_always_comb_iface.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_always_comb_multidriven_bad.pl b/test_regress/t/t_lint_always_comb_multidriven_bad.pl deleted file mode 100755 index 4786ecc50..000000000 --- a/test_regress/t/t_lint_always_comb_multidriven_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--lint-only'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_always_comb_multidriven_bad.py b/test_regress/t/t_lint_always_comb_multidriven_bad.py new file mode 100755 index 000000000..d6dde1012 --- /dev/null +++ b/test_regress/t/t_lint_always_comb_multidriven_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.pl b/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.pl deleted file mode 100755 index 48576365b..000000000 --- a/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_lint_always_comb_multidriven_bad.v"); - -lint( - verilator_flags2 => ['--public-flat-rw --lint-only'], - fails => 1, - expect_filename => "t/t_lint_always_comb_multidriven_bad.out", - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.py b/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.py new file mode 100755 index 000000000..58bab8994 --- /dev/null +++ b/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_always_comb_multidriven_bad.v" + +test.lint(verilator_flags2=['--public-flat-rw --lint-only'], + fails=True, + expect_filename="t/t_lint_always_comb_multidriven_bad.out") + +test.passes() diff --git a/test_regress/t/t_lint_blksync_bad.pl b/test_regress/t/t_lint_blksync_bad.pl deleted file mode 100755 index 57bd2d964..000000000 --- a/test_regress/t/t_lint_blksync_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_blksync_bad.py b/test_regress/t/t_lint_blksync_bad.py new file mode 100755 index 000000000..f27c3eae1 --- /dev/null +++ b/test_regress/t/t_lint_blksync_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_blksync_loop.pl b/test_regress/t/t_lint_blksync_loop.pl deleted file mode 100755 index 8a474235a..000000000 --- a/test_regress/t/t_lint_blksync_loop.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_blksync_loop.py b/test_regress/t/t_lint_blksync_loop.py new file mode 100755 index 000000000..e822338c0 --- /dev/null +++ b/test_regress/t/t_lint_blksync_loop.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"]) + +test.passes() diff --git a/test_regress/t/t_lint_block_redecl_bad.out b/test_regress/t/t_lint_block_redecl_bad.out index a3729f293..257b5fb51 100644 --- a/test_regress/t/t_lint_block_redecl_bad.out +++ b/test_regress/t/t_lint_block_redecl_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_lint_block_redecl_bad.v:21:34: Duplicate declaration of block: 'COMB' - 21 | for(i=0; i<9; i++ ) begin: COMB +%Error: t/t_lint_block_redecl_bad.v:17:34: Duplicate declaration of block: 'COMB' + 17 | for(i=0; i<9; i++ ) begin: COMB | ^~~~ - t/t_lint_block_redecl_bad.v:18:35: ... Location of original declaration - 18 | for(i=0; i<10; i++ ) begin: COMB + t/t_lint_block_redecl_bad.v:14:35: ... Location of original declaration + 14 | for(i=0; i<10; i++ ) begin: COMB | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_block_redecl_bad.pl b/test_regress/t/t_lint_block_redecl_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_lint_block_redecl_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_block_redecl_bad.py b/test_regress/t/t_lint_block_redecl_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_block_redecl_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_block_redecl_bad.v b/test_regress/t/t_lint_block_redecl_bad.v index 0536ef0c3..fac1d041e 100644 --- a/test_regress/t/t_lint_block_redecl_bad.v +++ b/test_regress/t/t_lint_block_redecl_bad.v @@ -6,11 +6,7 @@ //bug485, but see t_gen_forif.v for an OK example. -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); always_comb begin integer i; diff --git a/test_regress/t/t_lint_bsspace_bad.pl b/test_regress/t/t_lint_bsspace_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_lint_bsspace_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_bsspace_bad.py b/test_regress/t/t_lint_bsspace_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_bsspace_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_caseincomplete_bad.pl b/test_regress/t/t_lint_caseincomplete_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_caseincomplete_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_caseincomplete_bad.py b/test_regress/t/t_lint_caseincomplete_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_caseincomplete_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_cmpconst_bad.pl b/test_regress/t/t_lint_cmpconst_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_cmpconst_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_cmpconst_bad.py b/test_regress/t/t_lint_cmpconst_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_cmpconst_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_colonplus_bad.pl b/test_regress/t/t_lint_colonplus_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_lint_colonplus_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_colonplus_bad.py b/test_regress/t/t_lint_colonplus_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_colonplus_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_comb_bad.pl b/test_regress/t/t_lint_comb_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_lint_comb_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_comb_bad.py b/test_regress/t/t_lint_comb_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_comb_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_comb_use.pl b/test_regress/t/t_lint_comb_use.pl deleted file mode 100755 index 9c58f64a3..000000000 --- a/test_regress/t/t_lint_comb_use.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-sys"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_comb_use.py b/test_regress/t/t_lint_comb_use.py new file mode 100755 index 000000000..b39e4b760 --- /dev/null +++ b/test_regress/t/t_lint_comb_use.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --bbox-sys"]) + +test.passes() diff --git a/test_regress/t/t_lint_const_func_dpi_bad.pl b/test_regress/t/t_lint_const_func_dpi_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_lint_const_func_dpi_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_const_func_dpi_bad.py b/test_regress/t/t_lint_const_func_dpi_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_const_func_dpi_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_const_func_gen_bad.pl b/test_regress/t/t_lint_const_func_gen_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_lint_const_func_gen_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_const_func_gen_bad.py b/test_regress/t/t_lint_const_func_gen_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_const_func_gen_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_contassreg_bad.pl b/test_regress/t/t_lint_contassreg_bad.pl deleted file mode 100755 index 46010fd1c..000000000 --- a/test_regress/t/t_lint_contassreg_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ['--language 1364-2001'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_contassreg_bad.py b/test_regress/t/t_lint_contassreg_bad.py new file mode 100755 index 000000000..129a49d56 --- /dev/null +++ b/test_regress/t/t_lint_contassreg_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--language 1364-2001'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_declfilename.pl b/test_regress/t/t_lint_declfilename.pl deleted file mode 100755 index 1366501ca..000000000 --- a/test_regress/t/t_lint_declfilename.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_declfilename.py b/test_regress/t/t_lint_declfilename.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_declfilename.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_declfilename_bad.pl b/test_regress/t/t_lint_declfilename_bad.pl deleted file mode 100755 index a884e811f..000000000 --- a/test_regress/t/t_lint_declfilename_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_lint_declfilename.v"); - -lint( - verilator_flags2 => ["--lint-only -Wall"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_declfilename_bad.py b/test_regress/t/t_lint_declfilename_bad.py new file mode 100755 index 000000000..8877eb52f --- /dev/null +++ b/test_regress/t/t_lint_declfilename_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_declfilename.v" + +test.lint(verilator_flags2=["--lint-only -Wall"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_declfilename_bbox.pl b/test_regress/t/t_lint_declfilename_bbox.pl deleted file mode 100755 index f73da325a..000000000 --- a/test_regress/t/t_lint_declfilename_bbox.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_declfilename_bbox.py b/test_regress/t/t_lint_declfilename_bbox.py new file mode 100755 index 000000000..f31da0fcd --- /dev/null +++ b/test_regress/t/t_lint_declfilename_bbox.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall"]) + +test.passes() diff --git a/test_regress/t/t_lint_defparam.pl b/test_regress/t/t_lint_defparam.pl deleted file mode 100755 index 1366501ca..000000000 --- a/test_regress/t/t_lint_defparam.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_defparam.py b/test_regress/t/t_lint_defparam.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_defparam.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_defparam_bad.pl b/test_regress/t/t_lint_defparam_bad.pl deleted file mode 100755 index 9b7fa451e..000000000 --- a/test_regress/t/t_lint_defparam_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_lint_defparam.v"); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-style -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_defparam_bad.py b/test_regress/t/t_lint_defparam_bad.py new file mode 100755 index 000000000..a707e9afc --- /dev/null +++ b/test_regress/t/t_lint_defparam_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_defparam.v" + +test.lint(verilator_flags2=["--lint-only -Wwarn-style -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_didnotconverge_bad.pl b/test_regress/t/t_lint_didnotconverge_bad.pl deleted file mode 100755 index 7e7872f63..000000000 --- a/test_regress/t/t_lint_didnotconverge_bad.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - compile( - verilator_flags2 => ["--prof-cfuncs"], - ); - - execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_DIDNOTCONVERGE_faulty.rst", - lines => "16-17"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_DIDNOTCONVERGE_msg.rst", - lines => "1-2"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_didnotconverge_bad.py b/test_regress/t/t_lint_didnotconverge_bad.py new file mode 100755 index 000000000..40e40f26e --- /dev/null +++ b/test_regress/t/t_lint_didnotconverge_bad.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.compile(verilator_flags2=["--prof-cfuncs"]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_DIDNOTCONVERGE_faulty.rst", + lines="16-17") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_DIDNOTCONVERGE_msg.rst", + lines="1-2") + +test.passes() diff --git a/test_regress/t/t_lint_didnotconverge_nodbg_bad.pl b/test_regress/t/t_lint_didnotconverge_nodbg_bad.pl deleted file mode 100755 index b0de186ba..000000000 --- a/test_regress/t/t_lint_didnotconverge_nodbg_bad.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - top_filename("t/t_lint_didnotconverge_bad.v"); - - compile( - make_flags => 'CPPFLAGS_ADD=-UVL_DEBUG', - ); - - execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst", - lines => "1"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_didnotconverge_nodbg_bad.py b/test_regress/t/t_lint_didnotconverge_nodbg_bad.py new file mode 100755 index 000000000..1d53c8c93 --- /dev/null +++ b/test_regress/t/t_lint_didnotconverge_nodbg_bad.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_didnotconverge_bad.v" + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.compile(make_flags=['CPPFLAGS_ADD=-UVL_DEBUG']) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst", + lines="1") + +test.passes() diff --git a/test_regress/t/t_lint_edge_real_bad.pl b/test_regress/t/t_lint_edge_real_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_edge_real_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_edge_real_bad.py b/test_regress/t/t_lint_edge_real_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_edge_real_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_eofline.pl b/test_regress/t/t_lint_eofline.pl deleted file mode 100755 index 709ff432e..000000000 --- a/test_regress/t/t_lint_eofline.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(vlt => 1); - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - # Empty file should not EOFLINE warn -} - -top_filename("$Self->{obj_dir}/t_lint_eofline_bad.v"); - -gen($Self->{top_filename}); - -lint( - verilator_flags2 => ["-E -Wall -Wno-DECLFILENAME"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_eofline.py b/test_regress/t/t_lint_eofline.py new file mode 100755 index 000000000..0c46692ef --- /dev/null +++ b/test_regress/t/t_lint_eofline.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_lint_eofline_bad.v" + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: # pylint: disable=unused-variable + pass + # Empty file should not EOFLINE warn + + +gen(test.top_filename) + +test.lint(verilator_flags2=["-E -Wall -Wno-DECLFILENAME"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_eofline_bad.pl b/test_regress/t/t_lint_eofline_bad.pl deleted file mode 100755 index 1528e4cef..000000000 --- a/test_regress/t/t_lint_eofline_bad.pl +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(vlt => 1); - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_lint_eofline_bad.pl\n"); - $fh->print("module t;\n"); - $fh->print("// No newline below:\n"); - $fh->print("endmodule"); # Intentionally no newline -} - -top_filename("$Self->{obj_dir}/t_lint_eofline_bad.v"); - -gen($Self->{top_filename}); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_eofline_bad.py b/test_regress/t/t_lint_eofline_bad.py new file mode 100755 index 000000000..c39e86fc6 --- /dev/null +++ b/test_regress/t/t_lint_eofline_bad.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_lint_eofline_bad.v" + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_lint_eofline_bad.py\n") + fh.write("module t;\n") + fh.write("// No newline below:\n") + fh.write("endmodule") + # Intentionally no newline + + +gen(test.top_filename) + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_eofline_vlt.pl b/test_regress/t/t_lint_eofline_vlt.pl deleted file mode 100755 index 9bea83d86..000000000 --- a/test_regress/t/t_lint_eofline_vlt.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(vlt => 1); - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_lint_eofline_bad.pl\n"); - $fh->print("module t;\n"); - $fh->print("// No newline below:\n"); - $fh->print("endmodule"); # Intentionally no newline -} - -top_filename("$Self->{obj_dir}/t_lint_eofline_bad.v"); - -gen($Self->{top_filename}); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME t/t_lint_eofline_vlt.vlt"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_eofline_vlt.py b/test_regress/t/t_lint_eofline_vlt.py new file mode 100755 index 000000000..43944fe94 --- /dev/null +++ b/test_regress/t/t_lint_eofline_vlt.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_lint_eofline_bad.v" + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_lint_eofline_bad.py\n") + fh.write("module t;\n") + fh.write("// No newline below:\n") + fh.write("endmodule") + # Intentionally no newline + + +gen(test.top_filename) + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME t/t_lint_eofline_vlt.vlt"]) + +test.passes() diff --git a/test_regress/t/t_lint_ftask_output_assign_bad.pl b/test_regress/t/t_lint_ftask_output_assign_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_lint_ftask_output_assign_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_ftask_output_assign_bad.py b/test_regress/t/t_lint_ftask_output_assign_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_ftask_output_assign_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_genunnamed_bad.pl b/test_regress/t/t_lint_genunnamed_bad.pl deleted file mode 100755 index 4ad25735e..000000000 --- a/test_regress/t/t_lint_genunnamed_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_genunnamed_bad.py b/test_regress/t/t_lint_genunnamed_bad.py new file mode 100755 index 000000000..f05a78df6 --- /dev/null +++ b/test_regress/t/t_lint_genunnamed_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, + verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_historical.pl b/test_regress/t/t_lint_historical.pl deleted file mode 100755 index a6e8d4033..000000000 --- a/test_regress/t/t_lint_historical.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_historical.py b/test_regress/t/t_lint_historical.py new file mode 100755 index 000000000..9ab47796d --- /dev/null +++ b/test_regress/t/t_lint_historical.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only"]) + +test.passes() diff --git a/test_regress/t/t_lint_iface_array_topmodule1.pl b/test_regress/t/t_lint_iface_array_topmodule1.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_array_topmodule1.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_array_topmodule1.py b/test_regress/t/t_lint_iface_array_topmodule1.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_array_topmodule1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_array_topmodule2.pl b/test_regress/t/t_lint_iface_array_topmodule2.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_array_topmodule2.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_array_topmodule2.py b/test_regress/t/t_lint_iface_array_topmodule2.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_array_topmodule2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_array_topmodule3.pl b/test_regress/t/t_lint_iface_array_topmodule3.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_array_topmodule3.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_array_topmodule3.py b/test_regress/t/t_lint_iface_array_topmodule3.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_array_topmodule3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_array_topmodule_bad.pl b/test_regress/t/t_lint_iface_array_topmodule_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_iface_array_topmodule_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_array_topmodule_bad.py b/test_regress/t/t_lint_iface_array_topmodule_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_iface_array_topmodule_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_iface_topmodule1.pl b/test_regress/t/t_lint_iface_topmodule1.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_topmodule1.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_topmodule1.py b/test_regress/t/t_lint_iface_topmodule1.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_topmodule1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_topmodule2.pl b/test_regress/t/t_lint_iface_topmodule2.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_topmodule2.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_topmodule2.py b/test_regress/t/t_lint_iface_topmodule2.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_topmodule2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_topmodule3.pl b/test_regress/t/t_lint_iface_topmodule3.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_topmodule3.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_topmodule3.py b/test_regress/t/t_lint_iface_topmodule3.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_topmodule3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_topmodule_bad.pl b/test_regress/t/t_lint_iface_topmodule_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_iface_topmodule_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_topmodule_bad.py b/test_regress/t/t_lint_iface_topmodule_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_iface_topmodule_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_ifdepth_bad.pl b/test_regress/t/t_lint_ifdepth_bad.pl deleted file mode 100755 index 76be13063..000000000 --- a/test_regress/t/t_lint_ifdepth_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_ifdepth_bad.py b/test_regress/t/t_lint_ifdepth_bad.py new file mode 100755 index 000000000..2d9f441cf --- /dev/null +++ b/test_regress/t/t_lint_ifdepth_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_implicit.pl b/test_regress/t/t_lint_implicit.pl deleted file mode 100755 index f666ab867..000000000 --- a/test_regress/t/t_lint_implicit.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-Wno-IMPLICIT"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_implicit.py b/test_regress/t/t_lint_implicit.py new file mode 100755 index 000000000..837cc7107 --- /dev/null +++ b/test_regress/t/t_lint_implicit.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-Wno-IMPLICIT"]) + +test.passes() diff --git a/test_regress/t/t_lint_implicit_bad.pl b/test_regress/t/t_lint_implicit_bad.pl deleted file mode 100755 index abf5d91f2..000000000 --- a/test_regress/t/t_lint_implicit_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_lint_implicit.v"); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-IMPLICIT"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_implicit_bad.py b/test_regress/t/t_lint_implicit_bad.py new file mode 100755 index 000000000..3713dce09 --- /dev/null +++ b/test_regress/t/t_lint_implicit_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_implicit.v" + +test.lint(verilator_flags2=["--lint-only -Wwarn-IMPLICIT"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_implicit_def_bad.pl b/test_regress/t/t_lint_implicit_def_bad.pl deleted file mode 100755 index 7539b1bd9..000000000 --- a/test_regress/t/t_lint_implicit_def_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_implicit_def_bad.py b/test_regress/t/t_lint_implicit_def_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_implicit_def_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_implicit_func_bad.out b/test_regress/t/t_lint_implicit_func_bad.out new file mode 100644 index 000000000..6d790a04c --- /dev/null +++ b/test_regress/t/t_lint_implicit_func_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_lint_implicit_func_bad.v:12:11: Illegal call of a task as a function: 'imp_func_conflict' + 12 | assign imp_func_conflict = 1'b1; + | ^~~~~~~~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_func_bad.py b/test_regress/t/t_lint_implicit_func_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_implicit_func_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_implicit_func_bad.v b/test_regress/t/t_lint_implicit_func_bad.v new file mode 100644 index 000000000..2d3dbe2fb --- /dev/null +++ b/test_regress/t/t_lint_implicit_func_bad.v @@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + function void imp_func_conflict(); + endfunction + +`default_nettype wire + assign imp_func_conflict = 1'b1; +endmodule diff --git a/test_regress/t/t_lint_implicit_port.pl b/test_regress/t/t_lint_implicit_port.pl deleted file mode 100755 index f666ab867..000000000 --- a/test_regress/t/t_lint_implicit_port.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-Wno-IMPLICIT"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_implicit_port.py b/test_regress/t/t_lint_implicit_port.py new file mode 100755 index 000000000..837cc7107 --- /dev/null +++ b/test_regress/t/t_lint_implicit_port.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-Wno-IMPLICIT"]) + +test.passes() diff --git a/test_regress/t/t_lint_implicit_type_bad.out b/test_regress/t/t_lint_implicit_type_bad.out new file mode 100644 index 000000000..8f0e6e645 --- /dev/null +++ b/test_regress/t/t_lint_implicit_type_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_lint_implicit_type_bad.v:11:11: syntax error, unexpected TYPE-IDENTIFIER + 11 | assign imp_type_conflict = 1'b1; + | ^~~~~~~~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_type_bad.py b/test_regress/t/t_lint_implicit_type_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_implicit_type_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_implicit_type_bad.v b/test_regress/t/t_lint_implicit_type_bad.v new file mode 100644 index 000000000..24a373808 --- /dev/null +++ b/test_regress/t/t_lint_implicit_type_bad.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + typedef int imp_type_conflict; + +`default_nettype wire + assign imp_type_conflict = 1'b1; +endmodule diff --git a/test_regress/t/t_lint_import_name2_bad.pl b/test_regress/t/t_lint_import_name2_bad.pl deleted file mode 100755 index 7539b1bd9..000000000 --- a/test_regress/t/t_lint_import_name2_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_import_name2_bad.py b/test_regress/t/t_lint_import_name2_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_import_name2_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_import_name_bad.out b/test_regress/t/t_lint_import_name_bad.out index 36a7cf18e..03aadb71a 100644 --- a/test_regress/t/t_lint_import_name_bad.out +++ b/test_regress/t/t_lint_import_name_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_lint_import_name_bad.v:11:12: Import object not found: 'defs::sigs' +%Error: t/t_lint_import_name_bad.v:11:12: Import object not found: 'defs' 11 | import defs::sigs; | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_import_name_bad.pl b/test_regress/t/t_lint_import_name_bad.pl deleted file mode 100755 index 7539b1bd9..000000000 --- a/test_regress/t/t_lint_import_name_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_import_name_bad.py b/test_regress/t/t_lint_import_name_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_import_name_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_importstar_bad.pl b/test_regress/t/t_lint_importstar_bad.pl deleted file mode 100755 index 7539b1bd9..000000000 --- a/test_regress/t/t_lint_importstar_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_importstar_bad.py b/test_regress/t/t_lint_importstar_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_importstar_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_in_inc_bad.pl b/test_regress/t/t_lint_in_inc_bad.pl deleted file mode 100755 index 0661a705e..000000000 --- a/test_regress/t/t_lint_in_inc_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - v_flags2 => ["-Wall -Wno-DECLFILENAME --if-depth 10"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_in_inc_bad.py b/test_regress/t/t_lint_in_inc_bad.py new file mode 100755 index 000000000..6307c426b --- /dev/null +++ b/test_regress/t/t_lint_in_inc_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(v_flags2=["-Wall -Wno-DECLFILENAME --if-depth 10"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_incabspath.pl b/test_regress/t/t_lint_incabspath.pl deleted file mode 100755 index 1366501ca..000000000 --- a/test_regress/t/t_lint_incabspath.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_incabspath.py b/test_regress/t/t_lint_incabspath.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_incabspath.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_incabspath_bad.pl b/test_regress/t/t_lint_incabspath_bad.pl deleted file mode 100755 index 80a2b601f..000000000 --- a/test_regress/t/t_lint_incabspath_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_lint_incabspath.v"); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_incabspath_bad.py b/test_regress/t/t_lint_incabspath_bad.py new file mode 100755 index 000000000..a825eadf4 --- /dev/null +++ b/test_regress/t/t_lint_incabspath_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_incabspath.v" + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_infinite.pl b/test_regress/t/t_lint_infinite.pl deleted file mode 100755 index 7964ebe90..000000000 --- a/test_regress/t/t_lint_infinite.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_infinite.py b/test_regress/t/t_lint_infinite.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_lint_infinite.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lint_infinite_bad.pl b/test_regress/t/t_lint_infinite_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_infinite_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_infinite_bad.py b/test_regress/t/t_lint_infinite_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_infinite_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_inherit.pl b/test_regress/t/t_lint_inherit.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_lint_inherit.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_inherit.py b/test_regress/t/t_lint_inherit.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_lint_inherit.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_lint_input_eq_good.pl b/test_regress/t/t_lint_input_eq_good.pl deleted file mode 100755 index 8b318d39c..000000000 --- a/test_regress/t/t_lint_input_eq_good.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_input_eq_good.py b/test_regress/t/t_lint_input_eq_good.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_input_eq_good.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_1.pl b/test_regress/t/t_lint_latch_1.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_1.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_1.py b/test_regress/t/t_lint_latch_1.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_2.pl b/test_regress/t/t_lint_latch_2.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_2.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_2.py b/test_regress/t/t_lint_latch_2.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_3.pl b/test_regress/t/t_lint_latch_3.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_3.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_3.py b/test_regress/t/t_lint_latch_3.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_4.pl b/test_regress/t/t_lint_latch_4.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_4.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_4.py b/test_regress/t/t_lint_latch_4.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_4.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_5.pl b/test_regress/t/t_lint_latch_5.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_5.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_5.py b/test_regress/t/t_lint_latch_5.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_5.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_6.pl b/test_regress/t/t_lint_latch_6.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_6.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_6.py b/test_regress/t/t_lint_latch_6.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_6.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_7.pl b/test_regress/t/t_lint_latch_7.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_7.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_7.py b/test_regress/t/t_lint_latch_7.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_7.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_bad.pl b/test_regress/t/t_lint_latch_bad.pl deleted file mode 100755 index 6755217bb..000000000 --- a/test_regress/t/t_lint_latch_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-style -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_bad.py b/test_regress/t/t_lint_latch_bad.py new file mode 100755 index 000000000..8441aff14 --- /dev/null +++ b/test_regress/t/t_lint_latch_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wwarn-style -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_latch_bad_2.pl b/test_regress/t/t_lint_latch_bad_2.pl deleted file mode 100755 index 70301e9b6..000000000 --- a/test_regress/t/t_lint_latch_bad_2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_bad_2.py b/test_regress/t/t_lint_latch_bad_2.py new file mode 100755 index 000000000..dece38f4e --- /dev/null +++ b/test_regress/t/t_lint_latch_bad_2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_latch_bad_3.pl b/test_regress/t/t_lint_latch_bad_3.pl deleted file mode 100755 index 70301e9b6..000000000 --- a/test_regress/t/t_lint_latch_bad_3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_bad_3.py b/test_regress/t/t_lint_latch_bad_3.py new file mode 100755 index 000000000..dece38f4e --- /dev/null +++ b/test_regress/t/t_lint_latch_bad_3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_literal_bad.pl b/test_regress/t/t_lint_literal_bad.pl deleted file mode 100755 index 5ece32e17..000000000 --- a/test_regress/t/t_lint_literal_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_literal_bad.py b/test_regress/t/t_lint_literal_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_literal_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_misindent_bad.pl b/test_regress/t/t_lint_misindent_bad.pl deleted file mode 100755 index 4ad25735e..000000000 --- a/test_regress/t/t_lint_misindent_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_misindent_bad.py b/test_regress/t/t_lint_misindent_bad.py new file mode 100755 index 000000000..f05a78df6 --- /dev/null +++ b/test_regress/t/t_lint_misindent_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, + verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_mod_paren_bad.pl b/test_regress/t/t_lint_mod_paren_bad.pl deleted file mode 100755 index 0b0675898..000000000 --- a/test_regress/t/t_lint_mod_paren_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_mod_paren_bad.py b/test_regress/t/t_lint_mod_paren_bad.py new file mode 100755 index 000000000..3ce9351b2 --- /dev/null +++ b/test_regress/t/t_lint_mod_paren_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_modport_dir_bad.pl b/test_regress/t/t_lint_modport_dir_bad.pl deleted file mode 100755 index abf587bd3..000000000 --- a/test_regress/t/t_lint_modport_dir_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_modport_dir_bad.py b/test_regress/t/t_lint_modport_dir_bad.py new file mode 100755 index 000000000..53e81eb85 --- /dev/null +++ b/test_regress/t/t_lint_modport_dir_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_multidriven_bad.out b/test_regress/t/t_lint_multidriven_bad.out index 788f63032..5c68a4018 100644 --- a/test_regress/t/t_lint_multidriven_bad.out +++ b/test_regress/t/t_lint_multidriven_bad.out @@ -1,17 +1,17 @@ -%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:22: Signal has multiple driving blocks with different clocking: 'out2' - t/t_lint_multidriven_bad.v:35:7: ... Location of first driving block - 35 | out2[15:8] <= d0; - | ^~~~ - t/t_lint_multidriven_bad.v:32:7: ... Location of other driving block - 32 | out2[7:0] <= d0; - | ^~~~ - ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest - ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:21:22: Signal has multiple driving blocks with different clocking: 't.mem' - t/t_lint_multidriven_bad.v:27:7: ... Location of first driving block - 27 | mem[a0] <= d1; - | ^~~ - t/t_lint_multidriven_bad.v:24:7: ... Location of other driving block + t/t_lint_multidriven_bad.v:24:7: ... Location of first driving block 24 | mem[a0] <= d0; | ^~~ + t/t_lint_multidriven_bad.v:27:7: ... Location of other driving block + 27 | mem[a0] <= d1; + | ^~~ + ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest + ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. +%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:22: Signal has multiple driving blocks with different clocking: 'out2' + t/t_lint_multidriven_bad.v:32:7: ... Location of first driving block + 32 | out2[7:0] <= d0; + | ^~~~ + t/t_lint_multidriven_bad.v:35:7: ... Location of other driving block + 35 | out2[15:8] <= d0; + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_multidriven_bad.pl b/test_regress/t/t_lint_multidriven_bad.pl deleted file mode 100755 index 2ec245f15..000000000 --- a/test_regress/t/t_lint_multidriven_bad.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_MULTIDRIVEN_faulty.rst", - lines => "31-36"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_MULTIDRIVEN_msg.rst", - lines => "10,11,14"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_multidriven_bad.py b/test_regress/t/t_lint_multidriven_bad.py new file mode 100755 index 000000000..ed3410fdd --- /dev/null +++ b/test_regress/t/t_lint_multidriven_bad.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_MULTIDRIVEN_faulty.rst", + lines="31-36") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_MULTIDRIVEN_msg.rst", + lines="10,11,14") + +test.passes() diff --git a/test_regress/t/t_lint_nolatch_bad.pl b/test_regress/t/t_lint_nolatch_bad.pl deleted file mode 100755 index a8b75812f..000000000 --- a/test_regress/t/t_lint_nolatch_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_nolatch_bad.py b/test_regress/t/t_lint_nolatch_bad.py new file mode 100755 index 000000000..dece38f4e --- /dev/null +++ b/test_regress/t/t_lint_nolatch_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_nullport_bad.pl b/test_regress/t/t_lint_nullport_bad.pl deleted file mode 100755 index 4f29861db..000000000 --- a/test_regress/t/t_lint_nullport_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_nullport_bad.py b/test_regress/t/t_lint_nullport_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_nullport_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_numwidth.pl b/test_regress/t/t_lint_numwidth.pl deleted file mode 100755 index 9fe706c85..000000000 --- a/test_regress/t/t_lint_numwidth.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--max-num-width 131072"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_numwidth.py b/test_regress/t/t_lint_numwidth.py new file mode 100755 index 000000000..9f7577b1b --- /dev/null +++ b/test_regress/t/t_lint_numwidth.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--max-num-width 131072"]) + +test.passes() diff --git a/test_regress/t/t_lint_once_bad.pl b/test_regress/t/t_lint_once_bad.pl deleted file mode 100755 index 4937974bc..000000000 --- a/test_regress/t/t_lint_once_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-UNUSED"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_once_bad.py b/test_regress/t/t_lint_once_bad.py new file mode 100755 index 000000000..9690ccd5f --- /dev/null +++ b/test_regress/t/t_lint_once_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-UNUSED"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_only.pl b/test_regress/t/t_lint_only.pl deleted file mode 100755 index d1e2ac8bc..000000000 --- a/test_regress/t/t_lint_only.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -foreach my $file (glob("$Self->{obj_dir}/*")) { - next if $file =~ /\.log/; # Made by driver.pl, not Verilator sources - next if $file =~ /\.status/; # Made by driver.pl, not Verilator sources - next if $file =~ /\.gcda/; # Made by gcov, not Verilator sources - error("%Error: Created $file, but --lint-only shouldn't create files"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_only.py b/test_regress/t/t_lint_only.py new file mode 100755 index 000000000..6bd600182 --- /dev/null +++ b/test_regress/t/t_lint_only.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +for filename in glob.glob(test.obj_dir + "/*"): + if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources + or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources + or re.search(r'\.gcda', filename)): # Made by gcov, not Verilator sources + continue + test.error("%Error: Created '" + filename + "', but --lint-only shouldn't create files") + +test.passes() diff --git a/test_regress/t/t_lint_pindup_bad.pl b/test_regress/t/t_lint_pindup_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_pindup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pindup_bad.py b/test_regress/t/t_lint_pindup_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_pindup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_pinmissing_bad.pl b/test_regress/t/t_lint_pinmissing_bad.pl deleted file mode 100755 index b48fa0bc9..000000000 --- a/test_regress/t/t_lint_pinmissing_bad.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_PINMISSING_faulty.rst", - lines => "7-12"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_PINMISSING_msg.rst", - lines => "1-1"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_pinmissing_bad.py b/test_regress/t/t_lint_pinmissing_bad.py new file mode 100755 index 000000000..3f80106f9 --- /dev/null +++ b/test_regress/t/t_lint_pinmissing_bad.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_PINMISSING_faulty.rst", + lines="7-12") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_PINMISSING_msg.rst", + lines="1-1") + +test.passes() diff --git a/test_regress/t/t_lint_pinnotfound.pl b/test_regress/t/t_lint_pinnotfound.pl deleted file mode 100755 index aca1cb3c1..000000000 --- a/test_regress/t/t_lint_pinnotfound.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pinnotfound.py b/test_regress/t/t_lint_pinnotfound.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_pinnotfound_bad.pl b/test_regress/t/t_lint_pinnotfound_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_pinnotfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pinnotfound_bad.py b/test_regress/t/t_lint_pinnotfound_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_pkg_colon_bad.pl b/test_regress/t/t_lint_pkg_colon_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_pkg_colon_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pkg_colon_bad.py b/test_regress/t/t_lint_pkg_colon_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_pkg_colon_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_pkgnodecl_bad.pl b/test_regress/t/t_lint_pkgnodecl_bad.pl deleted file mode 100755 index 7a81df912..000000000 --- a/test_regress/t/t_lint_pkgnodecl_bad.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_PKGNODECL_faulty.rst", - lines => "7-12"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_PKGNODECL_msg.rst", - lines => "1"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_pkgnodecl_bad.py b/test_regress/t/t_lint_pkgnodecl_bad.py new file mode 100755 index 000000000..21d9be319 --- /dev/null +++ b/test_regress/t/t_lint_pkgnodecl_bad.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_PKGNODECL_faulty.rst", + lines="7-12") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_PKGNODECL_msg.rst", + lines="1") + +test.passes() diff --git a/test_regress/t/t_lint_pragma_protected.pl b/test_regress/t/t_lint_pragma_protected.pl deleted file mode 100755 index 26a2c09ae..000000000 --- a/test_regress/t/t_lint_pragma_protected.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - - -lint( - verilator_flags2 => ['--lint-only -Wno-PROTECTED'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pragma_protected.py b/test_regress/t/t_lint_pragma_protected.py new file mode 100755 index 000000000..e0fa30056 --- /dev/null +++ b/test_regress/t/t_lint_pragma_protected.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only -Wno-PROTECTED']) + +test.passes() diff --git a/test_regress/t/t_lint_pragma_protected_bad.pl b/test_regress/t/t_lint_pragma_protected_bad.pl deleted file mode 100755 index ad84f1b54..000000000 --- a/test_regress/t/t_lint_pragma_protected_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - verilator_flags2 => ['--lint-only -Wpedantic'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pragma_protected_bad.py b/test_regress/t/t_lint_pragma_protected_bad.py new file mode 100755 index 000000000..dde27733d --- /dev/null +++ b/test_regress/t/t_lint_pragma_protected_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, + verilator_flags2=['--lint-only -Wpedantic'], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_realcvt_bad.out b/test_regress/t/t_lint_realcvt_bad.out index 41625798c..b68e7e362 100644 --- a/test_regress/t/t_lint_realcvt_bad.out +++ b/test_regress/t/t_lint_realcvt_bad.out @@ -1,6 +1,15 @@ -%Warning-REALCVT: t/t_lint_realcvt_bad.v:10:11: Implicit conversion of real to integer - 10 | i = 23.2; - | ^~~~ +%Warning-REALCVT: t/t_lint_realcvt_bad.v:12:18: Implicit conversion of real to integer + 12 | time t_bad1 = 9.001ns; + | ^~~~~~~ ... For warning description see https://verilator.org/warn/REALCVT?v=latest ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. +%Warning-REALCVT: t/t_lint_realcvt_bad.v:13:18: Implicit conversion of real to integer + 13 | time t_bad2 = 9.999ns; + | ^~~~~~~ +%Warning-REALCVT: t/t_lint_realcvt_bad.v:17:18: Implicit conversion of real to integer + 17 | time t_bad3 = 9ps; + | ^~~ +%Warning-REALCVT: t/t_lint_realcvt_bad.v:23:22: Implicit conversion of real to integer + 23 | integer i_bad21 = 23.1; + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_realcvt_bad.pl b/test_regress/t/t_lint_realcvt_bad.pl deleted file mode 100755 index 49de1747e..000000000 --- a/test_regress/t/t_lint_realcvt_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-REALCVT"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_realcvt_bad.py b/test_regress/t/t_lint_realcvt_bad.py new file mode 100755 index 000000000..acbdae169 --- /dev/null +++ b/test_regress/t/t_lint_realcvt_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-REALCVT"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_realcvt_bad.v b/test_regress/t/t_lint_realcvt_bad.v index 3ebd6ed7c..daefdda26 100644 --- a/test_regress/t/t_lint_realcvt_bad.v +++ b/test_regress/t/t_lint_realcvt_bad.v @@ -4,10 +4,22 @@ // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +`timescale 1ns/1ps + module sub; - integer i; - initial begin - i = 23.2; - i = 23.0; // No warning - often happens with units of time - end + + time t_ok1 = 9ns; // > 1ns units + time t_bad1 = 9.001ns; // < 1ns units + time t_bad2 = 9.999ns; // < 1ns units + + time t_ok2 = 9.001us; // > 1ns units + + time t_bad3 = 9ps; // < 1ns units + + realtime rt_ok10 = 9.001ns; // < 1ns units + realtime rt_ok11 = 9ps; // < 1ns units + + integer i_ok20 = 23.0; // No warning + integer i_bad21 = 23.1; + endmodule diff --git a/test_regress/t/t_lint_removed_unused_loop_bad.pl b/test_regress/t/t_lint_removed_unused_loop_bad.pl deleted file mode 100755 index d4d0ecb72..000000000 --- a/test_regress/t/t_lint_removed_unused_loop_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ["--top-module t", "-Wall"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_removed_unused_loop_bad.py b/test_regress/t/t_lint_removed_unused_loop_bad.py new file mode 100755 index 000000000..61e258882 --- /dev/null +++ b/test_regress/t/t_lint_removed_unused_loop_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, + expect_filename=test.golden_filename, + verilator_flags2=["--top-module t", "-Wall"]) + +test.passes() diff --git a/test_regress/t/t_lint_repeat_bad.pl b/test_regress/t/t_lint_repeat_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_repeat_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_repeat_bad.py b/test_regress/t/t_lint_repeat_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_repeat_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_restore_bad.pl b/test_regress/t/t_lint_restore_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_restore_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_restore_bad.py b/test_regress/t/t_lint_restore_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_restore_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_restore_prag_bad.pl b/test_regress/t/t_lint_restore_prag_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_restore_prag_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_restore_prag_bad.py b/test_regress/t/t_lint_restore_prag_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_restore_prag_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_rsvd_bad.pl b/test_regress/t/t_lint_rsvd_bad.pl deleted file mode 100755 index 49de1747e..000000000 --- a/test_regress/t/t_lint_rsvd_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-REALCVT"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_rsvd_bad.py b/test_regress/t/t_lint_rsvd_bad.py new file mode 100755 index 000000000..acbdae169 --- /dev/null +++ b/test_regress/t/t_lint_rsvd_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-REALCVT"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_setout_bad.pl b/test_regress/t/t_lint_setout_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_setout_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_setout_bad.py b/test_regress/t/t_lint_setout_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_setout_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_setout_bad_noinl.pl b/test_regress/t/t_lint_setout_bad_noinl.pl deleted file mode 100755 index cbbf96bb4..000000000 --- a/test_regress/t/t_lint_setout_bad_noinl.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_lint_setout_bad.v"); - -lint( - verilator_flags2 => ["--lint-only -fno-inline"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_setout_bad_noinl.py b/test_regress/t/t_lint_setout_bad_noinl.py new file mode 100755 index 000000000..c10fcd5f7 --- /dev/null +++ b/test_regress/t/t_lint_setout_bad_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_lint_setout_bad.v" + +test.lint(verilator_flags2=["--lint-only -fno-inline"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_sideeffect_bad.pl b/test_regress/t/t_lint_sideeffect_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_sideeffect_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_sideeffect_bad.py b/test_regress/t/t_lint_sideeffect_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_sideeffect_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_stmtdly_bad.pl b/test_regress/t/t_lint_stmtdly_bad.pl deleted file mode 100755 index e9c855466..000000000 --- a/test_regress/t/t_lint_stmtdly_bad.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - verilator_flags2 => ["--no-timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_STMTDLY_faulty.rst", - lines => "10"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_STMTDLY_msg.rst", - lines => "1"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_stmtdly_bad.py b/test_regress/t/t_lint_stmtdly_bad.py new file mode 100755 index 000000000..cf06e63a2 --- /dev/null +++ b/test_regress/t/t_lint_stmtdly_bad.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_STMTDLY_faulty.rst", + lines="10") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_STMTDLY_msg.rst", + lines="1") + +test.passes() diff --git a/test_regress/t/t_lint_subout_bad.pl b/test_regress/t/t_lint_subout_bad.pl deleted file mode 100755 index 88f90f1d4..000000000 --- a/test_regress/t/t_lint_subout_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # No --lint-only as got compile error - verilator_flags2 => ["--trace"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_subout_bad.py b/test_regress/t/t_lint_subout_bad.py new file mode 100755 index 000000000..2ea3b149a --- /dev/null +++ b/test_regress/t/t_lint_subout_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # No --lint-only as got compile error + verilator_flags2=["--trace"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_syncasyncnet_bad.pl b/test_regress/t/t_lint_syncasyncnet_bad.pl deleted file mode 100755 index a40f3dab1..000000000 --- a/test_regress/t/t_lint_syncasyncnet_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_syncasyncnet_bad.py b/test_regress/t/t_lint_syncasyncnet_bad.py new file mode 100755 index 000000000..44eef5de9 --- /dev/null +++ b/test_regress/t/t_lint_syncasyncnet_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_top_bad.pl b/test_regress/t/t_lint_top_bad.pl deleted file mode 100755 index b1d44e6a9..000000000 --- a/test_regress/t/t_lint_top_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['-O0 --trace-fst'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_top_bad.py b/test_regress/t/t_lint_top_bad.py new file mode 100755 index 000000000..161c81983 --- /dev/null +++ b/test_regress/t/t_lint_top_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['-O0 --trace-fst'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_top_bad.v b/test_regress/t/t_lint_top_bad.v index eb3ae9d37..22980818f 100644 --- a/test_regress/t/t_lint_top_bad.v +++ b/test_regress/t/t_lint_top_bad.v @@ -7,7 +7,7 @@ module sub(input wire clk, cpu_reset); reg reset_r; always @(posedge clk) begin - reset_r <= cpu_reset; // The problematic one + reset_r <= cpu_reset; // The problematic one end endmodule diff --git a/test_regress/t/t_lint_unsigned_bad.pl b/test_regress/t/t_lint_unsigned_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_unsigned_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unsigned_bad.py b/test_regress/t/t_lint_unsigned_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_unsigned_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_unsized_bad.out b/test_regress/t/t_lint_unsized_bad.out deleted file mode 100644 index 3da13350f..000000000 --- a/test_regress/t/t_lint_unsized_bad.out +++ /dev/null @@ -1,6 +0,0 @@ -%Error: t/t_lint_unsized_bad.v:8:22: Too many digits for 32 bit number: 'd123456789123456789123456789 - ... As that number was unsized ('d...) it is limited to 32 bits (IEEE 1800-2023 5.7.1) - ... Suggest adding a size to it. - 8 | bit [256:0] num = 'd123456789123456789123456789; - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -%Error: Exiting due to diff --git a/test_regress/t/t_lint_unsized_bad.pl b/test_regress/t/t_lint_unsized_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_unsized_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unsized_bad.v b/test_regress/t/t_lint_unsized_bad.v deleted file mode 100644 index 2449ade13..000000000 --- a/test_regress/t/t_lint_unsized_bad.v +++ /dev/null @@ -1,9 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t; - bit [256:0] num = 'd123456789123456789123456789; -endmodule diff --git a/test_regress/t/t_lint_unsup_deassign.pl b/test_regress/t/t_lint_unsup_deassign.pl deleted file mode 100755 index d4a6fe9d8..000000000 --- a/test_regress/t/t_lint_unsup_deassign.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-unsup"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unsup_deassign.py b/test_regress/t/t_lint_unsup_deassign.py new file mode 100755 index 000000000..ef40a09c4 --- /dev/null +++ b/test_regress/t/t_lint_unsup_deassign.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --bbox-unsup"]) + +test.passes() diff --git a/test_regress/t/t_lint_unsup_mixed.pl b/test_regress/t/t_lint_unsup_mixed.pl deleted file mode 100755 index d4a6fe9d8..000000000 --- a/test_regress/t/t_lint_unsup_mixed.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-unsup"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unsup_mixed.py b/test_regress/t/t_lint_unsup_mixed.py new file mode 100755 index 000000000..ef40a09c4 --- /dev/null +++ b/test_regress/t/t_lint_unsup_mixed.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --bbox-unsup"]) + +test.passes() diff --git a/test_regress/t/t_lint_unused.pl b/test_regress/t/t_lint_unused.pl deleted file mode 100755 index ab8a6023e..000000000 --- a/test_regress/t/t_lint_unused.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unused.py b/test_regress/t/t_lint_unused.py new file mode 100755 index 000000000..3993e1fec --- /dev/null +++ b/test_regress/t/t_lint_unused.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME"]) + +test.passes() diff --git a/test_regress/t/t_lint_unused_bad.pl b/test_regress/t/t_lint_unused_bad.pl deleted file mode 100755 index feee5f9e4..000000000 --- a/test_regress/t/t_lint_unused_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME", - "--unused-regexp 'cmdln*'"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unused_bad.py b/test_regress/t/t_lint_unused_bad.py new file mode 100755 index 000000000..4108fcca7 --- /dev/null +++ b/test_regress/t/t_lint_unused_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=[ + "--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME", "--unused-regexp 'cmdln*'" +], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_unused_iface.pl b/test_regress/t/t_lint_unused_iface.pl deleted file mode 100755 index 3679f5264..000000000 --- a/test_regress/t/t_lint_unused_iface.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unused_iface.py b/test_regress/t/t_lint_unused_iface.py new file mode 100755 index 000000000..8bb4f3a66 --- /dev/null +++ b/test_regress/t/t_lint_unused_iface.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"]) + +test.passes() diff --git a/test_regress/t/t_lint_unused_iface_bad.pl b/test_regress/t/t_lint_unused_iface_bad.pl deleted file mode 100755 index 1c2a82989..000000000 --- a/test_regress/t/t_lint_unused_iface_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unused_iface_bad.py b/test_regress/t/t_lint_unused_iface_bad.py new file mode 100755 index 000000000..c6b6f1747 --- /dev/null +++ b/test_regress/t/t_lint_unused_iface_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_unused_tri.pl b/test_regress/t/t_lint_unused_tri.pl deleted file mode 100755 index 3679f5264..000000000 --- a/test_regress/t/t_lint_unused_tri.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unused_tri.py b/test_regress/t/t_lint_unused_tri.py new file mode 100755 index 000000000..8bb4f3a66 --- /dev/null +++ b/test_regress/t/t_lint_unused_tri.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"]) + +test.passes() diff --git a/test_regress/t/t_lint_vcmarker_bad.pl b/test_regress/t/t_lint_vcmarker_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_vcmarker_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_vcmarker_bad.py b/test_regress/t/t_lint_vcmarker_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_vcmarker_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_wait_bad.pl b/test_regress/t/t_lint_wait_bad.pl deleted file mode 100755 index b92ab79f3..000000000 --- a/test_regress/t/t_lint_wait_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_timing_wait1.v"); - -lint( - verilator_flags2 => ["--timing"], - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_wait_bad.py b/test_regress/t/t_lint_wait_bad.py new file mode 100755 index 000000000..a449d4a24 --- /dev/null +++ b/test_regress/t/t_lint_wait_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_timing_wait1.v" + +test.lint(verilator_flags2=["--timing"], expect_filename=test.golden_filename, fails=True) + +test.passes() diff --git a/test_regress/t/t_lint_warn_incfile2_bad.pl b/test_regress/t/t_lint_warn_incfile2_bad.pl deleted file mode 100755 index b3cdb56a9..000000000 --- a/test_regress/t/t_lint_warn_incfile2_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # See also t/t_lint_warn_incfile1_bad - # See also t/t_vlt_warn_file_bad - verilator_flags2 => ["--no-std"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_warn_incfile2_bad.py b/test_regress/t/t_lint_warn_incfile2_bad.py new file mode 100755 index 000000000..1add606d3 --- /dev/null +++ b/test_regress/t/t_lint_warn_incfile2_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # See also t/t_lint_warn_incfile1_bad + # See also t/t_vlt_warn_file_bad + verilator_flags2=["--no-std"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_warn_line_bad.pl b/test_regress/t/t_lint_warn_line_bad.pl deleted file mode 100755 index b3cdb56a9..000000000 --- a/test_regress/t/t_lint_warn_line_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # See also t/t_lint_warn_incfile1_bad - # See also t/t_vlt_warn_file_bad - verilator_flags2 => ["--no-std"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_warn_line_bad.py b/test_regress/t/t_lint_warn_line_bad.py new file mode 100755 index 000000000..1add606d3 --- /dev/null +++ b/test_regress/t/t_lint_warn_line_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # See also t/t_lint_warn_incfile1_bad + # See also t/t_vlt_warn_file_bad + verilator_flags2=["--no-std"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_width.pl b/test_regress/t/t_lint_width.pl deleted file mode 100755 index cc34dc85f..000000000 --- a/test_regress/t/t_lint_width.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width.py b/test_regress/t/t_lint_width.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_width.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_width_arraydecl.pl b/test_regress/t/t_lint_width_arraydecl.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_width_arraydecl.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width_arraydecl.py b/test_regress/t/t_lint_width_arraydecl.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_width_arraydecl.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_width_bad.pl b/test_regress/t/t_lint_width_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_width_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width_bad.py b/test_regress/t/t_lint_width_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_width_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_width_cast.py b/test_regress/t/t_lint_width_cast.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_lint_width_cast.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lint_width_cast.v b/test_regress/t/t_lint_width_cast.v new file mode 100644 index 000000000..80413b2a2 --- /dev/null +++ b/test_regress/t/t_lint_width_cast.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); + +module t(/*AUTOARG*/); + + wire [5:0] b1 = 6'b101101; + wire [5:0] b2 = 6'b011110; + logic [5:0] a6; + logic [9:0] a10; + + initial begin + // issue #3417 + a6 = b2 - b1; + `checkh(a6, 6'h31); + a10 = 10'(b2 - b1); + `checkh(a10, 10'h3f1); // This being not 31 indicates operator expands + `checkh($bits(10'(b1)), 10); + `checkh($bits(10'(b2 - b1)), 10); + `checkh($bits(b2 - b1), 6); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_lint_width_genfor.pl b/test_regress/t/t_lint_width_genfor.pl deleted file mode 100755 index d4dec648c..000000000 --- a/test_regress/t/t_lint_width_genfor.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -$Self->{vlt_all}; - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width_genfor.py b/test_regress/t/t_lint_width_genfor.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_width_genfor.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_width_genfor_bad.pl b/test_regress/t/t_lint_width_genfor_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_lint_width_genfor_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width_genfor_bad.py b/test_regress/t/t_lint_width_genfor_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_width_genfor_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_width_shift_bad.pl b/test_regress/t/t_lint_width_shift_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_width_shift_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width_shift_bad.py b/test_regress/t/t_lint_width_shift_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_width_shift_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_widthexpand_docs_bad.pl b/test_regress/t/t_lint_widthexpand_docs_bad.pl deleted file mode 100755 index 5dc62a3fc..000000000 --- a/test_regress/t/t_lint_widthexpand_docs_bad.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - verilator_flags2 => ["--lint-only"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_WIDTHEXPAND_1_faulty.rst", - lines => "8-10"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_WIDTHEXPAND_1_msg.rst", - lineno_adjust => -7, - regexp => qr/Warning-WIDTH/); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_WIDTHEXPAND_1_fixed.rst", - lines => "18"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_widthexpand_docs_bad.py b/test_regress/t/t_lint_widthexpand_docs_bad.py new file mode 100755 index 000000000..2b57b2bd5 --- /dev/null +++ b/test_regress/t/t_lint_widthexpand_docs_bad.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(verilator_flags2=["--lint-only"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_WIDTHEXPAND_1_faulty.rst", + lines="8-10") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_WIDTHEXPAND_1_msg.rst", + lineno_adjust=-7, + regexp=r'Warning-WIDTH') + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_WIDTHEXPAND_1_fixed.rst", + lines="18") + +test.passes() diff --git a/test_regress/t/t_mailbox.pl b/test_regress/t/t_mailbox.pl deleted file mode 100755 index 41f6e2a53..000000000 --- a/test_regress/t/t_mailbox.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing -Wall"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox.py b/test_regress/t/t_mailbox.py new file mode 100755 index 000000000..e84a7d7e7 --- /dev/null +++ b/test_regress/t/t_mailbox.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing -Wall"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mailbox_bad.pl b/test_regress/t/t_mailbox_bad.pl deleted file mode 100755 index a083f46f5..000000000 --- a/test_regress/t/t_mailbox_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_bad.py b/test_regress/t/t_mailbox_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_mailbox_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mailbox_class.pl b/test_regress/t/t_mailbox_class.pl deleted file mode 100755 index 91589388d..000000000 --- a/test_regress/t/t_mailbox_class.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_class.py b/test_regress/t/t_mailbox_class.py new file mode 100755 index 000000000..bbbcfc078 --- /dev/null +++ b/test_regress/t/t_mailbox_class.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.passes() diff --git a/test_regress/t/t_mailbox_concurrent.pl b/test_regress/t/t_mailbox_concurrent.pl deleted file mode 100755 index e99ff9766..000000000 --- a/test_regress/t/t_mailbox_concurrent.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Liam Braun and Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"] - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_concurrent.py b/test_regress/t/t_mailbox_concurrent.py new file mode 100755 index 000000000..a74b0c7ec --- /dev/null +++ b/test_regress/t/t_mailbox_concurrent.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mailbox_notiming.pl b/test_regress/t/t_mailbox_notiming.pl deleted file mode 100755 index 70368f851..000000000 --- a/test_regress/t/t_mailbox_notiming.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --no-timing -Wall"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_notiming.py b/test_regress/t/t_mailbox_notiming.py new file mode 100755 index 000000000..e504226e4 --- /dev/null +++ b/test_regress/t/t_mailbox_notiming.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --no-timing -Wall"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mailbox_std.pl b/test_regress/t/t_mailbox_std.pl deleted file mode 100755 index 8f575f2f2..000000000 --- a/test_regress/t/t_mailbox_std.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mailbox.v"); - -compile( - verilator_flags2 => ["--exe --main --timing -Wall --Wpedantic -DMAILBOX_T=std::mailbox"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_std.py b/test_regress/t/t_mailbox_std.py new file mode 100755 index 000000000..10f8af694 --- /dev/null +++ b/test_regress/t/t_mailbox_std.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mailbox.v" + +test.compile(verilator_flags2=["--exe --main --timing -Wall --Wpedantic -DMAILBOX_T=std::mailbox"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mailbox_unbounded.pl b/test_regress/t/t_mailbox_unbounded.pl deleted file mode 100755 index 41f6e2a53..000000000 --- a/test_regress/t/t_mailbox_unbounded.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing -Wall"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_unbounded.py b/test_regress/t/t_mailbox_unbounded.py new file mode 100755 index 000000000..e84a7d7e7 --- /dev/null +++ b/test_regress/t/t_mailbox_unbounded.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing -Wall"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_arith.pl b/test_regress/t/t_math_arith.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_arith.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_arith.py b/test_regress/t/t_math_arith.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_arith.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_clog2.pl b/test_regress/t/t_math_clog2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_clog2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_clog2.py b/test_regress/t/t_math_clog2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_clog2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_cmp.pl b/test_regress/t/t_math_cmp.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_cmp.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_cmp.py b/test_regress/t/t_math_cmp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_cmp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_concat.pl b/test_regress/t/t_math_concat.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_concat.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_concat.py b/test_regress/t/t_math_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_concat0.pl b/test_regress/t/t_math_concat0.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_concat0.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_concat0.py b/test_regress/t/t_math_concat0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_concat0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_concat64.pl b/test_regress/t/t_math_concat64.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_concat64.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_concat64.py b/test_regress/t/t_math_concat64.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_concat64.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_cond_clean.pl b/test_regress/t/t_math_cond_clean.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_math_cond_clean.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_cond_clean.py b/test_regress/t/t_math_cond_clean.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_cond_clean.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_cond_huge.pl b/test_regress/t/t_math_cond_huge.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_cond_huge.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_cond_huge.py b/test_regress/t/t_math_cond_huge.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_cond_huge.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_cond_huge_noexpand.pl b/test_regress/t/t_math_cond_huge_noexpand.pl deleted file mode 100755 index 15399cb9f..000000000 --- a/test_regress/t/t_math_cond_huge_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_cond_huge.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_cond_huge_noexpand.py b/test_regress/t/t_math_cond_huge_noexpand.py new file mode 100755 index 000000000..fe079527b --- /dev/null +++ b/test_regress/t/t_math_cond_huge_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_cond_huge.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_const.pl b/test_regress/t/t_math_const.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_const.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_const.py b/test_regress/t/t_math_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_countbits.pl b/test_regress/t/t_math_countbits.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_math_countbits.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_countbits.py b/test_regress/t/t_math_countbits.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_countbits.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_countbits_bad.out b/test_regress/t/t_math_countbits_bad.out index 7b4675c8f..479d0b3dc 100644 --- a/test_regress/t/t_math_countbits_bad.out +++ b/test_regress/t/t_math_countbits_bad.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_math_countbits_bad.v:14:54: Unsupported: $countbits with more than 3 control fields - 14 | assign count = $countbits(32'h123456, '0, '1, 'x, 'z); +%Error-UNSUPPORTED: t/t_math_countbits_bad.v:10:54: Unsupported: $countbits with more than 3 control fields + 10 | assign count = $countbits(32'h123456, '0, '1, 'x, 'z); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_math_countbits_bad.pl b/test_regress/t/t_math_countbits_bad.pl deleted file mode 100755 index 487e3aadf..000000000 --- a/test_regress/t/t_math_countbits_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_countbits_bad.py b/test_regress/t/t_math_countbits_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_countbits_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_countbits_bad.v b/test_regress/t/t_math_countbits_bad.v index 6560d2303..95cc4a443 100644 --- a/test_regress/t/t_math_countbits_bad.v +++ b/test_regress/t/t_math_countbits_bad.v @@ -4,11 +4,7 @@ // any use, without warranty, 2020 Yossi Nivin. // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t(/*AUTOARG*/); integer count; assign count = $countbits(32'h123456, '0, '1, 'x, 'z); diff --git a/test_regress/t/t_math_countbits_tri.py b/test_regress/t/t_math_countbits_tri.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_math_countbits_tri.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_countbits_tri.v b/test_regress/t/t_math_countbits_tri.v new file mode 100644 index 000000000..421ce6e5d --- /dev/null +++ b/test_regress/t/t_math_countbits_tri.v @@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Outputs + num_zeros, num_ones, + // Inputs + clk, reset_l, vec + ); + + input logic clk; + input logic reset_l; + input logic [7:0] vec; + output logic [7:0] num_zeros; + output logic [7:0] num_ones; + + always_comb begin + num_zeros = '0; + num_ones = '0; + for (int i = 0; i < 8; i++) begin + if (vec[i] == 0) begin + num_zeros++; + end else begin + num_ones++; + end + end + end + assert property (@(negedge clk) disable iff (~reset_l) (num_ones == $countones(vec))); + assert property (@(negedge clk) disable iff (~reset_l) (num_zeros == $countbits(vec, '0))); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_math_div.pl b/test_regress/t/t_math_div.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_div.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_div.py b/test_regress/t/t_math_div.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_div.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_div0.pl b/test_regress/t/t_math_div0.pl deleted file mode 100755 index 20346f7b4..000000000 --- a/test_regress/t/t_math_div0.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--x-assign 0'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_div0.py b/test_regress/t/t_math_div0.py new file mode 100755 index 000000000..1c1006dc8 --- /dev/null +++ b/test_regress/t/t_math_div0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--x-assign 0']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_div_noexpand.pl b/test_regress/t/t_math_div_noexpand.pl deleted file mode 100755 index fa7ecd2ec..000000000 --- a/test_regress/t/t_math_div_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_div.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_div_noexpand.py b/test_regress/t/t_math_div_noexpand.py new file mode 100755 index 000000000..59a7dbcac --- /dev/null +++ b/test_regress/t/t_math_div_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_div.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_divw.pl b/test_regress/t/t_math_divw.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_divw.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_divw.py b/test_regress/t/t_math_divw.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_divw.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_divw.v b/test_regress/t/t_math_divw.v index d85b3d7ff..7d2f852fa 100644 --- a/test_regress/t/t_math_divw.v +++ b/test_regress/t/t_math_divw.v @@ -4,12 +4,7 @@ // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); // verilator lint_off WIDTH diff --git a/test_regress/t/t_math_eq.pl b/test_regress/t/t_math_eq.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_eq.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_eq.py b/test_regress/t/t_math_eq.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_eq.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_eq_bad.pl b/test_regress/t/t_math_eq_bad.pl deleted file mode 100755 index bce2416ed..000000000 --- a/test_regress/t/t_math_eq_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_eq_bad.py b/test_regress/t/t_math_eq_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_eq_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_eq_noexpand.pl b/test_regress/t/t_math_eq_noexpand.pl deleted file mode 100755 index 2c3907b70..000000000 --- a/test_regress/t/t_math_eq_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_eq.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_eq_noexpand.py b/test_regress/t/t_math_eq_noexpand.py new file mode 100755 index 000000000..9ee292fb7 --- /dev/null +++ b/test_regress/t/t_math_eq_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_eq.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_equal.pl b/test_regress/t/t_math_equal.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_math_equal.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_equal.py b/test_regress/t/t_math_equal.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_equal.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_imm.pl b/test_regress/t/t_math_imm.pl deleted file mode 100755 index 7d49cd2cd..000000000 --- a/test_regress/t/t_math_imm.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_imm.py b/test_regress/t/t_math_imm.py new file mode 100755 index 000000000..539f320b1 --- /dev/null +++ b/test_regress/t/t_math_imm.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test) + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_imm2.pl b/test_regress/t/t_math_imm2.pl deleted file mode 100755 index 19193485f..000000000 --- a/test_regress/t/t_math_imm2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_imm2.py b/test_regress/t/t_math_imm2.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_math_imm2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_insert_bound.pl b/test_regress/t/t_math_insert_bound.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_math_insert_bound.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_insert_bound.py b/test_regress/t/t_math_insert_bound.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_insert_bound.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_mul.pl b/test_regress/t/t_math_mul.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_mul.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_mul.py b/test_regress/t/t_math_mul.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_mul.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pick.pl b/test_regress/t/t_math_pick.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_pick.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pick.py b/test_regress/t/t_math_pick.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pick.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow.pl b/test_regress/t/t_math_pow.pl deleted file mode 100755 index 7dcc17df2..000000000 --- a/test_regress/t/t_math_pow.pl +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-fno-gate'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -# Check for coverage on all POW functions -system("cat $Self->{obj_dir}/$Self->{vm_prefix}_*.cpp > $Self->{obj_dir}/all.cpp"); - -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_III/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_IIQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_IIW/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQI/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQW/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWI/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWW/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_III/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_IIQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_IIW/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQI/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQW/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWI/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWW/); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow.py b/test_regress/t/t_math_pow.py new file mode 100755 index 000000000..774a16957 --- /dev/null +++ b/test_regress/t/t_math_pow.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-fno-gate']) + +test.execute(expect_filename=test.golden_filename) + +# Check for coverage on all POW functions +os.system("cat " + test.obj_dir + "/" + test.vm_prefix + "_*.cpp > " + test.obj_dir + "/all.cpp") + +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_III') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_IIQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_IIW') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_QQI') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_QQQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_QQW') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_WWI') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_WWQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_WWW') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_III') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_IIQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_IIW') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_QQI') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_QQQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_QQW') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_WWI') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_WWQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_WWW') + +test.passes() diff --git a/test_regress/t/t_math_pow2.pl b/test_regress/t/t_math_pow2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_pow2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow2.py b/test_regress/t/t_math_pow2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pow2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow3.pl b/test_regress/t/t_math_pow3.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_pow3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow3.py b/test_regress/t/t_math_pow3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pow3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow4.pl b/test_regress/t/t_math_pow4.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_pow4.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow4.py b/test_regress/t/t_math_pow4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pow4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow5.pl b/test_regress/t/t_math_pow5.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_pow5.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow5.py b/test_regress/t/t_math_pow5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pow5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow6.pl b/test_regress/t/t_math_pow6.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_pow6.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow6.py b/test_regress/t/t_math_pow6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pow6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow7.pl b/test_regress/t/t_math_pow7.pl deleted file mode 100755 index 0a4dc8a6b..000000000 --- a/test_regress/t/t_math_pow7.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - "--exe", - "$Self->{t_dir}/$Self->{name}.cpp" - ], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow7.py b/test_regress/t/t_math_pow7.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_math_pow7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_precedence.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_precedence.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_precedence.py b/test_regress/t/t_math_precedence.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_precedence.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_real.pl b/test_regress/t/t_math_real.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_real.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_real.py b/test_regress/t/t_math_real.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_real.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_real.v b/test_regress/t/t_math_real.v index f9ee46d5b..5e2344e5b 100644 --- a/test_regress/t/t_math_real.v +++ b/test_regress/t/t_math_real.v @@ -8,7 +8,7 @@ `define stop $stop `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) module t (/*AUTOARG*/ @@ -178,7 +178,7 @@ module t (/*AUTOARG*/ // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d\n", $time, cyc); `endif cyc <= cyc + 1; if (cyc==0) begin diff --git a/test_regress/t/t_math_real_public.pl b/test_regress/t/t_math_real_public.pl deleted file mode 100755 index c8654558c..000000000 --- a/test_regress/t/t_math_real_public.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --public'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_real_public.py b/test_regress/t/t_math_real_public.py new file mode 100755 index 000000000..d219f422e --- /dev/null +++ b/test_regress/t/t_math_real_public.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --public']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_real_public.v b/test_regress/t/t_math_real_public.v index 8f5e46fd2..58f4c2017 100644 --- a/test_regress/t/t_math_real_public.v +++ b/test_regress/t/t_math_real_public.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module t; - sub #(.REAL(2.0)) sub; + sub #(.REAL(2.0)) sub(); endmodule module sub (); diff --git a/test_regress/t/t_math_real_random.pl b/test_regress/t/t_math_real_random.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_math_real_random.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_real_random.py b/test_regress/t/t_math_real_random.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_real_random.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_real_round.pl b/test_regress/t/t_math_real_round.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_real_round.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_real_round.py b/test_regress/t/t_math_real_round.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_real_round.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_red.pl b/test_regress/t/t_math_red.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_red.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_red.py b/test_regress/t/t_math_red.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_red.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_red_noexpand.pl b/test_regress/t/t_math_red_noexpand.pl deleted file mode 100755 index 655ce0246..000000000 --- a/test_regress/t/t_math_red_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_red.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_red_noexpand.py b/test_regress/t/t_math_red_noexpand.py new file mode 100755 index 000000000..eb44fb046 --- /dev/null +++ b/test_regress/t/t_math_red_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_red.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_repl.pl b/test_regress/t/t_math_repl.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_repl.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_repl.py b/test_regress/t/t_math_repl.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_repl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_repl2_bad.pl b/test_regress/t/t_math_repl2_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_math_repl2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_repl2_bad.py b/test_regress/t/t_math_repl2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_repl2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_repl_bad.pl b/test_regress/t/t_math_repl_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_math_repl_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_repl_bad.py b/test_regress/t/t_math_repl_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_repl_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_reverse.pl b/test_regress/t/t_math_reverse.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_reverse.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_reverse.py b/test_regress/t/t_math_reverse.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_reverse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift.pl b/test_regress/t/t_math_shift.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_shift.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift.py b/test_regress/t/t_math_shift.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shift.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift_extend.pl b/test_regress/t/t_math_shift_extend.pl deleted file mode 100755 index 763e64f5b..000000000 --- a/test_regress/t/t_math_shift_extend.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_extend.py b/test_regress/t/t_math_shift_extend.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shift_extend.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift_huge.pl b/test_regress/t/t_math_shift_huge.pl deleted file mode 100755 index 8c2ca139b..000000000 --- a/test_regress/t/t_math_shift_huge.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_huge.py b/test_regress/t/t_math_shift_huge.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_math_shift_huge.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_math_shift_noexpand.pl b/test_regress/t/t_math_shift_noexpand.pl deleted file mode 100755 index e27343a72..000000000 --- a/test_regress/t/t_math_shift_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_shift.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_noexpand.py b/test_regress/t/t_math_shift_noexpand.py new file mode 100755 index 000000000..72d3f29af --- /dev/null +++ b/test_regress/t/t_math_shift_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_shift.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift_rep.pl b/test_regress/t/t_math_shift_rep.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_shift_rep.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_rep.py b/test_regress/t/t_math_shift_rep.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shift_rep.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift_sel.pl b/test_regress/t/t_math_shift_sel.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_shift_sel.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_sel.py b/test_regress/t/t_math_shift_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shift_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift_side.pl b/test_regress/t/t_math_shift_side.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_math_shift_side.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_side.py b/test_regress/t/t_math_shift_side.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shift_side.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shiftrs.pl b/test_regress/t/t_math_shiftrs.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_shiftrs.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shiftrs.py b/test_regress/t/t_math_shiftrs.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shiftrs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shortcircuit_assocsel.py b/test_regress/t/t_math_shortcircuit_assocsel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shortcircuit_assocsel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shortcircuit_assocsel.v b/test_regress/t/t_math_shortcircuit_assocsel.v new file mode 100644 index 000000000..c12b80d36 --- /dev/null +++ b/test_regress/t/t_math_shortcircuit_assocsel.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + logic [31:0] dict [int]; + // verilator lint_off WIDTHTRUNC + function automatic logic f(int a); + int dict_size = dict.size; + logic next_exists = dict.next(a); + // incorrectly inserts element at `a` + logic next_nonzero = !next_exists || (dict[a] != 0); + if (dict_size != dict.size) begin + $display("Assertion failed: dict_size mismatch"); + $display("Initial size: %0d, New size: %0d", dict_size, dict.size); + $display("Dictionary contents:"); + foreach (dict[key]) begin + $display(" Key: %0d, Value: %0d", key, dict[key]); + end + $error; + end + return next_nonzero; + endfunction + initial begin + logic r = f(0); + $display(r); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_math_shortcircuit_dynsel.py b/test_regress/t/t_math_shortcircuit_dynsel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shortcircuit_dynsel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shortcircuit_dynsel.v b/test_regress/t/t_math_shortcircuit_dynsel.v new file mode 100644 index 000000000..52b4bf995 --- /dev/null +++ b/test_regress/t/t_math_shortcircuit_dynsel.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + logic [31:0] dict [int] []; + // verilator lint_off WIDTHTRUNC + function automatic logic f(int a); + int dict_size = dict.size; + logic next_exists = dict.next(a); + // incorrectly inserts element at `a` + logic next_nonzero = !next_exists || (dict[a].size != 0); + if (dict_size != dict.size) begin + $display("Assertion failed: dict_size mismatch"); + $display("Initial size: %0d, New size: %0d", dict_size, dict.size); + $display("Dictionary contents:"); + foreach (dict[key]) begin + $display(" Key: %0d, Value: %0d", key, dict[key]); + end + $error; + end + return next_nonzero; + endfunction + initial begin + logic r = f(0); + $display(r); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_math_shortreal.pl b/test_regress/t/t_math_shortreal.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_shortreal.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shortreal.py b/test_regress/t/t_math_shortreal.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shortreal.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shortreal.v b/test_regress/t/t_math_shortreal.v index 554297b44..faf30f99a 100644 --- a/test_regress/t/t_math_shortreal.v +++ b/test_regress/t/t_math_shortreal.v @@ -86,7 +86,7 @@ module t (/*AUTOARG*/ // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d\n", $time, cyc); `endif cyc <= cyc + 1; if (cyc==0) begin diff --git a/test_regress/t/t_math_shortreal_unsup_bad.pl b/test_regress/t/t_math_shortreal_unsup_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_math_shortreal_unsup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shortreal_unsup_bad.py b/test_regress/t/t_math_shortreal_unsup_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_shortreal_unsup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_sign_extend.pl b/test_regress/t/t_math_sign_extend.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_sign_extend.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_sign_extend.py b/test_regress/t/t_math_sign_extend.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_sign_extend.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_sign_extend.v b/test_regress/t/t_math_sign_extend.v index 4ca6a714b..10b6aed61 100644 --- a/test_regress/t/t_math_sign_extend.v +++ b/test_regress/t/t_math_sign_extend.v @@ -7,12 +7,7 @@ // without warranty, 2015 by Mike Thyer. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - +module t (/*AUTOARG*/); localparam [ 0:0] one1_lp = 1; localparam [ 1:0] one2_lp = 1; diff --git a/test_regress/t/t_math_signed.pl b/test_regress/t/t_math_signed.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_signed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed.py b/test_regress/t/t_math_signed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed2.pl b/test_regress/t/t_math_signed2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_signed2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed2.py b/test_regress/t/t_math_signed2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed3.pl b/test_regress/t/t_math_signed3.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_signed3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed3.py b/test_regress/t/t_math_signed3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed4.pl b/test_regress/t/t_math_signed4.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_signed4.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed4.py b/test_regress/t/t_math_signed4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed5.pl b/test_regress/t/t_math_signed5.pl deleted file mode 100755 index 39ae2a784..000000000 --- a/test_regress/t/t_math_signed5.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --no-timing'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed5.py b/test_regress/t/t_math_signed5.py new file mode 100755 index 000000000..46560bc9c --- /dev/null +++ b/test_regress/t/t_math_signed5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --no-timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed5_timing.pl b/test_regress/t/t_math_signed5_timing.pl deleted file mode 100755 index 695a67c98..000000000 --- a/test_regress/t/t_math_signed5_timing.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_math_signed5.v"); - -compile( - verilator_flags2 => ['--binary --timing'], - timing_loop => 1, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed5_timing.py b/test_regress/t/t_math_signed5_timing.py new file mode 100755 index 000000000..dd77ccb19 --- /dev/null +++ b/test_regress/t/t_math_signed5_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_math_signed5.v" + +test.compile(verilator_flags2=['--binary --timing'], timing_loop=True) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed6.pl b/test_regress/t/t_math_signed6.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_signed6.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed6.py b/test_regress/t/t_math_signed6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed7.pl b/test_regress/t/t_math_signed7.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_signed7.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed7.py b/test_regress/t/t_math_signed7.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed_calc.pl b/test_regress/t/t_math_signed_calc.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_math_signed_calc.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed_calc.py b/test_regress/t/t_math_signed_calc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed_calc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed_noexpand.pl b/test_regress/t/t_math_signed_noexpand.pl deleted file mode 100755 index b086af557..000000000 --- a/test_regress/t/t_math_signed_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_signed.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed_noexpand.py b/test_regress/t/t_math_signed_noexpand.py new file mode 100755 index 000000000..52c2b4c7a --- /dev/null +++ b/test_regress/t/t_math_signed_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_signed.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed_wire.pl b/test_regress/t/t_math_signed_wire.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_signed_wire.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed_wire.py b/test_regress/t/t_math_signed_wire.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed_wire.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_strwidth.pl b/test_regress/t/t_math_strwidth.pl deleted file mode 100755 index 3940e9623..000000000 --- a/test_regress/t/t_math_strwidth.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => [], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_strwidth.py b/test_regress/t/t_math_strwidth.py new file mode 100755 index 000000000..272dabc9b --- /dev/null +++ b/test_regress/t/t_math_strwidth.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_svl.pl b/test_regress/t/t_math_svl.pl deleted file mode 100755 index 3b0f6ade3..000000000 --- a/test_regress/t/t_math_svl.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - # Make sure we get the finish statement called - expect => -'\*-\* All Finished \*-\* -Goodbye world, at cycle \d+.*', - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_svl.py b/test_regress/t/t_math_svl.py new file mode 100755 index 000000000..f5ff115eb --- /dev/null +++ b/test_regress/t/t_math_svl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +# Make sure we get the finish statement called +test.file_grep(test.run_log_filename, r'Goodbye world, at cycle \d') + +test.passes() diff --git a/test_regress/t/t_math_svl2.pl b/test_regress/t/t_math_svl2.pl deleted file mode 100755 index 038e7a835..000000000 --- a/test_regress/t/t_math_svl2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2006 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_svl2.py b/test_regress/t/t_math_svl2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_svl2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_swap.pl b/test_regress/t/t_math_swap.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_swap.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_swap.py b/test_regress/t/t_math_swap.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_swap.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_tri.pl b/test_regress/t/t_math_tri.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_tri.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_tri.py b/test_regress/t/t_math_tri.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_tri.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_trig.pl b/test_regress/t/t_math_trig.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_trig.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_trig.py b/test_regress/t/t_math_trig.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_trig.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_vgen.pl b/test_regress/t/t_math_vgen.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_vgen.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_vgen.py b/test_regress/t/t_math_vgen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_vgen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_vliw.pl b/test_regress/t/t_math_vliw.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_vliw.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_vliw.py b/test_regress/t/t_math_vliw.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_vliw.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_vliw_noexpand.pl b/test_regress/t/t_math_vliw_noexpand.pl deleted file mode 100755 index 5ca1e425f..000000000 --- a/test_regress/t/t_math_vliw_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_vliw.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_vliw_noexpand.py b/test_regress/t/t_math_vliw_noexpand.py new file mode 100755 index 000000000..ca6a4fa58 --- /dev/null +++ b/test_regress/t/t_math_vliw_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_vliw.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_wide_bad.pl b/test_regress/t/t_math_wide_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_math_wide_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_wide_bad.py b/test_regress/t/t_math_wide_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_wide_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_wide_inc.pl b/test_regress/t/t_math_wide_inc.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_wide_inc.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_wide_inc.py b/test_regress/t/t_math_wide_inc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_wide_inc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_width.pl b/test_regress/t/t_math_width.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_math_width.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_width.py b/test_regress/t/t_math_width.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_width.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_yosys.pl b/test_regress/t/t_math_yosys.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_math_yosys.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_yosys.py b/test_regress/t/t_math_yosys.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_yosys.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem.pl b/test_regress/t/t_mem.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mem.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem.py b/test_regress/t/t_mem.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_banks.pl b/test_regress/t/t_mem_banks.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mem_banks.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_banks.py b/test_regress/t/t_mem_banks.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_banks.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_bound_bad.pl b/test_regress/t/t_mem_bound_bad.pl deleted file mode 100755 index d86162476..000000000 --- a/test_regress/t/t_mem_bound_bad.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => !$Self->{vlt_all}, # Should fail, but doesn't - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_bound_bad.py b/test_regress/t/t_mem_bound_bad.py new file mode 100755 index 000000000..c038d3707 --- /dev/null +++ b/test_regress/t/t_mem_bound_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + # Should fail, but doesn't) + fails=not test.vlt_all) + +test.passes() diff --git a/test_regress/t/t_mem_cond.pl b/test_regress/t/t_mem_cond.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mem_cond.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_cond.py b/test_regress/t/t_mem_cond.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_cond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_fifo.pl b/test_regress/t/t_mem_fifo.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mem_fifo.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_fifo.py b/test_regress/t/t_mem_fifo.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_fifo.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_file.pl b/test_regress/t/t_mem_file.pl deleted file mode 100755 index 987de13d5..000000000 --- a/test_regress/t/t_mem_file.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => [$Self->wno_unopthreads_for_few_cores()] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_file.py b/test_regress/t/t_mem_file.py new file mode 100755 index 000000000..a06492309 --- /dev/null +++ b/test_regress/t/t_mem_file.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=[test.wno_unopthreads_for_few_cores]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_first.pl b/test_regress/t/t_mem_first.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mem_first.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_first.py b/test_regress/t/t_mem_first.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_func.pl b/test_regress/t/t_mem_func.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mem_func.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_func.py b/test_regress/t/t_mem_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_iforder.pl b/test_regress/t/t_mem_iforder.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_mem_iforder.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_iforder.py b/test_regress/t/t_mem_iforder.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_iforder.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multi_io.pl b/test_regress/t/t_mem_multi_io.pl deleted file mode 100755 index 4e371f1d7..000000000 --- a/test_regress/t/t_mem_multi_io.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Disable inlining, this test is trivial without it - verilator_flags2 => ["-fno-inline --trace"], - verilator_flags3 => [], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_io.py b/test_regress/t/t_mem_multi_io.py new file mode 100755 index 000000000..7b164ec7b --- /dev/null +++ b/test_regress/t/t_mem_multi_io.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # Disable inlining, this test is trivial without it + verilator_flags2=["-fno-inline --trace"], + verilator_flags3=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multi_io2_cc.pl b/test_regress/t/t_mem_multi_io2_cc.pl deleted file mode 100755 index bfd551aed..000000000 --- a/test_regress/t/t_mem_multi_io2_cc.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_mem_multi_io2.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io2.cpp -fno-inline"], - verilator_flags3 => [], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_io2_cc.py b/test_regress/t/t_mem_multi_io2_cc.py new file mode 100755 index 000000000..de38bbd98 --- /dev/null +++ b/test_regress/t/t_mem_multi_io2_cc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_mem_multi_io2.cpp" +test.top_filename = "t/t_mem_multi_io2.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "-fno-inline"], + verilator_flags3=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multi_io2_sc.pl b/test_regress/t/t_mem_multi_io2_sc.pl deleted file mode 100755 index 2fb4bf70c..000000000 --- a/test_regress/t/t_mem_multi_io2_sc.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_mem_multi_io2.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io2.cpp --sc -fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_io2_sc.py b/test_regress/t/t_mem_multi_io2_sc.py new file mode 100755 index 000000000..25fa435f5 --- /dev/null +++ b/test_regress/t/t_mem_multi_io2_sc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_mem_multi_io2.cpp" +test.top_filename = "t/t_mem_multi_io2.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "--sc -fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multi_io3_cc.pl b/test_regress/t/t_mem_multi_io3_cc.pl deleted file mode 100755 index b6090a775..000000000 --- a/test_regress/t/t_mem_multi_io3_cc.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_mem_multi_io3.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io3.cpp -fno-inline"], - verilator_flags3 => [], - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_io3_cc.py b/test_regress/t/t_mem_multi_io3_cc.py new file mode 100755 index 000000000..4cd1b4166 --- /dev/null +++ b/test_regress/t/t_mem_multi_io3_cc.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_mem_multi_io3.cpp" +test.top_filename = "t/t_mem_multi_io3.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "-fno-inline"], + verilator_flags3=[]) + +test.passes() diff --git a/test_regress/t/t_mem_multi_io3_sc.pl b/test_regress/t/t_mem_multi_io3_sc.pl deleted file mode 100755 index f37d9dedd..000000000 --- a/test_regress/t/t_mem_multi_io3_sc.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_mem_multi_io3.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io3.cpp --sc -fno-inline"], - verilator_flags3 => [], - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_io3_sc.py b/test_regress/t/t_mem_multi_io3_sc.py new file mode 100755 index 000000000..49c0e89c1 --- /dev/null +++ b/test_regress/t/t_mem_multi_io3_sc.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_mem_multi_io3.cpp" +test.top_filename = "t/t_mem_multi_io3.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "--sc -fno-inline"], + verilator_flags3=[]) + +test.passes() diff --git a/test_regress/t/t_mem_multi_ref_bad.pl b/test_regress/t/t_mem_multi_ref_bad.pl deleted file mode 100755 index 7121b42e4..000000000 --- a/test_regress/t/t_mem_multi_ref_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - nc => 0, # Need to get it not to give the prompt - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_ref_bad.py b/test_regress/t/t_mem_multi_ref_bad.py new file mode 100755 index 000000000..6e8952fd0 --- /dev/null +++ b/test_regress/t/t_mem_multi_ref_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + fails=test.vlt_all, + nc=False, # Need to get it not to give the prompt + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mem_multidim.pl b/test_regress/t/t_mem_multidim.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mem_multidim.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multidim.py b/test_regress/t/t_mem_multidim.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_multidim.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multidim_Ox.pl b/test_regress/t/t_mem_multidim_Ox.pl deleted file mode 100755 index ccde0bbbd..000000000 --- a/test_regress/t/t_mem_multidim_Ox.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mem_multidim.v"); - -compile( - verilator_flags2 => ['--fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multidim_Ox.py b/test_regress/t/t_mem_multidim_Ox.py new file mode 100755 index 000000000..7b2c5a036 --- /dev/null +++ b/test_regress/t/t_mem_multidim_Ox.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mem_multidim.v" + +test.compile(verilator_flags2=['--fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multidim_trace.pl b/test_regress/t/t_mem_multidim_trace.pl deleted file mode 100755 index 4f4fed861..000000000 --- a/test_regress/t/t_mem_multidim_trace.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mem_multidim.v"); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multidim_trace.py b/test_regress/t/t_mem_multidim_trace.py new file mode 100755 index 000000000..8ac322e79 --- /dev/null +++ b/test_regress/t/t_mem_multidim_trace.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mem_multidim.v" + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multiwire.pl b/test_regress/t/t_mem_multiwire.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mem_multiwire.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multiwire.py b/test_regress/t/t_mem_multiwire.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_multiwire.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_packed.pl b/test_regress/t/t_mem_packed.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mem_packed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_packed.py b/test_regress/t/t_mem_packed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_packed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_packed_assign.pl b/test_regress/t/t_mem_packed_assign.pl deleted file mode 100755 index 1d8540ca0..000000000 --- a/test_regress/t/t_mem_packed_assign.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_packed_assign.py b/test_regress/t/t_mem_packed_assign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_packed_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_packed_bad.pl b/test_regress/t/t_mem_packed_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_mem_packed_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_packed_bad.py b/test_regress/t/t_mem_packed_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_mem_packed_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mem_packed_noexpand.pl b/test_regress/t/t_mem_packed_noexpand.pl deleted file mode 100755 index df4c82d6d..000000000 --- a/test_regress/t/t_mem_packed_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_mem_packed.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_packed_noexpand.py b/test_regress/t/t_mem_packed_noexpand.py new file mode 100755 index 000000000..0dcc3d32a --- /dev/null +++ b/test_regress/t/t_mem_packed_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_mem_packed.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_shift.pl b/test_regress/t/t_mem_shift.pl deleted file mode 100755 index 7f4359712..000000000 --- a/test_regress/t/t_mem_shift.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Delayed shared-sets\s+(\d+)/i, 14); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_shift.py b/test_regress/t/t_mem_shift.py new file mode 100755 index 000000000..7258ac668 --- /dev/null +++ b/test_regress/t/t_mem_shift.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, NBA flags shared\s+(\d+)', 14) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_slice.pl b/test_regress/t/t_mem_slice.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mem_slice.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_slice.py b/test_regress/t/t_mem_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_slice_bad.pl b/test_regress/t/t_mem_slice_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_mem_slice_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_slice_bad.py b/test_regress/t/t_mem_slice_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_mem_slice_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mem_slice_conc_bad.pl b/test_regress/t/t_mem_slice_conc_bad.pl deleted file mode 100755 index 3be843059..000000000 --- a/test_regress/t/t_mem_slice_conc_bad.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_slice_conc_bad.py b/test_regress/t/t_mem_slice_conc_bad.py new file mode 100755 index 000000000..d14db8ce3 --- /dev/null +++ b/test_regress/t/t_mem_slice_conc_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True) + +test.passes() diff --git a/test_regress/t/t_mem_slice_dtype_bad.pl b/test_regress/t/t_mem_slice_dtype_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_mem_slice_dtype_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_slice_dtype_bad.py b/test_regress/t/t_mem_slice_dtype_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_mem_slice_dtype_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mem_slot.pl b/test_regress/t/t_mem_slot.pl deleted file mode 100755 index 9e97f1977..000000000 --- a/test_regress/t/t_mem_slot.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp --no-timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_slot.py b/test_regress/t/t_mem_slot.py new file mode 100755 index 000000000..7b94250d8 --- /dev/null +++ b/test_regress/t/t_mem_slot.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "--no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_trace_split.py b/test_regress/t/t_mem_trace_split.py new file mode 100755 index 000000000..ec8e60aae --- /dev/null +++ b/test_regress/t/t_mem_trace_split.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--trace", "--trace-structs", "--output-split-ctrace", "32"]) + +if test.vlt_all: + test.file_grep_count(test.obj_dir + "/V" + test.name + "__Trace__0.cpp", + r'void Vt.*trace_chg_.*sub.*{', 3) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_trace_split.v b/test_regress/t/t_mem_trace_split.v new file mode 100644 index 000000000..8554ef831 --- /dev/null +++ b/test_regress/t/t_mem_trace_split.v @@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Demonstrate complex user typea problem with --x-assign +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + logic [31:0] mem_a [32]; + logic [15:0] mem_b [32]; + + int cyc = 0; + + // finish report + always @ (posedge clk) begin + cyc <= cyc + 1; + mem_a[cyc] <= cyc; + mem_b[cyc] <= 16'(cyc); + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + +endmodule diff --git a/test_regress/t/t_mem_twoedge.pl b/test_regress/t/t_mem_twoedge.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mem_twoedge.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_twoedge.py b/test_regress/t/t_mem_twoedge.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_twoedge.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_merge_cond.pl b/test_regress/t/t_merge_cond.pl deleted file mode 100755 index 971a808af..000000000 --- a/test_regress/t/t_merge_cond.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["-unroll-count 64", "--stats"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt}) { - # Note, with vltmt this might be split differently, so only checking vlt - file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i, - 9); - file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/i, - 580); - file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/i, - 128); -} - -ok(1); -1; diff --git a/test_regress/t/t_merge_cond.py b/test_regress/t/t_merge_cond.py new file mode 100755 index 000000000..34bb401c0 --- /dev/null +++ b/test_regress/t/t_merge_cond.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["-unroll-count 64", "--stats"]) + +test.execute() + +if test.vlt: + # Note, with vltmt this might be split differently, so only checking vlt + test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 9) + test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 580) + test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 128) + +test.passes() diff --git a/test_regress/t/t_merge_cond_blowup.pl b/test_regress/t/t_merge_cond_blowup.pl deleted file mode 100755 index aa9e8e1fe..000000000 --- a/test_regress/t/t_merge_cond_blowup.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# TODO: This takes excessively long on vltmt, this should be fixed - -compile( - verilator_flags2 => ["--unroll-count 1000000000", "--output-split 0", "--stats"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt}) { - # Note, with vltmt this might be split differently, so only checking vlt - file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i, - 500); # V3MergeCond.cpp MAX_DISTANCE - file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/i, - 1000); # V3MergeCond.cpp MAX_DISTANCE *2 - file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/i, - 2); -} - -ok(1); -1; diff --git a/test_regress/t/t_merge_cond_blowup.py b/test_regress/t/t_merge_cond_blowup.py new file mode 100755 index 000000000..9602f04f6 --- /dev/null +++ b/test_regress/t/t_merge_cond_blowup.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# TODO: This takes excessively long on vltmt, this should be fixed + +test.compile(verilator_flags2=["--unroll-count 1000000000", "--output-split 0", "--stats"]) + +test.execute() + +if test.vlt: + # Note, with vltmt this might be split differently, so only checking vlt + test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 500) + # V3MergeCond.cpp MAX_DISTANCE + test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 1000) + # V3MergeCond.cpp MAX_DISTANCE *2 + test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 2) + +test.passes() diff --git a/test_regress/t/t_merge_cond_bug_3409.pl b/test_regress/t/t_merge_cond_bug_3409.pl deleted file mode 100755 index bb6c1fab4..000000000 --- a/test_regress/t/t_merge_cond_bug_3409.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2=> ["--stats"] - ); - -execute(); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i, - 0); - file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/i, - 0); - file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/i, - 0); -} - -ok(1); -1; diff --git a/test_regress/t/t_merge_cond_bug_3409.py b/test_regress/t/t_merge_cond_bug_3409.py new file mode 100755 index 000000000..e5bc05874 --- /dev/null +++ b/test_regress/t/t_merge_cond_bug_3409.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 0) + test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 0) + test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_merge_cond_no_extend.pl b/test_regress/t/t_merge_cond_no_extend.pl deleted file mode 100755 index 5fd0b644e..000000000 --- a/test_regress/t/t_merge_cond_no_extend.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i, 0); - -ok(1); -1; diff --git a/test_regress/t/t_merge_cond_no_extend.py b/test_regress/t/t_merge_cond_no_extend.py new file mode 100755 index 000000000..d85958438 --- /dev/null +++ b/test_regress/t/t_merge_cond_no_extend.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats"]) + +test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_merge_cond_no_motion.pl b/test_regress/t/t_merge_cond_no_motion.pl deleted file mode 100755 index 113b054db..000000000 --- a/test_regress/t/t_merge_cond_no_motion.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_merge_cond.v"); - -compile( - verilator_flags2 => ["-unroll-count 64", "--stats", "-fno-merge-cond-motion"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt}) { - # Note, with vltmt this might be split differently, so only checking vlt - file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i, - 10); - file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/i, - 580); - file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/i, - 64); -} - -ok(1); -1; diff --git a/test_regress/t/t_merge_cond_no_motion.py b/test_regress/t/t_merge_cond_no_motion.py new file mode 100755 index 000000000..241c21a12 --- /dev/null +++ b/test_regress/t/t_merge_cond_no_motion.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_merge_cond.v" + +test.compile(verilator_flags2=["-unroll-count 64", "--stats", "-fno-merge-cond-motion"]) + +test.execute() + +if test.vlt: + # Note, with vltmt this might be split differently, so only checking vlt + test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 10) + test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 580) + test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 64) + +test.passes() diff --git a/test_regress/t/t_metacmt_onoff.pl b/test_regress/t/t_metacmt_onoff.pl deleted file mode 100755 index 674687687..000000000 --- a/test_regress/t/t_metacmt_onoff.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_metacmt_onoff.py b/test_regress/t/t_metacmt_onoff.py new file mode 100755 index 000000000..6585af685 --- /dev/null +++ b/test_regress/t/t_metacmt_onoff.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mod_dollar$.pl b/test_regress/t/t_mod_dollar$.pl deleted file mode 100755 index e4855df5c..000000000 --- a/test_regress/t/t_mod_dollar$.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# This doesn't use the general compile rule as we want to make sure we form -# prefix properly using post-escaped identifiers -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator", - "--cc", - "--Mdir " . $Self->{obj_dir} . "/t_mod_dollar", - "--exe --build --main", - 't/t_mod_dollar$.v', - ], - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_dollar$.py b/test_regress/t/t_mod_dollar$.py new file mode 100755 index 000000000..926c9b4d4 --- /dev/null +++ b/test_regress/t/t_mod_dollar$.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# This doesn't use the general compile rule as we want to make sure we form +# prefix properly using post-escaped identifiers +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator", + "--cc", + "--Mdir " + test.obj_dir + "/t_mod_dollar", + "--exe --build --main", + 't/t_mod_dollar$.v', +], + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_mod_dup_bad.pl b/test_regress/t/t_mod_dup_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_mod_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_dup_bad.py b/test_regress/t/t_mod_dup_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_mod_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mod_dup_ign.pl b/test_regress/t/t_mod_dup_ign.pl deleted file mode 100755 index 8b318d39c..000000000 --- a/test_regress/t/t_mod_dup_ign.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_mod_dup_ign.py b/test_regress/t/t_mod_dup_ign.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_mod_dup_ign.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array0.pl b/test_regress/t/t_mod_interface_array0.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mod_interface_array0.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array0.py b/test_regress/t/t_mod_interface_array0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array0_noinl.pl b/test_regress/t/t_mod_interface_array0_noinl.pl deleted file mode 100755 index 56032e0d9..000000000 --- a/test_regress/t/t_mod_interface_array0_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mod_interface_array0.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array0_noinl.py b/test_regress/t/t_mod_interface_array0_noinl.py new file mode 100755 index 000000000..d82128883 --- /dev/null +++ b/test_regress/t/t_mod_interface_array0_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mod_interface_array0.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array1.pl b/test_regress/t/t_mod_interface_array1.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mod_interface_array1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array1.py b/test_regress/t/t_mod_interface_array1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array1_noinl.pl b/test_regress/t/t_mod_interface_array1_noinl.pl deleted file mode 100755 index 651bb1c65..000000000 --- a/test_regress/t/t_mod_interface_array1_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mod_interface_array1.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array1_noinl.py b/test_regress/t/t_mod_interface_array1_noinl.py new file mode 100755 index 000000000..6d7fc4468 --- /dev/null +++ b/test_regress/t/t_mod_interface_array1_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mod_interface_array1.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array2.pl b/test_regress/t/t_mod_interface_array2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mod_interface_array2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array2.py b/test_regress/t/t_mod_interface_array2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array2_noinl.pl b/test_regress/t/t_mod_interface_array2_noinl.pl deleted file mode 100755 index 2afa9e020..000000000 --- a/test_regress/t/t_mod_interface_array2_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mod_interface_array2.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array2_noinl.py b/test_regress/t/t_mod_interface_array2_noinl.py new file mode 100755 index 000000000..c0f6c74f7 --- /dev/null +++ b/test_regress/t/t_mod_interface_array2_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mod_interface_array2.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array3.out b/test_regress/t/t_mod_interface_array3.out index 0d200dc13..2e9aaf9d7 100644 --- a/test_regress/t/t_mod_interface_array3.out +++ b/test_regress/t/t_mod_interface_array3.out @@ -1,8 +1,8 @@ -%Error-UNSUPPORTED: t/t_mod_interface_array3.v:26:20: Unsupported: Multidimensional instances/interfaces. - 26 | a_if iface [2:0][1:0]; +%Error-UNSUPPORTED: t/t_mod_interface_array3.v:22:20: Unsupported: Multidimensional instances/interfaces. + 22 | a_if iface [2:0][1:0]; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_mod_interface_array3.v:28:18: Unsupported: Multidimensional instances/interfaces. - 28 | sub i_sub[2:0][1:0] (.s(str)); +%Error-UNSUPPORTED: t/t_mod_interface_array3.v:24:18: Unsupported: Multidimensional instances/interfaces. + 24 | sub i_sub[2:0][1:0] (.s(str)); | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mod_interface_array3.pl b/test_regress/t/t_mod_interface_array3.pl deleted file mode 100755 index a29ead0ed..000000000 --- a/test_regress/t/t_mod_interface_array3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array3.py b/test_regress/t/t_mod_interface_array3.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_mod_interface_array3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mod_interface_array3.v b/test_regress/t/t_mod_interface_array3.v index 354fd04a4..7ea8a209e 100644 --- a/test_regress/t/t_mod_interface_array3.v +++ b/test_regress/t/t_mod_interface_array3.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 `define stop $stop -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); interface a_if (); string s; @@ -15,11 +15,7 @@ module sub (output string s); initial s = $sformatf("%m"); endmodule -module t - ( - clk - ); - input clk; +module t; string str [2:0][1:0]; diff --git a/test_regress/t/t_mod_interface_array4.pl b/test_regress/t/t_mod_interface_array4.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_mod_interface_array4.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array4.py b/test_regress/t/t_mod_interface_array4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array4_noinl.pl b/test_regress/t/t_mod_interface_array4_noinl.pl deleted file mode 100755 index 62ad2ca24..000000000 --- a/test_regress/t/t_mod_interface_array4_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mod_interface_array4.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array4_noinl.py b/test_regress/t/t_mod_interface_array4_noinl.py new file mode 100755 index 000000000..5c330f73d --- /dev/null +++ b/test_regress/t/t_mod_interface_array4_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mod_interface_array4.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array5.pl b/test_regress/t/t_mod_interface_array5.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_mod_interface_array5.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array5.py b/test_regress/t/t_mod_interface_array5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array6.pl b/test_regress/t/t_mod_interface_array6.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_mod_interface_array6.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array6.py b/test_regress/t/t_mod_interface_array6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array6_noinl.pl b/test_regress/t/t_mod_interface_array6_noinl.pl deleted file mode 100755 index f07ea1917..000000000 --- a/test_regress/t/t_mod_interface_array6_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mod_interface_array6.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array6_noinl.py b/test_regress/t/t_mod_interface_array6_noinl.py new file mode 100755 index 000000000..1740bd164 --- /dev/null +++ b/test_regress/t/t_mod_interface_array6_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mod_interface_array6.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_longname.pl b/test_regress/t/t_mod_longname.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mod_longname.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_longname.py b/test_regress/t/t_mod_longname.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_longname.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_nomod.pl b/test_regress/t/t_mod_nomod.pl deleted file mode 100755 index e26d2aa31..000000000 --- a/test_regress/t/t_mod_nomod.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_nomod.py b/test_regress/t/t_mod_nomod.py new file mode 100755 index 000000000..3527cdb06 --- /dev/null +++ b/test_regress/t/t_mod_nomod.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_mod_recurse.pl b/test_regress/t/t_mod_recurse.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mod_recurse.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_recurse.py b/test_regress/t/t_mod_recurse.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_recurse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_recurse1.pl b/test_regress/t/t_mod_recurse1.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_mod_recurse1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_recurse1.py b/test_regress/t/t_mod_recurse1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_recurse1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_recurse1.v b/test_regress/t/t_mod_recurse1.v index 785e38869..1c0c742d5 100644 --- a/test_regress/t/t_mod_recurse1.v +++ b/test_regress/t/t_mod_recurse1.v @@ -15,13 +15,13 @@ module rec; generate if (DEPTH==1) begin - rec #(.DEPTH(DEPTH+1)) sub; + rec #(.DEPTH(DEPTH+1)) sub(); end else if (DEPTH==2) begin - rec #(.DEPTH(DEPTH+1)) subb; + rec #(.DEPTH(DEPTH+1)) subb(); end else if (DEPTH==3) begin - bottom #(.DEPTH(DEPTH+1)) bot; + bottom #(.DEPTH(DEPTH+1)) bot(); end endgenerate endmodule diff --git a/test_regress/t/t_mod_topmodule.pl b/test_regress/t/t_mod_topmodule.pl deleted file mode 100755 index 914a14238..000000000 --- a/test_regress/t/t_mod_topmodule.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--top-module top"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_topmodule.py b/test_regress/t/t_mod_topmodule.py new file mode 100755 index 000000000..2ea7dd9e0 --- /dev/null +++ b/test_regress/t/t_mod_topmodule.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--top-module top"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_topmodule_nest.pl b/test_regress/t/t_mod_topmodule_nest.pl deleted file mode 100755 index 914a14238..000000000 --- a/test_regress/t/t_mod_topmodule_nest.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--top-module top"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_topmodule_nest.py b/test_regress/t/t_mod_topmodule_nest.py new file mode 100755 index 000000000..2ea7dd9e0 --- /dev/null +++ b/test_regress/t/t_mod_topmodule_nest.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--top-module top"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_uselib.pl b/test_regress/t/t_mod_uselib.pl deleted file mode 100755 index 8fbc2f576..000000000 --- a/test_regress/t/t_mod_uselib.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_uselib.py b/test_regress/t/t_mod_uselib.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_mod_uselib.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_module_class_static_method.pl b/test_regress/t/t_module_class_static_method.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_module_class_static_method.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_class_static_method.py b/test_regress/t/t_module_class_static_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_module_class_static_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_module_input_default_value.pl b/test_regress/t/t_module_input_default_value.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_module_input_default_value.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_input_default_value.py b/test_regress/t/t_module_input_default_value.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_module_input_default_value.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_module_input_default_value_1_bad.pl b/test_regress/t/t_module_input_default_value_1_bad.pl deleted file mode 100755 index b9057722c..000000000 --- a/test_regress/t/t_module_input_default_value_1_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_input_default_value_1_bad.py b/test_regress/t/t_module_input_default_value_1_bad.py new file mode 100755 index 000000000..3def97587 --- /dev/null +++ b/test_regress/t/t_module_input_default_value_1_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_module_input_default_value_2_bad.pl b/test_regress/t/t_module_input_default_value_2_bad.pl deleted file mode 100755 index b9057722c..000000000 --- a/test_regress/t/t_module_input_default_value_2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_input_default_value_2_bad.py b/test_regress/t/t_module_input_default_value_2_bad.py new file mode 100755 index 000000000..3def97587 --- /dev/null +++ b/test_regress/t/t_module_input_default_value_2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_module_input_default_value_3_bad.pl b/test_regress/t/t_module_input_default_value_3_bad.pl deleted file mode 100755 index b9057722c..000000000 --- a/test_regress/t/t_module_input_default_value_3_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_input_default_value_3_bad.py b/test_regress/t/t_module_input_default_value_3_bad.py new file mode 100755 index 000000000..3def97587 --- /dev/null +++ b/test_regress/t/t_module_input_default_value_3_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_module_input_default_value_noinl.pl b/test_regress/t/t_module_input_default_value_noinl.pl deleted file mode 100755 index 85d6cc977..000000000 --- a/test_regress/t/t_module_input_default_value_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_module_input_default_value.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_input_default_value_noinl.py b/test_regress/t/t_module_input_default_value_noinl.py new file mode 100755 index 000000000..7858944b8 --- /dev/null +++ b/test_regress/t/t_module_input_default_value_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_module_input_default_value.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multiline_waivers.pl b/test_regress/t/t_multiline_waivers.pl deleted file mode 100755 index 6cfad5889..000000000 --- a/test_regress/t/t_multiline_waivers.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.vlt"; -my $waiver_filename = "$Self->{obj_dir}/$Self->{name}_waiver.vlt"; - -compile( - v_flags2 => ['--waiver-output', $out_filename], - fails => 1, - ); - -file_sed($out_filename, $waiver_filename, - sub { s/\/\/ lint_off/lint_off/g; }); - -compile( - v_flags2 => [$waiver_filename], - ); - -ok(1); -1; diff --git a/test_regress/t/t_multiline_waivers.py b/test_regress/t/t_multiline_waivers.py new file mode 100755 index 000000000..3f3414f68 --- /dev/null +++ b/test_regress/t/t_multiline_waivers.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/" + test.name + "_waiver_gen.vlt" +waiver_filename = test.obj_dir + "/" + test.name + "_waiver.vlt" + +test.compile(v_flags2=['--waiver-output', out_filename], fails=True) + +test.file_sed(out_filename, waiver_filename, + lambda line: re.sub(r'\/\/ lint_off', 'lint_off', line)) + +test.compile(v_flags2=[waiver_filename]) + +test.passes() diff --git a/test_regress/t/t_multitop1.pl b/test_regress/t/t_multitop1.pl deleted file mode 100755 index e70f69cd0..000000000 --- a/test_regress/t/t_multitop1.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - check_finished => 0, - ); - -# Order of lines is unspecified, so don't use a golden file -file_grep($Self->{run_log_filename}, qr!In 'top.t'!); -file_grep($Self->{run_log_filename}, qr!In 'top.t.s'!); -file_grep_not($Self->{run_log_filename}, qr!in_subfile!); - -ok(1); -1; diff --git a/test_regress/t/t_multitop1.py b/test_regress/t/t_multitop1.py new file mode 100755 index 000000000..86e5ab5e5 --- /dev/null +++ b/test_regress/t/t_multitop1.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute(check_finished=False) + +# Order of lines is unspecified, so don't use a golden file +test.file_grep(test.run_log_filename, r"In 'top.t'") +test.file_grep(test.run_log_filename, r"In 'top.t.s'") +test.file_grep_not(test.run_log_filename, r"in_subfile") + +test.passes() diff --git a/test_regress/t/t_multitop_sig.pl b/test_regress/t/t_multitop_sig.pl deleted file mode 100755 index e53b59f79..000000000 --- a/test_regress/t/t_multitop_sig.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["-Wno-MULTITOP --exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{run_log_filename}, qr!In 'a'!); -file_grep($Self->{run_log_filename}, qr!In 'a.sub'!); -file_grep($Self->{run_log_filename}, qr!In 'b'!); -file_grep($Self->{run_log_filename}, qr!In 'b.sub'!); -file_grep($Self->{run_log_filename}, qr!In 'c'!); -file_grep($Self->{run_log_filename}, qr!In 'c.sub'!); - -ok(1); -1; diff --git a/test_regress/t/t_multitop_sig.py b/test_regress/t/t_multitop_sig.py new file mode 100755 index 000000000..b70faf4bc --- /dev/null +++ b/test_regress/t/t_multitop_sig.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["-Wno-MULTITOP --exe", test.pli_filename]) + +test.execute() + +test.file_grep(test.run_log_filename, r"In 'a'") +test.file_grep(test.run_log_filename, r"In 'a.sub'") +test.file_grep(test.run_log_filename, r"In 'b'") +test.file_grep(test.run_log_filename, r"In 'b.sub'") +test.file_grep(test.run_log_filename, r"In 'c'") +test.file_grep(test.run_log_filename, r"In 'c.sub'") + +test.passes() diff --git a/test_regress/t/t_multitop_sig_bad.pl b/test_regress/t/t_multitop_sig_bad.pl deleted file mode 100755 index f3b7679b6..000000000 --- a/test_regress/t/t_multitop_sig_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_multitop_sig.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_multitop_sig_bad.py b/test_regress/t/t_multitop_sig_bad.py new file mode 100755 index 000000000..b76511c6c --- /dev/null +++ b/test_regress/t/t_multitop_sig_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_multitop_sig.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_name_collision.pl b/test_regress/t/t_name_collision.pl deleted file mode 100755 index 0723e1873..000000000 --- a/test_regress/t/t_name_collision.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--coverage'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_name_collision.py b/test_regress/t/t_name_collision.py new file mode 100755 index 000000000..fdaf03625 --- /dev/null +++ b/test_regress/t/t_name_collision.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--coverage']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_nba_commit_queue.pl b/test_regress/t/t_nba_commit_queue.pl deleted file mode 100755 index c7b151c9c..000000000 --- a/test_regress/t/t_nba_commit_queue.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["-unroll-count 1", "--stats"], - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{stats}, qr/Dynamic NBA, variables needing commit queue without partial updates\s+(\d+)/i, - 6); -file_grep($Self->{stats}, qr/Dynamic NBA, variables needing commit queue with partial updates\s+(\d+)/i, - 3); - -ok(1); -1; diff --git a/test_regress/t/t_nba_commit_queue.py b/test_regress/t/t_nba_commit_queue.py new file mode 100755 index 000000000..f2f141378 --- /dev/null +++ b/test_regress/t/t_nba_commit_queue.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["-unroll-count 1", "--stats"]) + +test.execute() + +test.file_grep(test.stats, r'NBA, variables using ValueQueueWhole scheme\s+(\d+)', 6) +test.file_grep(test.stats, r'NBA, variables using ValueQueuePartial scheme\s+(\d+)', 3) + +test.passes() diff --git a/test_regress/t/t_nba_commit_queue.v b/test_regress/t/t_nba_commit_queue.v index 527374cbe..632762b22 100644 --- a/test_regress/t/t_nba_commit_queue.v +++ b/test_regress/t/t_nba_commit_queue.v @@ -7,7 +7,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); diff --git a/test_regress/t/t_nba_commit_queue_suspenable.py b/test_regress/t/t_nba_commit_queue_suspenable.py new file mode 100755 index 000000000..edf692f39 --- /dev/null +++ b/test_regress/t/t_nba_commit_queue_suspenable.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--exe", "--main", "--timing", "-unroll-count 1", "--stats"]) + +test.execute() + +test.file_grep(test.stats, r'NBA, variables using ValueQueueWhole scheme\s+(\d+)', 2) +test.file_grep(test.stats, r'NBA, variables using ValueQueuePartial scheme\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_nba_commit_queue_suspenable.v b/test_regress/t/t_nba_commit_queue_suspenable.v new file mode 100644 index 000000000..3ba826ea9 --- /dev/null +++ b/test_regress/t/t_nba_commit_queue_suspenable.v @@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Test of select from constant +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t; + + reg clk = 0; + + always #50 clk = ~clk; + + initial begin + #1000; + $write("*-* All Finished *-*\n"); + $finish; + end + + int cyc = 0; + always @(posedge clk) cyc <= cyc + 1; + + localparam SIZE = 65536; + + // Case 1: Array NBA inside suspendable + int array1 [SIZE]; + always @ (posedge clk) begin + #1; + for (int i=0; i 1) begin + for (int i=0; i 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_negated_property.py b/test_regress/t/t_negated_property.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_negated_property.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_net_delay.out b/test_regress/t/t_net_delay.out index 40a84f0f0..2d09dd7e0 100644 --- a/test_regress/t/t_net_delay.out +++ b/test_regress/t/t_net_delay.out @@ -1,15 +1,35 @@ -%Warning-STMTDLY: t/t_net_delay.v:16:14: Ignoring delay on this statement due to --no-timing +%Warning-STMTDLY: t/t_net_delay.v:14:11: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 16 | wire[3:0] #4 val1 = half_cyc; - | ^ + 14 | always #2 clk = ~clk; + | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. -%Warning-STMTDLY: t/t_net_delay.v:17:14: Ignoring delay on this statement due to --no-timing +%Warning-STMTDLY: t/t_net_delay.v:20:14: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 17 | wire[3:0] #4 val2; + 20 | wire[3:0] #3 val1; | ^ -%Warning-ASSIGNDLY: t/t_net_delay.v:20:11: Ignoring timing control on this assignment/primitive due to --no-timing +%Warning-STMTDLY: t/t_net_delay.v:21:14: Ignoring delay on this statement due to --no-timing + : ... note: In instance 't' + 21 | wire[3:0] #3 val2; + | ^ +%Warning-ASSIGNDLY: t/t_net_delay.v:22:14: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' - 20 | assign #4 val2 = half_cyc; + 22 | wire[3:0] #5 val3 = cyc; + | ^ +%Warning-STMTDLY: t/t_net_delay.v:23:14: Ignoring delay on this statement due to --no-timing + : ... note: In instance 't' + 23 | wire[3:0] #5 val4; + | ^ +%Warning-ASSIGNDLY: t/t_net_delay.v:24:14: Ignoring timing control on this assignment/primitive due to --no-timing + : ... note: In instance 't' + 24 | wire[3:0] #3 val5 = x, val6 = cyc; + | ^ +%Warning-ASSIGNDLY: t/t_net_delay.v:27:11: Ignoring timing control on this assignment/primitive due to --no-timing + : ... note: In instance 't' + 27 | assign #3 val2 = cyc; | ^ +%Warning-STMTDLY: t/t_net_delay.v:39:26: Ignoring delay on this statement due to --no-timing + : ... note: In instance 't' + 39 | always @(posedge clk) #1 begin + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_net_delay.pl b/test_regress/t/t_net_delay.pl deleted file mode 100755 index 09ee1bbae..000000000 --- a/test_regress/t/t_net_delay.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ['-Wall -Wno-DECLFILENAME --no-timing'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_net_delay.py b/test_regress/t/t_net_delay.py new file mode 100755 index 000000000..2424f0de5 --- /dev/null +++ b/test_regress/t/t_net_delay.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME --no-timing'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_net_delay.v b/test_regress/t/t_net_delay.v index 4d8190e6a..514504a6b 100644 --- a/test_regress/t/t_net_delay.v +++ b/test_regress/t/t_net_delay.v @@ -7,30 +7,47 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t; + // verilator lint_off UNOPTFLAT + logic clk = 0; + // verilator lint_on UNOPTFLAT + always #2 clk = ~clk; - wire[3:0] #4 val1 = half_cyc; - wire[3:0] #4 val2; - reg[3:0] half_cyc = 0; + // verilator lint_off UNDRIVEN + wire[3:0] x; + // verilator lint_on UNDRIVEN + reg[3:0] cyc = 0; + wire[3:0] #3 val1; + wire[3:0] #3 val2; + wire[3:0] #5 val3 = cyc; + wire[3:0] #5 val4; + wire[3:0] #3 val5 = x, val6 = cyc; - assign #4 val2 = half_cyc; + assign val1 = cyc; + assign #3 val2 = cyc; + assign val4 = cyc; + assign val5 = cyc; - always @(clk) begin - if ($time > 0) half_cyc <= half_cyc + 1; -`ifdef TEST_VERBOSE - $strobe("[%0t] half_cyc=%0d, val1=%0d, val2=%0d", $time, half_cyc, val1, val2); -`endif - if (half_cyc >= 7) begin - `checkh(val1, half_cyc - 3); - `checkh(val2, half_cyc - 7); - end - if (half_cyc == 15) begin + always @(posedge clk) begin + if ($time > 0) cyc <= cyc + 1; + if (cyc == 15) begin $write("*-* All Finished *-*\n"); $finish; end end + + always @(posedge clk) #1 begin +`ifdef TEST_VERBOSE + $display("[%0t] cyc=%0d val1=%0d val2=%0d val3=%0d val4=%0d val5=%0d val6=%0d", + $time, cyc, val1, val2, val3, val4, val5, val6); +`endif + if (cyc >= 3) begin + `checkh(val1, cyc - 1); + `checkh(val2, cyc - 2); + `checkh(val3, 0); + `checkh(val4, 0); + `checkh(val5, cyc); + `checkh(val6, cyc - 1); + end + end endmodule diff --git a/test_regress/t/t_net_delay_timing.pl b/test_regress/t/t_net_delay_timing.pl deleted file mode 100755 index 0ebdb8a45..000000000 --- a/test_regress/t/t_net_delay_timing.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_net_delay.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_net_delay_timing.py b/test_regress/t/t_net_delay_timing.py new file mode 100755 index 000000000..bc41b20a9 --- /dev/null +++ b/test_regress/t/t_net_delay_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_net_delay.v" + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_net_delay_timing_sc.pl b/test_regress/t/t_net_delay_timing_sc.pl deleted file mode 100755 index 3dd55e6e1..000000000 --- a/test_regress/t/t_net_delay_timing_sc.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 2; - -top_filename("t/t_net_delay.v"); - -compile( - verilator_flags2 => ["--sc --exe --timing --timescale 10ps/1ps"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_net_delay_timing_sc.py b/test_regress/t/t_net_delay_timing_sc.py new file mode 100755 index 000000000..9e15c738f --- /dev/null +++ b/test_regress/t/t_net_delay_timing_sc.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_net_delay.v" +test.main_time_multiplier = 2 + +test.compile(verilator_flags2=["--sc --exe --timing --timescale 10ps/1ps"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_nettype.out b/test_regress/t/t_nettype.out index dc401b4c9..f7581cc3f 100644 --- a/test_regress/t/t_nettype.out +++ b/test_regress/t/t_nettype.out @@ -1,14 +1,14 @@ -%Error-UNSUPPORTED: t/t_nettype.v:25:4: Unsupported: nettype +%Error-UNSUPPORTED: t/t_nettype.v:25:4: Unsupported: nettype with 25 | nettype real real1_n with Pkg::resolver; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_nettype.v:29:4: Unsupported: nettype +%Error-UNSUPPORTED: t/t_nettype.v:29:4: Unsupported: nettype with 29 | nettype real real2_n with local_resolver; | ^~~~~~~ %Error-UNSUPPORTED: t/t_nettype.v:34:4: Unsupported: nettype 34 | nettype real2_n real3_n; | ^~~~~~~ -%Error-UNSUPPORTED: t/t_nettype.v:38:4: Unsupported: nettype +%Error-UNSUPPORTED: t/t_nettype.v:38:4: Unsupported: nettype with 38 | nettype Pkg::real_t real4_n with Pkg::resolver; | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_nettype.pl b/test_regress/t/t_nettype.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_nettype.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_nettype.py b/test_regress/t/t_nettype.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_nettype.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_no_sel_assign_merge_in_cpp.pl b/test_regress/t/t_no_sel_assign_merge_in_cpp.pl deleted file mode 100755 index 72441b2f8..000000000 --- a/test_regress/t/t_no_sel_assign_merge_in_cpp.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_no_sel_assign_merge_in_cpp.py b/test_regress/t/t_no_sel_assign_merge_in_cpp.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_no_sel_assign_merge_in_cpp.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_no_std_bad.pl b/test_regress/t/t_no_std_bad.pl deleted file mode 100755 index b7236cf3c..000000000 --- a/test_regress/t/t_no_std_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint(fails => 1, - verilator_flags2 => ["--no-std", "--exe --main --timing -Wall"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_no_std_bad.py b/test_regress/t/t_no_std_bad.py new file mode 100755 index 000000000..1f7e09325 --- /dev/null +++ b/test_regress/t/t_no_std_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, + verilator_flags2=["--no-std", "--exe --main --timing -Wall"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_no_trace_top.pl b/test_regress/t/t_no_trace_top.pl deleted file mode 100755 index 100fef756..000000000 --- a/test_regress/t/t_no_trace_top.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_cat.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --no-trace-top --exe $Self->{t_dir}/t_no_trace_top.cpp"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simno_trace_top.vcd", - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_no_trace_top.py b/test_regress/t/t_no_trace_top.py new file mode 100755 index 000000000..06f1eac14 --- /dev/null +++ b/test_regress/t/t_no_trace_top.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_cat.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["--trace --no-trace-top --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.obj_dir + "/simno_trace_top.vcd", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_no_typedef_bad.out b/test_regress/t/t_no_typedef_bad.out deleted file mode 100644 index 8b5c328f7..000000000 --- a/test_regress/t/t_no_typedef_bad.out +++ /dev/null @@ -1,4 +0,0 @@ -%Error: t/t_no_typedef_bad.v:10:4: Can't find typedef: 'sometype' - 10 | sometype p; - | ^~~~~~~~ -%Error: Exiting due to diff --git a/test_regress/t/t_no_typedef_bad.pl b/test_regress/t/t_no_typedef_bad.pl deleted file mode 100755 index a9a904f17..000000000 --- a/test_regress/t/t_no_typedef_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--json-only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_notiming.pl b/test_regress/t/t_notiming.pl deleted file mode 100755 index bf475c910..000000000 --- a/test_regress/t/t_notiming.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--no-timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_notiming.py b/test_regress/t/t_notiming.py new file mode 100755 index 000000000..6f71603b5 --- /dev/null +++ b/test_regress/t/t_notiming.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_notiming_off.pl b/test_regress/t/t_notiming_off.pl deleted file mode 100755 index 955b160b1..000000000 --- a/test_regress/t/t_notiming_off.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_off.v"); - -lint( - verilator_flags2 => ["--no-timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_notiming_off.py b/test_regress/t/t_notiming_off.py new file mode 100755 index 000000000..a1cb5082f --- /dev/null +++ b/test_regress/t/t_notiming_off.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_off.v" + +test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_number_bad.out b/test_regress/t/t_number_bad.out deleted file mode 100644 index 4a4568375..000000000 --- a/test_regress/t/t_number_bad.out +++ /dev/null @@ -1,25 +0,0 @@ -%Error: t/t_number_bad.v:9:29: Number is missing value digits: 32'd - 9 | parameter integer FOO2 = 32'd-6; - | ^~~~ -%Error: t/t_number_bad.v:10:29: Number is missing value digits: 32'd - 10 | parameter integer FOO3 = 32'd; - | ^~~~ -%Error: t/t_number_bad.v:11:29: Number is missing value digits: 32'h - 11 | parameter integer FOO4 = 32'h; - | ^~~~ -%Error: t/t_number_bad.v:13:29: Illegal character in binary constant: 2 - 13 | parameter integer FOO5 = 32'b2; - | ^~~~~ -%Error: t/t_number_bad.v:14:29: Illegal character in octal constant - 14 | parameter integer FOO6 = 32'o8; - | ^~~~~ -%Error: t/t_number_bad.v:17:33: Illegal character in binary constant: 4 - 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; - | ^~~~~~ -%Error: t/t_number_bad.v:17:33: Too many digits for 1 bit number: 1'b1?4 - 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; - | ^~~~~~ -%Error: t/t_number_bad.v:17:39: syntax error, unexpected INTEGER NUMBER, expecting ';' - 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; - | ^~~ -%Error: Exiting due to diff --git a/test_regress/t/t_number_bad.pl b/test_regress/t/t_number_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_number_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_number_v_bad.out b/test_regress/t/t_number_v_bad.out deleted file mode 100644 index af57029f9..000000000 --- a/test_regress/t/t_number_v_bad.out +++ /dev/null @@ -1,21 +0,0 @@ -%Warning-NEWERSTD: t/t_number_v_bad.v:11:25: Unbased unsized literals require IEEE 1800-2005 or later. - 11 | wire [127:0] FOO1 = '0; - | ^~ - ... For warning description see https://verilator.org/warn/NEWERSTD?v=latest - ... Use "/* verilator lint_off NEWERSTD */" and lint_on around source to disable this message. -%Warning-NEWERSTD: t/t_number_v_bad.v:12:25: Unbased unsized literals require IEEE 1800-2005 or later. - 12 | wire [127:0] FOO2 = '1; - | ^~ -%Warning-NEWERSTD: t/t_number_v_bad.v:13:25: Unbased unsized literals require IEEE 1800-2005 or later. - 13 | wire [127:0] FOO3 = 'x; - | ^~ -%Warning-NEWERSTD: t/t_number_v_bad.v:14:25: Unbased unsized literals require IEEE 1800-2005 or later. - 14 | wire [127:0] FOO4 = 'X; - | ^~ -%Warning-NEWERSTD: t/t_number_v_bad.v:15:25: Unbased unsized literals require IEEE 1800-2005 or later. - 15 | wire [127:0] FOO5 = 'z; - | ^~ -%Warning-NEWERSTD: t/t_number_v_bad.v:16:25: Unbased unsized literals require IEEE 1800-2005 or later. - 16 | wire [127:0] FOO6 = 'Z; - | ^~ -%Error: Exiting due to diff --git a/test_regress/t/t_number_v_bad.pl b/test_regress/t/t_number_v_bad.pl deleted file mode 100755 index 24b1e474d..000000000 --- a/test_regress/t/t_number_v_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Ethan Sifferman and Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--language 1364-2005"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_opt.cpp b/test_regress/t/t_opt_const.cpp similarity index 100% rename from test_regress/t/t_const_opt.cpp rename to test_regress/t/t_opt_const.cpp diff --git a/test_regress/t/t_opt_const.py b/test_regress/t/t_opt_const.py new file mode 100755 index 000000000..29f9350f8 --- /dev/null +++ b/test_regress/t/t_opt_const.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "-fno-dfg", "--stats", test.pli_filename]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 45) + +test.passes() diff --git a/test_regress/t/t_const_opt.v b/test_regress/t/t_opt_const.v similarity index 100% rename from test_regress/t/t_const_opt.v rename to test_regress/t/t_opt_const.v diff --git a/test_regress/t/t_opt_const_cov.py b/test_regress/t/t_opt_const_cov.py new file mode 100755 index 000000000..1af2400b7 --- /dev/null +++ b/test_regress/t/t_opt_const_cov.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", "--coverage", "--trace"]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 144) + +test.passes() diff --git a/test_regress/t/t_const_opt_cov.v b/test_regress/t/t_opt_const_cov.v similarity index 100% rename from test_regress/t/t_const_opt_cov.v rename to test_regress/t/t_opt_const_cov.v diff --git a/test_regress/t/t_opt_const_dfg.py b/test_regress/t/t_opt_const_dfg.py new file mode 100755 index 000000000..eed838d28 --- /dev/null +++ b/test_regress/t/t_opt_const_dfg.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_opt_const.v" + +test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", test.t_dir + "/t_opt_const.cpp"]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 40) + +test.passes() diff --git a/test_regress/t/t_opt_const_no_expand.py b/test_regress/t/t_opt_const_no_expand.py new file mode 100755 index 000000000..34f51af28 --- /dev/null +++ b/test_regress/t/t_opt_const_no_expand.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_opt_const.v" + +test.compile(verilator_flags2=[ + "-Wno-UNOPTTHREADS", "-fno-dfg", "-fno-expand", "--stats", test.t_dir + "/t_opt_const.cpp" +]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_opt_const_or.py b/test_regress/t/t_opt_const_or.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_opt_const_or.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_opt_or.v b/test_regress/t/t_opt_const_or.v similarity index 100% rename from test_regress/t/t_const_opt_or.v rename to test_regress/t/t_opt_const_or.v diff --git a/test_regress/t/t_opt_const_red.py b/test_regress/t/t_opt_const_red.py new file mode 100755 index 000000000..ab1e823fe --- /dev/null +++ b/test_regress/t/t_opt_const_red.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats"]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 158) + +test.passes() diff --git a/test_regress/t/t_const_opt_red.v b/test_regress/t/t_opt_const_red.v similarity index 100% rename from test_regress/t/t_const_opt_red.v rename to test_regress/t/t_opt_const_red.v diff --git a/test_regress/t/t_const_opt_shortcut.cpp b/test_regress/t/t_opt_const_shortcut.cpp similarity index 100% rename from test_regress/t/t_const_opt_shortcut.cpp rename to test_regress/t/t_opt_const_shortcut.cpp diff --git a/test_regress/t/t_opt_const_shortcut.py b/test_regress/t/t_opt_const_shortcut.py new file mode 100755 index 000000000..340f595be --- /dev/null +++ b/test_regress/t/t_opt_const_shortcut.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/" + test.name + ".cpp"], + verilator_flags2=["-Wno-UNOPTTHREADS", "--stats"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_opt_shortcut.v b/test_regress/t/t_opt_const_shortcut.v similarity index 100% rename from test_regress/t/t_const_opt_shortcut.v rename to test_regress/t/t_opt_const_shortcut.v diff --git a/test_regress/t/t_opt_dead.pl b/test_regress/t/t_opt_dead.pl deleted file mode 100755 index 0ba7b4fd1..000000000 --- a/test_regress/t/t_opt_dead.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -# bug2227, Verilator unsupported, class dead -# This is what we really want: -# file_grep_not("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/dead/ix); -file_grep("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/dead/ix); - -ok(1); -1; diff --git a/test_regress/t/t_opt_dead.py b/test_regress/t/t_opt_dead.py new file mode 100755 index 000000000..10b9c67ff --- /dev/null +++ b/test_regress/t/t_opt_dead.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +# bug2227, Verilator unsupported, class dead +# This is what we really want: +# test.file_grep_not(test.obj_dir + "/V"+test.name+"__Syms.h", r'dead') +test.file_grep(test.obj_dir + "/V" + test.name + "__Syms.h", r'dead') + +test.passes() diff --git a/test_regress/t/t_opt_dead_noassigns.pl b/test_regress/t/t_opt_dead_noassigns.pl deleted file mode 100755 index 2efc82758..000000000 --- a/test_regress/t/t_opt_dead_noassigns.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--fno-dead-assigns'], - ); - -execute( - check_finished => 1, - ); - -my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}_*.cpp"); -file_grep_any(\@files, qr/keptdead/ix); - -ok(1); -1; diff --git a/test_regress/t/t_opt_dead_noassigns.py b/test_regress/t/t_opt_dead_noassigns.py new file mode 100755 index 000000000..c191088d1 --- /dev/null +++ b/test_regress/t/t_opt_dead_noassigns.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--fno-dead-assigns']) + +test.execute() + +files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "_*.cpp") +test.file_grep_any(files, r'keptdead') + +test.passes() diff --git a/test_regress/t/t_opt_dead_nocells.pl b/test_regress/t/t_opt_dead_nocells.pl deleted file mode 100755 index 2d89b8430..000000000 --- a/test_regress/t/t_opt_dead_nocells.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--fno-inline', '--fno-dead-cells'], - ); - -my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}_*.h"); -file_grep_any(\@files, qr/keptdead/ix); - -ok(1); -1; diff --git a/test_regress/t/t_opt_dead_nocells.py b/test_regress/t/t_opt_dead_nocells.py new file mode 100755 index 000000000..3637842f4 --- /dev/null +++ b/test_regress/t/t_opt_dead_nocells.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--fno-inline', '--fno-dead-cells']) + +files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "_*.h") +test.file_grep_any(files, r'keptdead') + +test.passes() diff --git a/test_regress/t/t_opt_localize_deep.pl b/test_regress/t/t_opt_localize_deep.pl deleted file mode 100755 index 7d49cd2cd..000000000 --- a/test_regress/t/t_opt_localize_deep.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_localize_deep.py b/test_regress/t/t_opt_localize_deep.py new file mode 100755 index 000000000..539f320b1 --- /dev/null +++ b/test_regress/t/t_opt_localize_deep.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test) + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_opt_localize_max_size.pl b/test_regress/t/t_opt_localize_max_size.pl deleted file mode 100755 index a7a0b1e7b..000000000 --- a/test_regress/t/t_opt_localize_max_size.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute( - check_finished => 1, - ); - -# Value must differ from that in t_opt_localize_max_size.pl -file_grep($Self->{stats}, qr/Optimizations, Vars localized\s+(\d+)/i, 5); - -ok(1); -1; diff --git a/test_regress/t/t_opt_localize_max_size.py b/test_regress/t/t_opt_localize_max_size.py new file mode 100755 index 000000000..0e8655407 --- /dev/null +++ b/test_regress/t/t_opt_localize_max_size.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--stats"]) + +test.execute() + +# Value must differ from that in t_opt_localize_max_size.py +test.file_grep(test.stats, r'Optimizations, Vars localized\s+(\d+)', 5) + +test.passes() diff --git a/test_regress/t/t_opt_localize_max_size_1.pl b/test_regress/t/t_opt_localize_max_size_1.pl deleted file mode 100755 index f59d5f62e..000000000 --- a/test_regress/t/t_opt_localize_max_size_1.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_opt_localize_max_size.v"); - -compile( - verilator_flags2 => ["--stats --localize-max-size 1"], - ); - -execute( - check_finished => 1, - ); - -# Value must differ from that in t_opt_localize_max_size.pl -file_grep($Self->{stats}, qr/Optimizations, Vars localized\s+(\d+)/i, 4); - -ok(1); -1; diff --git a/test_regress/t/t_opt_localize_max_size_1.py b/test_regress/t/t_opt_localize_max_size_1.py new file mode 100755 index 000000000..72657566d --- /dev/null +++ b/test_regress/t/t_opt_localize_max_size_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_opt_localize_max_size.v" + +test.compile(verilator_flags2=["--stats --localize-max-size 1"]) + +test.execute() + +# Value must differ from that in t_opt_localize_max_size.py +test.file_grep(test.stats, r'Optimizations, Vars localized\s+(\d+)', 4) + +test.passes() diff --git a/test_regress/t/t_opt_table_display.pl b/test_regress/t/t_opt_table_display.pl deleted file mode 100755 index e08f4a744..000000000 --- a/test_regress/t/t_opt_table_display.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_display.py b/test_regress/t/t_opt_table_display.py new file mode 100755 index 000000000..e8fd08599 --- /dev/null +++ b/test_regress/t/t_opt_table_display.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_enum.pl b/test_regress/t/t_opt_table_enum.pl deleted file mode 100755 index a3f38c7f6..000000000 --- a/test_regress/t/t_opt_table_enum.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 1); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_enum.py b/test_regress/t/t_opt_table_enum.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_enum.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_packed_array.pl b/test_regress/t/t_opt_table_packed_array.pl deleted file mode 100755 index a3f38c7f6..000000000 --- a/test_regress/t/t_opt_table_packed_array.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 1); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_packed_array.py b/test_regress/t/t_opt_table_packed_array.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_packed_array.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_real.pl b/test_regress/t/t_opt_table_real.pl deleted file mode 100755 index 6eb66ed4b..000000000 --- a/test_regress/t/t_opt_table_real.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 1); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_real.py b/test_regress/t/t_opt_table_real.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_real.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_same.pl b/test_regress/t/t_opt_table_same.pl deleted file mode 100755 index 2fc8ef4eb..000000000 --- a/test_regress/t/t_opt_table_same.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 2); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 1); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_same.py b/test_regress/t/t_opt_table_same.py new file mode 100755 index 000000000..622bd1b1b --- /dev/null +++ b/test_regress/t/t_opt_table_same.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 2) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_signed.pl b/test_regress/t/t_opt_table_signed.pl deleted file mode 100755 index a3f38c7f6..000000000 --- a/test_regress/t/t_opt_table_signed.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 1); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_signed.py b/test_regress/t/t_opt_table_signed.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_signed.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_sparse.pl b/test_regress/t/t_opt_table_sparse.pl deleted file mode 100755 index 7a079bee2..000000000 --- a/test_regress/t/t_opt_table_sparse.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 2); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_sparse.py b/test_regress/t/t_opt_table_sparse.py new file mode 100755 index 000000000..9d5ac0261 --- /dev/null +++ b/test_regress/t/t_opt_table_sparse.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 2) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_sparse_output_split.pl b/test_regress/t/t_opt_table_sparse_output_split.pl deleted file mode 100755 index f451aeecb..000000000 --- a/test_regress/t/t_opt_table_sparse_output_split.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_opt_table_sparse.v"); -golden_filename("t/t_opt_table_sparse.out"); - -compile( - verilator_flags2 => ["--stats", "--output-split 1"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 2); -} - -# Splitting should set VM_PARALLEL_BUILDS to 1 by default -file_grep("$Self->{obj_dir}/$Self->{vm_prefix}_classes.mk", qr/VM_PARALLEL_BUILDS\s*=\s*1/); - -check_splits(2); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; - -sub check_splits { - my $expected = shift; - my $n; - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - if ($file =~ /__ConstPool_/) { - $n += 1; - } - } - $n == $expected or error("__ConstPool*.cpp not split: $n"); -} diff --git a/test_regress/t/t_opt_table_sparse_output_split.py b/test_regress/t/t_opt_table_sparse_output_split.py new file mode 100755 index 000000000..bc87cb9fc --- /dev/null +++ b/test_regress/t/t_opt_table_sparse_output_split.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_opt_table_sparse.v" +test.golden_filename = "t/t_opt_table_sparse.out" + + +def check_splits(expected): + n = 0 + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'__ConstPool_', filename): + n += 1 + if n != expected: + test.error("__ConstPool*.cpp not split: " + str(n)) + + +test.compile(verilator_flags2=["--stats", "--output-split 1"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 2) + +# Splitting should set VM_PARALLEL_BUILDS to 1 by default +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*1') + +check_splits(2) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_string.pl b/test_regress/t/t_opt_table_string.pl deleted file mode 100755 index a3f38c7f6..000000000 --- a/test_regress/t/t_opt_table_string.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 1); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_string.py b/test_regress/t/t_opt_table_string.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_string.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_struct.pl b/test_regress/t/t_opt_table_struct.pl deleted file mode 100755 index a3f38c7f6..000000000 --- a/test_regress/t/t_opt_table_struct.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 1); -} - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_struct.py b/test_regress/t/t_opt_table_struct.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_struct.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_optm_if_array.pl b/test_regress/t/t_optm_if_array.pl deleted file mode 100755 index 482484eb4..000000000 --- a/test_regress/t/t_optm_if_array.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root*.cpp")) { - file_grep_not($file, qr/rstn_r/); -} - -ok(1); -1; diff --git a/test_regress/t/t_optm_if_array.py b/test_regress/t/t_optm_if_array.py new file mode 100755 index 000000000..0739b468a --- /dev/null +++ b/test_regress/t/t_optm_if_array.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root*.cpp"): + test.file_grep_not(filename, r'rstn_r') + +test.passes() diff --git a/test_regress/t/t_optm_if_array.v b/test_regress/t/t_optm_if_array.v index 4ec2472cc..2004c58eb 100644 --- a/test_regress/t/t_optm_if_array.v +++ b/test_regress/t/t_optm_if_array.v @@ -21,7 +21,7 @@ module t (/*AUTOARG*/ reg [31:0] dinit [0:1]; wire [31:0] dinitout = dinit[0] | dinit[1]; - reg rstn_r; // .pl file checks that this signal gets optimized away + reg rstn_r; // .py file checks that this signal gets optimized away always @(posedge clk) begin rstn_r <= rstn; end diff --git a/test_regress/t/t_optm_redor.pl b/test_regress/t/t_optm_redor.pl deleted file mode 100755 index 482484eb4..000000000 --- a/test_regress/t/t_optm_redor.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root*.cpp")) { - file_grep_not($file, qr/rstn_r/); -} - -ok(1); -1; diff --git a/test_regress/t/t_optm_redor.py b/test_regress/t/t_optm_redor.py new file mode 100755 index 000000000..0739b468a --- /dev/null +++ b/test_regress/t/t_optm_redor.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root*.cpp"): + test.file_grep_not(filename, r'rstn_r') + +test.passes() diff --git a/test_regress/t/t_order.pl b/test_regress/t/t_order.pl deleted file mode 100755 index 800b5bdc4..000000000 --- a/test_regress/t/t_order.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 1e-8 / 1e-9; - -compile( - verilator_flags2 => ["--timescale 10ns/1ns --no-timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order.py b/test_regress/t/t_order.py new file mode 100755 index 000000000..77acf6161 --- /dev/null +++ b/test_regress/t/t_order.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.main_time_multiplier = 1e-8 / 1e-9 + +test.compile(verilator_flags2=["--timescale 10ns/1ns --no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_2d.pl b/test_regress/t/t_order_2d.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_order_2d.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_2d.py b/test_regress/t/t_order_2d.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_2d.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_blkandnblk_bad.pl b/test_regress/t/t_order_blkandnblk_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_order_blkandnblk_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_blkandnblk_bad.py b/test_regress/t/t_order_blkandnblk_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_order_blkandnblk_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_order_blkloopinit_bad.out b/test_regress/t/t_order_blkloopinit_bad.out index d34918ab9..bff530c62 100644 --- a/test_regress/t/t_order_blkloopinit_bad.out +++ b/test_regress/t/t_order_blkloopinit_bad.out @@ -1,18 +1,6 @@ -%Error-BLKLOOPINIT: t/t_order_blkloopinit_bad.v:26:20: Unsupported: Non-blocking assignment to array inside loop in suspendable process or fork +%Error-BLKLOOPINIT: t/t_order_blkloopinit_bad.v:26:20: Unsupported: Non-blocking assignment to array with compound element type inside loop : ... note: In instance 't' - 26 | array1[i] <= 0; + 26 | array2[i] <= null; | ^~ ... For error description see https://verilator.org/warn/BLKLOOPINIT?v=latest -%Error-BLKLOOPINIT: t/t_order_blkloopinit_bad.v:36:20: Unsupported: Non-blocking assignment to array with compound element type inside loop - : ... note: In instance 't' - 36 | array2[i] <= null; - | ^~ -%Error-BLKLOOPINIT: t/t_order_blkloopinit_bad.v:45:20: Unsupported: Non-blocking assignment to array in both loop and suspendable process/fork - : ... note: In instance 't' - t/t_order_blkloopinit_bad.v:50:20: ... Location of non-blocking assignment in suspendable process/fork - 50 | #1 array3[0] <= 0; - | ^~ - t/t_order_blkloopinit_bad.v:45:20: ... Location of non-blocking assignment inside loop - 45 | array3[i] <= 0; - | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_order_blkloopinit_bad.pl b/test_regress/t/t_order_blkloopinit_bad.pl deleted file mode 100755 index e3fd94eb8..000000000 --- a/test_regress/t/t_order_blkloopinit_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_blkloopinit_bad.py b/test_regress/t/t_order_blkloopinit_bad.py new file mode 100755 index 000000000..7009ab7ce --- /dev/null +++ b/test_regress/t/t_order_blkloopinit_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=[], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_order_blkloopinit_bad.v b/test_regress/t/t_order_blkloopinit_bad.v index db0581a5a..74725cbf7 100644 --- a/test_regress/t/t_order_blkloopinit_bad.v +++ b/test_regress/t/t_order_blkloopinit_bad.v @@ -17,17 +17,7 @@ module t (/*AUTOARG*/ localparam SIZE = 65536; - // Unsupported case 1: Array NBA inside suspendable - int array1 [SIZE]; - always @ (posedge clk) begin - #1; - o <= array1[1]; - for (int i=0; i 1); - -# On Verilator, we expect this to pass. -# -# TBD: Will event-based simulators match Verilator's behavior -# closely enough to pass the same test? -# If not -- probably we should switch this to be vlt-only. - -compile(verilator_flags2 => ["--trace"]); - -execute(check_finished => 1); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_order_clkinst.py b/test_regress/t/t_order_clkinst.py new file mode 100755 index 000000000..7b88a42a2 --- /dev/null +++ b/test_regress/t/t_order_clkinst.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# On Verilator, we expect this to pass. +# +# TBD: Will event-based simulators match Verilator's behavior +# closely enough to pass the same test? +# If not -- probably we should switch this to be vlt-only. + +test.compile(verilator_flags2=["--trace"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_order_comboclkloop.pl b/test_regress/t/t_order_comboclkloop.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_order_comboclkloop.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_comboclkloop.py b/test_regress/t/t_order_comboclkloop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_comboclkloop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_comboloop.pl b/test_regress/t/t_order_comboloop.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_order_comboloop.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_comboloop.py b/test_regress/t/t_order_comboloop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_comboloop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_doubleloop.pl b/test_regress/t/t_order_doubleloop.pl deleted file mode 100755 index ce1f8586f..000000000 --- a/test_regress/t/t_order_doubleloop.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_doubleloop.py b/test_regress/t/t_order_doubleloop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_doubleloop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_1.pl b/test_regress/t/t_order_dpi_export_1.pl deleted file mode 100755 index e76a9afcd..000000000 --- a/test_regress/t/t_order_dpi_export_1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_1.py b/test_regress/t/t_order_dpi_export_1.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_2.pl b/test_regress/t/t_order_dpi_export_2.pl deleted file mode 100755 index e76a9afcd..000000000 --- a/test_regress/t/t_order_dpi_export_2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_2.py b/test_regress/t/t_order_dpi_export_2.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_3.pl b/test_regress/t/t_order_dpi_export_3.pl deleted file mode 100755 index e76a9afcd..000000000 --- a/test_regress/t/t_order_dpi_export_3.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_3.py b/test_regress/t/t_order_dpi_export_3.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_4.pl b/test_regress/t/t_order_dpi_export_4.pl deleted file mode 100755 index e76a9afcd..000000000 --- a/test_regress/t/t_order_dpi_export_4.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_4.py b/test_regress/t/t_order_dpi_export_4.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_5.pl b/test_regress/t/t_order_dpi_export_5.pl deleted file mode 100755 index e76a9afcd..000000000 --- a/test_regress/t/t_order_dpi_export_5.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_5.py b/test_regress/t/t_order_dpi_export_5.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_6.pl b/test_regress/t/t_order_dpi_export_6.pl deleted file mode 100755 index e76a9afcd..000000000 --- a/test_regress/t/t_order_dpi_export_6.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_6.py b/test_regress/t/t_order_dpi_export_6.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_7.pl b/test_regress/t/t_order_dpi_export_7.pl deleted file mode 100755 index e76a9afcd..000000000 --- a/test_regress/t/t_order_dpi_export_7.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_7.py b/test_regress/t/t_order_dpi_export_7.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_8.pl b/test_regress/t/t_order_dpi_export_8.pl deleted file mode 100755 index 2c9b6e9f0..000000000 --- a/test_regress/t/t_order_dpi_export_8.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_8.py b/test_regress/t/t_order_dpi_export_8.py new file mode 100755 index 000000000..38f29b4e6 --- /dev/null +++ b/test_regress/t/t_order_dpi_export_8.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_first.pl b/test_regress/t/t_order_first.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_order_first.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_first.py b/test_regress/t/t_order_first.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_loop_bad.pl b/test_regress/t/t_order_loop_bad.pl deleted file mode 100755 index c35bc85ef..000000000 --- a/test_regress/t/t_order_loop_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_loop_bad.py b/test_regress/t/t_order_loop_bad.py new file mode 100755 index 000000000..fc5a55e3f --- /dev/null +++ b/test_regress/t/t_order_loop_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_multialways.pl b/test_regress/t/t_order_multialways.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_order_multialways.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_multialways.py b/test_regress/t/t_order_multialways.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_multialways.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_multidriven.pl b/test_regress/t/t_order_multidriven.pl deleted file mode 100755 index b03a52169..000000000 --- a/test_regress/t/t_order_multidriven.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_order_multidriven.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_multidriven.py b/test_regress/t/t_order_multidriven.py new file mode 100755 index 000000000..ec6142999 --- /dev/null +++ b/test_regress/t/t_order_multidriven.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_quad.pl b/test_regress/t/t_order_quad.pl deleted file mode 100755 index 68f1f0e47..000000000 --- a/test_regress/t/t_order_quad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_quad.py b/test_regress/t/t_order_quad.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_order_quad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_timing.pl b/test_regress/t/t_order_timing.pl deleted file mode 100755 index d00f26d4a..000000000 --- a/test_regress/t/t_order_timing.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 1e-8 / 1e-9; - -top_filename("t/t_order.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timescale 10ns/1ns --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_timing.py b/test_regress/t/t_order_timing.py new file mode 100755 index 000000000..cee17e347 --- /dev/null +++ b/test_regress/t/t_order_timing.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_order.v" +test.main_time_multiplier = 1e-8 / 1e-9 + +test.compile(timing_loop=True, verilator_flags2=["--timescale 10ns/1ns --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_wireloop.pl b/test_regress/t/t_order_wireloop.pl deleted file mode 100755 index 41a50e716..000000000 --- a/test_regress/t/t_order_wireloop.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. - # However we no longer gate optimize this - # Can't use expect_filename here as unstable output - expect => -'%Warning-UNOPTFLAT: t/t_order_wireloop.v:\d+:\d+: Signal unoptimizable: Circular combinational logic: \'bar\' -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_wireloop.py b/test_regress/t/t_order_wireloop.py new file mode 100755 index 000000000..2a9b7aa62 --- /dev/null +++ b/test_regress/t/t_order_wireloop.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all) + +# Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. +# However we no longer gate optimize this +# Can't use expect_filename here as unstable output +test.file_grep( + test.compile_log_filename, + r"%Warning-UNOPTFLAT: t/t_order_wireloop.v:\d+:\d+: Signal unoptimizable: Circular combinational logic: \'bar\'" +) + +test.passes() diff --git a/test_regress/t/t_output_groups.py b/test_regress/t/t_output_groups.py new file mode 100755 index 000000000..37cfd95d2 --- /dev/null +++ b/test_regress/t/t_output_groups.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--output-groups", "2"]) + +test.execute() + +# Check that only vm_classes_*.cpp are to be compiled +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "Foo") +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_Slow_1") +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_1") +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_Slow_2") +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_2") + +test.passes() diff --git a/test_regress/t/t_output_groups.v b/test_regress/t/t_output_groups.v new file mode 100644 index 000000000..7b44e03df --- /dev/null +++ b/test_regress/t/t_output_groups.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +virtual class Base; + pure virtual function int get_param; +endclass +class Foo#(int N = 17) extends Base; + function int get_param; + return N; + endfunction +endclass + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + localparam MAX = 128; + Base q[$]; + generate + // should result in many C++ files + genvar i; + for (i = 0; i < MAX; i++) + initial begin + Foo#(i) item = new; + q.push_back(item); + end + endgenerate + always @(posedge clk) begin + int sum = 0; + foreach (q[i]) + sum += q[i].get_param(); + if (sum != MAX * (MAX - 1) / 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_package.pl b/test_regress/t/t_package.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_package.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package.py b/test_regress/t/t_package.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_abs.pl b/test_regress/t/t_package_abs.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_package_abs.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_abs.py b/test_regress/t/t_package_abs.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_abs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_alone_bad.pl b/test_regress/t/t_package_alone_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_package_alone_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_alone_bad.py b/test_regress/t/t_package_alone_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_package_alone_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_ddecl.pl b/test_regress/t/t_package_ddecl.pl deleted file mode 100755 index 39ae2a784..000000000 --- a/test_regress/t/t_package_ddecl.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --no-timing'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_ddecl.py b/test_regress/t/t_package_ddecl.py new file mode 100755 index 000000000..46560bc9c --- /dev/null +++ b/test_regress/t/t_package_ddecl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --no-timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_ddecl_timing.pl b/test_regress/t/t_package_ddecl_timing.pl deleted file mode 100755 index 85bccb16b..000000000 --- a/test_regress/t/t_package_ddecl_timing.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_package_ddecl.v"); - -compile( - verilator_flags2 => ['--binary --timing'], - timing_loop => 1, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_ddecl_timing.py b/test_regress/t/t_package_ddecl_timing.py new file mode 100755 index 000000000..092a05315 --- /dev/null +++ b/test_regress/t/t_package_ddecl_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_package_ddecl.v" + +test.compile(verilator_flags2=['--binary --timing'], timing_loop=True) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_dimport.pl b/test_regress/t/t_package_dimport.pl deleted file mode 100755 index 1e8c14055..000000000 --- a/test_regress/t/t_package_dimport.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -# Compile only - -ok(1); -1; diff --git a/test_regress/t/t_package_dimport.py b/test_regress/t/t_package_dimport.py new file mode 100755 index 000000000..d474feea7 --- /dev/null +++ b/test_regress/t/t_package_dimport.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +# Compile only + +test.passes() diff --git a/test_regress/t/t_package_dimport.v b/test_regress/t/t_package_dimport.v index 7676ab881..1efb1e5b2 100644 --- a/test_regress/t/t_package_dimport.v +++ b/test_regress/t/t_package_dimport.v @@ -38,10 +38,7 @@ module sub(); endmodule -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t(/*AUTOARG*/); import defs::*; @@ -51,8 +48,6 @@ module t(/*AUTOARG*/ localparam MAX_EXPONENT = log2(MAX_COUNT); localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1); - input clk; - generate if (WHICH == 1) begin : which_true diff --git a/test_regress/t/t_package_dot.pl b/test_regress/t/t_package_dot.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_package_dot.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_dot.py b/test_regress/t/t_package_dot.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_dot.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_dup_bad.pl b/test_regress/t/t_package_dup_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_package_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_dup_bad.py b/test_regress/t/t_package_dup_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_package_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_enum.pl b/test_regress/t/t_package_enum.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_package_enum.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_enum.py b/test_regress/t/t_package_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_export.pl b/test_regress/t/t_package_export.pl deleted file mode 100755 index bfe9a1c14..000000000 --- a/test_regress/t/t_package_export.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['+define+T_PACKAGE_EXPORT',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_export.py b/test_regress/t/t_package_export.py new file mode 100755 index 000000000..06f34925c --- /dev/null +++ b/test_regress/t/t_package_export.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['+define+T_PACKAGE_EXPORT']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_export.v b/test_regress/t/t_package_export.v index a0c297915..1aa9af4bd 100644 --- a/test_regress/t/t_package_export.v +++ b/test_regress/t/t_package_export.v @@ -50,11 +50,7 @@ package pkg31; import pkg30::*; endpackage -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); reg [pkg11::PARAM1 : 0] bus11; reg [pkg11::PARAM2 : 0] bus12; diff --git a/test_regress/t/t_package_export_bad.out b/test_regress/t/t_package_export_bad.out index caa0aa233..d205953d0 100644 --- a/test_regress/t/t_package_export_bad.out +++ b/test_regress/t/t_package_export_bad.out @@ -1,28 +1,28 @@ %Error: t/t_package_export.v:45:17: Export object not found: 'pkg1::BAD_DOES_NOT_EXIST' 45 | export pkg1::BAD_DOES_NOT_EXIST; | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_package_export.v:56:16: Can't find definition of scope/variable/func: 'PARAM2' + : ... Suggested alternative: 'PARAM1' + 56 | reg [pkg11::PARAM2 : 0] bus12; + | ^~~~~~ +%Error: t/t_package_export.v:57:16: Can't find definition of scope/variable/func: 'PARAM3' + : ... Suggested alternative: 'PARAM1' + 57 | reg [pkg11::PARAM3 : 0] bus13; + | ^~~~~~ %Error: t/t_package_export.v:60:16: Can't find definition of scope/variable/func: 'PARAM2' : ... Suggested alternative: 'PARAM1' - 60 | reg [pkg11::PARAM2 : 0] bus12; + 60 | reg [pkg21::PARAM2 : 0] bus22; | ^~~~~~ %Error: t/t_package_export.v:61:16: Can't find definition of scope/variable/func: 'PARAM3' : ... Suggested alternative: 'PARAM1' - 61 | reg [pkg11::PARAM3 : 0] bus13; + 61 | reg [pkg21::PARAM3 : 0] bus23; | ^~~~~~ %Error: t/t_package_export.v:64:16: Can't find definition of scope/variable/func: 'PARAM2' : ... Suggested alternative: 'PARAM1' - 64 | reg [pkg21::PARAM2 : 0] bus22; + 64 | reg [pkg31::PARAM2 : 0] bus32; | ^~~~~~ %Error: t/t_package_export.v:65:16: Can't find definition of scope/variable/func: 'PARAM3' : ... Suggested alternative: 'PARAM1' - 65 | reg [pkg21::PARAM3 : 0] bus23; - | ^~~~~~ -%Error: t/t_package_export.v:68:16: Can't find definition of scope/variable/func: 'PARAM2' - : ... Suggested alternative: 'PARAM1' - 68 | reg [pkg31::PARAM2 : 0] bus32; - | ^~~~~~ -%Error: t/t_package_export.v:69:16: Can't find definition of scope/variable/func: 'PARAM3' - : ... Suggested alternative: 'PARAM1' - 69 | reg [pkg31::PARAM3 : 0] bus33; + 65 | reg [pkg31::PARAM3 : 0] bus33; | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_package_export_bad.pl b/test_regress/t/t_package_export_bad.pl deleted file mode 100755 index e454e2252..000000000 --- a/test_regress/t/t_package_export_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_package_export.v"); - -lint( - v_flags2 => ['+define+T_PACKAGE_EXPORT_BAD',], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - -ok(1); -1; diff --git a/test_regress/t/t_package_export_bad.py b/test_regress/t/t_package_export_bad.py new file mode 100755 index 000000000..593de1e5b --- /dev/null +++ b/test_regress/t/t_package_export_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_package_export.v" + +test.lint(v_flags2=['+define+T_PACKAGE_EXPORT_BAD'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_export_bad2.out b/test_regress/t/t_package_export_bad2.out new file mode 100644 index 000000000..82934dfb3 --- /dev/null +++ b/test_regress/t/t_package_export_bad2.out @@ -0,0 +1,4 @@ +%Error: t/t_package_export_bad2.v:12:18: Export package not found: 'Pkg1b' + 12 | export Pkg1b::*; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_package_export_bad2.py b/test_regress/t/t_package_export_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_package_export_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_export_bad2.v b/test_regress/t/t_package_export_bad2.v new file mode 100644 index 000000000..e2075d7a9 --- /dev/null +++ b/test_regress/t/t_package_export_bad2.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +package Pkg1; +endpackage + +package Pkg10; + // verilator lint_off PKGNODECL + export Pkg1b::*; // BAD - typo in package name +endpackage + +module t (/*AUTOARG*/); +endmodule diff --git a/test_regress/t/t_package_import_bad2.out b/test_regress/t/t_package_import_bad2.out new file mode 100644 index 000000000..a0aed8c9a --- /dev/null +++ b/test_regress/t/t_package_import_bad2.out @@ -0,0 +1,4 @@ +%Error: t/t_package_import_bad2.v:12:11: Importing from missing package 'Pkg1b' + 12 | import Pkg1b::*; + | ^~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_package_import_bad2.py b/test_regress/t/t_package_import_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_package_import_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_import_bad2.v b/test_regress/t/t_package_import_bad2.v new file mode 100644 index 000000000..fd8501c51 --- /dev/null +++ b/test_regress/t/t_package_import_bad2.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +package Pkg1; +endpackage + +package Pkg10; + // verilator lint_off PKGNODECL + import Pkg1b::*; // BAD - typo in package name +endpackage + +module t (/*AUTOARG*/); +endmodule diff --git a/test_regress/t/t_package_local_bad.pl b/test_regress/t/t_package_local_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_package_local_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_local_bad.py b/test_regress/t/t_package_local_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_package_local_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_param.pl b/test_regress/t/t_package_param.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_package_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_param.py b/test_regress/t/t_package_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_struct.pl b/test_regress/t/t_package_struct.pl deleted file mode 100755 index 11eeb66fe..000000000 --- a/test_regress/t/t_package_struct.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_struct.py b/test_regress/t/t_package_struct.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_package_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_twodeep.pl b/test_regress/t/t_package_twodeep.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_package_twodeep.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_twodeep.py b/test_regress/t/t_package_twodeep.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_twodeep.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_twodeep.v b/test_regress/t/t_package_twodeep.v index ff88ff992..0593ae060 100644 --- a/test_regress/t/t_package_twodeep.v +++ b/test_regress/t/t_package_twodeep.v @@ -17,11 +17,7 @@ endpackage // pkg1 module t import pkg1::*; // Test SV 2012 import format - (/*AUTOARG*/ - // Inputs - clk - ); - input clk; + (/*AUTOARG*/); reg [PARAM1:0] bus1; diff --git a/test_regress/t/t_package_verb.pl b/test_regress/t/t_package_verb.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_package_verb.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_verb.py b/test_regress/t/t_package_verb.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_verb.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_packed_concat.v b/test_regress/t/t_packed_concat.v index 39d97a672..1ce2a3eee 100644 --- a/test_regress/t/t_packed_concat.v +++ b/test_regress/t/t_packed_concat.v @@ -4,12 +4,7 @@ // without warranty, 2019 by Driss Hafdi // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); typedef logic [15:0] count_t; typedef bit [31:0] bit_int_t; diff --git a/test_regress/t/t_packed_concat_bad.out b/test_regress/t/t_packed_concat_bad.out index c508f1635..bb7829997 100644 --- a/test_regress/t/t_packed_concat_bad.out +++ b/test_regress/t/t_packed_concat_bad.out @@ -1,15 +1,15 @@ -%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:17:47: Unsized numbers/parameters not allowed in replications. +%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:12:47: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' - 17 | localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; + 12 | localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. -%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:18:46: Unsized numbers/parameters not allowed in concatenations. +%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:13:46: Unsized numbers/parameters not allowed in concatenations. : ... note: In instance 't' - 18 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; + 13 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; | ^~~~~ -%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:18:60: Unsized numbers/parameters not allowed in replications. +%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:13:60: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' - 18 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; + 13 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_packed_concat_bad.pl b/test_regress/t/t_packed_concat_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_packed_concat_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_packed_concat_bad.py b/test_regress/t/t_packed_concat_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_packed_concat_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_packed_concat_bad.v b/test_regress/t/t_packed_concat_bad.v index ee0e3fc07..fb7c04b7a 100644 --- a/test_regress/t/t_packed_concat_bad.v +++ b/test_regress/t/t_packed_concat_bad.v @@ -4,12 +4,7 @@ // without warranty, 2019 by Driss Hafdi // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); typedef logic [15:0] count_t; typedef bit [31:0] bit_int_t; diff --git a/test_regress/t/t_param.pl b/test_regress/t/t_param.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param.py b/test_regress/t/t_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array.pl b/test_regress/t/t_param_array.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_array.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array.py b/test_regress/t/t_param_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array2.pl b/test_regress/t/t_param_array2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_array2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array2.py b/test_regress/t/t_param_array2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array3.pl b/test_regress/t/t_param_array3.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_array3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array3.py b/test_regress/t/t_param_array3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array4.pl b/test_regress/t/t_param_array4.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_array4.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array4.py b/test_regress/t/t_param_array4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array5.pl b/test_regress/t/t_param_array5.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_array5.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array5.py b/test_regress/t/t_param_array5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array6.pl b/test_regress/t/t_param_array6.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_array6.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array6.py b/test_regress/t/t_param_array6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array7.pl b/test_regress/t/t_param_array7.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_array7.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array7.py b/test_regress/t/t_param_array7.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array8.pl b/test_regress/t/t_param_array8.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_array8.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array8.py b/test_regress/t/t_param_array8.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array8.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_avec.pl b/test_regress/t/t_param_avec.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_avec.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_avec.py b/test_regress/t/t_param_avec.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_avec.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_avec.v b/test_regress/t/t_param_avec.v index d56974f9a..87f70486d 100644 --- a/test_regress/t/t_param_avec.v +++ b/test_regress/t/t_param_avec.v @@ -12,9 +12,9 @@ module t (/*AUTOARG*/ clk ); input clk; - sub #(.IDX(0), .CHK(10)) i0; - sub #(.IDX(2), .CHK(12)) i2; - sub #(.IDX(7), .CHK(17)) i7; + sub #(.IDX(0), .CHK(10)) i0(); + sub #(.IDX(2), .CHK(12)) i2(); + sub #(.IDX(7), .CHK(17)) i7(); always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_param_bit_sel.pl b/test_regress/t/t_param_bit_sel.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_bit_sel.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_bit_sel.py b/test_regress/t/t_param_bit_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_bit_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_bracket.pl b/test_regress/t/t_param_bracket.pl deleted file mode 100755 index 09b2ce4eb..000000000 --- a/test_regress/t/t_param_bracket.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_bracket.py b/test_regress/t/t_param_bracket.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_param_bracket.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_param_ceil.pl b/test_regress/t/t_param_ceil.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_ceil.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_ceil.py b/test_regress/t/t_param_ceil.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_ceil.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_chain.pl b/test_regress/t/t_param_chain.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_chain.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_chain.py b/test_regress/t/t_param_chain.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_chain.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_circ_bad.pl b/test_regress/t/t_param_circ_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_param_circ_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_circ_bad.py b/test_regress/t/t_param_circ_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_circ_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_concat.pl b/test_regress/t/t_param_concat.pl deleted file mode 100755 index 563fa5dd7..000000000 --- a/test_regress/t/t_param_concat.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--Wno-WIDTHCONCAT"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_concat.py b/test_regress/t/t_param_concat.py new file mode 100755 index 000000000..8ecb93fe4 --- /dev/null +++ b/test_regress/t/t_param_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--Wno-WIDTHCONCAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_concat_bad.pl b/test_regress/t/t_param_concat_bad.pl deleted file mode 100755 index 33177b739..000000000 --- a/test_regress/t/t_param_concat_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_param_concat.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_concat_bad.py b/test_regress/t/t_param_concat_bad.py new file mode 100755 index 000000000..65a84a628 --- /dev/null +++ b/test_regress/t/t_param_concat_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_param_concat.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_const_part.pl b/test_regress/t/t_param_const_part.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_const_part.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_const_part.py b/test_regress/t/t_param_const_part.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_const_part.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_ddeep_width.pl b/test_regress/t/t_param_ddeep_width.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_param_ddeep_width.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_param_ddeep_width.py b/test_regress/t/t_param_ddeep_width.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_param_ddeep_width.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_param_default.pl b/test_regress/t/t_param_default.pl deleted file mode 100755 index 371f9ce97..000000000 --- a/test_regress/t/t_param_default.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_default.py b/test_regress/t/t_param_default.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_default.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_default_bad.pl b/test_regress/t/t_param_default_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_param_default_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_default_bad.py b/test_regress/t/t_param_default_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_default_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_default_presv_bad.pl b/test_regress/t/t_param_default_presv_bad.pl deleted file mode 100755 index 7cc88a04c..000000000 --- a/test_regress/t/t_param_default_presv_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_param_default_bad.v"); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2005"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_default_presv_bad.py b/test_regress/t/t_param_default_presv_bad.py new file mode 100755 index 000000000..a99a63850 --- /dev/null +++ b/test_regress/t/t_param_default_presv_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_param_default_bad.v" + +test.lint(verilator_flags2=["--lint-only --language 1800-2005"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_first.pl b/test_regress/t/t_param_first.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_first.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_first.py b/test_regress/t/t_param_first.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_func.pl b/test_regress/t/t_param_func.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_param_func.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_func.py b/test_regress/t/t_param_func.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_param_func.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_param_func2.pl b/test_regress/t/t_param_func2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_func2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_func2.py b/test_regress/t/t_param_func2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_func2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_if_blk.pl b/test_regress/t/t_param_if_blk.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_if_blk.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_if_blk.py b/test_regress/t/t_param_if_blk.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_if_blk.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_implicit_local_bad.pl b/test_regress/t/t_param_implicit_local_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_param_implicit_local_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_implicit_local_bad.py b/test_regress/t/t_param_implicit_local_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_implicit_local_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_in_func.pl b/test_regress/t/t_param_in_func.pl deleted file mode 100755 index 06352942b..000000000 --- a/test_regress/t/t_param_in_func.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute(check_finished => 1); - -# The parameter array should have been put in the constant pool -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 3); -} - -# Shouldn't have any references to the parameter array -foreach my $file ( - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.h"), - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp") - ) { - file_grep_not($file, qr/digits/i); -} - -ok(1); -1; diff --git a/test_regress/t/t_param_in_func.py b/test_regress/t/t_param_in_func.py new file mode 100755 index 000000000..e636de991 --- /dev/null +++ b/test_regress/t/t_param_in_func.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +test.execute() + +# The parameter array should have been put in the constant pool +if test.vlt_all: + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 3) + +# Shouldn't have any references to the parameter array +for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): + test.file_grep_not(filename, r'digits') + +test.passes() diff --git a/test_regress/t/t_param_in_func_noinline.pl b/test_regress/t/t_param_in_func_noinline.pl deleted file mode 100755 index 3898be53f..000000000 --- a/test_regress/t/t_param_in_func_noinline.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_param_in_func.v"); - -compile( - verilator_flags2 => ["--stats", "+define+NO_INLINE=1"], - ); - -execute(check_finished => 1); - -# The parameter array should have been put in the constant pool -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 3); -} - -# Shouldn't have any references to the parameter array -foreach my $file ( - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.h"), - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp") - ) { - file_grep_not($file, qr/digits/i); -} - -ok(1); -1; diff --git a/test_regress/t/t_param_in_func_noinline.py b/test_regress/t/t_param_in_func_noinline.py new file mode 100755 index 000000000..6fe5459f1 --- /dev/null +++ b/test_regress/t/t_param_in_func_noinline.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_param_in_func.v" + +test.compile(verilator_flags2=["--stats", "+define+NO_INLINE=1"]) + +test.execute() + +# The parameter array should have been put in the constant pool +if test.vlt_all: + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 3) + +# Shouldn't have any references to the parameter array +for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): + test.file_grep_not(filename, r'digits') + +test.passes() diff --git a/test_regress/t/t_param_local.pl b/test_regress/t/t_param_local.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_local.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_local.py b/test_regress/t/t_param_local.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_long.pl b/test_regress/t/t_param_long.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_long.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_long.py b/test_regress/t/t_param_long.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_long.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_mem_attr.pl b/test_regress/t/t_param_mem_attr.pl deleted file mode 100755 index 184ceb13d..000000000 --- a/test_regress/t/t_param_mem_attr.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile only test. -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_mem_attr.py b/test_regress/t/t_param_mem_attr.py new file mode 100755 index 000000000..84ad9365e --- /dev/null +++ b/test_regress/t/t_param_mem_attr.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# Compile only test. +test.compile() + +test.passes() diff --git a/test_regress/t/t_param_mintypmax.pl b/test_regress/t/t_param_mintypmax.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_mintypmax.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_mintypmax.py b/test_regress/t/t_param_mintypmax.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_mintypmax.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_module.pl b/test_regress/t/t_param_module.pl deleted file mode 100755 index 9270d7e08..000000000 --- a/test_regress/t/t_param_module.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile only test -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_module.py b/test_regress/t/t_param_module.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_module.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_named.pl b/test_regress/t/t_param_named.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_named.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_named.py b/test_regress/t/t_param_named.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_named.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_named_2.pl b/test_regress/t/t_param_named_2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_named_2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_named_2.py b/test_regress/t/t_param_named_2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_named_2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_no_parentheses.pl b/test_regress/t/t_param_no_parentheses.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_no_parentheses.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_no_parentheses.py b/test_regress/t/t_param_no_parentheses.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_no_parentheses.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_noval_bad.pl b/test_regress/t/t_param_noval_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_param_noval_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_noval_bad.py b/test_regress/t/t_param_noval_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_noval_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_package.pl b/test_regress/t/t_param_package.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_package.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_package.py b/test_regress/t/t_param_package.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_package.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_passed_to_port.pl b/test_regress/t/t_param_passed_to_port.pl deleted file mode 100755 index e191e87f4..000000000 --- a/test_regress/t/t_param_passed_to_port.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_passed_to_port.py b/test_regress/t/t_param_passed_to_port.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_passed_to_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_pattern.pl b/test_regress/t/t_param_pattern.pl deleted file mode 100755 index e0e57ed54..000000000 --- a/test_regress/t/t_param_pattern.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--dump-tree'] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_pattern.py b/test_regress/t/t_param_pattern.py new file mode 100755 index 000000000..835a031c1 --- /dev/null +++ b/test_regress/t/t_param_pattern.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--dump-tree']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_public.pl b/test_regress/t/t_param_public.pl deleted file mode 100755 index 6cec8bc56..000000000 --- a/test_regress/t/t_param_public.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{vlt_all}) { - compile( - verilator_flags2 => ["-GTOP_PARAM=30 --exe $Self->{t_dir}/$Self->{name}.cpp"], - make_top_shell => 0, - make_main => 0, - ); -} else { - compile( - ); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_public.py b/test_regress/t/t_param_public.py new file mode 100755 index 000000000..a5d71a2d5 --- /dev/null +++ b/test_regress/t/t_param_public.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.vlt_all: + test.compile(verilator_flags2=["-GTOP_PARAM=30 --exe", test.pli_filename], + make_top_shell=False, + make_main=False) +else: + test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_public.v b/test_regress/t/t_param_public.v index 3d44c62e8..325b4ff74 100644 --- a/test_regress/t/t_param_public.v +++ b/test_regress/t/t_param_public.v @@ -6,11 +6,7 @@ //bug505 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); parameter TOP_PARAM /*verilator public*/ = 20; diff --git a/test_regress/t/t_param_real.pl b/test_regress/t/t_param_real.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_real.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_real.py b/test_regress/t/t_param_real.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_real.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_real2.pl b/test_regress/t/t_param_real2.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_param_real2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_real2.py b/test_regress/t/t_param_real2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_real2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_real2_collision.pl b/test_regress/t/t_param_real2_collision.pl deleted file mode 100755 index bcb6b3d38..000000000 --- a/test_regress/t/t_param_real2_collision.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_param_real2.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_real2_collision.py b/test_regress/t/t_param_real2_collision.py new file mode 100755 index 000000000..9d6a5295f --- /dev/null +++ b/test_regress/t/t_param_real2_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_param_real2.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_repl.pl b/test_regress/t/t_param_repl.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_repl.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_repl.py b/test_regress/t/t_param_repl.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_repl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_scope_bad.pl b/test_regress/t/t_param_scope_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_param_scope_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_scope_bad.py b/test_regress/t/t_param_scope_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_scope_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_seg.pl b/test_regress/t/t_param_seg.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_seg.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_seg.py b/test_regress/t/t_param_seg.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_seg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_sel.pl b/test_regress/t/t_param_sel.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_sel.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_sel.py b/test_regress/t/t_param_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_sel_range.pl b/test_regress/t/t_param_sel_range.pl deleted file mode 100755 index 0a78f9749..000000000 --- a/test_regress/t/t_param_sel_range.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wno-SELRANGE"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_sel_range.py b/test_regress/t/t_param_sel_range.py new file mode 100755 index 000000000..905b4884b --- /dev/null +++ b/test_regress/t/t_param_sel_range.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wno-SELRANGE"]) + +test.passes() diff --git a/test_regress/t/t_param_sel_range_bad.pl b/test_regress/t/t_param_sel_range_bad.pl deleted file mode 100755 index d1780f53f..000000000 --- a/test_regress/t/t_param_sel_range_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_param_sel_range.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_sel_range_bad.py b/test_regress/t/t_param_sel_range_bad.py new file mode 100755 index 000000000..916df8696 --- /dev/null +++ b/test_regress/t/t_param_sel_range_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_param_sel_range.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_shift.pl b/test_regress/t/t_param_shift.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_shift.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_shift.py b/test_regress/t/t_param_shift.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_shift.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type.pl b/test_regress/t/t_param_type.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_type.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type.py b/test_regress/t/t_param_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type2.pl b/test_regress/t/t_param_type2.pl deleted file mode 100755 index 00de9b0a7..000000000 --- a/test_regress/t/t_param_type2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -#execute( -# check_finished => 1, -# ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type2.py b/test_regress/t/t_param_type2.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_param_type2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type3.pl b/test_regress/t/t_param_type3.pl deleted file mode 100755 index 00de9b0a7..000000000 --- a/test_regress/t/t_param_type3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -#execute( -# check_finished => 1, -# ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type3.py b/test_regress/t/t_param_type3.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_param_type3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type4.pl b/test_regress/t/t_param_type4.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_type4.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type4.py b/test_regress/t/t_param_type4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_type4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type4_collision.pl b/test_regress/t/t_param_type4_collision.pl deleted file mode 100755 index c2b4251c7..000000000 --- a/test_regress/t/t_param_type4_collision.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_param_type4.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type4_collision.py b/test_regress/t/t_param_type4_collision.py new file mode 100755 index 000000000..202e9dda9 --- /dev/null +++ b/test_regress/t/t_param_type4_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_param_type4.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type5.pl b/test_regress/t/t_param_type5.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_type5.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type5.py b/test_regress/t/t_param_type5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_type5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type_bad.out b/test_regress/t/t_param_type_bad.out index b2a9ea9de..528bd8fc5 100644 --- a/test_regress/t/t_param_type_bad.out +++ b/test_regress/t/t_param_type_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_param_type_bad.v:9:27: syntax error, unexpected INTEGER NUMBER, expecting TYPE-IDENTIFIER +%Error: t/t_param_type_bad.v:9:27: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER or TYPE-IDENTIFIER or randomize 9 | localparam type bad2 = 2; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_param_type_bad.pl b/test_regress/t/t_param_type_bad.pl deleted file mode 100755 index 7e61cd843..000000000 --- a/test_regress/t/t_param_type_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # Bug1575 required trace to crash - verilator_flags2 => ["--trace"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_bad.py b/test_regress/t/t_param_type_bad.py new file mode 100755 index 000000000..13aced9dc --- /dev/null +++ b/test_regress/t/t_param_type_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # Bug1575 required trace to crash + verilator_flags2=["--trace"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_type_bad2.pl b/test_regress/t/t_param_type_bad2.pl deleted file mode 100755 index 9151f32e0..000000000 --- a/test_regress/t/t_param_type_bad2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # Bug1575 required trace to crash - verilator_flags2 => ["--trace --cc"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_bad2.py b/test_regress/t/t_param_type_bad2.py new file mode 100755 index 000000000..dd2d92256 --- /dev/null +++ b/test_regress/t/t_param_type_bad2.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # Bug1575 required trace to crash + verilator_flags2=["--trace --cc"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_type_bit.pl b/test_regress/t/t_param_type_bit.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_param_type_bit.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_bit.py b/test_regress/t/t_param_type_bit.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_param_type_bit.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_param_type_cmp.pl b/test_regress/t/t_param_type_cmp.pl deleted file mode 100755 index 0b0739b0a..000000000 --- a/test_regress/t/t_param_type_cmp.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_cmp.py b/test_regress/t/t_param_type_cmp.py new file mode 100755 index 000000000..671072f97 --- /dev/null +++ b/test_regress/t/t_param_type_cmp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type_collision.pl b/test_regress/t/t_param_type_collision.pl deleted file mode 100755 index b7dcfce11..000000000 --- a/test_regress/t/t_param_type_collision.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_param_type.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_collision.py b/test_regress/t/t_param_type_collision.py new file mode 100755 index 000000000..9cc944889 --- /dev/null +++ b/test_regress/t/t_param_type_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_param_type.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type_fwd.pl b/test_regress/t/t_param_type_fwd.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_param_type_fwd.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_fwd.py b/test_regress/t/t_param_type_fwd.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_param_type_fwd.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_type_id_bad.out b/test_regress/t/t_param_type_id_bad.out new file mode 100644 index 000000000..4a4d2fb89 --- /dev/null +++ b/test_regress/t/t_param_type_id_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_param_type_id_bad.v:9:34: Expecting a data type: 'i' + 9 | class Cls #(parameter type P_T = i); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_param_type_id_bad.py b/test_regress/t/t_param_type_id_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_param_type_id_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_type_id_bad.v b/test_regress/t/t_param_type_id_bad.v new file mode 100644 index 000000000..fd4482a5f --- /dev/null +++ b/test_regress/t/t_param_type_id_bad.v @@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +int i; + +class Cls #(parameter type P_T = i); +endclass diff --git a/test_regress/t/t_param_unreachable.pl b/test_regress/t/t_param_unreachable.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_unreachable.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_unreachable.py b/test_regress/t/t_param_unreachable.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_unreachable.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_up_bad.pl b/test_regress/t/t_param_up_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_param_up_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_up_bad.py b/test_regress/t/t_param_up_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_up_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_value.pl b/test_regress/t/t_param_value.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_value.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_value.py b/test_regress/t/t_param_value.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_value.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_while.pl b/test_regress/t/t_param_while.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_while.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_while.py b/test_regress/t/t_param_while.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_while.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_while.v b/test_regress/t/t_param_while.v index 8a08f8a44..ac13302af 100644 --- a/test_regress/t/t_param_while.v +++ b/test_regress/t/t_param_while.v @@ -6,11 +6,7 @@ //bug505 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); parameter WIDTH = 33; localparam MAX_WIDTH = 11; diff --git a/test_regress/t/t_param_wide_io.pl b/test_regress/t/t_param_wide_io.pl deleted file mode 100755 index bc18ea2b2..000000000 --- a/test_regress/t/t_param_wide_io.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -#execute(); - -ok(1); -1; diff --git a/test_regress/t/t_param_wide_io.py b/test_regress/t/t_param_wide_io.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_param_wide_io.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_param_width.pl b/test_regress/t/t_param_width.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_param_width.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_width.py b/test_regress/t/t_param_width.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_width.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_width_loc_bad.out b/test_regress/t/t_param_width_loc_bad.out index 985c3ddca..5d3a3b9de 100644 --- a/test_regress/t/t_param_width_loc_bad.out +++ b/test_regress/t/t_param_width_loc_bad.out @@ -1,6 +1,6 @@ -%Warning-WIDTHTRUNC: t/t_param_width_loc_bad.v:25:21: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits. +%Warning-WIDTHTRUNC: t/t_param_width_loc_bad.v:20:21: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits. : ... note: In instance 't.test_i' - 25 | parameter logic param = 1'b0 + 20 | parameter logic param = 1'b0 | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_param_width_loc_bad.pl b/test_regress/t/t_param_width_loc_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_param_width_loc_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_width_loc_bad.py b/test_regress/t/t_param_width_loc_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_width_loc_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_width_loc_bad.v b/test_regress/t/t_param_width_loc_bad.v index 3d61f5d93..bb950d98e 100644 --- a/test_regress/t/t_param_width_loc_bad.v +++ b/test_regress/t/t_param_width_loc_bad.v @@ -4,15 +4,10 @@ // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); // bug1624 - test #(.param(32'd0)) test_i; + test #(.param(32'd0)) test_i(); initial begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_param_x_unique.pl b/test_regress/t/t_param_x_unique.pl deleted file mode 100755 index 688171716..000000000 --- a/test_regress/t/t_param_x_unique.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--trace-fst --x-assign unique"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_x_unique.py b/test_regress/t/t_param_x_unique.py new file mode 100755 index 000000000..b60fcce63 --- /dev/null +++ b/test_regress/t/t_param_x_unique.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--trace-fst --x-assign unique"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_parse_delay.pl b/test_regress/t/t_parse_delay.pl deleted file mode 100755 index d399f16df..000000000 --- a/test_regress/t/t_parse_delay.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --no-timing'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_parse_delay.py b/test_regress/t/t_parse_delay.py new file mode 100755 index 000000000..3436d0b33 --- /dev/null +++ b/test_regress/t/t_parse_delay.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --no-timing']) + +test.passes() diff --git a/test_regress/t/t_parse_delay_timing.pl b/test_regress/t/t_parse_delay_timing.pl deleted file mode 100755 index c5543a880..000000000 --- a/test_regress/t/t_parse_delay_timing.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_parse_delay.v"); - -compile( - verilator_flags2 => ['--binary --timing'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_parse_delay_timing.py b/test_regress/t/t_parse_delay_timing.py new file mode 100755 index 000000000..8143451d7 --- /dev/null +++ b/test_regress/t/t_parse_delay_timing.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_parse_delay.v" + +test.compile(verilator_flags2=['--binary --timing']) + +test.passes() diff --git a/test_regress/t/t_past.pl b/test_regress/t/t_past.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_past.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_past.py b/test_regress/t/t_past.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_past.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_past_bad.pl b/test_regress/t/t_past_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_past_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_past_bad.py b/test_regress/t/t_past_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_past_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_past_funcs.pl b/test_regress/t/t_past_funcs.pl deleted file mode 100755 index e2cfde569..000000000 --- a/test_regress/t/t_past_funcs.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_past_funcs.py b/test_regress/t/t_past_funcs.py new file mode 100755 index 000000000..e55d87378 --- /dev/null +++ b/test_regress/t/t_past_funcs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_past_strobe.pl b/test_regress/t/t_past_strobe.pl deleted file mode 100755 index a2660234f..000000000 --- a/test_regress/t/t_past_strobe.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_past_strobe.py b/test_regress/t/t_past_strobe.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_past_strobe.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_past_unsup.pl b/test_regress/t/t_past_unsup.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_past_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_past_unsup.py b/test_regress/t/t_past_unsup.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_past_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pgo_profoutofdate_bad.pl b/test_regress/t/t_pgo_profoutofdate_bad.pl deleted file mode 100755 index 3e78104a6..000000000 --- a/test_regress/t/t_pgo_profoutofdate_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -compile( - threads => 2, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pgo_profoutofdate_bad.py b/test_regress/t/t_pgo_profoutofdate_bad.py new file mode 100755 index 000000000..dcb5636b3 --- /dev/null +++ b/test_regress/t/t_pgo_profoutofdate_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') + +test.compile(threads=2, fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pgo_threads.pl b/test_regress/t/t_pgo_threads.pl deleted file mode 100755 index e132892fd..000000000 --- a/test_regress/t/t_pgo_threads.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -# It doesn't really matter what test -top_filename("t/t_gen_alw.v"); - -compile( - v_flags2 => ["--prof-pgo"], - threads => 2 - ); - -execute( - all_run_flags => ["+verilator+prof+exec+start+0", - " +verilator+prof+exec+file+/dev/null", - " +verilator+prof+vlt+file+$Self->{obj_dir}/profile.vlt", - ], - check_finished => 1, - ); - -file_grep("$Self->{obj_dir}/profile.vlt", qr/profile_data/i); - -compile( - # Intentionally no --prof-pgo here to make sure profile data can be read in - # without it (that is: --prof-pgo has no effect on profile_data hash names) - v_flags2 => [" $Self->{obj_dir}/profile.vlt"], - threads => 2 - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pgo_threads.py b/test_regress/t/t_pgo_threads.py new file mode 100755 index 000000000..9527e06d0 --- /dev/null +++ b/test_regress/t/t_pgo_threads.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_gen_alw.v" # It doesn't really matter what test + +test.compile(v_flags2=["--prof-pgo"], threads=2) + +test.execute(all_run_flags=[ + "+verilator+prof+exec+start+0", + " +verilator+prof+exec+file+/dev/null", + " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable + +test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data ') + +test.compile( + # Intentionally no --prof-pgo here to make sure profile data can be read in + # without it (that is: --prof-pgo has no effect on profile_data hash names) + v_flags2=[" " + test.obj_dir + "/profile.vlt"], + threads=2) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_pipe_exit_bad.pf b/test_regress/t/t_pipe_exit_bad.pf deleted file mode 100755 index 8f3c42b50..000000000 --- a/test_regress/t/t_pipe_exit_bad.pf +++ /dev/null @@ -1,14 +0,0 @@ -#!/usr/bin/env python3 -# pylint: disable=C0114 -# -# DESCRIPTION: Verilator: Verilog Test example --pipe-filter script -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import sys - -sys.exit("%Error: t_pipe_exit_bad.pf: Intentional bad exit status...") diff --git a/test_regress/t/t_pipe_exit_bad.pl b/test_regress/t/t_pipe_exit_bad.pl deleted file mode 100755 index 79df707f7..000000000 --- a/test_regress/t/t_pipe_exit_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010-2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_pipe_filter.v"); - -lint( - verilator_flags2 => ['-E --pipe-filter \'python3 t/t_pipe_exit_bad.pf\' '], - stdout_filename => $stdout_filename, - fails => 1, - expect => -'%Error: t_pipe_exit_bad.pf: Intentional bad exit status....*', - ); -ok(1); - -1; diff --git a/test_regress/t/t_pipe_exit_bad.py b/test_regress/t/t_pipe_exit_bad.py new file mode 100755 index 000000000..3d64d816b --- /dev/null +++ b/test_regress/t/t_pipe_exit_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_pipe_filter.v" + +test.lint(verilator_flags2=['-E --pipe-filter \'python3 t/t_pipe_exit_bad_pf.pf\' '], fails=True) + +test.file_grep(test.compile_log_filename, + r'%Error: t_pipe_exit_bad_pf.pf: Intentional bad exit status....*') + +test.passes() diff --git a/test_regress/t/t_pipe_exit_bad_pf.pf b/test_regress/t/t_pipe_exit_bad_pf.pf new file mode 100755 index 000000000..3ddf3b8bd --- /dev/null +++ b/test_regress/t/t_pipe_exit_bad_pf.pf @@ -0,0 +1,14 @@ +#!/usr/bin/env python3 +# pylint: disable=C0114 +# +# DESCRIPTION: Verilator: Verilog Test example --pipe-filter script +# +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import sys + +sys.exit("%Error: t_pipe_exit_bad_pf.pf: Intentional bad exit status...") diff --git a/test_regress/t/t_pipe_filter.pf b/test_regress/t/t_pipe_filter.pf deleted file mode 100755 index fe52740c7..000000000 --- a/test_regress/t/t_pipe_filter.pf +++ /dev/null @@ -1,62 +0,0 @@ -#!/usr/bin/env python3 -# pylint: disable=C0103,C0114 -# -# DESCRIPTION: Verilator: Verilog Test example --pipe-filter script -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import re -import sys - -Debug = False - -if Debug: - sys.stderr.write("t_pipe_filter.pf: Hello from t_pipe_filter.pf\n") - -for cmd in sys.stdin: - if Debug: - sys.stderr.write("t_pipe_filter.pf: gotcmd: " + cmd) - - match = re.match(r'read "(.*)"', cmd) - if match: - filename = match.group(1) - - wholefile = "" - # It's faster to slurp the whole file then scan (if needed) - with open(filename, "r", encoding="utf8") as fh: - wholefile = fh.read() - - if 'example_lint' in wholefile: # else short circuit - lineno = 1 - pos = 0 - prefixes = [] - while True: - newpos = wholefile.find('\n', pos) - if newpos < pos: - break - line = wholefile[pos:newpos] - if 'example_lint' in line: - # We don't have a way to specify this yet, so just for now - # sys.stderr.write($line) - prefixes.append("int lint_off_line_" + str(lineno) + - " = 1;\n") - - lineno += 1 - pos = newpos + 1 - - # sys.stderr.write("Line count: %d\n" % lineno) - wholefile = ''.join(prefixes) + wholefile - - print("Content-Length: " + str(len(wholefile)) + "\n" + wholefile) - sys.stdout.flush() - else: - sys.exit("t_pipe_filter.pf: %Error: Unknown command: " + cmd) - -if Debug: - sys.stderr.write("t_pipe_filter.pf: Fin\n") - -sys.exit(0) diff --git a/test_regress/t/t_pipe_filter.pl b/test_regress/t/t_pipe_filter.pl deleted file mode 100755 index c303cef67..000000000 --- a/test_regress/t/t_pipe_filter.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010-2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-E --pipe-filter \'python3 t/t_pipe_filter.pf\' '], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_pipe_filter.py b/test_regress/t/t_pipe_filter.py new file mode 100755 index 000000000..0ca83d0d1 --- /dev/null +++ b/test_regress/t/t_pipe_filter.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-E --pipe-filter \'python3 t/t_pipe_filter_pf.pf\' '], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pipe_filter_pf.pf b/test_regress/t/t_pipe_filter_pf.pf new file mode 100755 index 000000000..d638a1245 --- /dev/null +++ b/test_regress/t/t_pipe_filter_pf.pf @@ -0,0 +1,61 @@ +#!/usr/bin/env python3 +# pylint: disable=C0103,C0114 +# +# DESCRIPTION: Verilator: Verilog Test example --pipe-filter script +# +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import re +import sys + +Debug = False + +if Debug: + sys.stderr.write("t_pipe_filter_pf.pf: Hello from t_pipe_filter_pf.pf\n") + +for cmd in sys.stdin: + if Debug: + sys.stderr.write("t_pipe_filter_pf.pf: gotcmd: " + cmd) + + match = re.match(r'read "(.*)"', cmd) + if match: + filename = match.group(1) + + wholefile = "" + # It's faster to slurp the whole file then scan (if needed) + with open(filename, "r", encoding="utf8") as fh: + wholefile = fh.read() + + if 'example_lint' in wholefile: # else short circuit + lineno = 1 + pos = 0 + prefixes = [] + while True: + newpos = wholefile.find('\n', pos) + if newpos < pos: + break + line = wholefile[pos:newpos] + if 'example_lint' in line: + # We don't have a way to specify this yet, so just for now + # sys.stderr.write($line) + prefixes.append("int lint_off_line_" + str(lineno) + " = 1;\n") + + lineno += 1 + pos = newpos + 1 + + # sys.stderr.write("Line count: %d\n" % lineno) + wholefile = ''.join(prefixes) + wholefile + + print("Content-Length: " + str(len(wholefile)) + "\n" + wholefile) + sys.stdout.flush() + else: + sys.exit("t_pipe_filter_pf.pf: %Error: Unknown command: " + cmd) + +if Debug: + sys.stderr.write("t_pipe_filter_pf.pf: Fin\n") + +sys.exit(0) diff --git a/test_regress/t/t_pkg_identifier_bad.pl b/test_regress/t/t_pkg_identifier_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_pkg_identifier_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pkg_identifier_bad.py b/test_regress/t/t_pkg_identifier_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_pkg_identifier_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pkg_using_dollar_unit_items.pl b/test_regress/t/t_pkg_using_dollar_unit_items.pl deleted file mode 100755 index 7b483d32e..000000000 --- a/test_regress/t/t_pkg_using_dollar_unit_items.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pkg_using_dollar_unit_items.py b/test_regress/t/t_pkg_using_dollar_unit_items.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_pkg_using_dollar_unit_items.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_pli_bad.pl b/test_regress/t/t_pli_bad.pl deleted file mode 100755 index 828e0df38..000000000 --- a/test_regress/t/t_pli_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_pli_bad.py b/test_regress/t/t_pli_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_pli_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pli_bbox.pl b/test_regress/t/t_pli_bbox.pl deleted file mode 100755 index b30ede91e..000000000 --- a/test_regress/t/t_pli_bbox.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_pli_bad.v"); - -lint( - verilator_flags2 => ["--bbox-sys"], - ); - -ok(1); - -1; diff --git a/test_regress/t/t_pli_bbox.py b/test_regress/t/t_pli_bbox.py new file mode 100755 index 000000000..6962d0be1 --- /dev/null +++ b/test_regress/t/t_pli_bbox.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_pli_bad.v" + +test.lint(verilator_flags2=["--bbox-sys"]) + +test.passes() diff --git a/test_regress/t/t_pp_circ_subst_bad.pl b/test_regress/t/t_pp_circ_subst_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_pp_circ_subst_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_circ_subst_bad.py b/test_regress/t/t_pp_circ_subst_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_pp_circ_subst_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_circdef_bad.pl b/test_regress/t/t_pp_circdef_bad.pl deleted file mode 100755 index 98a317817..000000000 --- a/test_regress/t/t_pp_circdef_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - # EOF result varies with Bison version, so can't use .out - expect => qr/define or other nested inclusion/, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_circdef_bad.py b/test_regress/t/t_pp_circdef_bad.py new file mode 100755 index 000000000..0478d07b9 --- /dev/null +++ b/test_regress/t/t_pp_circdef_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True) + +# EOF result varies with Bison version, so can't use .out +test.file_grep(test.compile_log_filename, r'define or other nested inclusion') + +test.passes() diff --git a/test_regress/t/t_pp_defkwd_bad.pl b/test_regress/t/t_pp_defkwd_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_pp_defkwd_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_defkwd_bad.py b/test_regress/t/t_pp_defkwd_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_pp_defkwd_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_defnettype_bad.pl b/test_regress/t/t_pp_defnettype_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_pp_defnettype_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_defnettype_bad.py b/test_regress/t/t_pp_defnettype_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_pp_defnettype_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_defparen_bad.pl b/test_regress/t/t_pp_defparen_bad.pl deleted file mode 100755 index 9de6b85ee..000000000 --- a/test_regress/t/t_pp_defparen_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Wpedantic"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_defparen_bad.py b/test_regress/t/t_pp_defparen_bad.py new file mode 100755 index 000000000..4cc015636 --- /dev/null +++ b/test_regress/t/t_pp_defparen_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Wpedantic"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_display.pl b/test_regress/t/t_pp_display.pl deleted file mode 100755 index 761258c0e..000000000 --- a/test_regress/t/t_pp_display.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_display.py b/test_regress/t/t_pp_display.py new file mode 100755 index 000000000..97abb660e --- /dev/null +++ b/test_regress/t/t_pp_display.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_dupdef.pl b/test_regress/t/t_pp_dupdef.pl deleted file mode 100755 index 723508870..000000000 --- a/test_regress/t/t_pp_dupdef.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-Wno-REDEFMACRO"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_dupdef.py b/test_regress/t/t_pp_dupdef.py new file mode 100755 index 000000000..759a466d9 --- /dev/null +++ b/test_regress/t/t_pp_dupdef.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-Wno-REDEFMACRO"]) + +test.passes() diff --git a/test_regress/t/t_pp_dupdef_bad.pl b/test_regress/t/t_pp_dupdef_bad.pl deleted file mode 100755 index b2d49e566..000000000 --- a/test_regress/t/t_pp_dupdef_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_pp_dupdef.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_dupdef_bad.py b/test_regress/t/t_pp_dupdef_bad.py new file mode 100755 index 000000000..e9153a9f4 --- /dev/null +++ b/test_regress/t/t_pp_dupdef_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_pp_dupdef.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_dupdef_pragma_bad.pl b/test_regress/t/t_pp_dupdef_pragma_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_pp_dupdef_pragma_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_dupdef_pragma_bad.py b/test_regress/t/t_pp_dupdef_pragma_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_pp_dupdef_pragma_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_lib.pl b/test_regress/t/t_pp_lib.pl deleted file mode 100755 index 921a3878f..000000000 --- a/test_regress/t/t_pp_lib.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ['-v', 't/t_pp_lib_library.v'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_lib.py b/test_regress/t/t_pp_lib.py new file mode 100755 index 000000000..1fc2440ba --- /dev/null +++ b/test_regress/t/t_pp_lib.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=['-v', 't/t_pp_lib_library.v']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_pp_line.pl b/test_regress/t/t_pp_line.pl deleted file mode 100755 index d1ed9a923..000000000 --- a/test_regress/t/t_pp_line.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_line.py b/test_regress/t/t_pp_line.py new file mode 100755 index 000000000..ccec64024 --- /dev/null +++ b/test_regress/t/t_pp_line.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_line_bad.pl b/test_regress/t/t_pp_line_bad.pl deleted file mode 100755 index 887b07b64..000000000 --- a/test_regress/t/t_pp_line_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['-no-std'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_line_bad.py b/test_regress/t/t_pp_line_bad.py new file mode 100755 index 000000000..2819d29cf --- /dev/null +++ b/test_regress/t/t_pp_line_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['-no-std'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_misdef_bad.pl b/test_regress/t/t_pp_misdef_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_pp_misdef_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_misdef_bad.py b/test_regress/t/t_pp_misdef_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_pp_misdef_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_pragma_bad.pl b/test_regress/t/t_pp_pragma_bad.pl deleted file mode 100755 index 219eb9526..000000000 --- a/test_regress/t/t_pp_pragma_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["-E -Wpedantic"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_pragma_bad.py b/test_regress/t/t_pp_pragma_bad.py new file mode 100755 index 000000000..f570493aa --- /dev/null +++ b/test_regress/t/t_pp_pragma_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["-E -Wpedantic"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_pragmas.pl b/test_regress/t/t_pp_pragmas.pl deleted file mode 100755 index b26f9434f..000000000 --- a/test_regress/t/t_pp_pragmas.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_pragmas.py b/test_regress/t/t_pp_pragmas.py new file mode 100755 index 000000000..fc5a55e3f --- /dev/null +++ b/test_regress/t/t_pp_pragmas.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_pp_recursedef_bad.pl b/test_regress/t/t_pp_recursedef_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_pp_recursedef_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_recursedef_bad.py b/test_regress/t/t_pp_recursedef_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_pp_recursedef_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_resetall_bad.pl b/test_regress/t/t_pp_resetall_bad.pl deleted file mode 100755 index bfb6f2bb1..000000000 --- a/test_regress/t/t_pp_resetall_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["-Wpedantic"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_resetall_bad.py b/test_regress/t/t_pp_resetall_bad.py new file mode 100755 index 000000000..8df222dcf --- /dev/null +++ b/test_regress/t/t_pp_resetall_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["-Wpedantic"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_underline_bad.pl b/test_regress/t/t_pp_underline_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_pp_underline_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_underline_bad.py b/test_regress/t/t_pp_underline_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_pp_underline_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_underline_bad.v b/test_regress/t/t_pp_underline_bad.v index adcd87d58..7d1ee1bc9 100644 --- a/test_regress/t/t_pp_underline_bad.v +++ b/test_regress/t/t_pp_underline_bad.v @@ -8,6 +8,7 @@ module t; // verilator_no_inline_module initial begin case (1'b1) // synopsys_full_case + 1'b0: $stop; endcase $stop; // Should have failed end diff --git a/test_regress/t/t_premit_rw.pl b/test_regress/t/t_premit_rw.pl deleted file mode 100755 index 691e0fb35..000000000 --- a/test_regress/t/t_premit_rw.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -#execute( -# check_finished => 1, -# ); - -ok(1); -1; diff --git a/test_regress/t/t_premit_rw.py b/test_regress/t/t_premit_rw.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_premit_rw.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_preproc.pl b/test_regress/t/t_preproc.pl deleted file mode 100755 index 1a9daee70..000000000 --- a/test_regress/t/t_preproc.pl +++ /dev/null @@ -1,62 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-DDEF_A0 -DPREDEF_COMMAND_LINE -E'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -preproc_check($Self->{top_filename}, $stdout_filename); -files_identical($stdout_filename, $Self->{golden_filename}); -ok(1); - -sub preproc_check { - my $filename1 = shift; - my $filename2 = shift; - - my @Line_Checks; - { # Read line comments. - my $fh = IO::File->new($filename1) or die "%Error: $! $filename1\n"; - while (defined(my $line = $fh->getline)) { - if ($line =~ /^Line_Preproc_Check/) { - push @Line_Checks, $.; - } - } - $fh->close; - } - { # See if output file agrees. - my $fh = IO::File->new($filename2) or die "%Error: $! $filename2\n"; - my $lineno = 0; - while (defined(my $line = $fh->getline)) { - $lineno++; - if ($line =~ /^\`line\s+(\d+)/) { - $lineno = $1 - 1; - } - if ($line =~ /^Line_Preproc_Check\s+(\d+)/) { - my $linecmt = $1; - my $check = shift @Line_Checks; - if (!$check) { error("$filename2:$.: Extra Line_Preproc_Check\n"); } - if ($linecmt != $check) { error("$filename2:$.: __LINE__ inserted $linecmt, exp=$check\n"); } - if ($lineno != $check) { error("$filename2:$.: __LINE__ on `line $lineno, exp=$check\n"); } - } - } - $fh->close; - } - if ($Line_Checks[0]) { error("$filename2: Missing a Line_Preproc_Check\n"); } -} - -1; diff --git a/test_regress/t/t_preproc.py b/test_regress/t/t_preproc.py new file mode 100755 index 000000000..8ccc75e7a --- /dev/null +++ b/test_regress/t/t_preproc.py @@ -0,0 +1,63 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import collections + +test.scenarios('vlt') + + +def preproc_check(filename1, filename2): + # Read line comments. + line_checks = collections.deque() + with open(filename1, 'r', encoding="latin-1", newline='\n') as fh: + lineno = 0 + for line in fh: + lineno += 1 + if re.match(r'^Line_Preproc_Check', line): + line_checks.append(lineno) + + # See if output file agrees. + with open(filename2, 'r', encoding="latin-1", newline='\n') as fh: + lineno = 0 + for line in fh: + lineno += 1 + m = re.match(r'^\`line\s+(\d+)', line) + if m: + lineno = int(m.group(1)) - 1 + m = re.match(r'^Line_Preproc_Check\s+(\d+)', line) + if m: + linecmt = m.group(1) + check = line_checks.popleft() + file2ln = filename2 + ":" + str(lineno) + if not check: + test.error(file2ln + ": Extra Line_Preproc_Check") + if str(linecmt) != str(check): + test.error(file2ln + ": __LINE__ inserted " + str(linecmt) + ", exp=" + + str(check)) + if str(lineno) != str(check): + test.error(file2ln + ": __LINE__ on `line " + str(lineno) + ", exp=" + + str(check)) + + if len(line_checks): + test.error(filename2 + ": Missing a Line_Preproc_Check") + + +stdout_filename = test.obj_dir + "/" + test.name + "__test.vpp" + +test.compile(verilator_flags2=['-DDEF_A0 -DPREDEF_COMMAND_LINE -E'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +preproc_check(test.top_filename, stdout_filename) +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_cmtend_bad.pl b/test_regress/t/t_preproc_cmtend_bad.pl deleted file mode 100755 index 47d394e3b..000000000 --- a/test_regress/t/t_preproc_cmtend_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - verilator_flags2 => ['--no-std'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_cmtend_bad.py b/test_regress/t/t_preproc_cmtend_bad.py new file mode 100755 index 000000000..889534217 --- /dev/null +++ b/test_regress/t/t_preproc_cmtend_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, verilator_flags2=['--no-std'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_comments.pl b/test_regress/t/t_preproc_comments.pl deleted file mode 100755 index 7aa405ee4..000000000 --- a/test_regress/t/t_preproc_comments.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_preproc.v"); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --pp-comments'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_comments.py b/test_regress/t/t_preproc_comments.py new file mode 100755 index 000000000..87b6cbeb8 --- /dev/null +++ b/test_regress/t/t_preproc_comments.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_preproc.v" + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --pp-comments'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_debugi.pl b/test_regress/t/t_preproc_debugi.pl deleted file mode 100755 index 11755e0d7..000000000 --- a/test_regress/t/t_preproc_debugi.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# Hit the debug statements in the preprocessor for internal coverage - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator", - "-E", - "t/t_preproc_debugi.v", - "--debug", - "--debugi-V3PreShell 10", - ], - tee => $Self->{verbose}, - logfile => "$Self->{obj_dir}/sim.log", - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_debugi.py b/test_regress/t/t_preproc_debugi.py new file mode 100755 index 000000000..a8df3f568 --- /dev/null +++ b/test_regress/t/t_preproc_debugi.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# Hit the debug statements in the preprocessor for internal coverage + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator", + "-E", + "t/t_preproc_debugi.v", + "--debug", + "--debugi-V3PreShell 10", +], + tee=test.verbose, + logfile=test.obj_dir + "/sim.log", + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_preproc_def09.pl b/test_regress/t/t_preproc_def09.pl deleted file mode 100755 index e0a41bb51..000000000 --- a/test_regress/t/t_preproc_def09.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-E'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_def09.py b/test_regress/t/t_preproc_def09.py new file mode 100755 index 000000000..fe9e90689 --- /dev/null +++ b/test_regress/t/t_preproc_def09.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-E'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_defarg_bad.pl b/test_regress/t/t_preproc_defarg_bad.pl deleted file mode 100755 index aa47819e1..000000000 --- a/test_regress/t/t_preproc_defarg_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ["-Wno-context"], - # The .vh file has the error, not the .v file - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_defarg_bad.py b/test_regress/t/t_preproc_defarg_bad.py new file mode 100755 index 000000000..8e1a07120 --- /dev/null +++ b/test_regress/t/t_preproc_defarg_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + fails=True, + verilator_flags2=["-Wno-context"], + # The .vh file has the error, not the .v file + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_defines.pl b/test_regress/t/t_preproc_defines.pl deleted file mode 100755 index c632aecf7..000000000 --- a/test_regress/t/t_preproc_defines.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_preproc.v"); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --dump-defines'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_defines.py b/test_regress/t/t_preproc_defines.py new file mode 100755 index 000000000..433946a97 --- /dev/null +++ b/test_regress/t/t_preproc_defines.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_preproc.v" + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --dump-defines'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_dos.pl b/test_regress/t/t_preproc_dos.pl deleted file mode 100755 index f43a54cd5..000000000 --- a/test_regress/t/t_preproc_dos.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2006-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("$Self->{obj_dir}/$Self->{name}.v"); -golden_filename("$Self->{obj_dir}/$Self->{name}.out"); - -# Rather then having to maintain a new .v and .out, add returns -# to all lines of the existing t_preproc test. - -{ - my $wholefile = file_contents("$Self->{t_dir}/t_preproc.v"); - $wholefile =~ s/\n/\r\n/og; - write_wholefile("$Self->{obj_dir}/$Self->{name}.v", $wholefile); -} -{ - my $wholefile = file_contents("$Self->{t_dir}/t_preproc.out"); - $wholefile =~ s!t/t_preproc.v!$Self->{obj_dir}/t_preproc_dos.v!og; # Fix `line's - write_wholefile($Self->{golden_filename}, $wholefile); -} - -do 't/t_preproc.pl'; - -1; diff --git a/test_regress/t/t_preproc_dos.py b/test_regress/t/t_preproc_dos.py new file mode 100755 index 000000000..ca72b6ab7 --- /dev/null +++ b/test_regress/t/t_preproc_dos.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import runpy + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/" + test.name + ".v" +test.golden_filename = test.obj_dir + "/" + test.name + ".out" + +# Rather then having to maintain a new .v and .out, add returns +# to all lines of the existing t_preproc test. + +wholefile = test.file_contents(test.t_dir + "/t_preproc.v") +wholefile = re.sub(r'\n', r'\r\n', wholefile) +test.write_wholefile(test.obj_dir + "/" + test.name + ".v", wholefile) + +wholefile = test.file_contents(test.t_dir + "/t_preproc.out") +wholefile = re.sub(r't/t_preproc.v', test.obj_dir + "/t_preproc_dos.v", wholefile) # Fix `line's +test.write_wholefile(test.golden_filename, wholefile) + +runpy.run_path('t/t_preproc.py', globals()) diff --git a/test_regress/t/t_preproc_elsif_bad.pl b/test_regress/t/t_preproc_elsif_bad.pl deleted file mode 100755 index cdeb5a8e1..000000000 --- a/test_regress/t/t_preproc_elsif_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - # The .vh file has the error, not the .v file - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_elsif_bad.py b/test_regress/t/t_preproc_elsif_bad.py new file mode 100755 index 000000000..b16466729 --- /dev/null +++ b/test_regress/t/t_preproc_elsif_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + fails=True, + # The .vh file has the error, not the .v file + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof1_bad.pl b/test_regress/t/t_preproc_eof1_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_eof1_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof1_bad.py b/test_regress/t/t_preproc_eof1_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_eof1_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof2_bad.pl b/test_regress/t/t_preproc_eof2_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_eof2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof2_bad.py b/test_regress/t/t_preproc_eof2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_eof2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof3_bad.pl b/test_regress/t/t_preproc_eof3_bad.pl deleted file mode 100755 index 47d394e3b..000000000 --- a/test_regress/t/t_preproc_eof3_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - verilator_flags2 => ['--no-std'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof3_bad.py b/test_regress/t/t_preproc_eof3_bad.py new file mode 100755 index 000000000..889534217 --- /dev/null +++ b/test_regress/t/t_preproc_eof3_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, verilator_flags2=['--no-std'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof4_bad.pl b/test_regress/t/t_preproc_eof4_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_eof4_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof4_bad.py b/test_regress/t/t_preproc_eof4_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_eof4_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof5_bad.pl b/test_regress/t/t_preproc_eof5_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_eof5_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof5_bad.py b/test_regress/t/t_preproc_eof5_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_eof5_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof6_bad.pl b/test_regress/t/t_preproc_eof6_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_eof6_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof6_bad.py b/test_regress/t/t_preproc_eof6_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_eof6_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_ifdef.pl b/test_regress/t/t_preproc_ifdef.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_preproc_ifdef.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_ifdef.py b/test_regress/t/t_preproc_ifdef.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_preproc_ifdef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_preproc_ifexpr.pl b/test_regress/t/t_preproc_ifexpr.pl deleted file mode 100755 index 37bb50fe5..000000000 --- a/test_regress/t/t_preproc_ifexpr.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-E -P'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_ifexpr.py b/test_regress/t/t_preproc_ifexpr.py new file mode 100755 index 000000000..977858180 --- /dev/null +++ b/test_regress/t/t_preproc_ifexpr.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-E -P'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_ifexpr_bad.pl b/test_regress/t/t_preproc_ifexpr_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_ifexpr_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_ifexpr_bad.py b/test_regress/t/t_preproc_ifexpr_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_ifexpr_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_inc_bad.out b/test_regress/t/t_preproc_inc_bad.out index 2f46dacbd..006f0ec09 100644 --- a/test_regress/t/t_preproc_inc_bad.out +++ b/test_regress/t/t_preproc_inc_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_preproc_inc_inc_bad.vh:11:1: syntax error, unexpected endmodule, expecting IDENTIFIER or '(' or randomize +%Error: t/t_preproc_inc_inc_bad.vh:11:1: syntax error, unexpected endmodule, expecting IDENTIFIER or randomize 11 | endmodule | ^~~~~~~~~ t/t_preproc_inc_bad.v:10:1: ... note: In file included from 't_preproc_inc_bad.v' diff --git a/test_regress/t/t_preproc_inc_bad.pl b/test_regress/t/t_preproc_inc_bad.pl deleted file mode 100755 index cdeb5a8e1..000000000 --- a/test_regress/t/t_preproc_inc_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - # The .vh file has the error, not the .v file - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_inc_bad.py b/test_regress/t/t_preproc_inc_bad.py new file mode 100755 index 000000000..b16466729 --- /dev/null +++ b/test_regress/t/t_preproc_inc_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + fails=True, + # The .vh file has the error, not the .v file + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_inc_fn_bad.pl b/test_regress/t/t_preproc_inc_fn_bad.pl deleted file mode 100755 index cdeb5a8e1..000000000 --- a/test_regress/t/t_preproc_inc_fn_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - # The .vh file has the error, not the .v file - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_inc_fn_bad.py b/test_regress/t/t_preproc_inc_fn_bad.py new file mode 100755 index 000000000..b16466729 --- /dev/null +++ b/test_regress/t/t_preproc_inc_fn_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + fails=True, + # The .vh file has the error, not the .v file + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_inc_notfound_bad.pl b/test_regress/t/t_preproc_inc_notfound_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_inc_notfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_inc_notfound_bad.py b/test_regress/t/t_preproc_inc_notfound_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_inc_notfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_inc_recurse_bad.pl b/test_regress/t/t_preproc_inc_recurse_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_inc_recurse_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_inc_recurse_bad.py b/test_regress/t/t_preproc_inc_recurse_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_inc_recurse_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_kwd.pl b/test_regress/t/t_preproc_kwd.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_preproc_kwd.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_kwd.py b/test_regress/t/t_preproc_kwd.py new file mode 100755 index 000000000..fc5a55e3f --- /dev/null +++ b/test_regress/t/t_preproc_kwd.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_preproc_kwd.v b/test_regress/t/t_preproc_kwd.v index e9318dc75..bb3afe655 100644 --- a/test_regress/t/t_preproc_kwd.v +++ b/test_regress/t/t_preproc_kwd.v @@ -4,11 +4,7 @@ // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); v95 v95 (); v01nc v01nc (); diff --git a/test_regress/t/t_preproc_kwd_bad.pl b/test_regress/t/t_preproc_kwd_bad.pl deleted file mode 100755 index 47f9bc97a..000000000 --- a/test_regress/t/t_preproc_kwd_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - verilator_flags2 => ['--no-std'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_kwd_bad.py b/test_regress/t/t_preproc_kwd_bad.py new file mode 100755 index 000000000..291d7509d --- /dev/null +++ b/test_regress/t/t_preproc_kwd_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, verilator_flags2=['--no-std'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_nodef_bad.pl b/test_regress/t/t_preproc_nodef_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_preproc_nodef_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_nodef_bad.py b/test_regress/t/t_preproc_nodef_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_preproc_nodef_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_noline.pl b/test_regress/t/t_preproc_noline.pl deleted file mode 100755 index 6ecbb7651..000000000 --- a/test_regress/t/t_preproc_noline.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -top_filename("t/t_preproc_noline.v"); - -compile( - verilator_flags2 => ['-E -P'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_noline.py b/test_regress/t/t_preproc_noline.py new file mode 100755 index 000000000..60dd75a8c --- /dev/null +++ b/test_regress/t/t_preproc_noline.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_preproc_noline.v" + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-E -P'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_persist.pl b/test_regress/t/t_preproc_persist.pl deleted file mode 100755 index 4f6ffcf30..000000000 --- a/test_regress/t/t_preproc_persist.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - # Override default flags - v_flags => [''], - v_other_filenames => ["t_preproc_persist2.v"], - verilator_flags => ["-E -P +incdir+t -Mdir $Self->{obj_dir}", ], - verilator_flags2 => ['',], - verilator_flags3 => ['',], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_persist.py b/test_regress/t/t_preproc_persist.py new file mode 100755 index 000000000..1fba47b6f --- /dev/null +++ b/test_regress/t/t_preproc_persist.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile( + # Override default flags + v_flags=[''], + v_other_filenames=["t_preproc_persist2.v"], + verilator_flags=["-E -P +incdir+t -Mdir", test.obj_dir], + verilator_flags2=[''], + verilator_flags3=[''], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_preproczero_bad.pl b/test_regress/t/t_preproc_preproczero_bad.pl deleted file mode 100755 index abcaaca95..000000000 --- a/test_regress/t/t_preproc_preproczero_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-E -P'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_preproczero_bad.py b/test_regress/t/t_preproc_preproczero_bad.py new file mode 100755 index 000000000..b213d98c3 --- /dev/null +++ b/test_regress/t/t_preproc_preproczero_bad.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-E -P'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_str_undef.pl b/test_regress/t/t_preproc_str_undef.pl deleted file mode 100755 index c6a015747..000000000 --- a/test_regress/t/t_preproc_str_undef.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_str_undef.py b/test_regress/t/t_preproc_str_undef.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_preproc_str_undef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_stringend_bad.pl b/test_regress/t/t_preproc_stringend_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_stringend_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_stringend_bad.py b/test_regress/t/t_preproc_stringend_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_stringend_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_ttempty.pl b/test_regress/t/t_preproc_ttempty.pl deleted file mode 100755 index 411276940..000000000 --- a/test_regress/t/t_preproc_ttempty.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - # Override default flags - v_flags => [''], - verilator_flags => ["-E -P +incdir+t -Mdir $Self->{obj_dir}", ], - verilator_flags2 => ['',], - verilator_flags3 => ['',], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_ttempty.py b/test_regress/t/t_preproc_ttempty.py new file mode 100755 index 000000000..28ad7e4b2 --- /dev/null +++ b/test_regress/t/t_preproc_ttempty.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile( + # Override default flags + v_flags=[''], + verilator_flags=["-E -P +incdir+t -Mdir", test.obj_dir], + verilator_flags2=[''], + verilator_flags3=[''], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_undefineall.pl b/test_regress/t/t_preproc_undefineall.pl deleted file mode 100755 index 26a1f8cbb..000000000 --- a/test_regress/t/t_preproc_undefineall.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - v_flags2 => ['+define+PREDEF_COMMAND_LINE'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_undefineall.py b/test_regress/t/t_preproc_undefineall.py new file mode 100755 index 000000000..07b8cc53a --- /dev/null +++ b/test_regress/t/t_preproc_undefineall.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(v_flags2=['+define+PREDEF_COMMAND_LINE']) + +test.passes() diff --git a/test_regress/t/t_priority_case.pl b/test_regress/t/t_priority_case.pl deleted file mode 100755 index 4f29861db..000000000 --- a/test_regress/t/t_priority_case.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_priority_case.py b/test_regress/t/t_priority_case.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_priority_case.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_probdist.pl b/test_regress/t/t_probdist.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_probdist.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_probdist.py b/test_regress/t/t_probdist.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_probdist.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_probdist_bad.pl b/test_regress/t/t_probdist_bad.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_probdist_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_probdist_bad.py b/test_regress/t/t_probdist_bad.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_probdist_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_probdist_cmake.pl b/test_regress/t/t_probdist_cmake.pl deleted file mode 100755 index f9854219c..000000000 --- a/test_regress/t/t_probdist_cmake.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_probdist.v"); - -compile( - verilator_make_gmake => 0, - verilator_make_cmake => 1, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_probdist_cmake.py b/test_regress/t/t_probdist_cmake.py new file mode 100755 index 000000000..3dba41365 --- /dev/null +++ b/test_regress/t/t_probdist_cmake.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_probdist.v" + +test.compile(verilator_make_gmake=False, verilator_make_cmake=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_process.pl b/test_regress/t/t_process.pl deleted file mode 100755 index 1ef7ad890..000000000 --- a/test_regress/t/t_process.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--binary --timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process.py b/test_regress/t/t_process.py new file mode 100755 index 000000000..2d2607d45 --- /dev/null +++ b/test_regress/t/t_process.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--binary --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_process.v b/test_regress/t/t_process.v index 9d4f3fbb8..63844225e 100644 --- a/test_regress/t/t_process.v +++ b/test_regress/t/t_process.v @@ -34,7 +34,7 @@ module t(/*AUTOARG*/); if (0) p.await(); if (0) p.suspend(); if (0) p.resume(); - // See also t_urandom.pl + // See also t_urandom.py p.srandom(0); p.set_randstate(p.get_randstate()); diff --git a/test_regress/t/t_process_bad.pl b/test_regress/t/t_process_bad.pl deleted file mode 100755 index 6c378f2d6..000000000 --- a/test_regress/t/t_process_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--json-only", "--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_bad.py b/test_regress/t/t_process_bad.py new file mode 100755 index 000000000..786f00c3e --- /dev/null +++ b/test_regress/t/t_process_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--json-only", "--timing"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_process_copy_constr.py b/test_regress/t/t_process_copy_constr.py new file mode 100755 index 000000000..34b0247e9 --- /dev/null +++ b/test_regress/t/t_process_copy_constr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_process_copy_constr.v b/test_regress/t/t_process_copy_constr.v new file mode 100644 index 000000000..13f57775e --- /dev/null +++ b/test_regress/t/t_process_copy_constr.v @@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +class Cls; + int x = 1; + function new(); + int p = process::self(); + endfunction +endclass + +module t (/*AUTOARG*/ + ); + initial begin + Cls c, d; + c = new; + c.x = 2; + d = new c; + if (d.x != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_process_finished.pl b/test_regress/t/t_process_finished.pl deleted file mode 100755 index b267631e9..000000000 --- a/test_regress/t/t_process_finished.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_finished.py b/test_regress/t/t_process_finished.py new file mode 100755 index 000000000..34b0247e9 --- /dev/null +++ b/test_regress/t/t_process_finished.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_process_fork.pl b/test_regress/t/t_process_fork.pl deleted file mode 100755 index 67c7c9e67..000000000 --- a/test_regress/t/t_process_fork.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_fork.py b/test_regress/t/t_process_fork.py new file mode 100755 index 000000000..a74b0c7ec --- /dev/null +++ b/test_regress/t/t_process_fork.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_process_kill.pl b/test_regress/t/t_process_kill.pl deleted file mode 100755 index b267631e9..000000000 --- a/test_regress/t/t_process_kill.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_kill.py b/test_regress/t/t_process_kill.py new file mode 100755 index 000000000..34b0247e9 --- /dev/null +++ b/test_regress/t/t_process_kill.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_process_notiming.pl b/test_regress/t/t_process_notiming.pl deleted file mode 100755 index f7118bd7d..000000000 --- a/test_regress/t/t_process_notiming.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_process.v"); - -lint( - expect_filename => $Self->{golden_filename}, - v_flags2 => ["+define+T_PROCESS+std::process", "--no-timing"], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_notiming.py b/test_regress/t/t_process_notiming.py new file mode 100755 index 000000000..a4f6917ce --- /dev/null +++ b/test_regress/t/t_process_notiming.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_process.v" + +test.lint(expect_filename=test.golden_filename, + v_flags2=["+define+T_PROCESS+std::process", "--no-timing"], + fails=True) + +test.passes() diff --git a/test_regress/t/t_process_parse.pl b/test_regress/t/t_process_parse.pl deleted file mode 100755 index 4b6b64de0..000000000 --- a/test_regress/t/t_process_parse.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t_process.v"); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["--debug-exit-uvm", "--json-only"], - make_main => 0, - make_top_shell => 0, - verilator_make_gmake => 0, - ); - -file_grep($out_filename, qr/./); # Exists - -ok(1); -1; diff --git a/test_regress/t/t_process_parse.py b/test_regress/t/t_process_parse.py new file mode 100755 index 000000000..5bda0b542 --- /dev/null +++ b/test_regress/t/t_process_parse.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_process.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=["--debug-exit-uvm", "--json-only"], + make_main=False, + make_top_shell=False, + verilator_make_gmake=False) + +test.file_grep(out_filename, r'.') # Exists + +test.passes() diff --git a/test_regress/t/t_process_propagation.pl b/test_regress/t/t_process_propagation.pl deleted file mode 100755 index 7964ebe90..000000000 --- a/test_regress/t/t_process_propagation.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_propagation.py b/test_regress/t/t_process_propagation.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_process_propagation.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_process_rand.pl b/test_regress/t/t_process_rand.pl deleted file mode 100755 index eb241c303..000000000 --- a/test_regress/t/t_process_rand.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--binary --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_rand.py b/test_regress/t/t_process_rand.py new file mode 100755 index 000000000..bef04b878 --- /dev/null +++ b/test_regress/t/t_process_rand.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--binary --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_process_redecl.pl b/test_regress/t/t_process_redecl.pl deleted file mode 100755 index 10266d6f8..000000000 --- a/test_regress/t/t_process_redecl.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_redecl.py b/test_regress/t/t_process_redecl.py new file mode 100755 index 000000000..c8dddaddf --- /dev/null +++ b/test_regress/t/t_process_redecl.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_process_std.pl b/test_regress/t/t_process_std.pl deleted file mode 100755 index 207d1490a..000000000 --- a/test_regress/t/t_process_std.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_process.v"); - -compile( - v_flags2 => ["--binary --timing", "+define+T_PROCESS+std::process"], - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_process_std.py b/test_regress/t/t_process_std.py new file mode 100755 index 000000000..7d37afe6f --- /dev/null +++ b/test_regress/t/t_process_std.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_process.v" + +test.compile(v_flags2=["--binary --timing", "+define+T_PROCESS+std::process"]) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_process_task.pl b/test_regress/t/t_process_task.pl deleted file mode 100755 index ef9cff8c5..000000000 --- a/test_regress/t/t_process_task.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_task.py b/test_regress/t/t_process_task.py new file mode 100755 index 000000000..a57ed056c --- /dev/null +++ b/test_regress/t/t_process_task.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_prof.pl b/test_regress/t/t_prof.pl deleted file mode 100755 index 7150c0c0c..000000000 --- a/test_regress/t/t_prof.pl +++ /dev/null @@ -1,50 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# TODO below might no longer be required as configure checks for -pg -if ($ENV{VERILATOR_TEST_NO_GPROF}) { - skip("Skipping due to VERILATOR_TEST_NO_GPROF"); -} else { - dotest(); -} - -ok(1); - -sub dotest { - compile( - verilator_flags2 => ["--stats --prof-cfuncs +define+T_PROF"], - ); - - unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - setenv('GMON_OUT_PREFIX', "$Self->{obj_dir}/gmon.out"); - - execute( - check_finished => 1, - ); - - my $gmon_path; - $gmon_path = $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - $gmon_path or error("Profiler did not create a gmon.out"); - (my $gmon_base = $gmon_path) =~ s!.*[/\\]!!; - - run(cmd => ["cd $Self->{obj_dir} && gprof $Self->{vm_prefix} $gmon_base > gprof.log"], - check_finished => 0); - - run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_profcfunc gprof.log > profcfuncs.log"], - check_finished => 0); - - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/Overall summary by/); - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/VLib + VL_POWSS_QQQ/); - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/VBlock + t_prof:/); -} - -1; diff --git a/test_regress/t/t_prof.py b/test_regress/t/t_prof.py new file mode 100755 index 000000000..f47b92805 --- /dev/null +++ b/test_regress/t/t_prof.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats --prof-cfuncs +define+T_PROF"]) + +# TODO below might no longer be required as configure checks for -pg +if 'VERILATOR_TEST_NO_GPROF' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GPROF") + +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + test.unlink_ok(filename) +test.setenv('GMON_OUT_PREFIX', test.obj_dir + "/gmon.out") + +test.execute() + +gmon_path = None +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + gmon_path = filename +if not gmon_path: + test.error("Profiler did not create a gmon.out") +gmon_base = re.sub(r'.*[/\\]', '', gmon_path) + +test.run( + cmd=["cd " + test.obj_dir + " && gprof " + test.vm_prefix + " " + gmon_base + " > gprof.log"], + check_finished=False) + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + + "/bin/verilator_profcfunc gprof.log > profcfuncs.log" +], + check_finished=False) + +test.file_grep(test.obj_dir + "/profcfuncs.log", r'Overall summary by') +test.file_grep(test.obj_dir + "/profcfuncs.log", r'VLib + VL_POWSS_QQQ') +test.file_grep(test.obj_dir + "/profcfuncs.log", r'VBlock + t_prof:') + +test.passes() diff --git a/test_regress/t/t_prof_timing.pl b/test_regress/t/t_prof_timing.pl deleted file mode 100755 index 6bc05c186..000000000 --- a/test_regress/t/t_prof_timing.pl +++ /dev/null @@ -1,57 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_prof.v"); - -# TODO below might no longer be required as configure checks for -pg -if ($ENV{VERILATOR_TEST_NO_GPROF}) { - skip("Skipping due to VERILATOR_TEST_NO_GPROF"); -} elsif (!$Self->have_coroutines) { - skip("No coroutine support"); -} else { - dotest(); -} - -ok(1); - -sub dotest { - compile( - verilator_flags2 => ["--stats --prof-cfuncs --binary"], - ); - - unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - setenv('GMON_OUT_PREFIX', "$Self->{obj_dir}/gmon.out"); - - execute( - check_finished => 1, - ); - - my $gmon_path; - $gmon_path = $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - $gmon_path or error("Profiler did not create a gmon.out"); - (my $gmon_base = $gmon_path) =~ s!.*[/\\]!!; - - run(cmd => ["cd $Self->{obj_dir} && gprof $Self->{vm_prefix} $gmon_base > gprof.log"], - check_finished => 0); - - run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_profcfunc gprof.log > profcfuncs.log"], - check_finished => 0); - - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/Overall summary by/); -# Appears that GCC 11.4 has a bug whereby it doesn't trace function calls -# within coroutines; CLang seems to work correctly. -# file_grep("$Self->{obj_dir}/profcfuncs.log", qr/VLib + VL_POWSS_QQQ/); - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/VLib + VL_WRITEF/); - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/VBlock + t_prof:/); -} - -1; diff --git a/test_regress/t/t_prof_timing.py b/test_regress/t/t_prof_timing.py new file mode 100755 index 000000000..e06dc0024 --- /dev/null +++ b/test_regress/t/t_prof_timing.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_prof.v" + +# TODO below might no longer be required as configure checks for -pg +if 'VERILATOR_TEST_NO_GPROF' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GPROF") +if not test.have_coroutines: + test.skip("No coroutine support") + +test.compile(verilator_flags2=["--stats --prof-cfuncs --binary"]) + +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + test.unlink_ok(filename) +test.setenv('GMON_OUT_PREFIX', test.obj_dir + "/gmon.out") + +test.execute() + +gmon_path = None +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + gmon_path = filename +if not gmon_path: + test.error("Profiler did not create a gmon.out") +gmon_base = re.sub(r'.*[/\\]', '', gmon_path) + +test.run( + cmd=["cd " + test.obj_dir + " && gprof " + test.vm_prefix + " " + gmon_base + " > gprof.log"], + check_finished=False) + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + + "/bin/verilator_profcfunc gprof.log > profcfuncs.log" +], + check_finished=False) + +test.file_grep(test.obj_dir + "/profcfuncs.log", r'Overall summary by') +# Appears that GCC 11.4 has a bug whereby it doesn't trace function calls +# within coroutines; CLang seems to work correctly. +# test.file_grep(test.obj_dir + "/profcfuncs.log", r'VLib + VL_POWSS_QQQ') +test.file_grep(test.obj_dir + "/profcfuncs.log", r'VLib + VL_WRITEF') +test.file_grep(test.obj_dir + "/profcfuncs.log", r'VBlock + t_prof:') + +test.passes() diff --git a/test_regress/t/t_profc.pl b/test_regress/t/t_profc.pl deleted file mode 100755 index 453114d26..000000000 --- a/test_regress/t/t_profc.pl +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t_prof.v"); - -ok(1); - -sub dotest { - compile( - verilator_flags2 => ["--stats --prof-c"], - ); - - unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - setenv('GMON_OUT_PREFIX', "$Self->{obj_dir}/gmon.out"); - - execute( - check_finished => 1, - ); - - my $gmon_path; - $gmon_path = $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - $gmon_path or error("Profiler did not create a gmon.out"); - (my $gmon_base = $gmon_path) =~ s!.*[/\\]!!; - - run(cmd => ["cd $Self->{obj_dir} && gprof $Self->{vm_prefix} $gmon_base > gprof.log"], - check_finished => 0); -} - -1; diff --git a/test_regress/t/t_profc.py b/test_regress/t/t_profc.py new file mode 100755 index 000000000..74f928bb9 --- /dev/null +++ b/test_regress/t/t_profc.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_prof.v" + +test.compile(verilator_flags2=["--stats --prof-c +define+T_PROF"]) + +# TODO below might no longer be required as configure checks for -pg +if 'VERILATOR_TEST_NO_GPROF' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GPROF") + +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + test.unlink_ok(filename) +test.setenv('GMON_OUT_PREFIX', test.obj_dir + "/gmon.out") + +test.execute() + +gmon_path = None +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + gmon_path = filename +if not gmon_path: + test.error("Profiler did not create a gmon.out") +gmon_base = re.sub(r'.*[/\\]', '', gmon_path) + +test.run( + cmd=["cd " + test.obj_dir + " && gprof " + test.vm_prefix + " " + gmon_base + " > gprof.log"], + check_finished=False) + +test.passes() diff --git a/test_regress/t/t_profcfunc.pl b/test_regress/t/t_profcfunc.pl deleted file mode 100755 index ec29d69ff..000000000 --- a/test_regress/t/t_profcfunc.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_profcfunc $Self->{t_dir}/t_profcfunc.gprof > profcfuncs.log"], - check_finished => 0); - -files_identical("$Self->{obj_dir}/profcfuncs.log", $Self->{golden_filename}); - -ok(1); - -1; diff --git a/test_regress/t/t_profcfunc.py b/test_regress/t/t_profcfunc.py new file mode 100755 index 000000000..b9523a78b --- /dev/null +++ b/test_regress/t/t_profcfunc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc", + test.t_dir + "/t_profcfunc.gprof > profcfuncs.log" +], + check_finished=False) + +test.files_identical(test.obj_dir + "/profcfuncs.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_program.pl b/test_regress/t/t_program.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_program.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_program.py b/test_regress/t/t_program.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_program.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_program_anonymous.pl b/test_regress/t/t_program_anonymous.pl deleted file mode 100755 index be66c40e6..000000000 --- a/test_regress/t/t_program_anonymous.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_program_anonymous.py b/test_regress/t/t_program_anonymous.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_program_anonymous.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_program_extern.pl b/test_regress/t/t_program_extern.pl deleted file mode 100755 index be66c40e6..000000000 --- a/test_regress/t/t_program_extern.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_program_extern.py b/test_regress/t/t_program_extern.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_program_extern.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_protect_ids.pl b/test_regress/t/t_protect_ids.pl deleted file mode 100755 index 06ec6487b..000000000 --- a/test_regress/t/t_protect_ids.pl +++ /dev/null @@ -1,54 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# Use --debug-protect to assist debug - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d")) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY", - "--trace", - "--coverage", - "-Wno-INSECURE", - "t/t_protect_ids_c.cpp"], - ); - -execute( - check_finished => 1, - ); - -# 'to="PS"' indicates means we probably mis-protected something already protected -# Use --debug-protect to assist debugging these -file_grep_not("$Self->{obj_dir}/$Self->{vm_prefix}__idmap.xml", qr/to="PS/); - -if ($Self->{vlt_all}) { - # Check for secret in any outputs - my $any; - foreach my $filename (glob $Self->{obj_dir} . "/*.[ch]*") { - if ($filename =~ /secret/i) { - $Self->error("Secret found in a filename: " . $filename); - } - file_grep_not($filename, qr/secret/i); - $any = 1; - } - $any or $Self->error("No outputs found"); -} - -ok(1); -1; diff --git a/test_regress/t/t_protect_ids.py b/test_regress/t/t_protect_ids.py new file mode 100755 index 000000000..1c610fc8e --- /dev/null +++ b/test_regress/t/t_protect_ids.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +# Use --debug-protect to assist debug + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile(verilator_flags2=[ + "--protect-ids", "--protect-key SECRET_KEY", "--trace", "--coverage", "-Wno-INSECURE", + "t/t_protect_ids_c.cpp" +]) + +test.execute() + +# 'to="PS"' indicates means we probably mis-protected something already protected +# Use --debug-protect to assist debugging these +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "__idmap.xml", r'to="PS') + +if test.vlt_all: + # Check for secret in any outputs + for filename in test.glob_some(test.obj_dir + "/*.[ch]*"): + if re.search(r'secret', filename, re.IGNORECASE): + test.error("Secret found in a filename: " + filename) + test.file_grep_not(filename, r'secret') + +test.passes() diff --git a/test_regress/t/t_protect_ids_bad.pl b/test_regress/t/t_protect_ids_bad.pl deleted file mode 100755 index 47ea4d4e1..000000000 --- a/test_regress/t/t_protect_ids_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--protect-ids", - "--trace", - "--public", - "--vpi", - ], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_protect_ids_bad.py b/test_regress/t/t_protect_ids_bad.py new file mode 100755 index 000000000..934f802f7 --- /dev/null +++ b/test_regress/t/t_protect_ids_bad.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=[ + "--protect-ids", + "--trace", + "--public", + "--vpi", +], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_protect_ids_debug.pl b/test_regress/t/t_protect_ids_debug.pl deleted file mode 100755 index d1da5019c..000000000 --- a/test_regress/t/t_protect_ids_debug.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_protect_ids.v"); - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY", - "--trace", - "--debug-protect", - "--coverage", - "-Wno-INSECURE",], - verilator_make_gmake => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_protect_ids_debug.py b/test_regress/t/t_protect_ids_debug.py new file mode 100755 index 000000000..10b0e15bb --- /dev/null +++ b/test_regress/t/t_protect_ids_debug.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_protect_ids.v" + +test.compile(verilator_flags2=[ + "--protect-ids", + "--protect-key SECRET_KEY", + "--trace", + "--debug-protect", + "--coverage", + "-Wno-INSECURE", +], + verilator_make_gmake=False) + +test.passes() diff --git a/test_regress/t/t_protect_ids_key.pl b/test_regress/t/t_protect_ids_key.pl deleted file mode 100755 index 8c38f80c2..000000000 --- a/test_regress/t/t_protect_ids_key.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_protect_ids.v"); - -compile( - verilator_flags2 => ["--protect-ids --protect-key SECRET_KEY", - "t/t_protect_ids_c.cpp"], - ); - -execute( - check_finished => 1, - ); - -# Since using a named key, we can check for always identical map -files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__idmap.xml", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_protect_ids_key.py b/test_regress/t/t_protect_ids_key.py new file mode 100755 index 000000000..3cf278fdf --- /dev/null +++ b/test_regress/t/t_protect_ids_key.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_protect_ids.v" + +test.compile(verilator_flags2=["--protect-ids --protect-key SECRET_KEY", "t/t_protect_ids_c.cpp"]) + +test.execute() + +# Since using a named key, we can check for always identical maptest.files_identical(test.obj_dir + "/"+test.vm_prefix+"__idmap.xml", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pub_unpacked_port.pl b/test_regress/t/t_pub_unpacked_port.pl deleted file mode 100755 index 55bd57e5c..000000000 --- a/test_regress/t/t_pub_unpacked_port.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_pub_unpacked_port.py b/test_regress/t/t_pub_unpacked_port.py new file mode 100755 index 000000000..fc5a55e3f --- /dev/null +++ b/test_regress/t/t_pub_unpacked_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_public_clk.pl b/test_regress/t/t_public_clk.pl deleted file mode 100755 index 89f3e05aa..000000000 --- a/test_regress/t/t_public_clk.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - "--exe", - "$Self->{t_dir}/$Self->{name}.cpp" - ], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_public_clk.py b/test_regress/t/t_public_clk.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_public_clk.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_public_seq.pl b/test_regress/t/t_public_seq.pl deleted file mode 100755 index 89f3e05aa..000000000 --- a/test_regress/t/t_public_seq.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - "--exe", - "$Self->{t_dir}/$Self->{name}.cpp" - ], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_public_seq.py b/test_regress/t/t_public_seq.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_public_seq.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue.pl b/test_regress/t/t_queue.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_queue.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue.py b/test_regress/t/t_queue.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue.v b/test_regress/t/t_queue.v index 8aada7da3..57a645f04 100644 --- a/test_regress/t/t_queue.v +++ b/test_regress/t/t_queue.v @@ -6,8 +6,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t (/*AUTOARG*/ @@ -22,9 +21,24 @@ module t (/*AUTOARG*/ typedef integer q_t[$]; + function void set_val(ref integer lhs, input integer rhs); + lhs = rhs; + endfunction + initial begin q_t iq; iq.push_back(42); + + // Resize via [] + set_val(iq[0], 9000); + `checkh(iq.size(), 1); + `checks(iq[0], 9000); + iq[1]++; + `checkh(iq.size(), 2); + `checks(iq[1], 1); + iq[1000] = 1000; + `checkh(iq.size(), 2); + `checks(iq[1000], 0); end always @ (posedge clk) begin @@ -184,6 +198,29 @@ module t (/*AUTOARG*/ `checks(q[0], "front"); //Unsup: `checks(q[$], "front"); + // Resize via [] + q[0] = "long"; + `checkh(q.size(), 1); + `checks(q[0], "long"); + end + + // Append to queue of queues using [] + begin + int q[$][$]; + q[0][0] = 1; + `checkh(q.size(), 1); + `checkh(q[0].size(), 1); + `checks(q[0][0], 1); + end + + // Do not append with [] if used as index + begin + int p[$]; + int q[$]; + q[p[0]] = 1; + `checkh(p.size(), 0); + `checkh(q.size(), 1); + `checks(q[0], 1); end begin diff --git a/test_regress/t/t_queue_back.pl b/test_regress/t/t_queue_back.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_queue_back.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_back.py b/test_regress/t/t_queue_back.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_back.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_back.v b/test_regress/t/t_queue_back.v index 1d8d2bb90..ed940f469 100644 --- a/test_regress/t/t_queue_back.v +++ b/test_regress/t/t_queue_back.v @@ -9,8 +9,14 @@ module t(/*AUTOARG*/); int q[$]; int r; + function void set_val(ref int lhs, input int rhs); + lhs = rhs; + endfunction + initial begin - q = { 20, 30, 40 }; + q = { 60, 50, 40 }; + set_val(q[$-1], 30); + q[$-2] = 20; r = q[$]; if (r != 40) $stop; diff --git a/test_regress/t/t_queue_bounded.pl b/test_regress/t/t_queue_bounded.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_queue_bounded.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_bounded.py b/test_regress/t/t_queue_bounded.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_bounded.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_bounded.v b/test_regress/t/t_queue_bounded.v index 05653887c..60a62378b 100644 --- a/test_regress/t/t_queue_bounded.v +++ b/test_regress/t/t_queue_bounded.v @@ -19,6 +19,8 @@ module t (/*AUTOARG*/); if (q.size() != 3) $stop; q.push_front(0); if (q.size() != 3) $stop; + q[3] = -1; + if (q.size() != 3) $stop; if (q[0] != 0) $stop; if (q[1] != 1) $stop; if (q[2] != 2) $stop; diff --git a/test_regress/t/t_queue_class.pl b/test_regress/t/t_queue_class.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_queue_class.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_class.py b/test_regress/t/t_queue_class.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_class.v b/test_regress/t/t_queue_class.v index 7424ff429..8dcede315 100644 --- a/test_regress/t/t_queue_class.v +++ b/test_regress/t/t_queue_class.v @@ -11,10 +11,15 @@ module t (/*AUTOARG*/); task push_data(int val); que.push_back(val); endtask + + function logic ok; + return '1; + endfunction endclass initial begin Cls c2 [1:0]; + Cls cq[$]; c2[0] = new(); @@ -25,6 +30,13 @@ module t (/*AUTOARG*/); c2[0].que.push_back(10); // Unsupported if (c2[0].que.size() != 2) $stop; + // Test there's no side effect warning on iteration + foreach (cq[i]) + case (cq[i].ok()) + '0: $stop; + '1: $stop; + endcase + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_queue_compare.pl b/test_regress/t/t_queue_compare.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_queue_compare.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_compare.py b/test_regress/t/t_queue_compare.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_concat_assign.py b/test_regress/t/t_queue_concat_assign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_concat_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_concat_assign.v b/test_regress/t/t_queue_concat_assign.v new file mode 100644 index 000000000..b3860878e --- /dev/null +++ b/test_regress/t/t_queue_concat_assign.v @@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + initial begin + bit q1[$] = {1'b1}; + bit q2[$]; + bit [1:0] d1[] = {2'b10}; + bit [1:0] d2[]; + q2 = {q1}; + if (q2[0] != 1) $stop; + + d2 = {2'b11}; + if (d2[0] != 2'b11) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_queue_empty_bad.pl b/test_regress/t/t_queue_empty_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_queue_empty_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_empty_bad.py b/test_regress/t/t_queue_empty_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_queue_empty_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_queue_empty_pin.pl b/test_regress/t/t_queue_empty_pin.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_queue_empty_pin.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_empty_pin.py b/test_regress/t/t_queue_empty_pin.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_empty_pin.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_init.pl b/test_regress/t/t_queue_init.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_queue_init.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_init.py b/test_regress/t/t_queue_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_insert_at_end.pl b/test_regress/t/t_queue_insert_at_end.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_queue_insert_at_end.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_insert_at_end.py b/test_regress/t/t_queue_insert_at_end.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_insert_at_end.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_method.pl b/test_regress/t/t_queue_method.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_queue_method.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_method.py b/test_regress/t/t_queue_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_method.v b/test_regress/t/t_queue_method.v index 88f8fb2c8..84919f529 100644 --- a/test_regress/t/t_queue_method.v +++ b/test_regress/t/t_queue_method.v @@ -1,16 +1,14 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); -`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); - class Cls; int x; function new(int a); @@ -28,6 +26,7 @@ module t (/*AUTOARG*/); int qvunused[$]; // Value returns (unused) int qi[$]; // Index returns int i; + bit b; string string_q[$]; string string_qv[$]; point_3d points_q[$]; // Same as q and qv, but complex value type @@ -188,9 +187,13 @@ module t (/*AUTOARG*/); i = qe.sum; `checkh(i, 32'h0); + i = qe.sum with (item + 1); + `checkh(i, 32'h0); i = qe.product; `checkh(i, 32'h0); + i = qe.product with (item + 1); + `checkh(i, 32'h0); q = '{32'b1100, 32'b1010}; i = q.and; @@ -208,16 +211,37 @@ module t (/*AUTOARG*/); i = qe.and; `checkh(i, 32'b0); + i = qe.and with (item + 1); + `checkh(i, 32'b0); i = qe.or; `checkh(i, 32'b0); + i = qe.or with (item + 1); + `checkh(i, 32'b0); i = qe.xor; `checkh(i, 32'b0); + i = qe.xor with (item + 1); + `checkh(i, 32'b0); q = '{1, 2}; qe = '{1, 2}; `checkh(q == qe, 1'b1); `checkh(q != qe, 1'b0); + string_q = {"a", "bc", "def", "ghij"}; + + i = string_q.sum with (item.len); + `checkh(i, 10); + i = string_q.product with (item.len); + `checkh(i, 24); + b = string_q.sum with (item == "bc"); + `checkh(b, 1'b1); + b = string_q.sum with (item == ""); + `checkh(b, 1'b0); + b = string_q.product with (item inside {"a", "bc", "def"}); + `checkh(b, 1'b0); + b = string_q.product with (item inside {"a", "bc", "def", "ghij"}); + `checkh(b, 1'b1); + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_queue_method2_bad.pl b/test_regress/t/t_queue_method2_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_queue_method2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_method2_bad.py b/test_regress/t/t_queue_method2_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_queue_method2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_queue_method3_bad.pl b/test_regress/t/t_queue_method3_bad.pl deleted file mode 100755 index a083f46f5..000000000 --- a/test_regress/t/t_queue_method3_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_method3_bad.py b/test_regress/t/t_queue_method3_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_queue_method3_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_queue_method_bad.pl b/test_regress/t/t_queue_method_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_queue_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_method_bad.py b/test_regress/t/t_queue_method_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_queue_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_queue_output_func.py b/test_regress/t/t_queue_output_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_output_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_output_func.v b/test_regress/t/t_queue_output_func.v new file mode 100644 index 000000000..eb92638ab --- /dev/null +++ b/test_regress/t/t_queue_output_func.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +class Cls; + int x = 1; +endclass + +task init_set_2 (output Cls c); + c = new; + c.x = 2; +endtask + +module t (/*AUTOARG*/); + + initial begin + Cls cls_q[$]; + init_set_2(cls_q[0]); + if (cls_q[0].x != 2) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_queue_persistence_inl.pl b/test_regress/t/t_queue_persistence_inl.pl deleted file mode 100755 index fee610ab8..000000000 --- a/test_regress/t/t_queue_persistence_inl.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_queue_persistence.v"); - -if (!$Self->have_coroutines) { - skip("No coroutine support"); -} -else { - compile( - timing_loop => 1, - verilator_flags2 => ["--timing"], - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_queue_persistence_inl.py b/test_regress/t/t_queue_persistence_inl.py new file mode 100755 index 000000000..07551a9f2 --- /dev/null +++ b/test_regress/t/t_queue_persistence_inl.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_queue_persistence.v" + +if not test.have_coroutines: + test.skip("No coroutine support") + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_persistence_noinl.pl b/test_regress/t/t_queue_persistence_noinl.pl deleted file mode 100755 index 2f2670fa9..000000000 --- a/test_regress/t/t_queue_persistence_noinl.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_queue_persistence.v"); - -if (!$Self->have_coroutines) { - skip("No coroutine support"); -} -else { - compile( - timing_loop => 1, - verilator_flags2 => ["--binary --timing --fno-inline +define+TEST_NOINLINE"], - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_queue_persistence_noinl.py b/test_regress/t/t_queue_persistence_noinl.py new file mode 100755 index 000000000..4737dc169 --- /dev/null +++ b/test_regress/t/t_queue_persistence_noinl.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_queue_persistence.v" + +if not test.have_coroutines: + test.skip("No coroutine support") + +test.compile(timing_loop=True, + verilator_flags2=["--binary --timing --fno-inline +define+TEST_NOINLINE"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_pushpop.pl b/test_regress/t/t_queue_pushpop.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_queue_pushpop.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_pushpop.py b/test_regress/t/t_queue_pushpop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_pushpop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_pushpop.v b/test_regress/t/t_queue_pushpop.v index acad0a3a2..94992c471 100644 --- a/test_regress/t/t_queue_pushpop.v +++ b/test_regress/t/t_queue_pushpop.v @@ -6,7 +6,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_queue_slice.pl b/test_regress/t/t_queue_slice.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_queue_slice.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_slice.py b/test_regress/t/t_queue_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_slice.v b/test_regress/t/t_queue_slice.v index 88eb8b8a3..07ffa7139 100644 --- a/test_regress/t/t_queue_slice.v +++ b/test_regress/t/t_queue_slice.v @@ -6,7 +6,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t (/*AUTOARG*/); diff --git a/test_regress/t/t_queue_struct.pl b/test_regress/t/t_queue_struct.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_queue_struct.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_struct.py b/test_regress/t/t_queue_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_struct.v b/test_regress/t/t_queue_struct.v index 45fe432c2..59bf57120 100644 --- a/test_regress/t/t_queue_struct.v +++ b/test_regress/t/t_queue_struct.v @@ -13,6 +13,10 @@ module t (/*AUTOARG*/); int b[$]; } st_t; + typedef struct { + int v; + } st_in_t; + function automatic st_t bar(); // verilator no_inline_task for (int i = 0; i < 4; ++i) begin @@ -21,6 +25,7 @@ module t (/*AUTOARG*/); endfunction // bar st_t res; + st_in_t q[$]; initial begin res = bar(); @@ -29,6 +34,10 @@ module t (/*AUTOARG*/); `checkd(res.b[2], 2); `checkd(res.b[3], 3); + q.push_back(st_in_t'{15}); + q[0].v++; + `checkd(q[0].v, 16); + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_queue_unknown_sel.pl b/test_regress/t/t_queue_unknown_sel.pl deleted file mode 100755 index 157d7a50b..000000000 --- a/test_regress/t/t_queue_unknown_sel.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_unknown_sel.py b/test_regress/t/t_queue_unknown_sel.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_queue_unknown_sel.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_queue_unknown_sel.v b/test_regress/t/t_queue_unknown_sel.v index a62e5f031..489c7bcee 100644 --- a/test_regress/t/t_queue_unknown_sel.v +++ b/test_regress/t/t_queue_unknown_sel.v @@ -16,21 +16,21 @@ package z_pkg; localparam int MASKW=DATAW/8; localparam int SIZEW=4; typedef enum logic [OPCODEW-1:0] { - A = 3'h 0, - B = 3'h 1 - } a_op_t; + A = 3'h 0, + B = 3'h 1 + } a_op_t; typedef enum logic [OPCODEW-1:0] { - C = 3'h 0, - D = 3'h 1 - } b_op_t; + C = 3'h 0, + D = 3'h 1 + } b_op_t; typedef enum logic [OPCODEW-1:0] { - E = 3'h 0, - F = 3'h 1 - } c_op_t; + E = 3'h 0, + F = 3'h 1 + } c_op_t; typedef enum logic [OPCODEW-1:0] { - G = 3'h 0, - H = 3'h 1 - } d_op_t; + G = 3'h 0, + H = 3'h 1 + } d_op_t; typedef logic [CIDW-1:0] cid_t; typedef logic [SIDW-1:0] sid_t; typedef logic [CTAGW-1:0] ctag_t; @@ -40,17 +40,17 @@ package z_pkg; typedef logic [SIZEW-1:0] size_t; typedef logic [DATAW-1:0] data_t; typedef logic [MASKW-1:0] mask_t; - typedef struct packed { + typedef struct packed { cid_t cid; a_op_t opcode; address_t address; } x1_ch_t; - typedef struct packed { + typedef struct packed { cid_t cid; b_op_t opcode; address_t address; } x2_ch_t; - typedef struct packed { + typedef struct packed { cid_t cid; sid_t sid; ctag_t ctag; @@ -59,61 +59,61 @@ package z_pkg; state_t state2; state_t state3; address_t address; - logic f4; + logic f4; size_t size; - logic f2; + logic f2; } x3_ch_t; - typedef struct packed { + typedef struct packed { cid_t cid; sid_t sid; ctag_t ctag; stag_t stag; d_op_t opcode; state_t state1; - logic f4; - logic f1; + logic f4; + logic f1; size_t size; - logic f3; + logic f3; } x4_ch_t; - typedef struct packed { + typedef struct packed { cid_t cid; ctag_t ctag; stag_t stag; d_op_t opcode; - logic f1; - logic f3; + logic f1; + logic f3; } x5_ch_t; - typedef struct packed { - logic last; - logic corrupt; + typedef struct packed { + logic last; + logic corrupt; } x6_ch_t; - typedef struct packed { + typedef struct packed { sid_t sid; stag_t stag; } x7_ch_t; - typedef enum { - CH_X1, - CH_Y1, - CH_Y2, - CH_X2, - CH_X3, - CH_Y3, - CH_X4, - CH_X5, - CH_X6, - CH_X7 - } channel_t; + typedef enum { + CH_X1, + CH_Y1, + CH_Y2, + CH_X2, + CH_X3, + CH_Y3, + CH_X4, + CH_X5, + CH_X6, + CH_X7 + } channel_t; parameter channel_t CH_ALL[CH_X7+1] = '{CH_X1, CH_Y1, CH_Y2, CH_X2, CH_X3, CH_Y3, CH_X4, CH_X5, CH_X6, CH_X7}; - typedef enum { - TXN_0, - TXN_1, - TXN_2, - TXN_3, - TXN_4, - TXN_5, - TXN_6, - TXN_7 - } txn_type_t; + typedef enum { + TXN_0, + TXN_1, + TXN_2, + TXN_3, + TXN_4, + TXN_5, + TXN_6, + TXN_7 + } txn_type_t; function txn_type_t txn_type(bit [2:0] opcode, channel_t ch); case(opcode) 3'd0: begin @@ -219,47 +219,47 @@ interface z_if; function automatic logic x5_trig(); return x5_valid; endfunction function automatic logic x6_trig(); return x6_valid; endfunction modport sender ( - output x1_valid, - output x1, - input x2_valid, - input x2, - output x3_valid, - output x3, - input x4_valid, - input x4, - input x5_valid, - input x5, - input x6_valid, - input x6, - input x6_data, - output x7_valid, - output x7, - import x2_trig, - import x4_trig, - import x5_trig, - import x6_trig - ); + output x1_valid, + output x1, + input x2_valid, + input x2, + output x3_valid, + output x3, + input x4_valid, + input x4, + input x5_valid, + input x5, + input x6_valid, + input x6, + input x6_data, + output x7_valid, + output x7, + import x2_trig, + import x4_trig, + import x5_trig, + import x6_trig + ); modport receiver ( - input x1_valid, - input x1, - output x2_valid, - output x2, - input x3_valid, - input x3, - output x4_valid, - output x4, - output x5_valid, - output x5, - output x6_valid, - output x6, - output x6_data, - input x7_valid, - input x7, - import x2_trig, - import x4_trig, - import x5_trig, - import x6_trig - ); + input x1_valid, + input x1, + output x2_valid, + output x2, + input x3_valid, + input x3, + output x4_valid, + output x4, + output x5_valid, + output x5, + output x6_valid, + output x6, + output x6_data, + input x7_valid, + input x7, + import x2_trig, + import x4_trig, + import x5_trig, + import x6_trig + ); endinterface class z_txn_class; import z_pkg::*; @@ -273,14 +273,14 @@ class z_txn_class; rand state_t state1; rand state_t state2; rand state_t state3; - rand logic f1; - rand logic f2; - rand logic f3; - rand logic f4; + rand logic f1; + rand logic f2; + rand logic f3; + rand logic f4; data_t data[]; mask_t mask[]; - bit corrupt[]; - logic [2:0] req_opcode; + bit corrupt[]; + logic [2:0] req_opcode; endclass module z_bfm_sender import z_pkg::*; ( @@ -294,93 +294,93 @@ module z_bfm_sender import z_pkg::*; z_txn_class z_txn[ch.num()]; always @(posedge clk or negedge reset_l) begin if (!reset_l) begin - z_if_sender.x1_valid <= '0; - z_if_sender.x3_valid <= '0; - z_if_sender.x7_valid <= '0; + z_if_sender.x1_valid <= '0; + z_if_sender.x3_valid <= '0; + z_if_sender.x7_valid <= '0; end else begin - foreach (CH_ALL[i]) begin - case(CH_ALL[i]) + foreach (CH_ALL[i]) begin + case(CH_ALL[i]) CH_X1: begin - if (z_txn_qs[i].size() > 0) begin - z_txn[i] = z_txn_qs[i].pop_front(); - z_if_sender.x1_valid <= '1; - z_if_sender.x1.cid <= z_txn[i].cid; - z_if_sender.x1.opcode <= a_op_t'(z_txn[i].req_opcode); - z_if_sender.x1.address <= z_txn[i].address; - end - end + if (z_txn_qs[i].size() > 0) begin + z_txn[i] = z_txn_qs[i].pop_front(); + z_if_sender.x1_valid <= '1; + z_if_sender.x1.cid <= z_txn[i].cid; + z_if_sender.x1.opcode <= a_op_t'(z_txn[i].req_opcode); + z_if_sender.x1.address <= z_txn[i].address; + end + end CH_X3: begin - if (z_txn_qs[i].size() > 0) begin - z_txn[i] = z_txn_qs[i].pop_front(); - z_if_sender.x3_valid <= '1; - z_if_sender.x3.cid <= z_txn[i].cid; - z_if_sender.x3.sid <= z_txn[i].sid; - z_if_sender.x3.ctag <= z_txn[i].ctag; - z_if_sender.x3.stag <= z_txn[i].stag; - z_if_sender.x3.opcode <= c_op_t'(z_txn[i].req_opcode); - z_if_sender.x3.state2 <= z_txn[i].state2; - z_if_sender.x3.state3 <= z_txn[i].state3; - z_if_sender.x3.address <= z_txn[i].address; - z_if_sender.x3.f4 <= z_txn[i].f4; - z_if_sender.x3.size <= z_txn[i].size; - z_if_sender.x3.f2 <= z_txn[i].f2; - end - end + if (z_txn_qs[i].size() > 0) begin + z_txn[i] = z_txn_qs[i].pop_front(); + z_if_sender.x3_valid <= '1; + z_if_sender.x3.cid <= z_txn[i].cid; + z_if_sender.x3.sid <= z_txn[i].sid; + z_if_sender.x3.ctag <= z_txn[i].ctag; + z_if_sender.x3.stag <= z_txn[i].stag; + z_if_sender.x3.opcode <= c_op_t'(z_txn[i].req_opcode); + z_if_sender.x3.state2 <= z_txn[i].state2; + z_if_sender.x3.state3 <= z_txn[i].state3; + z_if_sender.x3.address <= z_txn[i].address; + z_if_sender.x3.f4 <= z_txn[i].f4; + z_if_sender.x3.size <= z_txn[i].size; + z_if_sender.x3.f2 <= z_txn[i].f2; + end + end CH_X7: begin - if (z_txn_qs[i].size() > 0) begin - z_txn[i] = z_txn_qs[i].pop_front(); - z_if_sender.x7.sid <= z_txn[i].sid; - z_if_sender.x7.stag <= z_txn[i].stag; - end - end + if (z_txn_qs[i].size() > 0) begin + z_txn[i] = z_txn_qs[i].pop_front(); + z_if_sender.x7.sid <= z_txn[i].sid; + z_if_sender.x7.stag <= z_txn[i].stag; + end + end CH_X2: begin - if (z_if_sender.x2_trig()) begin - z_txn[i] = new; - z_txn[i].req_txn_type = txn_type(z_if_sender.x2.opcode, ch); - z_txn[i].cid = z_if_sender.x2.cid; - z_txn[i].address = z_if_sender.x2.address; - z_txn_qs[i].push_back(z_txn[i]); - end - end + if (z_if_sender.x2_trig()) begin + z_txn[i] = new; + z_txn[i].req_txn_type = txn_type(z_if_sender.x2.opcode, ch); + z_txn[i].cid = z_if_sender.x2.cid; + z_txn[i].address = z_if_sender.x2.address; + z_txn_qs[i].push_back(z_txn[i]); + end + end CH_X4: begin - if (z_if_sender.x4_trig()) begin - z_txn[i] = new; - z_txn[i].req_txn_type = txn_type(z_if_sender.x4.opcode, ch); - z_txn[i].cid = z_if_sender.x4.cid; - z_txn[i].sid = z_if_sender.x4.sid; - z_txn[i].ctag = z_if_sender.x4.ctag; - z_txn[i].stag = z_if_sender.x4.stag; - z_txn[i].state1 = z_if_sender.x4.state1; - z_txn[i].f1 = z_if_sender.x4.f1; - z_txn[i].f4 = z_if_sender.x4.f4; - z_txn[i].size = z_if_sender.x4.size; - z_txn[i].f3 = z_if_sender.x4.f3; - z_txn_qs[i].push_back(z_txn[i]); - end - end + if (z_if_sender.x4_trig()) begin + z_txn[i] = new; + z_txn[i].req_txn_type = txn_type(z_if_sender.x4.opcode, ch); + z_txn[i].cid = z_if_sender.x4.cid; + z_txn[i].sid = z_if_sender.x4.sid; + z_txn[i].ctag = z_if_sender.x4.ctag; + z_txn[i].stag = z_if_sender.x4.stag; + z_txn[i].state1 = z_if_sender.x4.state1; + z_txn[i].f1 = z_if_sender.x4.f1; + z_txn[i].f4 = z_if_sender.x4.f4; + z_txn[i].size = z_if_sender.x4.size; + z_txn[i].f3 = z_if_sender.x4.f3; + z_txn_qs[i].push_back(z_txn[i]); + end + end CH_X5: begin - if (z_if_sender.x5_trig()) begin - z_txn[i] = new; - z_txn[i].req_txn_type = txn_type(z_if_sender.x5.opcode, ch); - z_txn[i].cid = z_if_sender.x5.cid; - z_txn[i].ctag = z_if_sender.x5.ctag; - z_txn[i].f1 = z_if_sender.x5.f1; - z_txn_qs[i].push_back(z_txn[i]); - end + if (z_if_sender.x5_trig()) begin + z_txn[i] = new; + z_txn[i].req_txn_type = txn_type(z_if_sender.x5.opcode, ch); + z_txn[i].cid = z_if_sender.x5.cid; + z_txn[i].ctag = z_if_sender.x5.ctag; + z_txn[i].f1 = z_if_sender.x5.f1; + z_txn_qs[i].push_back(z_txn[i]); + end end CH_X6: begin - if (z_if_sender.x6_trig()) begin - z_txn[i] = new; - z_txn[i].data = new[1]; - z_txn[i].corrupt = new[1]; - z_txn[i].data[0] = z_if_sender.x6_data; - z_txn[i].corrupt[0] = z_if_sender.x6.corrupt; - z_txn_qs[i].push_back(z_txn[i]); - end - end - endcase - end + if (z_if_sender.x6_trig()) begin + z_txn[i] = new; + z_txn[i].data = new[1]; + z_txn[i].corrupt = new[1]; + z_txn[i].data[0] = z_if_sender.x6_data; + z_txn[i].corrupt[0] = z_if_sender.x6.corrupt; + z_txn_qs[i].push_back(z_txn[i]); + end + end + endcase + end end end endmodule @@ -392,9 +392,9 @@ module test_core_wrapper mmio_z ); z_bfm_sender mem_z_bfm( .z_if_sender(z), - .*); + .*); z_bfm_sender mmio_z_bfm( .z_if_sender(mmio_z), - .*); + .*); endmodule module t ( @@ -404,6 +404,6 @@ module t z_if z(), mmio_z(); test_core_wrapper tile( .z (z.sender), - .mmio_z(mmio_z.sender), - .*); + .mmio_z(mmio_z.sender), + .*); endmodule diff --git a/test_regress/t/t_queue_unpacked.pl b/test_regress/t/t_queue_unpacked.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_queue_unpacked.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_unpacked.py b/test_regress/t/t_queue_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_unpacked.v b/test_regress/t/t_queue_unpacked.v index 566de16b6..30c3b41f9 100644 --- a/test_regress/t/t_queue_unpacked.v +++ b/test_regress/t/t_queue_unpacked.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 `define stop $stop -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/); @@ -36,6 +36,11 @@ module t (/*AUTOARG*/); `checks(b0[1], "world"); `checks(b1[0], "bye"); `checks(b1[1], "world"); + + iq[2][0] = "goodbye"; + iq[2][1] = "world"; + `checks(iq[2][0], "goodbye"); + `checks(iq[2][1], "world"); end `ifndef verilator diff --git a/test_regress/t/t_queue_var_slice.pl b/test_regress/t/t_queue_var_slice.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_queue_var_slice.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_var_slice.py b/test_regress/t/t_queue_var_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_var_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_void_ops.pl b/test_regress/t/t_queue_void_ops.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_queue_void_ops.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_void_ops.py b/test_regress/t/t_queue_void_ops.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_void_ops.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randc.pl b/test_regress/t/t_randc.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_randc.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randc.py b/test_regress/t/t_randc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randc_oversize_bad.pl b/test_regress/t/t_randc_oversize_bad.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_randc_oversize_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randc_oversize_bad.py b/test_regress/t/t_randc_oversize_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randc_oversize_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randcase.pl b/test_regress/t/t_randcase.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_randcase.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randcase.py b/test_regress/t/t_randcase.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randcase.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randcase_bad.pl b/test_regress/t/t_randcase_bad.pl deleted file mode 100755 index e988c6264..000000000 --- a/test_regress/t/t_randcase_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randcase_bad.py b/test_regress/t/t_randcase_bad.py new file mode 100755 index 000000000..97abb660e --- /dev/null +++ b/test_regress/t/t_randcase_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize.out b/test_regress/t/t_randomize.out index 5c2adb883..136639289 100644 --- a/test_regress/t/t_randomize.out +++ b/test_regress/t/t_randomize.out @@ -1,4 +1,4 @@ -%Warning-CONSTRAINTIGN: t/t_randomize.v:22:14: Constraint expression ignored (unsupported) +%Warning-CONSTRAINTIGN: t/t_randomize.v:22:14: Constraint expression ignored (imperfect distribution) : ... note: In instance 't' 22 | length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; | ^~~~ @@ -8,7 +8,7 @@ : ... note: In instance 't' 40 | unique { array[0], array[1] }; | ^~~~~~ -%Warning-CONSTRAINTIGN: t/t_randomize.v:43:23: Constraint expression ignored (unsupported) +%Warning-CONSTRAINTIGN: t/t_randomize.v:43:23: Constraint expression ignored (imperfect distribution) : ... note: In instance 't' 43 | constraint order { solve length before header; } | ^~~~~ diff --git a/test_regress/t/t_randomize.pl b/test_regress/t/t_randomize.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_randomize.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize.py b/test_regress/t/t_randomize.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randomize.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_array.py b/test_regress/t/t_randomize_array.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_array.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_array.v b/test_regress/t/t_randomize_array.v new file mode 100755 index 000000000..63747653c --- /dev/null +++ b/test_regress/t/t_randomize_array.v @@ -0,0 +1,282 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by PlanV GmbH. +// SPDX-License-Identifier: CC0-1.0 + +`define check_rand(cl, field) \ +begin \ + longint prev_result; \ + int ok = 0; \ + void'(cl.randomize()); \ + prev_result = longint'(field); \ + repeat(9) begin \ + longint result; \ + void'(cl.randomize()); \ + result = longint'(field); \ + if (result != prev_result) ok = 1; \ + prev_result = result; \ + end \ + if (ok != 1) $stop; \ +end + +class unconstrained_packed_array_test; + + rand bit [3:0] [2:0] [15:0] packed_array; + function new(); + packed_array = '{default: '{default: '{default: 'h0}}}; + endfunction + + function void check_randomization(); + `check_rand(this, this.packed_array) + endfunction + +endclass + +class unconstrained_unpacked_array_test; + + rand bit [2:0] [15:0] unpacked_array [3][5]; + rand int unpacked_array1 [9:3][4:8]; + rand int unpacked_array2 [3:9][8:4]; + function new(); + unpacked_array = '{ '{default: '{default: 'h0}}, + '{default: '{default: 'h1}}, + '{default: '{default: 'h2}}}; + unpacked_array1 = '{default: '{default: 0}}; + unpacked_array2 = '{default: '{default: 0}}; + endfunction + + function void check_randomization(); + foreach (unpacked_array[i]) begin + foreach (unpacked_array[i][j]) begin + // At the innermost packed level, invoke check_rand + `check_rand(this, this.unpacked_array[i][j]) + end + end + foreach (unpacked_array1[i, j]) begin + `check_rand(this, this.unpacked_array1[i][j]) + end + foreach (unpacked_array2[i, j]) begin + `check_rand(this, this.unpacked_array2[i][j]) + end + endfunction + +endclass + +class Cls; + rand int x = 1; +endclass + +class unconstrained_dynamic_array_test; + + rand int dynamic_array_1d[]; + rand int dynamic_array_2d[][]; + rand Cls class_dynamic_array[]; + + function new(); + // Initialize 1D dynamic array + dynamic_array_1d = new[5]; + foreach(dynamic_array_1d[i]) begin + dynamic_array_1d[i] = 'h0 + i; + end + + // Initialize 2D dynamic array + dynamic_array_2d = new[3]; + foreach(dynamic_array_2d[i]) begin + dynamic_array_2d[i] = new[3]; + foreach(dynamic_array_2d[i][j]) begin + dynamic_array_2d[i][j] = 'h0 + i + j; + end + end + + class_dynamic_array = new[5]; + foreach(class_dynamic_array[i]) begin + class_dynamic_array[i] = new; + end + + endfunction + + function void check_randomization(); + foreach (dynamic_array_1d[i]) begin + `check_rand(this, dynamic_array_1d[i]) + end + foreach (dynamic_array_2d[i]) begin + foreach (dynamic_array_2d[i][j]) begin + `check_rand(this, dynamic_array_2d[i][j]) + end + end + foreach (class_dynamic_array[i]) begin + `check_rand(this, class_dynamic_array[i].x) + end + endfunction + +endclass + +class unconstrained_struct_with_array_test; + + typedef struct { + rand bit [7:0] byte_array[4]; + } struct_with_array_t; + + rand struct_with_array_t struct_with_array; + + function new(); + struct_with_array = '{'{default: 'h0}}; + endfunction + + function void check_randomization(); + foreach (struct_with_array.byte_array[i]) begin + `check_rand(this, struct_with_array.byte_array[i]) + end + endfunction + +endclass + +class unconstrained_struct_array_test; + + typedef struct { + rand int field_a; + rand int field_b; + } simple_struct_t; + rand simple_struct_t struct_array_1[3]; // Unpacked array + rand simple_struct_t struct_array_2[][]; // Dynamic array + + function new(); + struct_array_1 = '{'{default: 0}, '{default: 1}, '{default: 2}}; + + struct_array_2 = new[3]; + foreach (struct_array_2[i]) begin + struct_array_2[i] = new[4]; + end + endfunction + + function void check_randomization(); + foreach (struct_array_1[i]) begin + `check_rand(this, struct_array_1[i].field_a) + `check_rand(this, struct_array_1[i].field_b) + end + foreach (struct_array_2[i, j]) begin + `check_rand(this, struct_array_2[i][j].field_a) + `check_rand(this, struct_array_2[i][j].field_b) + end + endfunction + +endclass + +class unconstrained_associative_array_test; + + rand int associative_array_1d[string]; + rand int associative_array_3d[string][string][string]; + string key1, key2, key3; + + function new(); + associative_array_1d["key1"] = 1; + associative_array_1d["key2"] = 2; + + associative_array_3d["key1"]["subkey1"]["subsubkey1"] = 1; + associative_array_3d["key1"]["subkey1"]["subsubkey2"] = 2; + associative_array_3d["key1"]["subkey2"]["subsubkey1"] = 3; + associative_array_3d["key1"]["subkey3"]["subsubkey1"] = 4; + associative_array_3d["key1"]["subkey3"]["subsubkey2"] = 5; + associative_array_3d["key1"]["subkey3"]["subsubkey3"] = 6; + associative_array_3d["key2"]["subkey1"]["subsubkey1"] = 7; + associative_array_3d["key2"]["subkey1"]["subsubkey2"] = 8; + associative_array_3d["key2"]["subkey2"]["subsubkey1"] = 9; + associative_array_3d["key2"]["subkey3"]["subsubkey1"] = 10; + associative_array_3d["key2"]["subkey3"]["subsubkey2"] = 11; + endfunction + + function void check_randomization(); + `check_rand(this, associative_array_1d["key1"]); + `check_rand(this, associative_array_1d["key2"]); + + foreach(associative_array_3d[key1, key2, key3]) begin + `check_rand(this, associative_array_3d[key1][key2][key3]); + end + endfunction + +endclass + +class unconstrained_queue_test; + + rand int queue_array_1d[$]; + rand int queue_array_2d[$][$]; + + function new(); + queue_array_1d = {}; + for (int i = 0; i < 8; i++) begin + queue_array_1d.push_back('h0 + i); + end + queue_array_2d = {}; + queue_array_2d[0] = '{1, 2, 3}; + queue_array_2d[1] = '{4, 5, 6, 0, 10}; + queue_array_2d[2] = '{6, 7, 8, 9}; + endfunction + + function void check_randomization(); + foreach (queue_array_1d[i]) begin + `check_rand(this, queue_array_1d[i]); + end + foreach(queue_array_2d[i, j]) begin + `check_rand(this, queue_array_2d[i][j]); + end + endfunction + +endclass + +module t_randomize_array; + unconstrained_packed_array_test packed_class; + unconstrained_unpacked_array_test unpacked_class; + unconstrained_dynamic_array_test dynamic_class; + unconstrained_struct_with_array_test struct_with_array_class; + unconstrained_struct_array_test struct_array_class; + unconstrained_associative_array_test associative_array_class; + unconstrained_queue_test queue_class; + + initial begin + // Test 1: Packed Array Unconstrained Constrained Test + packed_class = new(); + repeat(2) begin + packed_class.check_randomization(); + end + + // Test 2: Unpacked Array Unconstrained Constrained Test + unpacked_class = new(); + repeat(2) begin + unpacked_class.check_randomization(); + end + + // Test 3: Dynamic Array Unconstrained Constrained Test + dynamic_class = new(); + repeat(2) begin + dynamic_class.check_randomization(); + end + + // Test 4: Struct Containing Array Test + struct_with_array_class = new(); + repeat(2) begin + struct_with_array_class.check_randomization(); + end + + struct_array_class = new(); + repeat(2) begin + struct_array_class.check_randomization(); + end + + // Test 5: Associative Array Unconstrained Test + associative_array_class = new(); + repeat(2) begin + associative_array_class.check_randomization(); + end + + // Test 6: Queue Unconstrained Test + queue_class = new(); + repeat(2) begin + queue_class.check_randomization(); + end + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_randomize_array_constraints.py b/test_regress/t/t_randomize_array_constraints.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_array_constraints.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_array_constraints.v b/test_regress/t/t_randomize_array_constraints.v new file mode 100755 index 000000000..f56cab447 --- /dev/null +++ b/test_regress/t/t_randomize_array_constraints.v @@ -0,0 +1,158 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by PlanV GmbH. +// SPDX-License-Identifier: CC0-1.0 + +`define check_rand(cl, field) \ +begin \ + longint prev_result; \ + int ok = 0; \ + void'(cl.randomize()); \ + prev_result = longint'(field); \ + repeat(9) begin \ + longint result; \ + void'(cl.randomize()); \ + result = longint'(field); \ + if (result != prev_result) ok = 1; \ + prev_result = result; \ + end \ + if (ok != 1) $stop; \ +end + +class con_rand_1d_array_test; + rand bit [7:0] data[5]; + + constraint c_data { + foreach (data[i]) { + data[i] inside {8'h10, 8'h20, 8'h30, 8'h40, 8'h50}; + } + } + + function new(); + data = '{default: 'h0}; + endfunction + + function void check_randomization(); + foreach (data[i]) begin + `check_rand(this, data[i]) + if (data[i] inside {8'h10, 8'h20, 8'h30, 8'h40, 8'h50}) begin + $display("data[%0d] = %h is valid", i, data[i]); + end else begin + $display("Error: data[%0d] = %h is out of bounds", i, data[i]); + $stop; + end + end + + endfunction + +endclass + + +class con_rand_2d_array_test; + rand bit [7:0] data[3][3]; + + constraint c_data { + foreach (data[i, j]) { + data[i][j] >= 8'h10; + data[i][j] <= 8'h50; + } + } + + function new(); + data = '{default: '{default: 'h0}}; + endfunction + + function void check_randomization(); + foreach (data[i, j]) begin + `check_rand(this, data[i][j]) + if (data[i][j] >= 8'h10 && data[i][j] <= 8'h50) begin + $display("data[%0d][%0d] = %h is valid", i, j, data[i][j]); + end else begin + $display("Error: data[%0d][%0d] = %h is out of bounds", i, j, data[i][j]); + $stop; + end + end + endfunction + +endclass + + +class con_rand_3d_array_test; + rand bit [7:0] data[2][2][2]; + + constraint c_data { + foreach (data[i, j, k]) { + data[i][j][k] >= 8'h10; + data[i][j][k] <= 8'h50; + if (i > 0) { + data[i][j][k] > data[i-1][j][k] + 8'h05; + } + if (j > 0) { + data[i][j][k] > data[i][j-1][k]; + } + } + } + + function new(); + data = '{default: '{default: '{default: 'h0}}}; + endfunction + + function void check_randomization(); + foreach (data[i, j, k]) begin + `check_rand(this, data[i][j][k]) + if (data[i][j][k] >= 8'h10 && data[i][j][k] <= 8'h50) begin + + if (i > 0 && data[i][j][k] <= data[i-1][j][k] + 8'h05) begin + $display("Error: data[%0d][%0d][%0d] = %h does not satisfy i > 0 constraint", i, j, k, data[i][j][k]); + $stop; + end + + if (j > 0 && data[i][j][k] <= data[i][j-1][k]) begin + $display("Error: data[%0d][%0d][%0d] = %h does not satisfy j > 0 constraint", i, j, k, data[i][j][k]); + $stop; + end + + $display("data[%0d][%0d][%0d] = %h is valid", i, j, k, data[i][j][k]); + + end else begin + $display("Error: data[%0d][%0d][%0d] = %h is out of bounds", i, j, k, data[i][j][k]); + $stop; + end + end + endfunction + +endclass + + +module t_randomize_array_constraints; + con_rand_1d_array_test rand_test_1; + con_rand_2d_array_test rand_test_2; + con_rand_3d_array_test rand_test_3; + + initial begin + // Test 1: Randomization for 1D array + $display("Test 1: Randomization for 1D array:"); + rand_test_1 = new(); + repeat(2) begin + rand_test_1.check_randomization(); + end + + // Test 2: Randomization for 2D array + $display("Test 2: Randomization for 2D array:"); + rand_test_2 = new(); + repeat(2) begin + rand_test_2.check_randomization(); + end + + // Test 3: Randomization for 3D array + $display("Test 3: Randomization for 3D array:"); + rand_test_3 = new(); + repeat(2) begin + rand_test_3.check_randomization(); + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_array_unsup.out b/test_regress/t/t_randomize_array_unsup.out new file mode 100644 index 000000000..e65a4c03c --- /dev/null +++ b/test_regress/t/t_randomize_array_unsup.out @@ -0,0 +1,8 @@ +%Error-UNSUPPORTED: t/t_randomize_array_unsup.v:28:8: Unsupported: CreateArrayForeachLoop currently does not support this data type. (Struct-Array unconstrained randomization is not fully supported) + 28 | rand simple_struct_t struct_array_2[]; + | ^~~~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_randomize_array_unsup.v:29:8: Unsupported: CreateArrayForeachLoop currently does not support this data type. (Struct-Array unconstrained randomization is not fully supported) + 29 | rand simple_struct_t struct_array_1[3]; + | ^~~~~~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_randomize_bbox.pl b/test_regress/t/t_randomize_bbox.pl deleted file mode 100755 index 2f89e3fb1..000000000 --- a/test_regress/t/t_randomize_bbox.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_randomize.v"); - -lint( - verilator_flags => ["--bbox-unsup"], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_bbox.py b/test_regress/t/t_randomize_bbox.py new file mode 100755 index 000000000..706273143 --- /dev/null +++ b/test_regress/t/t_randomize_bbox.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_randomize.v" + +test.lint(verilator_flags=["--bbox-unsup"], fails=True) + +test.passes() diff --git a/test_regress/t/t_randomize_extern.pl b/test_regress/t/t_randomize_extern.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_randomize_extern.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_extern.py b/test_regress/t/t_randomize_extern.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randomize_extern.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_inline_var_ctl.pl b/test_regress/t/t_randomize_inline_var_ctl.pl deleted file mode 100755 index 7b520d284..000000000 --- a/test_regress/t/t_randomize_inline_var_ctl.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_inline_var_ctl.py b/test_regress/t/t_randomize_inline_var_ctl.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_inline_var_ctl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_inline_var_ctl_bad.pl b/test_regress/t/t_randomize_inline_var_ctl_bad.pl deleted file mode 100755 index 14a6e3229..000000000 --- a/test_regress/t/t_randomize_inline_var_ctl_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_inline_var_ctl_bad.py b/test_regress/t/t_randomize_inline_var_ctl_bad.py new file mode 100755 index 000000000..6038b562c --- /dev/null +++ b/test_regress/t/t_randomize_inline_var_ctl_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.pl b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.pl deleted file mode 100755 index 14a6e3229..000000000 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.py b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.py new file mode 100755 index 000000000..6038b562c --- /dev/null +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.pl b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.pl deleted file mode 100755 index 14a6e3229..000000000 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.py b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.py new file mode 100755 index 000000000..6038b562c --- /dev/null +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method.pl b/test_regress/t/t_randomize_method.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_randomize_method.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method.py b/test_regress/t/t_randomize_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randomize_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_method.v b/test_regress/t/t_randomize_method.v index 9db38279b..1663f26ad 100644 --- a/test_regress/t/t_randomize_method.v +++ b/test_regress/t/t_randomize_method.v @@ -8,11 +8,13 @@ begin \ longint prev_result; \ int ok = 0; \ - for (int i = 0; i < 10; i++) begin \ + void'(cl.randomize()); \ + prev_result = longint'(field); \ + repeat(9) begin \ longint result; \ void'(cl.randomize()); \ result = longint'(field); \ - if (i > 0 && result != prev_result) ok = 1; \ + if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ diff --git a/test_regress/t/t_randomize_method_bad.pl b/test_regress/t/t_randomize_method_bad.pl deleted file mode 100755 index 66fa61649..000000000 --- a/test_regress/t/t_randomize_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_bad.py b/test_regress/t/t_randomize_method_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_randomize_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method_complex_bad.pl b/test_regress/t/t_randomize_method_complex_bad.pl deleted file mode 100755 index 66fa61649..000000000 --- a/test_regress/t/t_randomize_method_complex_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_complex_bad.py b/test_regress/t/t_randomize_method_complex_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_randomize_method_complex_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method_constraints.pl b/test_regress/t/t_randomize_method_constraints.pl deleted file mode 100755 index 8cec08c6a..000000000 --- a/test_regress/t/t_randomize_method_constraints.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_constraints.py b/test_regress/t/t_randomize_method_constraints.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_method_constraints.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_method_nclass_bad.pl b/test_regress/t/t_randomize_method_nclass_bad.pl deleted file mode 100755 index 66fa61649..000000000 --- a/test_regress/t/t_randomize_method_nclass_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_nclass_bad.py b/test_regress/t/t_randomize_method_nclass_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_randomize_method_nclass_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method_std.py b/test_regress/t/t_randomize_method_std.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randomize_method_std.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_method_std.v b/test_regress/t/t_randomize_method_std.v new file mode 100644 index 000000000..2e1d991cb --- /dev/null +++ b/test_regress/t/t_randomize_method_std.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +process p; // force importing std into top-level namespace + +class C; + function new; + if (randomize() != 1) $stop; + endfunction +endclass + +module t (/*AUTOARG*/); + initial begin + C c = new; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_method_types_unsup.out b/test_regress/t/t_randomize_method_types_unsup.out index cddf650b2..2526171bc 100644 --- a/test_regress/t/t_randomize_method_types_unsup.out +++ b/test_regress/t/t_randomize_method_types_unsup.out @@ -1,21 +1,10 @@ -%Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:19:25: Unsupported: random member variable with type 'int$[]' - 19 | constraint dynsize { dynarr.size < 20; } - | ^~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:12:13: Unsupported: random member variable with type 'int$[string]' +%Warning-CONSTRAINTIGN: t/t_randomize_method_types_unsup.v:13:32: Unsupported: randomizing this expression, treating as state + 13 | constraint dynsize { dynarr.size < 20; } + | ^~~~ + ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest + ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. +%Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:10:13: Unsupported: random member variable with the type of the containing class : ... note: In instance 't' - 12 | rand int assocarr[string]; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:14:13: Unsupported: random member variable with type 'int$[0:4]' - : ... note: In instance 't' - 14 | rand int unpackarr[5]; - | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:15:15: Unsupported: random member variable with type 'union{}$unit::Union' - : ... note: In instance 't' - 15 | rand Union uni; - | ^~~ -%Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:16:13: Unsupported: random member variable with the type of the containing class - : ... note: In instance 't' - 16 | rand Cls cls; + 10 | rand Cls cls; | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_randomize_method_types_unsup.pl b/test_regress/t/t_randomize_method_types_unsup.pl deleted file mode 100755 index 6ad7137de..000000000 --- a/test_regress/t/t_randomize_method_types_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_types_unsup.py b/test_regress/t/t_randomize_method_types_unsup.py new file mode 100755 index 000000000..710a094ab --- /dev/null +++ b/test_regress/t/t_randomize_method_types_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method_types_unsup.v b/test_regress/t/t_randomize_method_types_unsup.v index adc1a7bd0..8fbb96f52 100644 --- a/test_regress/t/t_randomize_method_types_unsup.v +++ b/test_regress/t/t_randomize_method_types_unsup.v @@ -4,15 +4,9 @@ // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -typedef union packed { - int x; -} Union; - class Cls; rand int assocarr[string]; rand int dynarr[]; - rand int unpackarr[5]; - rand Union uni; rand Cls cls; rand int i; int st; diff --git a/test_regress/t/t_randomize_method_with.pl b/test_regress/t/t_randomize_method_with.pl deleted file mode 100755 index 3037a8f30..000000000 --- a/test_regress/t/t_randomize_method_with.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - # Ensure we test captures of static variables - verilator_flags2 => ["--fno-inline"], - ); - - execute( - check_finished => 1, - ); -} - -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*Baz*.cpp")) { - # Check that "Baz" has no constrained random generator - file_grep_not($file, "this->__PVT__constraint"); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_with.py b/test_regress/t/t_randomize_method_with.py new file mode 100755 index 000000000..0652adf1b --- /dev/null +++ b/test_regress/t/t_randomize_method_with.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile( + # Ensure we test captures of static variables + verilator_flags2=["--fno-inline"]) + +test.execute() + +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*Baz*.cpp"): + # Check that "Baz" has no constrained random generator + test.file_grep_not(filename, "this->__PVT__constraint") + +test.passes() diff --git a/test_regress/t/t_randomize_method_with.v b/test_regress/t/t_randomize_method_with.v index 616864d7b..d6436baf2 100644 --- a/test_regress/t/t_randomize_method_with.v +++ b/test_regress/t/t_randomize_method_with.v @@ -8,11 +8,13 @@ begin \ longint prev_result; \ int ok = 0; \ - for (int i = 0; i < 10; i++) begin \ + void'(cl.randomize()); \ + prev_result = longint'(field); \ + repeat(9) begin \ longint result; \ void'(cl.randomize()); \ result = longint'(field); \ - if (i > 0 && result != prev_result) ok = 1; \ + if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ @@ -134,6 +136,13 @@ module mwith(); if (cls.b != 1) $stop; `check_rand(cls2, cls2.a); `check_rand(cls2, cls2.c); + + // Check randomize as a task + // verilator lint_off IGNOREDRETURN + cls.randomize() with { b == 2;}; + // verilator lint_on IGNOREDRETURN + if (cls.b != 2) $stop; + // Check capture of a static variable if (foo.randomize() with { a > sub1.sub_var; } != 1) $stop; // Check reference to a function diff --git a/test_regress/t/t_randomize_method_with_bad.pl b/test_regress/t/t_randomize_method_with_bad.pl deleted file mode 100755 index f48f2cb92..000000000 --- a/test_regress/t/t_randomize_method_with_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_with_bad.py b/test_regress/t/t_randomize_method_with_bad.py new file mode 100755 index 000000000..24e87157b --- /dev/null +++ b/test_regress/t/t_randomize_method_with_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method_with_scoping.pl b/test_regress/t/t_randomize_method_with_scoping.pl deleted file mode 100755 index c4618c2fd..000000000 --- a/test_regress/t/t_randomize_method_with_scoping.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_with_scoping.py b/test_regress/t/t_randomize_method_with_scoping.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_method_with_scoping.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_method_with_scoping.v b/test_regress/t/t_randomize_method_with_scoping.v index b5c8a5657..35c156abb 100644 --- a/test_regress/t/t_randomize_method_with_scoping.v +++ b/test_regress/t/t_randomize_method_with_scoping.v @@ -5,14 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 class c1; - rand int c1_f; + rand int c1_f; endclass class c2; - rand int c2_f; + rand int c2_f; endclass - +localparam int PARAM = 42; class Cls; rand int x; + int q[$] = {0}; rand enum { ONE_Y, TWO_Y @@ -80,6 +81,10 @@ class SubC extends SubB; if (doit != 1) $stop; if (f.en != SubA::AMBIG) $stop; + doit &= f.randomize() with { x == PARAM; }; + if (doit != 1) $stop; + if (f.x != PARAM) $stop; + f.en = SubA::ONE_A; doit &= f.randomize() with { en == ONE_A; }; doit &= f.randomize() with { local::en == local::AMBIG; }; @@ -94,6 +99,8 @@ class SubC extends SubB; if (f.x != 0) $stop; doit &= f.randomize() with { x == op(local::op(op(local::op(1)))); }; if (f.x != 1) $stop; + doit &= f.randomize() with { foreach (q[i]) x == i; }; + if (f.x != 0) $stop; endfunction endclass diff --git a/test_regress/t/t_randomize_prepost.pl b/test_regress/t/t_randomize_prepost.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_randomize_prepost.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_prepost.py b/test_regress/t/t_randomize_prepost.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_prepost.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_prepost.v b/test_regress/t/t_randomize_prepost.v index 734bb3c31..07b749c43 100644 --- a/test_regress/t/t_randomize_prepost.v +++ b/test_regress/t/t_randomize_prepost.v @@ -41,6 +41,14 @@ module t (/*AUTOARG*/); if (c.pre != 10) $stop; if (c.r != RANDOMIZED) $stop; if (c.post != 30) $stop; + + c = new; + rand_result = c.randomize() with { r == RANDOMIZED; }; + if (rand_result != 1) $stop; + if (c.pre != 10) $stop; + if (c.r != RANDOMIZED) $stop; + if (c.post != 30) $stop; + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_randomize_queue_constraints.py b/test_regress/t/t_randomize_queue_constraints.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_queue_constraints.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_queue_constraints.v b/test_regress/t/t_randomize_queue_constraints.v new file mode 100644 index 000000000..b88bace7b --- /dev/null +++ b/test_regress/t/t_randomize_queue_constraints.v @@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +`define check_rand(cl, field, cond) \ +begin \ + longint prev_result; \ + int ok = 0; \ + if (!bit'(cl.randomize())) $stop; \ + prev_result = longint'(field); \ + if (!(cond)) $stop; \ + repeat(9) begin \ + longint result; \ + if (!bit'(cl.randomize())) $stop; \ + result = longint'(field); \ + if (!(cond)) $stop; \ + if (result != prev_result) ok = 1; \ + prev_result = result; \ + end \ + if (ok != 1) $stop; \ +end + +class Foo; + rand int m_intQueue[$]; + rand int m_idx; + + function new; + m_intQueue = '{10{0}}; + endfunction + + constraint int_queue_c { + m_idx inside {[0:9]}; + m_intQueue[m_idx] == m_idx + 1; + foreach (m_intQueue[i]) { + m_intQueue[i] inside {[0:127]}; + } + } +endclass + +module t_randomize_queue_constraints; + initial begin + Foo foo = new; + + `check_rand(foo, foo.m_idx, foo.m_idx inside {[0:9]} && foo.m_intQueue[foo.m_idx] == foo.m_idx + 1); + $display("Queue: %p", foo.m_intQueue); + `check_rand(foo, foo.m_intQueue[3], foo.m_intQueue[5] inside {[0:127]}); + $display("Queue: %p", foo.m_intQueue); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_rand_mode.pl b/test_regress/t/t_randomize_rand_mode.pl deleted file mode 100755 index e45199a00..000000000 --- a/test_regress/t/t_randomize_rand_mode.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - - -ok(1); -1; diff --git a/test_regress/t/t_randomize_rand_mode.py b/test_regress/t/t_randomize_rand_mode.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_rand_mode_bad.pl b/test_regress/t/t_randomize_rand_mode_bad.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_randomize_rand_mode_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_rand_mode_bad.py b/test_regress/t/t_randomize_rand_mode_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_rand_mode_constr.pl b/test_regress/t/t_randomize_rand_mode_constr.pl deleted file mode 100755 index 7b520d284..000000000 --- a/test_regress/t/t_randomize_rand_mode_constr.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_rand_mode_constr.py b/test_regress/t/t_randomize_rand_mode_constr.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode_constr.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_rand_mode_unsup.pl b/test_regress/t/t_randomize_rand_mode_unsup.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_randomize_rand_mode_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_rand_mode_unsup.py b/test_regress/t/t_randomize_rand_mode_unsup.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_srandom.pl b/test_regress/t/t_randomize_srandom.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_randomize_srandom.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_srandom.py b/test_regress/t/t_randomize_srandom.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randomize_srandom.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_this.pl b/test_regress/t/t_randomize_this.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_randomize_this.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_this.py b/test_regress/t/t_randomize_this.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randomize_this.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_union.py b/test_regress/t/t_randomize_union.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_union.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_union.v b/test_regress/t/t_randomize_union.v new file mode 100755 index 000000000..900e606b4 --- /dev/null +++ b/test_regress/t/t_randomize_union.v @@ -0,0 +1,168 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by PlanV GmbH. +// SPDX-License-Identifier: CC0-1.0 + +typedef union packed { + int int_value; + bit [31:0] bits; +} SimpleUnion; + +typedef struct packed { + rand bit [3:0] field_a; + rand bit [7:0] field_b; +} PackedStruct; + +typedef union packed { + PackedStruct struct_fields; + bit [11:0] inner_bits; +} StructInUnion; + +typedef union packed { + StructInUnion inner_union; + bit [11:0] outer_bits; +} UnionInUnion; + +// SimpleUnion Constrained Test Class +class SimpleUnionConstrainedTest; + rand SimpleUnion union_instance; + + function new(); + union_instance.bits = 32'b0; + endfunction + + constraint union_constraint { + union_instance.bits[11:0] inside {[0:4095]}; + } +endclass + +// SimpleUnion Unconstrained Test Class +class SimpleUnionUnconstrainedTest; + rand SimpleUnion union_instance; + + function new(); + union_instance.bits = 32'b0; + endfunction +endclass + +// StructInUnion Constrained Test Class +class StructInUnionConstrainedTest; + rand StructInUnion union_instance; + + function new(); + union_instance.inner_bits = 12'b0; + endfunction + + constraint union_constraint { + union_instance.inner_bits inside {[0:4095]}; + } +endclass + +// StructInUnion Unconstrained Test Class +class StructInUnionUnconstrainedTest; + rand StructInUnion union_instance; + + function new(); + union_instance.inner_bits = 12'b0; + endfunction +endclass + +// UnionInUnion Constrained Test Class +class UnionInUnionConstrainedTest; + rand UnionInUnion union_instance; + + function new(); + union_instance.outer_bits = 12'b0; + endfunction + + constraint union_constraint { + union_instance.outer_bits inside {[0:4095]}; + } +endclass + +// UnionInUnion Unconstrained Test Class +class UnionInUnionUnconstrainedTest; + rand UnionInUnion union_instance; + + function new(); + union_instance.outer_bits = 12'b0; + endfunction +endclass + +// Top-Level Test Module +module t_randomize_union; + + // Instances of each test class + SimpleUnionConstrainedTest test_simple_union_constrained; + SimpleUnionUnconstrainedTest test_simple_union_unconstrained; + StructInUnionConstrainedTest test_struct_in_union_constrained; + StructInUnionUnconstrainedTest test_struct_in_union_unconstrained; + UnionInUnionConstrainedTest test_union_in_union_constrained; + UnionInUnionUnconstrainedTest test_union_in_union_unconstrained; + + initial begin + // Test 1: SimpleUnion Constrained Test + test_simple_union_constrained = new(); + $display("\n--- Test 1: SimpleUnion Constrained Test ---"); + repeat(10) begin + int success; + success = test_simple_union_constrained.randomize(); + if (success != 1) $stop; + $display("SimpleUnion (Constrained): int_value: %b, bits: %b", test_simple_union_constrained.union_instance.int_value, test_simple_union_constrained.union_instance.bits); + end + + // Test 2: SimpleUnion Unconstrained Test + test_simple_union_unconstrained = new(); + $display("\n--- Test 2: SimpleUnion Unconstrained Test ---"); + repeat(10) begin + int success; + success = test_simple_union_unconstrained.randomize(); + if (success != 1) $stop; + $display("SimpleUnion (Unconstrained): int_value: %b, bits: %b", test_simple_union_unconstrained.union_instance.int_value, test_simple_union_unconstrained.union_instance.bits); + end + + // Test 3: StructInUnion Constrained Test + test_struct_in_union_constrained = new(); + $display("\n--- Test 3: StructInUnion Constrained Test ---"); + repeat(10) begin + int success; + success = test_struct_in_union_constrained.randomize(); + if (success != 1) $stop; + $display("StructInUnion (Constrained): struct.a: %b, struct.b: %b, inner_bits: %b", test_struct_in_union_constrained.union_instance.struct_fields.field_a, test_struct_in_union_constrained.union_instance.struct_fields.field_b, test_struct_in_union_constrained.union_instance.inner_bits); + end + + // Test 4: StructInUnion Unconstrained Test + test_struct_in_union_unconstrained = new(); + $display("\n--- Test 4: StructInUnion Unconstrained Test ---"); + repeat(10) begin + int success; + success = test_struct_in_union_unconstrained.randomize(); + if (success != 1) $stop; + $display("StructInUnion (Unconstrained): struct.a: %b, struct.b: %b, inner_bits: %b", test_struct_in_union_unconstrained.union_instance.struct_fields.field_a, test_struct_in_union_unconstrained.union_instance.struct_fields.field_b, test_struct_in_union_unconstrained.union_instance.inner_bits); + end + + // Test 5: UnionInUnion Constrained Test + test_union_in_union_constrained = new(); + $display("\n--- Test 5: UnionInUnion Constrained Test ---"); + repeat(10) begin + int success; + success = test_union_in_union_constrained.randomize(); + if (success != 1) $stop; + $display("UnionInUnion (Constrained): outer_bits: %b, inner_union.struct: %b, b: %b", test_union_in_union_constrained.union_instance.outer_bits, test_union_in_union_constrained.union_instance.inner_union.struct_fields.field_a, test_union_in_union_constrained.union_instance.inner_union.struct_fields.field_b); + end + + // Test 6: UnionInUnion Unconstrained Test + test_union_in_union_unconstrained = new(); + $display("\n--- Test 6: UnionInUnion Unconstrained Test ---"); + repeat(10) begin + int success; + success = test_union_in_union_unconstrained.randomize(); + if (success != 1) $stop; + $display("UnionInUnion (Unconstrained): outer_bits: %b, inner_union.struct: %b, inner_union.inner_bits: %b", test_union_in_union_unconstrained.union_instance.outer_bits, test_union_in_union_unconstrained.union_instance.inner_union.struct_fields, test_union_in_union_unconstrained.union_instance.inner_union.inner_bits); + end + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_randomize_union_bad.out b/test_regress/t/t_randomize_union_bad.out new file mode 100644 index 000000000..61cde78f2 --- /dev/null +++ b/test_regress/t/t_randomize_union_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_randomize_union_bad.v:7:9: Unpacked unions shall not be declared as rand or randc. (IEEE 1800-2023 18.4) + 7 | typedef union { + | ^~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_randomize_union_bad.py b/test_regress/t/t_randomize_union_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_randomize_union_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_union_bad.v b/test_regress/t/t_randomize_union_bad.v new file mode 100644 index 000000000..4fb462b74 --- /dev/null +++ b/test_regress/t/t_randomize_union_bad.v @@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by PlanV GmbH. +// SPDX-License-Identifier: CC0-1.0 + +typedef union { + int int_value; + bit [31:0] bits; +} UnpackedUnion; + +class UnpackedUnionErrorTest; + rand UnpackedUnion union_instance; + + function new(); + union_instance.bits = 32'b0; + endfunction + +endclass + +module t_randomize_union_bad; + + UnpackedUnionErrorTest test_unpacked_union; + + initial begin + test_unpacked_union = new(); + repeat(10) begin + int success; + success = test_unpacked_union.randomize(); + if (success != 1) $stop; + $display("UnpackedUnion: int_value: %b, bits: %b", test_unpacked_union.union_instance.int_value, test_unpacked_union.union_instance.bits); + end + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randsequence.pl b/test_regress/t/t_randsequence.pl deleted file mode 100755 index b003e3144..000000000 --- a/test_regress/t/t_randsequence.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_randsequence.py b/test_regress/t/t_randsequence.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_randsequence.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_randsequence_bad.pl b/test_regress/t/t_randsequence_bad.pl deleted file mode 100755 index a083f46f5..000000000 --- a/test_regress/t/t_randsequence_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randsequence_bad.py b/test_regress/t/t_randsequence_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randsequence_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randstate_func.pl b/test_regress/t/t_randstate_func.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_randstate_func.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randstate_func.py b/test_regress/t/t_randstate_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randstate_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randstate_obj.pl b/test_regress/t/t_randstate_obj.pl deleted file mode 100755 index b50a85167..000000000 --- a/test_regress/t/t_randstate_obj.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - expect_filename => $Self->{golden_filename}, - fails => $Self->{vlt_all}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randstate_obj.py b/test_regress/t/t_randstate_obj.py new file mode 100755 index 000000000..710a094ab --- /dev/null +++ b/test_regress/t/t_randstate_obj.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randstate_seed_bad.pl b/test_regress/t/t_randstate_seed_bad.pl deleted file mode 100755 index c7c7ef8ca..000000000 --- a/test_regress/t/t_randstate_seed_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randstate_seed_bad.py b/test_regress/t/t_randstate_seed_bad.py new file mode 100755 index 000000000..97abb660e --- /dev/null +++ b/test_regress/t/t_randstate_seed_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_real_param.pl b/test_regress/t/t_real_param.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_real_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_real_param.py b/test_regress/t/t_real_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_real_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_recursive_method.pl b/test_regress/t/t_recursive_method.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_recursive_method.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_recursive_method.py b/test_regress/t/t_recursive_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_recursive_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_recursive_module_bug.pl b/test_regress/t/t_recursive_module_bug.pl deleted file mode 100755 index 2ef6db6a2..000000000 --- a/test_regress/t/t_recursive_module_bug.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_recursive_module_bug.py b/test_regress/t/t_recursive_module_bug.py new file mode 100755 index 000000000..16de8f485 --- /dev/null +++ b/test_regress/t/t_recursive_module_bug.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_recursive_module_bug_2.pl b/test_regress/t/t_recursive_module_bug_2.pl deleted file mode 100755 index 2ef6db6a2..000000000 --- a/test_regress/t/t_recursive_module_bug_2.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_recursive_module_bug_2.py b/test_regress/t/t_recursive_module_bug_2.py new file mode 100755 index 000000000..16de8f485 --- /dev/null +++ b/test_regress/t/t_recursive_module_bug_2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_reloop_cam.pl b/test_regress/t/t_reloop_cam.pl deleted file mode 100755 index 7046308bc..000000000 --- a/test_regress/t/t_reloop_cam.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-unroll-count 1024", - "--expand-limit 1024", - $Self->wno_unopthreads_for_few_cores(), - "--stats"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Reloop iterations\s+(\d+)/i, - 768); - file_grep($Self->{stats}, qr/Optimizations, Reloops\s+(\d+)/i, - 3); -} - -ok(1); -1; diff --git a/test_regress/t/t_reloop_cam.py b/test_regress/t/t_reloop_cam.py new file mode 100755 index 000000000..44a025926 --- /dev/null +++ b/test_regress/t/t_reloop_cam.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=[ + "-unroll-count 1024", "--expand-limit 1024", test.wno_unopthreads_for_few_cores, "--stats" +]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Reloop iterations\s+(\d+)', 768) + test.file_grep(test.stats, r'Optimizations, Reloops\s+(\d+)', 3) + +test.passes() diff --git a/test_regress/t/t_reloop_local.pl b/test_regress/t/t_reloop_local.pl deleted file mode 100755 index 8f8f11798..000000000 --- a/test_regress/t/t_reloop_local.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_reloop_local.py b/test_regress/t/t_reloop_local.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_reloop_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_reloop_offset.pl b/test_regress/t/t_reloop_offset.pl deleted file mode 100755 index 02f1f01fc..000000000 --- a/test_regress/t/t_reloop_offset.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-unroll-count 1024", - $Self->wno_unopthreads_for_few_cores(), - "--stats"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -if ($Self->{vlt}) { - # Note, with vltmt this might be split differently, so only checking vlt - file_grep($Self->{stats}, qr/Optimizations, Reloop iterations\s+(\d+)/i, - 125); - file_grep($Self->{stats}, qr/Optimizations, Reloops\s+(\d+)/i, - 2); -} - -ok(1); -1; diff --git a/test_regress/t/t_reloop_offset.py b/test_regress/t/t_reloop_offset.py new file mode 100755 index 000000000..a391e447b --- /dev/null +++ b/test_regress/t/t_reloop_offset.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + verilator_flags2=["-unroll-count 1024", test.wno_unopthreads_for_few_cores, "--stats"]) + +test.execute(expect_filename=test.golden_filename) + +if test.vlt: + # Note, with vltmt this might be split differently, so only checking vlt + test.file_grep(test.stats, r'Optimizations, Reloop iterations\s+(\d+)', 125) + test.file_grep(test.stats, r'Optimizations, Reloops\s+(\d+)', 2) + +test.passes() diff --git a/test_regress/t/t_reloop_offset_lim_63.pl b/test_regress/t/t_reloop_offset_lim_63.pl deleted file mode 100755 index 06d25c7b3..000000000 --- a/test_regress/t/t_reloop_offset_lim_63.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_reloop_offset.v"); -golden_filename("t/t_reloop_offset.out"); - -compile( - verilator_flags2 => ["-unroll-count 1024", - $Self->wno_unopthreads_for_few_cores(), - "--reloop-limit 63", - "--stats"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -if ($Self->{vlt}) { - # Note, with vltmt this might be split differently, so only checking vlt - file_grep($Self->{stats}, qr/Optimizations, Reloop iterations\s+(\d+)/i, - 63); - file_grep($Self->{stats}, qr/Optimizations, Reloops\s+(\d+)/i, - 1); -} - -ok(1); -1; diff --git a/test_regress/t/t_reloop_offset_lim_63.py b/test_regress/t/t_reloop_offset_lim_63.py new file mode 100755 index 000000000..9e9bd8b5f --- /dev/null +++ b/test_regress/t/t_reloop_offset_lim_63.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_reloop_offset.v" +test.golden_filename = "t/t_reloop_offset.out" + +test.compile(verilator_flags2=[ + "-unroll-count 1024", test.wno_unopthreads_for_few_cores, "--reloop-limit 63", "--stats" +]) + +test.execute(expect_filename=test.golden_filename) + +if test.vlt: + # Note, with vltmt this might be split differently, so only checking vlt + test.file_grep(test.stats, r'Optimizations, Reloop iterations\s+(\d+)', 63) + test.file_grep(test.stats, r'Optimizations, Reloops\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_repeat.pl b/test_regress/t/t_repeat.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_repeat.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_repeat.py b/test_regress/t/t_repeat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_repeat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_rnd.pl b/test_regress/t/t_rnd.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_rnd.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_rnd.py b/test_regress/t/t_rnd.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_rnd.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_runflag.pl b/test_regress/t/t_runflag.pl deleted file mode 100755 index f15ca2e20..000000000 --- a/test_regress/t/t_runflag.pl +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - all_run_flags => ["+verilator+debug +verilator+debugi+9 +verilator+rand+reset+1"], - check_finished => 1, - expect => (q{.*Verilated::debug is on.*}), - ); - -execute( - all_run_flags => ["+verilator+help"], - fails => 1, - expect => ( -q{.*For help, please see 'verilator --help' -.*}), - ); - -execute( - all_run_flags => ["+verilator+V"], - fails => 1, - expect => ( -q{.*Version:}), - ); - -execute( - all_run_flags => ["+verilator+version"], - fails => 1, - expect => ( -q{.*Version:}), - ); - -ok(1); - -1; diff --git a/test_regress/t/t_runflag.py b/test_regress/t/t_runflag.py new file mode 100755 index 000000000..3504e8aca --- /dev/null +++ b/test_regress/t/t_runflag.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute(all_run_flags=["+verilator+debug +verilator+debugi+9 +verilator+rand+reset+1"], + logfile=test.obj_dir + "/vlt_1.log") +test.file_grep(test.obj_dir + "/vlt_1.log", r'Verilated::debug is on') + +test.execute(all_run_flags=["+verilator+help"], fails=True, logfile=test.obj_dir + "/vlt_2.log") +test.file_grep(test.obj_dir + "/vlt_2.log", r"For help, please see 'verilator --help'") + +test.execute(all_run_flags=["+verilator+V"], fails=True, logfile=test.obj_dir + "/vlt_3.log") +test.file_grep(test.obj_dir + "/vlt_3.log", r'Version:') + +test.execute(all_run_flags=["+verilator+version"], fails=True, logfile=test.obj_dir + "/vlt_4.log") +test.file_grep(test.obj_dir + "/vlt_4.log", r'Version:') + +test.passes() diff --git a/test_regress/t/t_runflag_bad.pl b/test_regress/t/t_runflag_bad.pl deleted file mode 100755 index d96c0ccbf..000000000 --- a/test_regress/t/t_runflag_bad.pl +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - all_run_flags => ["+verilator+bad+flag+testing"], - fails => 1, - expect_filename => "t/" . $Self->{name} . "_a.out", - ); - -execute( - all_run_flags => ["+verilator+rand+reset+-1"], - fails => 1, - expect_filename => "t/" . $Self->{name} . "_b.out", - ); - -execute( - all_run_flags => ["+verilator+rand+reset+3"], - fails => 1, - expect_filename => "t/" . $Self->{name} . "_c.out", - ); - -execute( - all_run_flags => ["+verilator+prof+exec+window+0"], - fails => 1, - expect_filename => "t/" . $Self->{name} . "_d.out", - ); - -execute( - all_run_flags => ["+verilator+prof+exec+window+1000000000000000000000000"], - fails => 1, - expect_filename => "t/" . $Self->{name} . "_e.out", - ); - -ok(1); - -1; diff --git a/test_regress/t/t_runflag_bad.py b/test_regress/t/t_runflag_bad.py new file mode 100755 index 000000000..fc3933b43 --- /dev/null +++ b/test_regress/t/t_runflag_bad.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute(all_run_flags=["+verilator+bad+flag+testing"], + fails=True, + expect_filename="t/" + test.name + "_a.out") + +test.execute(all_run_flags=["+verilator+rand+reset+-1"], + fails=True, + expect_filename="t/" + test.name + "_b.out") + +test.execute(all_run_flags=["+verilator+rand+reset+3"], + fails=True, + expect_filename="t/" + test.name + "_c.out") + +test.execute(all_run_flags=["+verilator+prof+exec+window+0"], + fails=True, + expect_filename="t/" + test.name + "_d.out") + +test.execute(all_run_flags=["+verilator+prof+exec+window+1000000000000000000000000"], + fails=True, + expect_filename="t/" + test.name + "_e.out") + +test.passes() diff --git a/test_regress/t/t_runflag_errorlimit_bad.pl b/test_regress/t/t_runflag_errorlimit_bad.pl deleted file mode 100755 index 6651f9189..000000000 --- a/test_regress/t/t_runflag_errorlimit_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - all_run_flags => ["+verilator+error+limit+3"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_runflag_errorlimit_bad.py b/test_regress/t/t_runflag_errorlimit_bad.py new file mode 100755 index 000000000..2370a882b --- /dev/null +++ b/test_regress/t/t_runflag_errorlimit_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute(all_run_flags=["+verilator+error+limit+3"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_runflag_errorlimit_fatal_bad.out b/test_regress/t/t_runflag_errorlimit_fatal_bad.out new file mode 100644 index 000000000..e99870e4d --- /dev/null +++ b/test_regress/t/t_runflag_errorlimit_fatal_bad.out @@ -0,0 +1,5 @@ +[0] %Error: t_runflag_errorlimit_fatal_bad.v:9: Assertion failed in top.t: One +-Info: t/t_runflag_errorlimit_fatal_bad.v:9: Verilog $stop, ignored due to +verilator+error+limit +[0] %Fatal: t_runflag_errorlimit_fatal_bad.v:10: Assertion failed in top.t +%Error: t/t_runflag_errorlimit_fatal_bad.v:10: Verilog $stop +Aborting... diff --git a/test_regress/t/t_runflag_errorlimit_fatal_bad.py b/test_regress/t/t_runflag_errorlimit_fatal_bad.py new file mode 100755 index 000000000..2370a882b --- /dev/null +++ b/test_regress/t/t_runflag_errorlimit_fatal_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute(all_run_flags=["+verilator+error+limit+3"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_runflag_errorlimit_fatal_bad.v b/test_regress/t/t_runflag_errorlimit_fatal_bad.v new file mode 100644 index 000000000..e4c546f64 --- /dev/null +++ b/test_regress/t/t_runflag_errorlimit_fatal_bad.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + $error("One"); + $fatal; + $error("Two"); + $error("Three"); + $error("Four"); + $error("Five"); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_runflag_quiet.pl b/test_regress/t/t_runflag_quiet.pl deleted file mode 100755 index bfaab429e..000000000 --- a/test_regress/t/t_runflag_quiet.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--binary --quiet"], - ); - -execute( - all_run_flags => ["+verilator+quiet"], - logfile => "$Self->{obj_dir}/sim__quiet.log", - ); - -file_grep_not("$Self->{obj_dir}/sim__quiet.log", qr/S i m u l a t/i,); - -#--- - -execute( - all_run_flags => [""], - logfile => "$Self->{obj_dir}/sim__noquiet.log", - ); - -file_grep("$Self->{obj_dir}/sim__noquiet.log", qr/S i m u l a t/i,); - -ok(1); - -1; diff --git a/test_regress/t/t_runflag_quiet.py b/test_regress/t/t_runflag_quiet.py new file mode 100755 index 000000000..34c826b21 --- /dev/null +++ b/test_regress/t/t_runflag_quiet.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--binary --quiet"]) + +test.execute(all_run_flags=["+verilator+quiet"], logfile=test.obj_dir + "/sim__quiet.log") + +test.file_grep_not(test.obj_dir + "/sim__quiet.log", r'S i m u l a t') + +#--- + +test.execute(all_run_flags=[""], logfile=test.obj_dir + "/sim__noquiet.log") + +test.file_grep(test.obj_dir + "/sim__noquiet.log", r'S i m u l a t') + +test.passes() diff --git a/test_regress/t/t_runflag_seed.pl b/test_regress/t/t_runflag_seed.pl deleted file mode 100755 index 71a259e41..000000000 --- a/test_regress/t/t_runflag_seed.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - all_run_flags => ["+verilator+seed+5 +SEED=fffffff4"], - ); - -execute( - all_run_flags => ["+verilator+seed+6 +SEED=fffffff2"], - ); - -ok(1); - -1; diff --git a/test_regress/t/t_runflag_seed.py b/test_regress/t/t_runflag_seed.py new file mode 100755 index 000000000..836f602cd --- /dev/null +++ b/test_regress/t/t_runflag_seed.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute(all_run_flags=["+verilator+seed+5 +SEED=fffffff4"]) + +test.execute(all_run_flags=["+verilator+seed+6 +SEED=fffffff2"]) + +test.passes() diff --git a/test_regress/t/t_runflag_uninit_bad.pl b/test_regress/t/t_runflag_uninit_bad.pl deleted file mode 100755 index dada1b80d..000000000 --- a/test_regress/t/t_runflag_uninit_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--savable --exe $Self->{t_dir}/t_runflag_uninit_bad.cpp"], - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_runflag_uninit_bad.py b/test_regress/t/t_runflag_uninit_bad.py new file mode 100755 index 000000000..54b3952a5 --- /dev/null +++ b/test_regress/t/t_runflag_uninit_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--savable --exe", test.pli_filename], make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sampled_expr.pl b/test_regress/t/t_sampled_expr.pl deleted file mode 100755 index a86f4c404..000000000 --- a/test_regress/t/t_sampled_expr.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sampled_expr.py b/test_regress/t/t_sampled_expr.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_sampled_expr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sampled_expr_unsup.pl b/test_regress/t/t_sampled_expr_unsup.pl deleted file mode 100755 index 244d49cbd..000000000 --- a/test_regress/t/t_sampled_expr_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename=>$Self->{golden_filename}, - verilator_flags2=> ['--assert -Wno-UNSIGNED'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sampled_expr_unsup.py b/test_regress/t/t_sampled_expr_unsup.py new file mode 100755 index 000000000..09fb4cfa3 --- /dev/null +++ b/test_regress/t/t_sampled_expr_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, + verilator_flags2=['--assert -Wno-UNSIGNED'], + fails=True) + +test.passes() diff --git a/test_regress/t/t_savable.pl b/test_regress/t/t_savable.pl deleted file mode 100755 index 87137cbe3..000000000 --- a/test_regress/t/t_savable.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - ); - -execute( - check_finished => 0, - all_run_flags => ['+save_time=500'], - ); - --r "$Self->{obj_dir}/saved.vltsv" or error("Saved.vltsv not created\n"); - -execute( - all_run_flags => ['+save_restore=1'], - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable.py b/test_regress/t/t_savable.py new file mode 100755 index 000000000..289d8f855 --- /dev/null +++ b/test_regress/t/t_savable.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--savable"], save_time=500) + +test.execute(check_finished=False, all_run_flags=['+save_time=500']) + +if not os.path.exists(test.obj_dir + "/saved.vltsv"): + test.error("Saved.vltsv not created") + +test.execute(all_run_flags=['+save_restore=1']) + +test.passes() diff --git a/test_regress/t/t_savable_class_bad.pl b/test_regress/t/t_savable_class_bad.pl deleted file mode 100755 index 3911aee04..000000000 --- a/test_regress/t/t_savable_class_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_class_bad.py b/test_regress/t/t_savable_class_bad.py new file mode 100755 index 000000000..9ac0fdbc6 --- /dev/null +++ b/test_regress/t/t_savable_class_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--savable"], + save_time=500, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_coverage_bad.pl b/test_regress/t/t_savable_coverage_bad.pl deleted file mode 100755 index cb1123397..000000000 --- a/test_regress/t/t_savable_coverage_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--savable --coverage"], - save_time => 500, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_coverage_bad.py b/test_regress/t/t_savable_coverage_bad.py new file mode 100755 index 000000000..15eec4d60 --- /dev/null +++ b/test_regress/t/t_savable_coverage_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--savable --coverage"], + save_time=500, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_format1_bad.pl b/test_regress/t/t_savable_format1_bad.pl deleted file mode 100755 index 0731b7fe1..000000000 --- a/test_regress/t/t_savable_format1_bad.pl +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_savable.v"); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - ); - -execute( - check_finished => 0, - all_run_flags => ['+save_time=500'], - ); - --r "$Self->{obj_dir}/saved.vltsv" or error("Saved.vltsv not created\n"); -sleep(1); # Avoid make getting confused by very fast build - -compile( - v_flags2 => ["--savable -GMODEL_WIDTH=40"], - save_time => 500, - ); - -execute( - all_run_flags => ['+save_restore=1'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_format1_bad.py b/test_regress/t/t_savable_format1_bad.py new file mode 100755 index 000000000..6965c4a35 --- /dev/null +++ b/test_regress/t/t_savable_format1_bad.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import time + +test.scenarios('vlt') +test.top_filename = "t/t_savable.v" + +test.compile(v_flags2=["--savable"], save_time=500) + +test.execute(check_finished=False, all_run_flags=['+save_time=500']) + +if not os.path.exists(test.obj_dir + "/saved.vltsv"): + test.error("Saved.vltsv not created") + +time.sleep(1) +# Avoid make getting confused by very fast build + +test.compile(v_flags2=["--savable -GMODEL_WIDTH=40"], save_time=500) + +test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_format2_bad.pl b/test_regress/t/t_savable_format2_bad.pl deleted file mode 100755 index ee0a4d518..000000000 --- a/test_regress/t/t_savable_format2_bad.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_savable.v"); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - ); - -execute( - check_finished => 0, - all_run_flags => ['+save_time=500'], - ); - --r "$Self->{obj_dir}/saved.vltsv" or error("Saved.vltsv not created\n"); - -# Break the header -file_sed("$Self->{obj_dir}/saved.vltsv", - "$Self->{obj_dir}/saved.vltsv", - sub { s/verilatorsave/verilatorsavBAD/g; }); - -execute( - all_run_flags => ['+save_restore=1'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_format2_bad.py b/test_regress/t/t_savable_format2_bad.py new file mode 100755 index 000000000..8940d15ca --- /dev/null +++ b/test_regress/t/t_savable_format2_bad.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_savable.v" + +test.compile(v_flags2=["--savable"], save_time=500) + +test.execute(check_finished=False, all_run_flags=['+save_time=500']) + +if not os.path.exists(test.obj_dir + "/saved.vltsv"): + test.error("Saved.vltsv not created") + +# Break the header +test.file_sed(test.obj_dir + "/saved.vltsv", test.obj_dir + "/saved.vltsv", + lambda line: re.sub(r'verilatorsave', 'verilatorsavBAD', line)) + +test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_format3_bad.pl b/test_regress/t/t_savable_format3_bad.pl deleted file mode 100755 index ce78e55f1..000000000 --- a/test_regress/t/t_savable_format3_bad.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_savable.v"); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - ); - -execute( - check_finished => 0, - all_run_flags => ['+save_time=500'], - ); - --r "$Self->{obj_dir}/saved.vltsv" or error("Saved.vltsv not created\n"); - -# Break the header -file_sed("$Self->{obj_dir}/saved.vltsv", - "$Self->{obj_dir}/saved.vltsv", - sub { s/vltsaved/vltNOTed/g; }); - -execute( - all_run_flags => ['+save_restore=1'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_format3_bad.py b/test_regress/t/t_savable_format3_bad.py new file mode 100755 index 000000000..cadd098c2 --- /dev/null +++ b/test_regress/t/t_savable_format3_bad.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_savable.v" + +test.compile(v_flags2=["--savable"], save_time=500) + +test.execute(check_finished=False, all_run_flags=['+save_time=500']) + +if not os.path.exists(test.obj_dir + "/saved.vltsv"): + test.error("saved.vltsv not created") + +# Break the header +test.file_sed(test.obj_dir + "/saved.vltsv", test.obj_dir + "/saved.vltsv", + lambda line: re.sub(r'vltsaved', 'vltNOTed', line)) + +test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_open_bad.pl b/test_regress/t/t_savable_open_bad.pl deleted file mode 100755 index a2160366f..000000000 --- a/test_regress/t/t_savable_open_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_savable.v"); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - ); - -execute( - all_run_flags => ['+save_restore=1'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_open_bad.py b/test_regress/t/t_savable_open_bad.py new file mode 100755 index 000000000..b7a64c02d --- /dev/null +++ b/test_regress/t/t_savable_open_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_savable.v" + +test.compile(v_flags2=["--savable"], save_time=500) + +test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_open_bad2.pl b/test_regress/t/t_savable_open_bad2.pl deleted file mode 100755 index 445737f1a..000000000 --- a/test_regress/t/t_savable_open_bad2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--savable --exe $Self->{t_dir}/t_savable_open_bad2.cpp"], - make_main => 0, - ); - -execute( - check_finished => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_open_bad2.py b/test_regress/t/t_savable_open_bad2.py new file mode 100755 index 000000000..3a759f54f --- /dev/null +++ b/test_regress/t/t_savable_open_bad2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--savable --exe", test.pli_filename], make_main=False) + +test.execute(check_finished=False) + +test.passes() diff --git a/test_regress/t/t_sc_names.pl b/test_regress/t/t_sc_names.pl deleted file mode 100755 index c234cca69..000000000 --- a/test_regress/t/t_sc_names.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - compile( - make_main => 0, - verilator_flags2 => ["-sc --exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_sc_names.py b/test_regress/t/t_sc_names.py new file mode 100755 index 000000000..c891a1ee0 --- /dev/null +++ b/test_regress/t/t_sc_names.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(make_main=False, verilator_flags2=["-sc --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_0.pl b/test_regress/t/t_scheduling_0.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_scheduling_0.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_0.py b/test_regress/t/t_scheduling_0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_scheduling_0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_1.pl b/test_regress/t/t_scheduling_1.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_scheduling_1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_1.py b/test_regress/t/t_scheduling_1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_scheduling_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_2.pl b/test_regress/t/t_scheduling_2.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_scheduling_2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_2.py b/test_regress/t/t_scheduling_2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_scheduling_2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_3.pl b/test_regress/t/t_scheduling_3.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_scheduling_3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_3.py b/test_regress/t/t_scheduling_3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_scheduling_3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_4.pl b/test_regress/t/t_scheduling_4.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_scheduling_4.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_4.py b/test_regress/t/t_scheduling_4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_scheduling_4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_5.pl b/test_regress/t/t_scheduling_5.pl deleted file mode 100755 index c485f7c23..000000000 --- a/test_regress/t/t_scheduling_5.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-MULTIDRIVEN"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_5.py b/test_regress/t/t_scheduling_5.py new file mode 100755 index 000000000..b80b4f79f --- /dev/null +++ b/test_regress/t/t_scheduling_5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-MULTIDRIVEN"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scope_map.pl b/test_regress/t/t_scope_map.pl deleted file mode 100755 index 03dbdc1fd..000000000 --- a/test_regress/t/t_scope_map.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2015 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_scope_map.py b/test_regress/t/t_scope_map.py new file mode 100755 index 000000000..ec6142999 --- /dev/null +++ b/test_regress/t/t_scope_map.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_2d.pl b/test_regress/t/t_select_2d.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_select_2d.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_2d.py b/test_regress/t/t_select_2d.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_2d.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_ascending.pl b/test_regress/t/t_select_ascending.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_ascending.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_ascending.py b/test_regress/t/t_select_ascending.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_ascending.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_bad_msb.pl b/test_regress/t/t_select_bad_msb.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_select_bad_msb.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_msb.py b/test_regress/t/t_select_bad_msb.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_select_bad_msb.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range.pl b/test_regress/t/t_select_bad_range.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_range.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range.py b/test_regress/t/t_select_bad_range.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_range.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range2.pl b/test_regress/t/t_select_bad_range2.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_range2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range2.py b/test_regress/t/t_select_bad_range2.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_range2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range3.pl b/test_regress/t/t_select_bad_range3.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_range3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range3.py b/test_regress/t/t_select_bad_range3.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_range3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range4.pl b/test_regress/t/t_select_bad_range4.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_range4.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range4.py b/test_regress/t/t_select_bad_range4.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_range4.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range5.pl b/test_regress/t/t_select_bad_range5.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_range5.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range5.py b/test_regress/t/t_select_bad_range5.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_range5.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range6.pl b/test_regress/t/t_select_bad_range6.pl deleted file mode 100755 index 18791b049..000000000 --- a/test_regress/t/t_select_bad_range6.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range6.py b/test_regress/t/t_select_bad_range6.py new file mode 100755 index 000000000..a6f7c2c22 --- /dev/null +++ b/test_regress/t/t_select_bad_range6.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_tri.pl b/test_regress/t/t_select_bad_tri.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_tri.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_tri.py b/test_regress/t/t_select_bad_tri.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_tri.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_width0.pl b/test_regress/t/t_select_bad_width0.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_width0.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_width0.py b/test_regress/t/t_select_bad_width0.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_width0.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bound1.pl b/test_regress/t/t_select_bound1.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_bound1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bound1.py b/test_regress/t/t_select_bound1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_bound1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_bound1.v b/test_regress/t/t_select_bound1.v index adecef33b..811f2bea6 100644 --- a/test_regress/t/t_select_bound1.v +++ b/test_regress/t/t_select_bound1.v @@ -83,6 +83,8 @@ module Test (/*AUTOARG*/ // verilator lint_off WIDTH out <= p[15 + in -: 5]; // verilator lint_on WIDTH + end + always @(posedge clk) begin mask[3] <= ((15 + in - 5) < 12); mask[2] <= ((15 + in - 5) < 13); mask[1] <= ((15 + in - 5) < 14); diff --git a/test_regress/t/t_select_bound2.pl b/test_regress/t/t_select_bound2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_bound2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bound2.py b/test_regress/t/t_select_bound2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_bound2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_crazy.pl b/test_regress/t/t_select_crazy.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_crazy.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_crazy.py b/test_regress/t/t_select_crazy.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_crazy.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_index.pl b/test_regress/t/t_select_index.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_index.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_index.py b/test_regress/t/t_select_index.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_index.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_index2.pl b/test_regress/t/t_select_index2.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_select_index2.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_select_index2.py b/test_regress/t/t_select_index2.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_select_index2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_select_index2.v b/test_regress/t/t_select_index2.v index c62b69965..f0b711c48 100644 --- a/test_regress/t/t_select_index2.v +++ b/test_regress/t/t_select_index2.v @@ -4,11 +4,7 @@ // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); reg [7:0] x; wire [3:0] en; diff --git a/test_regress/t/t_select_lhs_oob.pl b/test_regress/t/t_select_lhs_oob.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_lhs_oob.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_lhs_oob.py b/test_regress/t/t_select_lhs_oob.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_lhs_oob.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_lhs_oob2.pl b/test_regress/t/t_select_lhs_oob2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_lhs_oob2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_lhs_oob2.py b/test_regress/t/t_select_lhs_oob2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_lhs_oob2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_little.pl b/test_regress/t/t_select_little.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_little.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_little.py b/test_regress/t/t_select_little.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_little.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_little_pack.pl b/test_regress/t/t_select_little_pack.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_little_pack.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_little_pack.py b/test_regress/t/t_select_little_pack.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_little_pack.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_little_pack.v b/test_regress/t/t_select_little_pack.v index 3f7492a84..bd0e7f397 100644 --- a/test_regress/t/t_select_little_pack.v +++ b/test_regress/t/t_select_little_pack.v @@ -4,11 +4,7 @@ // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); // No ascending range warning here reg [7:0] pack [3:0]; diff --git a/test_regress/t/t_select_loop.pl b/test_regress/t/t_select_loop.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_loop.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_loop.py b/test_regress/t/t_select_loop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_loop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_mul_extend.pl b/test_regress/t/t_select_mul_extend.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_select_mul_extend.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_mul_extend.py b/test_regress/t/t_select_mul_extend.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_mul_extend.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_mul_extend.v b/test_regress/t/t_select_mul_extend.v index 0803259b0..dc9d2a1d4 100644 --- a/test_regress/t/t_select_mul_extend.v +++ b/test_regress/t/t_select_mul_extend.v @@ -19,19 +19,19 @@ module t(/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v + wire [31:0] out; // From test of Test.v // End of automatics Test test(/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .in (in[31:0])); + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); Test2 test2(/*AUTOINST*/ - // Inputs - .clk (clk)); + // Inputs + .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; @@ -87,7 +87,7 @@ module Test(/*AUTOARG*/ if (i == (cond ? (2-cnt)%8 : 0)) begin q[i] = 31'(in); end - else begin + else begin q[i] = '0; end end diff --git a/test_regress/t/t_select_negative.pl b/test_regress/t/t_select_negative.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_negative.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_negative.py b/test_regress/t/t_select_negative.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_negative.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_out_of_range.py b/test_regress/t/t_select_out_of_range.py new file mode 100755 index 000000000..9fff37b43 --- /dev/null +++ b/test_regress/t/t_select_out_of_range.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-Wno-SELRANGE"]) + +test.passes() diff --git a/test_regress/t/t_select_out_of_range.v b/test_regress/t/t_select_out_of_range.v new file mode 100644 index 000000000..7ecbbe6fa --- /dev/null +++ b/test_regress/t/t_select_out_of_range.v @@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module serial_adder( + input cin, + output cout +); + localparam WIDTH = 8; + + wire [WIDTH:0] c; + + generate for (genvar i = 0; i < WIDTH; i++) + full_adder fa(c[i+1]); + endgenerate + + assign c[0] = cin; + assign cout = c[WIDTH+1]; // intentional out-of-range + +endmodule + +module full_adder (output cout); +endmodule diff --git a/test_regress/t/t_select_param.pl b/test_regress/t/t_select_param.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_param.py b/test_regress/t/t_select_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_plus.pl b/test_regress/t/t_select_plus.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_plus.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_plus.py b/test_regress/t/t_select_plus.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_plus.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_plus_mul_pow2.pl b/test_regress/t/t_select_plus_mul_pow2.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_select_plus_mul_pow2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_plus_mul_pow2.py b/test_regress/t/t_select_plus_mul_pow2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_plus_mul_pow2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_plusloop.pl b/test_regress/t/t_select_plusloop.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_plusloop.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_plusloop.py b/test_regress/t/t_select_plusloop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_plusloop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_runtime_range.pl b/test_regress/t/t_select_runtime_range.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_runtime_range.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_runtime_range.py b/test_regress/t/t_select_runtime_range.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_runtime_range.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_set.pl b/test_regress/t/t_select_set.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_select_set.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_set.py b/test_regress/t/t_select_set.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_set.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_width.pl b/test_regress/t/t_select_width.pl deleted file mode 100755 index 09b2ce4eb..000000000 --- a/test_regress/t/t_select_width.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_width.py b/test_regress/t/t_select_width.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_select_width.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_selextract_in_paramextends.pl b/test_regress/t/t_selextract_in_paramextends.pl deleted file mode 100755 index fec4c2942..000000000 --- a/test_regress/t/t_selextract_in_paramextends.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_selextract_in_paramextends.py b/test_regress/t/t_selextract_in_paramextends.py new file mode 100755 index 000000000..7bd93561b --- /dev/null +++ b/test_regress/t/t_selextract_in_paramextends.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_semaphore.pl b/test_regress/t/t_semaphore.pl deleted file mode 100755 index 41f6e2a53..000000000 --- a/test_regress/t/t_semaphore.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing -Wall"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore.py b/test_regress/t/t_semaphore.py new file mode 100755 index 000000000..e84a7d7e7 --- /dev/null +++ b/test_regress/t/t_semaphore.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing -Wall"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_semaphore_always.pl b/test_regress/t/t_semaphore_always.pl deleted file mode 100755 index b267631e9..000000000 --- a/test_regress/t/t_semaphore_always.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore_always.py b/test_regress/t/t_semaphore_always.py new file mode 100755 index 000000000..34b0247e9 --- /dev/null +++ b/test_regress/t/t_semaphore_always.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_semaphore_bad.pl b/test_regress/t/t_semaphore_bad.pl deleted file mode 100755 index a083f46f5..000000000 --- a/test_regress/t/t_semaphore_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore_bad.py b/test_regress/t/t_semaphore_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_semaphore_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_semaphore_class.pl b/test_regress/t/t_semaphore_class.pl deleted file mode 100755 index 91589388d..000000000 --- a/test_regress/t/t_semaphore_class.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore_class.py b/test_regress/t/t_semaphore_class.py new file mode 100755 index 000000000..bbbcfc078 --- /dev/null +++ b/test_regress/t/t_semaphore_class.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.passes() diff --git a/test_regress/t/t_semaphore_concurrent.pl b/test_regress/t/t_semaphore_concurrent.pl deleted file mode 100755 index e99ff9766..000000000 --- a/test_regress/t/t_semaphore_concurrent.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Liam Braun and Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"] - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore_concurrent.py b/test_regress/t/t_semaphore_concurrent.py new file mode 100755 index 000000000..a74b0c7ec --- /dev/null +++ b/test_regress/t/t_semaphore_concurrent.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_semaphore_std.pl b/test_regress/t/t_semaphore_std.pl deleted file mode 100755 index 39236c3d4..000000000 --- a/test_regress/t/t_semaphore_std.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_semaphore.v"); - -compile( - verilator_flags2 => ["--exe --main --timing -Wall -DSEMAPHORE_T=std::semaphore"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore_std.py b/test_regress/t/t_semaphore_std.py new file mode 100755 index 000000000..1b61c0548 --- /dev/null +++ b/test_regress/t/t_semaphore_std.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_semaphore.v" + +test.compile(verilator_flags2=["--exe --main --timing -Wall -DSEMAPHORE_T=std::semaphore"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sequence_sexpr_unsup.pl b/test_regress/t/t_sequence_sexpr_unsup.pl deleted file mode 100755 index 7284ec30e..000000000 --- a/test_regress/t/t_sequence_sexpr_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert --error-limit 1000'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sequence_sexpr_unsup.py b/test_regress/t/t_sequence_sexpr_unsup.py new file mode 100755 index 000000000..25f9960b8 --- /dev/null +++ b/test_regress/t/t_sequence_sexpr_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, + verilator_flags2=['--assert --error-limit 1000'], + fails=True) + +test.passes() diff --git a/test_regress/t/t_slice_cmp.pl b/test_regress/t/t_slice_cmp.pl deleted file mode 100755 index 2cb5eeaff..000000000 --- a/test_regress/t/t_slice_cmp.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_slice_cmp.py b/test_regress/t/t_slice_cmp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_slice_cmp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_slice_cond.pl b/test_regress/t/t_slice_cond.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_slice_cond.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_slice_cond.py b/test_regress/t/t_slice_cond.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_slice_cond.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_slice_init.pl b/test_regress/t/t_slice_init.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_slice_init.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_slice_init.py b/test_regress/t/t_slice_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_slice_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_slice_struct_array_modport.pl b/test_regress/t/t_slice_struct_array_modport.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_slice_struct_array_modport.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_slice_struct_array_modport.py b/test_regress/t/t_slice_struct_array_modport.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_slice_struct_array_modport.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_source_sync.out b/test_regress/t/t_source_sync.out deleted file mode 100644 index 92dd48e27..000000000 --- a/test_regress/t/t_source_sync.out +++ /dev/null @@ -1,7 +0,0 @@ -%Error: t/t_source_sync.v:8:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';' - 8 | logic clk /*verilator clocker*/ ; - | ^~~~~~~~~~~~~~~~~~~~~ -%Error: t/t_source_sync.v:10:1: syntax error, unexpected '}' - 10 | } ss_s; - | ^ -%Error: Exiting due to diff --git a/test_regress/t/t_source_sync.pl b/test_regress/t/t_source_sync.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_source_sync.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_source_sync.v b/test_regress/t/t_source_sync.v deleted file mode 100644 index 2ca3a7282..000000000 --- a/test_regress/t/t_source_sync.v +++ /dev/null @@ -1,12 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Dan Petrisko. -// SPDX-License-Identifier: CC0-1.0 - -typedef struct packed { - logic clk /*verilator clocker*/; - logic data; -} ss_s; - -endmodule diff --git a/test_regress/t/t_source_sync_bad.out b/test_regress/t/t_source_sync_bad.out new file mode 100644 index 000000000..081308b24 --- /dev/null +++ b/test_regress/t/t_source_sync_bad.out @@ -0,0 +1,16 @@ +%Error: t/t_source_sync_bad.v:17:16: syntax error, unexpected IDENTIFIER + 17 | Invalid1 invalid1; + | ^~~~~~~~ +%Error: t/t_source_sync_bad.v:20:16: syntax error, unexpected IDENTIFIER + 20 | Invalid2 invalid2; + | ^~~~~~~~ +%Error: t/t_source_sync_bad.v:24:22: syntax error, unexpected IDENTIFIER, expecting "'{" + 24 | pkg::cls::defi invalid; + | ^~~~~~~ +%Error: t/t_source_sync_bad.v:30:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';' + 30 | logic clk /*verilator clocker*/ ; + | ^~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_source_sync_bad.v:34:1: syntax error, unexpected endmodule + 34 | endmodule + | ^~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_source_sync_bad.py b/test_regress/t/t_source_sync_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_source_sync_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_source_sync_bad.v b/test_regress/t/t_source_sync_bad.v new file mode 100644 index 000000000..32b7559ab --- /dev/null +++ b/test_regress/t/t_source_sync_bad.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Dan Petrisko. +// SPDX-License-Identifier: CC0-1.0 + +package pkg; + class cls; + typedef unknown defu; + typedef int defi; + endclass +endpackage + +module t; + task tsk; + begin + Invalid1 invalid1; // invalid declaration + pkg::cls::defi valid1; // valid declaration + pkg::cls::defu valid2; // valid declaration + Invalid2 invalid2; // invalid declaration + + valid1 = 5; // valid statement + + pkg::cls::defi invalid; // invalid statement + end + endtask +endmodule + +typedef struct packed { + logic clk /*verilator clocker*/; + logic data; +} ss_s; + +endmodule diff --git a/test_regress/t/t_split_var_0.pl b/test_regress/t/t_split_var_0.pl deleted file mode 100755 index 6f0d325a3..000000000 --- a/test_regress/t/t_split_var_0.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -compile( - verilator_flags2 => ['--stats', "$Self->{t_dir}/t_split_var_0.vlt"], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 13); -file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 27); -ok(1); -1; diff --git a/test_regress/t/t_split_var_0.py b/test_regress/t/t_split_var_0.py new file mode 100755 index 000000000..552901963 --- /dev/null +++ b/test_regress/t/t_split_var_0.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. +test.compile(verilator_flags2=['--stats', test.t_dir + "/t_split_var_0.vlt"], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.stats, r'SplitVar,\s+Split packed variables\s+(\d+)', 13) +test.file_grep(test.stats, r'SplitVar,\s+Split unpacked arrays\s+(\d+)', 27) +test.passes() diff --git a/test_regress/t/t_split_var_1_bad.pl b/test_regress/t/t_split_var_1_bad.pl deleted file mode 100755 index 256bd9bc6..000000000 --- a/test_regress/t/t_split_var_1_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - verilator_flags2 => ['--stats'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_split_var_1_bad.py b/test_regress/t/t_split_var_1_bad.py new file mode 100755 index 000000000..699eafaf5 --- /dev/null +++ b/test_regress/t/t_split_var_1_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, verilator_flags2=['--stats'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_split_var_1_bad.v b/test_regress/t/t_split_var_1_bad.v index 110bd2c68..32f1f2107 100644 --- a/test_regress/t/t_split_var_1_bad.v +++ b/test_regress/t/t_split_var_1_bad.v @@ -24,8 +24,8 @@ module t(); sub0 i_sub0(.addr(addr), .rd_data(rd_data0)); sub1 i_sub1(.addr(addr), .rd_data(rd_data2)); - sub2 i_sub2; - sub3 i_sub3; + sub2 i_sub2(); + sub3 i_sub3(); ifs i_ifs(); function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/, diff --git a/test_regress/t/t_split_var_2_trace.pl b/test_regress/t/t_split_var_2_trace.pl deleted file mode 100755 index 6016b60f4..000000000 --- a/test_regress/t/t_split_var_2_trace.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_split_var_0.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -compile( - verilator_flags2 => ['--cc --trace --stats +define+TEST_ATTRIBUTES'], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 12); -file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 27); - -ok(1); -1; diff --git a/test_regress/t/t_split_var_2_trace.py b/test_regress/t/t_split_var_2_trace.py new file mode 100755 index 000000000..0c529d123 --- /dev/null +++ b/test_regress/t/t_split_var_2_trace.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_split_var_0.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. +test.compile(verilator_flags2=['--cc --trace --stats +define+TEST_ATTRIBUTES'], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) +test.file_grep(test.stats, r'SplitVar,\s+Split packed variables\s+(\d+)', 12) +test.file_grep(test.stats, r'SplitVar,\s+Split unpacked arrays\s+(\d+)', 27) + +test.passes() diff --git a/test_regress/t/t_split_var_3_wreal.pl b/test_regress/t/t_split_var_3_wreal.pl deleted file mode 100755 index 8baf1786c..000000000 --- a/test_regress/t/t_split_var_3_wreal.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--stats'], - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 0); -file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 3); -ok(1); -1; diff --git a/test_regress/t/t_split_var_3_wreal.py b/test_regress/t/t_split_var_3_wreal.py new file mode 100755 index 000000000..ad0e1af0e --- /dev/null +++ b/test_regress/t/t_split_var_3_wreal.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--stats']) + +test.execute() + +test.file_grep(test.stats, r'SplitVar,\s+Split packed variables\s+(\d+)', 0) +test.file_grep(test.stats, r'SplitVar,\s+Split unpacked arrays\s+(\d+)', 3) + +test.passes() diff --git a/test_regress/t/t_split_var_4.pl b/test_regress/t/t_split_var_4.pl deleted file mode 100755 index 9030a83e0..000000000 --- a/test_regress/t/t_split_var_4.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--stats', '-DENABLE_SPLIT_VAR=1'], - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 1); -file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 0); -ok(1); -1; diff --git a/test_regress/t/t_split_var_4.py b/test_regress/t/t_split_var_4.py new file mode 100755 index 000000000..60672ac88 --- /dev/null +++ b/test_regress/t/t_split_var_4.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--stats', '-DENABLE_SPLIT_VAR=1']) + +test.execute() + +test.file_grep(test.stats, r'SplitVar,\s+Split packed variables\s+(\d+)', 1) +test.file_grep(test.stats, r'SplitVar,\s+Split unpacked arrays\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_split_var_5.pl b/test_regress/t/t_split_var_5.pl deleted file mode 100755 index 41ddbc69c..000000000 --- a/test_regress/t/t_split_var_5.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_split_var_4.v"); - -compile( - verilator_flags2 => ['--stats'] - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 0); -file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 0); -ok(1); -1; diff --git a/test_regress/t/t_split_var_5.py b/test_regress/t/t_split_var_5.py new file mode 100755 index 000000000..2e70a4379 --- /dev/null +++ b/test_regress/t/t_split_var_5.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_split_var_4.v" + +test.compile(verilator_flags2=['--stats']) + +test.execute() + +test.file_grep(test.stats, r'SplitVar,\s+Split packed variables\s+(\d+)', 0) +test.file_grep(test.stats, r'SplitVar,\s+Split unpacked arrays\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_srandom_class_dep.pl b/test_regress/t/t_srandom_class_dep.pl deleted file mode 100755 index c74d44be5..000000000 --- a/test_regress/t/t_srandom_class_dep.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_srandom_class_dep.py b/test_regress/t/t_srandom_class_dep.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_srandom_class_dep.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_stack_check.pl b/test_regress/t/t_stack_check.pl deleted file mode 100755 index 2cf86f001..000000000 --- a/test_regress/t/t_stack_check.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--binary --debug-stack-check'], - ); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_stack_check.py b/test_regress/t/t_stack_check.py new file mode 100755 index 000000000..34009ba06 --- /dev/null +++ b/test_regress/t/t_stack_check.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --debug-stack-check']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stack_check_fail.pl b/test_regress/t/t_stack_check_fail.pl deleted file mode 100755 index a2ef01d76..000000000 --- a/test_regress/t/t_stack_check_fail.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_stack_check.v"); - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--binary --debug-stack-check', '--CFLAGS', '"-D_VL_TEST_RLIMIT_FAIL"'], - ); - -execute(); - -file_grep($Self->{run_log_filename}, qr/.*%Warning: System has stack size/); -ok(1); -1; diff --git a/test_regress/t/t_stack_check_fail.py b/test_regress/t/t_stack_check_fail.py new file mode 100755 index 000000000..fee5f470b --- /dev/null +++ b/test_regress/t/t_stack_check_fail.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_stack_check.v" + +test.compile( + verilator_flags2=['--binary --debug-stack-check', '--CFLAGS', '"-D_VL_TEST_RLIMIT_FAIL"']) + +test.execute() + +test.file_grep(test.run_log_filename, r'.*%Warning: System has stack size') +test.passes() diff --git a/test_regress/t/t_stacktrace.pl b/test_regress/t/t_stacktrace.pl deleted file mode 100755 index 4e42b8db0..000000000 --- a/test_regress/t/t_stacktrace.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_stacktrace.py b/test_regress/t/t_stacktrace.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stacktrace.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_dup_name.pl b/test_regress/t/t_static_dup_name.pl deleted file mode 100755 index db885e46d..000000000 --- a/test_regress/t/t_static_dup_name.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{verilated_randReset} = 1; - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_static_dup_name.py b/test_regress/t/t_static_dup_name.py new file mode 100755 index 000000000..629441927 --- /dev/null +++ b/test_regress/t/t_static_dup_name.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.verilated_randReset = 1 + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_elab.pl b/test_regress/t/t_static_elab.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_static_elab.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_static_elab.py b/test_regress/t/t_static_elab.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_static_elab.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_function_in_class.pl b/test_regress/t/t_static_function_in_class.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_static_function_in_class.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_static_function_in_class.py b/test_regress/t/t_static_function_in_class.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_static_function_in_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_function_in_class.v b/test_regress/t/t_static_function_in_class.v index ab9a80288..10a0b6e73 100644 --- a/test_regress/t/t_static_function_in_class.v +++ b/test_regress/t/t_static_function_in_class.v @@ -8,8 +8,8 @@ class string_utils; typedef string array_of_string[]; static function array_of_string split_by_dash(string s); - string parts[$]; - int last_char_position = -1; + string parts[$]; + int last_char_position = -1; for (int i = 0; i < s.len(); i++) begin if (i == s.len()-1) begin parts.push_back(s.substr(last_char_position+1, i)); diff --git a/test_regress/t/t_static_function_in_class_call_without_parentheses.pl b/test_regress/t/t_static_function_in_class_call_without_parentheses.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_static_function_in_class_call_without_parentheses.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_static_function_in_class_call_without_parentheses.py b/test_regress/t/t_static_function_in_class_call_without_parentheses.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_static_function_in_class_call_without_parentheses.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_in_loop_unsup.pl b/test_regress/t/t_static_in_loop_unsup.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_static_in_loop_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_static_in_loop_unsup.py b/test_regress/t/t_static_in_loop_unsup.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_static_in_loop_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_std_identifier.py b/test_regress/t/t_std_identifier.py new file mode 100755 index 000000000..6938ef706 --- /dev/null +++ b/test_regress/t/t_std_identifier.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["-DTEST_DECLARE_STD"]) + +test.passes() diff --git a/test_regress/t/t_std_identifier_bad.v b/test_regress/t/t_std_identifier.v similarity index 100% rename from test_regress/t/t_std_identifier_bad.v rename to test_regress/t/t_std_identifier.v diff --git a/test_regress/t/t_std_identifier_bad.out b/test_regress/t/t_std_identifier_bad.out index 72bcf599b..c33ae7695 100644 --- a/test_regress/t/t_std_identifier_bad.out +++ b/test_regress/t/t_std_identifier_bad.out @@ -1,4 +1,4 @@ -%Error-PKGNODECL: t/t_std_identifier_bad.v:16:20: Package/class 'std' not found, and needs to be predeclared (IEEE 1800-2023 26.3) +%Error-PKGNODECL: t/t_std_identifier.v:16:20: Package/class 'std' not found, and needs to be predeclared (IEEE 1800-2023 26.3) 16 | int baz = foo::std::bar; | ^~~ ... For error description see https://verilator.org/warn/PKGNODECL?v=latest diff --git a/test_regress/t/t_std_identifier_bad.pl b/test_regress/t/t_std_identifier_bad.pl deleted file mode 100755 index 3e2acea9f..000000000 --- a/test_regress/t/t_std_identifier_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -lint( - verilator_flags2 => ["-DTEST_DECLARE_STD"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_std_identifier_bad.py b/test_regress/t/t_std_identifier_bad.py new file mode 100755 index 000000000..cdc19d5ba --- /dev/null +++ b/test_regress/t/t_std_identifier_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_std_identifier.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_std_pkg_bad.pl b/test_regress/t/t_std_pkg_bad.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_std_pkg_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_std_pkg_bad.py b/test_regress/t/t_std_pkg_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_std_pkg_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_std_process_self.pl b/test_regress/t/t_std_process_self.pl deleted file mode 100755 index 80841859b..000000000 --- a/test_regress/t/t_std_process_self.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--exe --main --timing"], - ); - -lint( - verilator_flags2 => ["--exe --main --timing --DUSE_STD_PREFIX"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_std_process_self.py b/test_regress/t/t_std_process_self.py new file mode 100755 index 000000000..d8b6a325d --- /dev/null +++ b/test_regress/t/t_std_process_self.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--exe --main --timing"]) + +test.passes() diff --git a/test_regress/t/t_std_process_self_std.py b/test_regress/t/t_std_process_self_std.py new file mode 100755 index 000000000..94cce2d22 --- /dev/null +++ b/test_regress/t/t_std_process_self_std.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_std_process_self.v" + +test.lint(verilator_flags2=["--exe --main --timing --DUSE_STD_PREFIX"]) + +test.passes() diff --git a/test_regress/t/t_std_randomize_unsup_bad.pl b/test_regress/t/t_std_randomize_unsup_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_std_randomize_unsup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_std_randomize_unsup_bad.py b/test_regress/t/t_std_randomize_unsup_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_std_randomize_unsup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_stmt_incr_unsup.pl b/test_regress/t/t_stmt_incr_unsup.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_stmt_incr_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stmt_incr_unsup.py b/test_regress/t/t_stmt_incr_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_stmt_incr_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_stop_bad.pl b/test_regress/t/t_stop_bad.pl deleted file mode 100755 index 31a7a66ff..000000000 --- a/test_regress/t/t_stop_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => 1, - check_finished => 0, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_stop_bad.py b/test_regress/t/t_stop_bad.py new file mode 100755 index 000000000..2fdd6e92d --- /dev/null +++ b/test_regress/t/t_stop_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_stream.pl b/test_regress/t/t_stream.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_stream.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream.py b/test_regress/t/t_stream.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream.v b/test_regress/t/t_stream.v index b09985eeb..39f147be4 100644 --- a/test_regress/t/t_stream.v +++ b/test_regress/t/t_stream.v @@ -219,88 +219,88 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; if (cyc == 1) begin - din_i <= 32'h_00_00_00_01; - din_q <= 64'h_00_00_00_00_00_00_00_01; - din_w <= 96'h_00_00_00_00_00_00_00_00_00_00_00_01; + din_i <= 32'h00_00_00_01; + din_q <= 64'h00_00_00_00_00_00_00_01; + din_w <= 96'h00_00_00_00_00_00_00_00_00_00_00_01; - din_lhs <= 4'b_00_01; + din_lhs <= 4'b00_01; end if (cyc == 2) begin - din_i <= 32'h_04_03_02_01; - din_q <= 64'h_08_07_06_05_04_03_02_01; - din_w <= 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01; + din_i <= 32'h04_03_02_01; + din_q <= 64'h08_07_06_05_04_03_02_01; + din_w <= 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01; - din_lhs <= 4'b_01_11; + din_lhs <= 4'b01_11; - if (dout_rhs_ls_i != 32'h_80_00_00_00) $stop; - if (dout_rhs_ls_q != 64'h_80_00_00_00_00_00_00_00) $stop; - if (dout_rhs_ls_w != 96'h_80_00_00_00_00_00_00_00_00_00_00_00) $stop; + if (dout_rhs_ls_i != 32'h80_00_00_00) $stop; + if (dout_rhs_ls_q != 64'h80_00_00_00_00_00_00_00) $stop; + if (dout_rhs_ls_w != 96'h80_00_00_00_00_00_00_00_00_00_00_00) $stop; - if (dout_rhs_rs_i != 32'h_00_00_00_01) $stop; - if (dout_rhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop; - if (dout_rhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop; + if (dout_rhs_rs_i != 32'h00_00_00_01) $stop; + if (dout_rhs_rs_q != 64'h00_00_00_00_00_00_00_01) $stop; + if (dout_rhs_rs_w != 96'h00_00_00_00_00_00_00_00_00_00_00_01) $stop; - if (dout_lhs_ls_a != 2'b_01) $stop; - if (dout_lhs_ls_b != 2'b_00) $stop; + if (dout_lhs_ls_a != 2'b01) $stop; + if (dout_lhs_ls_b != 2'b00) $stop; - if (dout_lhs_rs_a != 2'b_00) $stop; - if (dout_lhs_rs_b != 2'b_01) $stop; + if (dout_lhs_rs_a != 2'b00) $stop; + if (dout_lhs_rs_b != 2'b01) $stop; - if (dout_bhs_rs_i != 32'h_00_00_00_01) $stop; - if (dout_bhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop; - if (dout_bhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop; + if (dout_bhs_rs_i != 32'h00_00_00_01) $stop; + if (dout_bhs_rs_q != 64'h00_00_00_00_00_00_00_01) $stop; + if (dout_bhs_rs_w != 96'h00_00_00_00_00_00_00_00_00_00_00_01) $stop; - if (dout_bhs_ls_i != 32'h_00_00_00_10) $stop; - if (dout_bhs_ls_q != 64'h_00_00_00_00_00_00_01_00) $stop; - if (dout_bhs_ls_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_04) $stop; + if (dout_bhs_ls_i != 32'h00_00_00_10) $stop; + if (dout_bhs_ls_q != 64'h00_00_00_00_00_00_01_00) $stop; + if (dout_bhs_ls_w != 96'h00_00_00_00_00_00_00_00_00_00_00_04) $stop; - if (dout_rhs_ls_i_23_3 != 23'h_10_00_00) $stop; - if (dout_rhs_ls_i_23_4 != 23'h_08_00_00) $stop; + if (dout_rhs_ls_i_23_3 != 23'h10_00_00) $stop; + if (dout_rhs_ls_i_23_4 != 23'h08_00_00) $stop; - if (dout_rhs_ls_q_37_3 != 37'h_04_00_00_00_00) $stop; - if (dout_rhs_ls_q_37_4 != 37'h_02_00_00_00_00) $stop; + if (dout_rhs_ls_q_37_3 != 37'h04_00_00_00_00) $stop; + if (dout_rhs_ls_q_37_4 != 37'h02_00_00_00_00) $stop; end if (cyc == 3) begin // The values below test the strange shift-merge done at the end of // the fast stream operators. // All-1s in the bits being streamed should end up as all-1s. - din_i <= 32'h_00_7f_ff_ff; - din_q <= 64'h_00_00_00_1f_ff_ff_ff_ff; + din_i <= 32'h00_7f_ff_ff; + din_q <= 64'h00_00_00_1f_ff_ff_ff_ff; - if (dout_rhs_ls_i != 32'h_80_40_c0_20) $stop; - if (dout_rhs_ls_q != 64'h_80_40_c0_20_a0_60_e0_10) $stop; - if (dout_rhs_ls_w != 96'h_80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop; + if (dout_rhs_ls_i != 32'h80_40_c0_20) $stop; + if (dout_rhs_ls_q != 64'h80_40_c0_20_a0_60_e0_10) $stop; + if (dout_rhs_ls_w != 96'h80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop; - if (dout_rhs_rs_i != 32'h_04_03_02_01) $stop; - if (dout_rhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop; - if (dout_rhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; + if (dout_rhs_rs_i != 32'h04_03_02_01) $stop; + if (dout_rhs_rs_q != 64'h08_07_06_05_04_03_02_01) $stop; + if (dout_rhs_rs_w != 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; - if (dout_bhs_ls_i != 32'h_40_30_00_18) $stop; - if (dout_bhs_ls_q != 64'h_06_00_c1_81_41_00_c1_80) $stop; - if (dout_bhs_ls_w != 96'h_30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop; + if (dout_bhs_ls_i != 32'h40_30_00_18) $stop; + if (dout_bhs_ls_q != 64'h06_00_c1_81_41_00_c1_80) $stop; + if (dout_bhs_ls_w != 96'h30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop; - if (dout_bhs_rs_i != 32'h_04_03_02_01) $stop; - if (dout_bhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop; - if (dout_bhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; + if (dout_bhs_rs_i != 32'h04_03_02_01) $stop; + if (dout_bhs_rs_q != 64'h08_07_06_05_04_03_02_01) $stop; + if (dout_bhs_rs_w != 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; - if (dout_lhs_ls_a != 2'b_11) $stop; - if (dout_lhs_ls_b != 2'b_01) $stop; + if (dout_lhs_ls_a != 2'b11) $stop; + if (dout_lhs_ls_b != 2'b01) $stop; - if (dout_lhs_rs_a != 2'b_01) $stop; - if (dout_lhs_rs_b != 2'b_11) $stop; + if (dout_lhs_rs_a != 2'b01) $stop; + if (dout_lhs_rs_b != 2'b11) $stop; - if (dout_rhs_ls_i_23_3 != 23'h_10_08_c0) $stop; - if (dout_rhs_ls_i_23_4 != 23'h_08_10_18) $stop; + if (dout_rhs_ls_i_23_3 != 23'h10_08_c0) $stop; + if (dout_rhs_ls_i_23_4 != 23'h08_10_18) $stop; - if (dout_rhs_ls_q_37_3 != 37'h_04_02_30_10_44) $stop; - if (dout_rhs_ls_q_37_4 != 37'h_02_04_06_08_0a) $stop; + if (dout_rhs_ls_q_37_3 != 37'h04_02_30_10_44) $stop; + if (dout_rhs_ls_q_37_4 != 37'h02_04_06_08_0a) $stop; end if (cyc == 4) begin - if (dout_rhs_ls_i_23_3 != 23'h_7f_ff_ff) $stop; - if (dout_rhs_ls_i_23_4 != 23'h_7f_ff_ff) $stop; + if (dout_rhs_ls_i_23_3 != 23'h7f_ff_ff) $stop; + if (dout_rhs_ls_i_23_4 != 23'h7f_ff_ff) $stop; - if (dout_rhs_ls_q_37_3 != 37'h_1f_ff_ff_ff_ff) $stop; - if (dout_rhs_ls_q_37_4 != 37'h_1f_ff_ff_ff_ff) $stop; + if (dout_rhs_ls_q_37_3 != 37'h1f_ff_ff_ff_ff) $stop; + if (dout_rhs_ls_q_37_4 != 37'h1f_ff_ff_ff_ff) $stop; end if (cyc == 9) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_stream2.pl b/test_regress/t/t_stream2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_stream2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream2.py b/test_regress/t/t_stream2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream3.pl b/test_regress/t/t_stream3.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_stream3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream3.py b/test_regress/t/t_stream3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream4.pl b/test_regress/t/t_stream4.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_stream4.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream4.py b/test_regress/t/t_stream4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream5.pl b/test_regress/t/t_stream5.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_stream5.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream5.py b/test_regress/t/t_stream5.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_stream5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_bad.pl b/test_regress/t/t_stream_bad.pl deleted file mode 100755 index a29ead0ed..000000000 --- a/test_regress/t/t_stream_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_bad.py b/test_regress/t/t_stream_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_stream_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_stream_dynamic.pl b/test_regress/t/t_stream_dynamic.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_stream_dynamic.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_dynamic.py b/test_regress/t/t_stream_dynamic.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_dynamic.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_integer_type.pl b/test_regress/t/t_stream_integer_type.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_stream_integer_type.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_integer_type.py b/test_regress/t/t_stream_integer_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_integer_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_integer_type.v b/test_regress/t/t_stream_integer_type.v index 4c4dced6d..9d3a463e6 100644 --- a/test_regress/t/t_stream_integer_type.v +++ b/test_regress/t/t_stream_integer_type.v @@ -15,11 +15,7 @@ // any use, without warranty, 2020 by Victor Besyakov. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); logic [31:0] packed_data_32; logic [31:0] packed_data_32_ref; diff --git a/test_regress/t/t_stream_string_array.pl b/test_regress/t/t_stream_string_array.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_stream_string_array.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_string_array.py b/test_regress/t/t_stream_string_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_string_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_struct.pl b/test_regress/t/t_stream_struct.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_stream_struct.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_struct.py b/test_regress/t/t_stream_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_unpack.pl b/test_regress/t/t_stream_unpack.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_stream_unpack.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_unpack.py b/test_regress/t/t_stream_unpack.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_unpack.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_unpack_lhs.pl b/test_regress/t/t_stream_unpack_lhs.pl deleted file mode 100755 index f486bc76e..000000000 --- a/test_regress/t/t_stream_unpack_lhs.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_stream_unpack_lhs.py b/test_regress/t/t_stream_unpack_lhs.py new file mode 100755 index 000000000..7b6840f68 --- /dev/null +++ b/test_regress/t/t_stream_unpack_lhs.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_unpack_narrower.pl b/test_regress/t/t_stream_unpack_narrower.pl deleted file mode 100755 index a29ead0ed..000000000 --- a/test_regress/t/t_stream_unpack_narrower.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_unpack_narrower.py b/test_regress/t/t_stream_unpack_narrower.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_stream_unpack_narrower.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_stream_unpack_wider.pl b/test_regress/t/t_stream_unpack_wider.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_stream_unpack_wider.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_unpack_wider.py b/test_regress/t/t_stream_unpack_wider.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_unpack_wider.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_unpack_wider.v b/test_regress/t/t_stream_unpack_wider.v index 94b522875..e3c5643ed 100644 --- a/test_regress/t/t_stream_unpack_wider.v +++ b/test_regress/t/t_stream_unpack_wider.v @@ -6,7 +6,7 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/); initial begin diff --git a/test_regress/t/t_strength_2_uneq_assign.pl b/test_regress/t/t_strength_2_uneq_assign.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_strength_2_uneq_assign.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_2_uneq_assign.py b/test_regress/t/t_strength_2_uneq_assign.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_strength_2_uneq_assign.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_strength_assignments_constants.pl b/test_regress/t/t_strength_assignments_constants.pl deleted file mode 100755 index 85ac7d5bc..000000000 --- a/test_regress/t/t_strength_assignments_constants.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -lint( - verilator_flags2 => ["--language 1364-2005"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_assignments_constants.py b/test_regress/t/t_strength_assignments_constants.py new file mode 100755 index 000000000..c30c310ba --- /dev/null +++ b/test_regress/t/t_strength_assignments_constants.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.lint(verilator_flags2=["--language 1364-2005"]) + +test.passes() diff --git a/test_regress/t/t_strength_bufif1.pl b/test_regress/t/t_strength_bufif1.pl deleted file mode 100755 index 52f7cc53a..000000000 --- a/test_regress/t/t_strength_bufif1.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_bufif1.py b/test_regress/t/t_strength_bufif1.py new file mode 100755 index 000000000..6585af685 --- /dev/null +++ b/test_regress/t/t_strength_bufif1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_strength_equal_strength.pl b/test_regress/t/t_strength_equal_strength.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_strength_equal_strength.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_equal_strength.py b/test_regress/t/t_strength_equal_strength.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_strength_equal_strength.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_strength_highz.pl b/test_regress/t/t_strength_highz.pl deleted file mode 100755 index 6537d741c..000000000 --- a/test_regress/t/t_strength_highz.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--language 1364-2005"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_highz.py b/test_regress/t/t_strength_highz.py new file mode 100755 index 000000000..3c9bbc984 --- /dev/null +++ b/test_regress/t/t_strength_highz.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--language 1364-2005"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_strength_strong1_strong1_bad.pl b/test_regress/t/t_strength_strong1_strong1_bad.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_strength_strong1_strong1_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_strong1_strong1_bad.py b/test_regress/t/t_strength_strong1_strong1_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_strength_strong1_strong1_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_strength_strongest_constant.pl b/test_regress/t/t_strength_strongest_constant.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_strength_strongest_constant.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_strongest_constant.py b/test_regress/t/t_strength_strongest_constant.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_strength_strongest_constant.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_strength_strongest_non_tristate.pl b/test_regress/t/t_strength_strongest_non_tristate.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_strength_strongest_non_tristate.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_strongest_non_tristate.py b/test_regress/t/t_strength_strongest_non_tristate.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_strength_strongest_non_tristate.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string.pl b/test_regress/t/t_string.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_string.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_string.py b/test_regress/t/t_string.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string_byte.pl b/test_regress/t/t_string_byte.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_string_byte.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_byte.py b/test_regress/t/t_string_byte.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_string_byte.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string_dyn_num.pl b/test_regress/t/t_string_dyn_num.pl deleted file mode 100755 index a2660234f..000000000 --- a/test_regress/t/t_string_dyn_num.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_dyn_num.py b/test_regress/t/t_string_dyn_num.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_string_dyn_num.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_string_repl.pl b/test_regress/t/t_string_repl.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_string_repl.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_repl.py b/test_regress/t/t_string_repl.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_string_repl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string_size.pl b/test_regress/t/t_string_size.pl deleted file mode 100755 index 03b63c1a0..000000000 --- a/test_regress/t/t_string_size.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_size.py b/test_regress/t/t_string_size.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_string_size.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_string_to_bit.pl b/test_regress/t/t_string_to_bit.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_string_to_bit.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_to_bit.py b/test_regress/t/t_string_to_bit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_string_to_bit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string_type_methods.pl b/test_regress/t/t_string_type_methods.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_string_type_methods.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_type_methods.py b/test_regress/t/t_string_type_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_string_type_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string_type_methods.v b/test_regress/t/t_string_type_methods.v index 7884f4a47..603706cd3 100644 --- a/test_regress/t/t_string_type_methods.v +++ b/test_regress/t/t_string_type_methods.v @@ -6,8 +6,8 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkg(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_string_type_methods_bad.pl b/test_regress/t/t_string_type_methods_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_string_type_methods_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_type_methods_bad.py b/test_regress/t/t_string_type_methods_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_string_type_methods_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_anon.pl b/test_regress/t/t_struct_anon.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_struct_anon.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_struct_anon.py b/test_regress/t/t_struct_anon.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_struct_anon.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_struct_array.pl b/test_regress/t/t_struct_array.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_struct_array.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_array.py b/test_regress/t/t_struct_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_array_assignment.py b/test_regress/t/t_struct_array_assignment.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_array_assignment.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_array_assignment.v b/test_regress/t/t_struct_array_assignment.v new file mode 100755 index 000000000..60e5d1532 --- /dev/null +++ b/test_regress/t/t_struct_array_assignment.v @@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by PlanV GmbH. +// SPDX-License-Identifier: CC0-1.0 + +class unconstrained_struct_array_test; + + typedef struct { + int field_a; + int field_b; + int field_c; + } simple_struct_t; + + simple_struct_t struct_array[3]; // Unpacked array + + function new(); + // Initialize struct_array + struct_array = '{'{default: 0}, '{default: 1}, '{default: 2}}; + endfunction + + // Self-check function to validate the array contents + function void self_test(); + foreach (struct_array[i]) begin + if (struct_array[i].field_a != i) $stop; + if (struct_array[i].field_b != i + 1) $stop; + if (struct_array[i].field_c != i + 2) $stop; + end + endfunction + +endclass + +module t_struct_array_assignment; + unconstrained_struct_array_test cl; + + initial begin + + cl = new(); + + foreach(cl.struct_array[i]) begin + cl.struct_array[i].field_a = i; + cl.struct_array[i].field_b = i + 1; + cl.struct_array[i].field_c = i + 2; + end + + cl.self_test(); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_struct_assign.pl b/test_regress/t/t_struct_assign.pl deleted file mode 100755 index 11eeb66fe..000000000 --- a/test_regress/t/t_struct_assign.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_assign.py b/test_regress/t/t_struct_assign.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_struct_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_clk.pl b/test_regress/t/t_struct_clk.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_struct_clk.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_clk.py b/test_regress/t/t_struct_clk.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_clk.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_cons_cast.pl b/test_regress/t/t_struct_cons_cast.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_struct_cons_cast.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_cons_cast.py b/test_regress/t/t_struct_cons_cast.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_cons_cast.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_contents.pl b/test_regress/t/t_struct_contents.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_struct_contents.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_contents.py b/test_regress/t/t_struct_contents.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_contents.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_contents_bad.pl b/test_regress/t/t_struct_contents_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_struct_contents_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_contents_bad.py b/test_regress/t/t_struct_contents_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_struct_contents_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_genfor.pl b/test_regress/t/t_struct_genfor.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_struct_genfor.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_struct_genfor.py b/test_regress/t/t_struct_genfor.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_struct_genfor.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_struct_init.pl b/test_regress/t/t_struct_init.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_struct_init.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_init.py b/test_regress/t/t_struct_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_init.v b/test_regress/t/t_struct_init.v index 4f154d190..79f2dd373 100644 --- a/test_regress/t/t_struct_init.v +++ b/test_regress/t/t_struct_init.v @@ -83,31 +83,31 @@ module t; // // Initialization begin - b4_t q = '{1'b1, 1'b1, 1'b0, 1'b0}; + b4_t q; q = '{1'b1, 1'b1, 1'b0, 1'b0}; if (q != 4'b1100) $stop; end begin - b4_t q = '{3{1'b1}, 1'b0}; + b4_t q; q = '{3{1'b1}, 1'b0}; if (q != 4'b1110) $stop; end begin - b4_t q = '{4{1'b1}}; // Repeats the {} + b4_t q; q = '{4{1'b1}}; // Repeats the {} if (q != 4'b1111) $stop; end begin - b4x2_t m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}}; + b4x2_t m; m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}}; if (m != 8'b10011011) $stop; end begin - b4_t q = '{default:1'b1}; + b4_t q; q = '{default:1'b1}; if (q != 4'b1111) $stop; end begin - b4_t q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0}; + b4_t q; q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0}; if (q != 4'b1101) $stop; end begin - b4_t q = '{b2:1'b0, default:1'b1}; + b4_t q; q = '{b2:1'b0, default:1'b1}; if (q != 4'b1011) $stop; end diff --git a/test_regress/t/t_struct_init_bad.pl b/test_regress/t/t_struct_init_bad.pl deleted file mode 100755 index c7da11338..000000000 --- a/test_regress/t/t_struct_init_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_struct_init.v"); - -lint( - v_flags2 => ['+define+T_STRUCT_INIT_BAD'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_init_bad.py b/test_regress/t/t_struct_init_bad.py new file mode 100755 index 000000000..eed2c4efc --- /dev/null +++ b/test_regress/t/t_struct_init_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_struct_init.v" + +test.lint(v_flags2=['+define+T_STRUCT_INIT_BAD'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_init_trace.pl b/test_regress/t/t_struct_init_trace.pl deleted file mode 100755 index 0b6e5073d..000000000 --- a/test_regress/t/t_struct_init_trace.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_struct_init.v"); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_init_trace.py b/test_regress/t/t_struct_init_trace.py new file mode 100755 index 000000000..4ca547717 --- /dev/null +++ b/test_regress/t/t_struct_init_trace.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_struct_init.v" + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_initial_assign.py b/test_regress/t/t_struct_initial_assign.py new file mode 100755 index 000000000..b044cabcd --- /dev/null +++ b/test_regress/t/t_struct_initial_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--timing"]) + +test.execute(fails=test.vlt_all) # Issue #5381 + +test.passes() diff --git a/test_regress/t/t_struct_initial_assign.v b/test_regress/t/t_struct_initial_assign.v new file mode 100644 index 000000000..74f3ecaaf --- /dev/null +++ b/test_regress/t/t_struct_initial_assign.v @@ -0,0 +1,80 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Issue #5381 + +typedef struct packed { + logic field0; + logic field1; +} str_t; + +module t (/*AUTOARG*/ + // Inputs + clk +); + input clk; + + str_t bar_in; + str_t bar_out; + + Sub sub(bar_in, bar_out); + + // Test procedure + initial begin + integer i; + str_t initOut; + + bar_in = '0; // Set bar_in to 0 initially + + // Wait for the first falling edge of the clock + @(negedge clk); + + // Capture the initial output value + initOut = bar_out; + + // Apply stimulus for 10 clock cycles + for (i = 0; i < 10; i = i + 1) begin + if (i > 0) begin + bar_in = '1; // Switch to 1 after the first cycle + end + + @(negedge clk); + + // Check if the output field0 has changed + $display("bar_out.field0 = %h", bar_out.field0); + $display("initOut.field0 = %h", initOut.field0); + if (bar_out.field0 !== initOut.field0) begin + $display("%%Error: bar_out value changed when it should not have"); + $stop; + end + end + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module Sub + ( + input str_t bar_in, + output str_t bar_out + ); + + // This is a continuous assignment + always_comb begin + bar_out.field1 = bar_in.field1; + end + + // This should be an initial assignment, but verilator thinks it's a continous assignment + logic temp0 = bar_in.field0; + // If it is observed (verilator public, coverage, etc.), then it switches correctly to initial + // logic temp0 /* verilator public */ = bar_in.field0; + + always_comb begin + bar_out.field0 = temp0; + end +endmodule diff --git a/test_regress/t/t_struct_initial_assign_public.py b/test_regress/t/t_struct_initial_assign_public.py new file mode 100755 index 000000000..48b2cf60e --- /dev/null +++ b/test_regress/t/t_struct_initial_assign_public.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_struct_initial_assign.v" + +test.compile(verilator_flags2=["--timing", "--public-flat-rw"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_literal_param.py b/test_regress/t/t_struct_literal_param.py new file mode 100755 index 000000000..7e2071c5d --- /dev/null +++ b/test_regress/t/t_struct_literal_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--debug"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_literal_param.v b/test_regress/t/t_struct_literal_param.v new file mode 100644 index 000000000..1e4ff1a2c --- /dev/null +++ b/test_regress/t/t_struct_literal_param.v @@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +package Some_pkg; + typedef struct packed { + int foo; + } some_struct_t; +endpackage + +module sub #( + parameter Some_pkg::some_struct_t the_some_struct +) (); +endmodule + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // finish report + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + sub #( + .the_some_struct( + Some_pkg::some_struct_t'{ + foo: 1 + })) + the_sub (); + +endmodule diff --git a/test_regress/t/t_struct_nest.pl b/test_regress/t/t_struct_nest.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_struct_nest.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_struct_nest.py b/test_regress/t/t_struct_nest.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_struct_nest.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_struct_nest_uarray.pl b/test_regress/t/t_struct_nest_uarray.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_struct_nest_uarray.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_nest_uarray.py b/test_regress/t/t_struct_nest_uarray.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_nest_uarray.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_notfound_bad.pl b/test_regress/t/t_struct_notfound_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_struct_notfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_notfound_bad.py b/test_regress/t/t_struct_notfound_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_struct_notfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_packed_init_bad.out b/test_regress/t/t_struct_packed_init_bad.out index 69e79b04c..19bfd9d0d 100644 --- a/test_regress/t/t_struct_packed_init_bad.out +++ b/test_regress/t/t_struct_packed_init_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_struct_packed_init_bad.v:12:17: Initial values not allowed in packed struct/union (IEEE 1800-2023 7.2.1) +%Error: t/t_struct_packed_init_bad.v:12:17: Initial values not allowed in packed struct/union (IEEE 1800-2023 7.2.2) : ... note: In instance 't' 12 | bit [3:0] m_lo = P; | ^~~~ diff --git a/test_regress/t/t_struct_packed_init_bad.pl b/test_regress/t/t_struct_packed_init_bad.pl deleted file mode 100755 index 35096464e..000000000 --- a/test_regress/t/t_struct_packed_init_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -#execute() - -ok(1); -1; diff --git a/test_regress/t/t_struct_packed_init_bad.py b/test_regress/t/t_struct_packed_init_bad.py new file mode 100755 index 000000000..5be413421 --- /dev/null +++ b/test_regress/t/t_struct_packed_init_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_packed_sysfunct.pl b/test_regress/t/t_struct_packed_sysfunct.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_struct_packed_sysfunct.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_packed_sysfunct.py b/test_regress/t/t_struct_packed_sysfunct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_packed_sysfunct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_packed_value_list.pl b/test_regress/t/t_struct_packed_value_list.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_struct_packed_value_list.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_packed_value_list.py b/test_regress/t/t_struct_packed_value_list.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_packed_value_list.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_packed_write_read.pl b/test_regress/t/t_struct_packed_write_read.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_struct_packed_write_read.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_packed_write_read.py b/test_regress/t/t_struct_packed_write_read.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_packed_write_read.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_param.pl b/test_regress/t/t_struct_param.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_struct_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_param.py b/test_regress/t/t_struct_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_param_overflow.pl b/test_regress/t/t_struct_param_overflow.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_struct_param_overflow.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_param_overflow.py b/test_regress/t/t_struct_param_overflow.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_param_overflow.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_pat.pl b/test_regress/t/t_struct_pat.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_struct_pat.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_pat.py b/test_regress/t/t_struct_pat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_pat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_pat_width.pl b/test_regress/t/t_struct_pat_width.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_struct_pat_width.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_pat_width.py b/test_regress/t/t_struct_pat_width.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_pat_width.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_port.pl b/test_regress/t/t_struct_port.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_struct_port.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_port.py b/test_regress/t/t_struct_port.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_portsel.pl b/test_regress/t/t_struct_portsel.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_struct_portsel.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_portsel.py b/test_regress/t/t_struct_portsel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_portsel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_type_bad.out b/test_regress/t/t_struct_type_bad.out new file mode 100644 index 000000000..0e0aeda51 --- /dev/null +++ b/test_regress/t/t_struct_type_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_struct_type_bad.v:13:7: Expecting a data type: 'i' + 13 | i badi; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_struct_type_bad.py b/test_regress/t/t_struct_type_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_struct_type_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_type_bad.v b/test_regress/t/t_struct_type_bad.v new file mode 100644 index 000000000..8bda6e66d --- /dev/null +++ b/test_regress/t/t_struct_type_bad.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + int i; + + typedef struct packed { + int i; + i badi; // Bad + } struct_t; + +endmodule diff --git a/test_regress/t/t_struct_unaligned.pl b/test_regress/t/t_struct_unaligned.pl deleted file mode 100755 index 624f04e28..000000000 --- a/test_regress/t/t_struct_unaligned.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Note: need to run at a higher optimization level to reproduce the issue -$Self->{benchmark} = 1; - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_unaligned.py b/test_regress/t/t_struct_unaligned.py new file mode 100755 index 000000000..97da89c5f --- /dev/null +++ b/test_regress/t/t_struct_unaligned.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# Note: need to run at a higher optimization level to reproduce the issue +test.benchmark = True + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_unpacked.pl b/test_regress/t/t_struct_unpacked.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_struct_unpacked.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_unpacked.py b/test_regress/t/t_struct_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_unpacked.v b/test_regress/t/t_struct_unpacked.v index ca22982bf..8008016a9 100644 --- a/test_regress/t/t_struct_unpacked.v +++ b/test_regress/t/t_struct_unpacked.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 `define stop $stop -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); class Cls; diff --git a/test_regress/t/t_struct_unpacked_array.pl b/test_regress/t/t_struct_unpacked_array.pl deleted file mode 100755 index eacb5f80e..000000000 --- a/test_regress/t/t_struct_unpacked_array.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2=>["--x-assign unique --x-initial unique -Wno-WIDTH -O0"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_unpacked_array.py b/test_regress/t/t_struct_unpacked_array.py new file mode 100755 index 000000000..1d39072e8 --- /dev/null +++ b/test_regress/t/t_struct_unpacked_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-assign unique --x-initial unique -Wno-WIDTH -O0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_unpacked_clean.pl b/test_regress/t/t_struct_unpacked_clean.pl deleted file mode 100755 index eacb5f80e..000000000 --- a/test_regress/t/t_struct_unpacked_clean.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2=>["--x-assign unique --x-initial unique -Wno-WIDTH -O0"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_unpacked_clean.py b/test_regress/t/t_struct_unpacked_clean.py new file mode 100755 index 000000000..1d39072e8 --- /dev/null +++ b/test_regress/t/t_struct_unpacked_clean.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-assign unique --x-initial unique -Wno-WIDTH -O0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_unpacked_init.pl b/test_regress/t/t_struct_unpacked_init.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_struct_unpacked_init.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_unpacked_init.py b/test_regress/t/t_struct_unpacked_init.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_struct_unpacked_init.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_unused.pl b/test_regress/t/t_struct_unused.pl deleted file mode 100755 index efbd21e12..000000000 --- a/test_regress/t/t_struct_unused.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# Use --debug-protect to assist debug - -compile( - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - # Check for unused structs in any outputs - my $any; - foreach my $filename (glob $Self->{obj_dir} . "/*.[ch]*") { - file_grep_not($filename, qr/useless/i); - $any = 1; - } - $any or $Self->error("No outputs found"); -} - -ok(1); -1; diff --git a/test_regress/t/t_struct_unused.py b/test_regress/t/t_struct_unused.py new file mode 100755 index 000000000..143e17cb5 --- /dev/null +++ b/test_regress/t/t_struct_unused.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +# Use --debug-protect to assist debug + +test.compile() + +test.execute() + +if test.vlt_all: + # Check for unused structs in any outputs + for filename in test.glob_some(test.obj_dir + "/*.[ch]*"): + test.file_grep_not(filename, r'useless') + +test.passes() diff --git a/test_regress/t/t_structu_dataType_assignment.pl b/test_regress/t/t_structu_dataType_assignment.pl deleted file mode 100755 index 45d42e7f6..000000000 --- a/test_regress/t/t_structu_dataType_assignment.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--structs-packed'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_structu_dataType_assignment.py b/test_regress/t/t_structu_dataType_assignment.py new file mode 100755 index 000000000..d80083531 --- /dev/null +++ b/test_regress/t/t_structu_dataType_assignment.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--structs-packed']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_structu_dataType_assignment_bad.pl b/test_regress/t/t_structu_dataType_assignment_bad.pl deleted file mode 100755 index d593ee907..000000000 --- a/test_regress/t/t_structu_dataType_assignment_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ['--structs-packed'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_structu_dataType_assignment_bad.py b/test_regress/t/t_structu_dataType_assignment_bad.py new file mode 100755 index 000000000..a5aa131e7 --- /dev/null +++ b/test_regress/t/t_structu_dataType_assignment_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=['--structs-packed'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_structu_wide.pl b/test_regress/t/t_structu_wide.pl deleted file mode 100755 index e039728bc..000000000 --- a/test_regress/t/t_structu_wide.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => [ '-DWIDE_WIDTH=128' ], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_structu_wide.py b/test_regress/t/t_structu_wide.py new file mode 100755 index 000000000..b1fdec1e8 --- /dev/null +++ b/test_regress/t/t_structu_wide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-DWIDE_WIDTH=128']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_suspendable_deep.pl b/test_regress/t/t_suspendable_deep.pl deleted file mode 100755 index 3b4f977f4..000000000 --- a/test_regress/t/t_suspendable_deep.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_suspendable_deep.py b/test_regress/t/t_suspendable_deep.py new file mode 100755 index 000000000..6e837dc78 --- /dev/null +++ b/test_regress/t/t_suspendable_deep.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.passes() diff --git a/test_regress/t/t_sv_bus_mux_demux.pl b/test_regress/t/t_sv_bus_mux_demux.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_sv_bus_mux_demux.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sv_bus_mux_demux.py b/test_regress/t/t_sv_bus_mux_demux.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sv_bus_mux_demux.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sv_conditional.pl b/test_regress/t/t_sv_conditional.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_sv_conditional.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sv_conditional.py b/test_regress/t/t_sv_conditional.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sv_conditional.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sv_cpu.pl b/test_regress/t/t_sv_cpu.pl deleted file mode 100755 index 5bc4f46a7..000000000 --- a/test_regress/t/t_sv_cpu.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett, -# Embecosm. - -compile( - # Taken from the original VCS command line. - v_flags2 => ["t/t_sv_cpu_code/timescale.sv", - "t/t_sv_cpu_code/program_h.sv", - "t/t_sv_cpu_code/pads_h.sv", - "t/t_sv_cpu_code/ports_h.sv", - "t/t_sv_cpu_code/pinout_h.sv", - "t/t_sv_cpu_code/genbus_if.sv", - "t/t_sv_cpu_code/pads_if.sv", - "t/t_sv_cpu_code/adrdec.sv", - "t/t_sv_cpu_code/pad_gpio.sv", - "t/t_sv_cpu_code/pad_vdd.sv", - "t/t_sv_cpu_code/pad_gnd.sv", - "t/t_sv_cpu_code/pads.sv", - "t/t_sv_cpu_code/ports.sv", - "t/t_sv_cpu_code/ac_dig.sv", - "t/t_sv_cpu_code/ac_ana.sv", - "t/t_sv_cpu_code/ac.sv", - "t/t_sv_cpu_code/cpu.sv", - "t/t_sv_cpu_code/chip.sv"], - vcs_flags2 => ["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"], - verilator_flags2 => ["-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t", - "--timescale-override 1ns/1ps"], - iv_flags2 => ["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sv_cpu.py b/test_regress/t/t_sv_cpu.py new file mode 100755 index 000000000..84a49ebb7 --- /dev/null +++ b/test_regress/t/t_sv_cpu.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett, +# Embecosm. + +test.compile( + # Taken from the original VCS command line. + v_flags2=[ + "t/t_sv_cpu_code/timescale.sv", "t/t_sv_cpu_code/program_h.sv", + "t/t_sv_cpu_code/pads_h.sv", "t/t_sv_cpu_code/ports_h.sv", "t/t_sv_cpu_code/pinout_h.sv", + "t/t_sv_cpu_code/genbus_if.sv", "t/t_sv_cpu_code/pads_if.sv", "t/t_sv_cpu_code/adrdec.sv", + "t/t_sv_cpu_code/pad_gpio.sv", "t/t_sv_cpu_code/pad_vdd.sv", "t/t_sv_cpu_code/pad_gnd.sv", + "t/t_sv_cpu_code/pads.sv", "t/t_sv_cpu_code/ports.sv", "t/t_sv_cpu_code/ac_dig.sv", + "t/t_sv_cpu_code/ac_ana.sv", "t/t_sv_cpu_code/ac.sv", "t/t_sv_cpu_code/cpu.sv", + "t/t_sv_cpu_code/chip.sv" + ], + vcs_flags2=["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"], + verilator_flags2=[ + "-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t", + "--timescale-override 1ns/1ps" + ], + iv_flags2=["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_delta_monitor.pl b/test_regress/t/t_sys_delta_monitor.pl deleted file mode 100755 index 0e34f196f..000000000 --- a/test_regress/t/t_sys_delta_monitor.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing --timescale 1ns/1ns"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_sys_delta_monitor.py b/test_regress/t/t_sys_delta_monitor.py new file mode 100755 index 000000000..f9e3a2b05 --- /dev/null +++ b/test_regress/t/t_sys_delta_monitor.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing --timescale 1ns/1ns"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_delta_monitor.v b/test_regress/t/t_sys_delta_monitor.v index 7cccf594c..69ef3982f 100644 --- a/test_regress/t/t_sys_delta_monitor.v +++ b/test_regress/t/t_sys_delta_monitor.v @@ -4,21 +4,21 @@ // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); -logic [31:0] tmp; -logic [31:0] tmp2; -logic [31:0] tmp3; -initial begin - tmp = 0; - $monitor("[%0t] monitor0 %h", $time, tmp); - while (tmp < 32) begin - tmp = tmp + 1; - if ((tmp % 5) == 1) begin + logic [31:0] tmp; + logic [31:0] tmp2; + logic [31:0] tmp3; + initial begin + tmp = 0; + $monitor("[%0t] monitor0 %h", $time, tmp); + while (tmp < 32) begin + tmp = tmp + 1; + if ((tmp % 5) == 1) begin tmp = tmp + 2; tmp = tmp + 1; - end - #1; - end - $write("*-* All Finished *-*\n"); - $finish(); -end + end + #1; + end + $write("*-* All Finished *-*\n"); + $finish(); + end endmodule diff --git a/test_regress/t/t_sys_file_autoflush.pl b/test_regress/t/t_sys_file_autoflush.pl deleted file mode 100755 index 058d7b858..000000000 --- a/test_regress/t/t_sys_file_autoflush.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_sys_file_basic.v"); - -compile( - v_flags2 => ['+incdir+../include', - '+define+AUTOFLUSH'], - verilator_flags2 => ['--autoflush'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_autoflush.py b/test_regress/t/t_sys_file_autoflush.py new file mode 100755 index 000000000..c753bd0e8 --- /dev/null +++ b/test_regress/t/t_sys_file_autoflush.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_sys_file_basic.v" + +test.compile(v_flags2=['+incdir+../include', '+define+AUTOFLUSH'], + verilator_flags2=['--autoflush']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_file_basic.pl b/test_regress/t/t_sys_file_basic.pl deleted file mode 100755 index fe1cedbce..000000000 --- a/test_regress/t/t_sys_file_basic.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -unlink("$Self->{obj_dir}/t_sys_file_basic_test.log"); - -compile( - # Build without cached objects, see bug363 - make_flags => 'VM_PARALLEL_BUILDS=0', - ); - -execute( - check_finished => 1, - ); - -files_identical("$Self->{obj_dir}/t_sys_file_basic_test.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_basic.py b/test_regress/t/t_sys_file_basic.py new file mode 100755 index 000000000..d36d66d7c --- /dev/null +++ b/test_regress/t/t_sys_file_basic.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.unlink_ok(test.obj_dir + "/t_sys_file_basic_test.log") + +test.compile( + # Build without cached objects, see bug363 + make_flags=['VM_PARALLEL_BUILDS=0']) + +test.execute() +test.files_identical(test.obj_dir + "/t_sys_file_basic_test.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_file_basic.v b/test_regress/t/t_sys_file_basic.v index bdd84128d..762c765d9 100644 --- a/test_regress/t/t_sys_file_basic.v +++ b/test_regress/t/t_sys_file_basic.v @@ -9,7 +9,7 @@ `define stop $stop `define checkr(gotv,expv) do if (`ratio_error((gotv),(expv))>0.0001) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; integer file; diff --git a/test_regress/t/t_sys_file_basic_mcd.pl b/test_regress/t/t_sys_file_basic_mcd.pl deleted file mode 100755 index e77ffbc08..000000000 --- a/test_regress/t/t_sys_file_basic_mcd.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -unlink("$Self->{obj_dir}/t_sys_file_basic_mcd.log"); - -compile(); -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -files_identical("$Self->{obj_dir}/t_sys_file_basic_mcd_test2_0.dat", - "$Self->{t_dir}/t_sys_file_basic_mcd_test2_0.dat"); -files_identical("$Self->{obj_dir}/t_sys_file_basic_mcd_test2_1.dat", - "$Self->{t_dir}/t_sys_file_basic_mcd_test2_1.dat"); -files_identical("$Self->{obj_dir}/t_sys_file_basic_mcd_test2_2.dat", - "$Self->{t_dir}/t_sys_file_basic_mcd_test2_2.dat"); -files_identical("$Self->{obj_dir}/t_sys_file_basic_mcd_test5.dat", - "$Self->{t_dir}/t_sys_file_basic_mcd_test5.dat"); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_basic_mcd.py b/test_regress/t/t_sys_file_basic_mcd.py new file mode 100755 index 000000000..307f60dff --- /dev/null +++ b/test_regress/t/t_sys_file_basic_mcd.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.unlink_ok(test.obj_dir + "/t_sys_file_basic_mcd.log") + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_0.dat", + test.t_dir + "/t_sys_file_basic_mcd_test2_0.dat") +test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_1.dat", + test.t_dir + "/t_sys_file_basic_mcd_test2_1.dat") +test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_2.dat", + test.t_dir + "/t_sys_file_basic_mcd_test2_2.dat") +test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test5.dat", + test.t_dir + "/t_sys_file_basic_mcd_test5.dat") + +test.passes() diff --git a/test_regress/t/t_sys_file_basic_uz.pl b/test_regress/t/t_sys_file_basic_uz.pl deleted file mode 100755 index e2be86bfc..000000000 --- a/test_regress/t/t_sys_file_basic_uz.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -unlink("$Self->{obj_dir}/t_sys_file_basic_uz_test.log"); - -compile(); - -execute( - check_finished => 1, - ); - -files_identical("$Self->{obj_dir}/t_sys_file_basic_uz_test.log", $Self->{golden_filename}); - -files_identical("$Self->{obj_dir}/t_sys_file_basic_uz_test.bin", - "$Self->{t_dir}/t_sys_file_basic_uz.dat"); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_basic_uz.py b/test_regress/t/t_sys_file_basic_uz.py new file mode 100755 index 000000000..8afc2b9d3 --- /dev/null +++ b/test_regress/t/t_sys_file_basic_uz.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.unlink_ok(test.obj_dir + "/t_sys_file_basic_uz_test.log") + +test.compile() + +test.execute() + +test.files_identical(test.obj_dir + "/t_sys_file_basic_uz_test.log", test.golden_filename) +test.files_identical(test.obj_dir + "/t_sys_file_basic_uz_test.bin", + test.t_dir + "/t_sys_file_basic_uz.dat") + +test.passes() diff --git a/test_regress/t/t_sys_file_eof.pl b/test_regress/t/t_sys_file_eof.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_sys_file_eof.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_eof.py b/test_regress/t/t_sys_file_eof.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_file_eof.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_file_null.pl b/test_regress/t/t_sys_file_null.pl deleted file mode 100755 index 8c1cc9e96..000000000 --- a/test_regress/t/t_sys_file_null.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -my $fn = "$Self->{obj_dir}/zeros.log"; -if (-s $fn != 16) { - $Self->error("$fn: Wrong file size"); -} - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_null.py b/test_regress/t/t_sys_file_null.py new file mode 100755 index 000000000..29e82f03c --- /dev/null +++ b/test_regress/t/t_sys_file_null.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +filename = test.obj_dir + "/zeros.log" +if os.path.getsize(filename) != 16: + test.error(filename + ": Wrong file size") + +test.passes() diff --git a/test_regress/t/t_sys_file_scan.pl b/test_regress/t/t_sys_file_scan.pl deleted file mode 100755 index 7169fcdde..000000000 --- a/test_regress/t/t_sys_file_scan.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -unlink("$Self->{obj_dir}/t_sys_file_scan_test.log"); - -compile( - ); - -execute( - check_finished => 1, - ); - -file_grep("$Self->{obj_dir}/t_sys_file_scan_test.log", -"# a - 1 -"); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_scan.py b/test_regress/t/t_sys_file_scan.py new file mode 100755 index 000000000..3f737df94 --- /dev/null +++ b/test_regress/t/t_sys_file_scan.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.unlink_ok(test.obj_dir + "/t_sys_file_scan_test.log") + +test.compile() + +test.execute() + +test.file_grep(test.obj_dir + "/t_sys_file_scan_test.log", r"""# a + 1 +""") + +test.passes() diff --git a/test_regress/t/t_sys_file_zero.pl b/test_regress/t/t_sys_file_zero.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_sys_file_zero.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_zero.py b/test_regress/t/t_sys_file_zero.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_file_zero.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_fmonitor.pl b/test_regress/t/t_sys_fmonitor.pl deleted file mode 100755 index 6bbedacab..000000000 --- a/test_regress/t/t_sys_fmonitor.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -files_identical("$Self->{obj_dir}/open.log", $Self->{golden_filename}); - -ok(1); - -1; diff --git a/test_regress/t/t_sys_fmonitor.py b/test_regress/t/t_sys_fmonitor.py new file mode 100755 index 000000000..8ec472516 --- /dev/null +++ b/test_regress/t/t_sys_fmonitor.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() +test.files_identical(test.obj_dir + "/open.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_fopen_bad.pl b/test_regress/t/t_sys_fopen_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_sys_fopen_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_fopen_bad.py b/test_regress/t/t_sys_fopen_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_sys_fopen_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_fread.pl b/test_regress/t/t_sys_fread.pl deleted file mode 100755 index 73bebd44f..000000000 --- a/test_regress/t/t_sys_fread.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; -#use Data::Dumper; -use strict; -use vars qw($Self); - -scenarios(simulator => 1); - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - for (my $copy = 0; $copy < 32; ++$copy) { - for (my $i = 0; $i <= 255; ++$i) { - $fh->print(chr($i)); - } - } -} - -gen("$Self->{obj_dir}/t_sys_fread.mem"); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_fread.py b/test_regress/t/t_sys_fread.py new file mode 100755 index 000000000..29f0832f0 --- /dev/null +++ b/test_regress/t/t_sys_fread.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + + +def gen(filename): + with open(filename, 'w', encoding="latin-1") as fh: + for copy in range(0, 32): # pylint: disable=unused-variable + for i in range(0, 256): + fh.write(chr(i)) + + +gen(test.obj_dir + "/t_sys_fread.mem") + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_fscanf_bad.pl b/test_regress/t/t_sys_fscanf_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_sys_fscanf_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_fscanf_bad.py b/test_regress/t/t_sys_fscanf_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_sys_fscanf_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_fstrobe.pl b/test_regress/t/t_sys_fstrobe.pl deleted file mode 100755 index 55224d3d6..000000000 --- a/test_regress/t/t_sys_fstrobe.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); # Not vltmt due to possible race - -compile( - ); - -execute( - check_finished => 1, - ); - -files_identical("$Self->{obj_dir}/open.log", $Self->{golden_filename}); - -ok(1); - -1; diff --git a/test_regress/t/t_sys_fstrobe.py b/test_regress/t/t_sys_fstrobe.py new file mode 100755 index 000000000..63d3560f9 --- /dev/null +++ b/test_regress/t/t_sys_fstrobe.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') # Not vltmt due to possible race + +test.compile() + +test.execute() + +test.files_identical(test.obj_dir + "/open.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_monitor.pl b/test_regress/t/t_sys_monitor.pl deleted file mode 100755 index 88b7809fc..000000000 --- a/test_regress/t/t_sys_monitor.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_sys_monitor.py b/test_regress/t/t_sys_monitor.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_sys_monitor.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_monitor.v b/test_regress/t/t_sys_monitor.v index 57e8d6c28..a1619464a 100644 --- a/test_regress/t/t_sys_monitor.v +++ b/test_regress/t/t_sys_monitor.v @@ -38,7 +38,7 @@ module t(/*AUTOARG*/ $monitoron; end else if (cyc == 30) begin - $monitoroff; // To avoid inconsistent output between --vlt and --vltmt + $monitoroff; // To avoid inconsistent output between --vlt and --vltmt $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_sys_plusargs.pl b/test_regress/t/t_sys_plusargs.pl deleted file mode 100755 index 362a0c53c..000000000 --- a/test_regress/t/t_sys_plusargs.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['-v', 't/t_flag_libinc.v'], - ); - -execute( - check_finished => 1, - all_run_flags => ['+PLUS +INT=1234 +STRSTR +REAL=1.2345 +IP%P101'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_plusargs.py b/test_regress/t/t_sys_plusargs.py new file mode 100755 index 000000000..51529220e --- /dev/null +++ b/test_regress/t/t_sys_plusargs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['-v', 't/t_flag_libinc.v']) + +test.execute(all_run_flags=['+PLUS +INT=1234 +STRSTR +REAL=1.2345 +IP%P101']) + +test.passes() diff --git a/test_regress/t/t_sys_plusargs_bad.pl b/test_regress/t/t_sys_plusargs_bad.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_sys_plusargs_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_plusargs_bad.py b/test_regress/t/t_sys_plusargs_bad.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_plusargs_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_psprintf.pl b/test_regress/t/t_sys_psprintf.pl deleted file mode 100755 index 2287e034e..000000000 --- a/test_regress/t/t_sys_psprintf.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wno-NONSTD'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_psprintf.py b/test_regress/t/t_sys_psprintf.py new file mode 100755 index 000000000..45836a507 --- /dev/null +++ b/test_regress/t/t_sys_psprintf.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wno-NONSTD']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_psprintf_warn_bad.pl b/test_regress/t/t_sys_psprintf_warn_bad.pl deleted file mode 100755 index 903983f53..000000000 --- a/test_regress/t/t_sys_psprintf_warn_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_sys_psprintf.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_psprintf_warn_bad.py b/test_regress/t/t_sys_psprintf_warn_bad.py new file mode 100755 index 000000000..092329b04 --- /dev/null +++ b/test_regress/t/t_sys_psprintf_warn_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_sys_psprintf.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_rand.pl b/test_regress/t/t_sys_rand.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_sys_rand.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_rand.py b/test_regress/t/t_sys_rand.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_rand.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_rand_concat.pl b/test_regress/t/t_sys_rand_concat.pl deleted file mode 100755 index 9c5d99e16..000000000 --- a/test_regress/t/t_sys_rand_concat.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root__DepSet*__Slow.cpp")) { - file_grep_not($file, qr/(<<|>>)/x); -} - -ok(1); -1; diff --git a/test_regress/t/t_sys_rand_concat.py b/test_regress/t/t_sys_rand_concat.py new file mode 100755 index 000000000..48dfd22b5 --- /dev/null +++ b/test_regress/t/t_sys_rand_concat.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + + "___024root__DepSet*__Slow.cpp"): + test.file_grep_not(filename, r'(<<|>>)') + +test.passes() diff --git a/test_regress/t/t_sys_rand_seed.pl b/test_regress/t/t_sys_rand_seed.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_sys_rand_seed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_rand_seed.py b/test_regress/t/t_sys_rand_seed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_rand_seed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_readmem.pl b/test_regress/t/t_sys_readmem.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_sys_readmem.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem.py b/test_regress/t/t_sys_readmem.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_readmem.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_readmem_4state.pl b/test_regress/t/t_sys_readmem_4state.pl deleted file mode 100755 index d82700967..000000000 --- a/test_regress/t/t_sys_readmem_4state.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--x-initial unique"], - ); - -execute( - all_run_flags => ["+verilator+rand+reset+1"], - check_finished => 1, - ); - -files_identical("$Self->{obj_dir}/t_sys_readmem_4state_b.mem", "t/t_sys_readmem_4state_b.out"); -files_identical("$Self->{obj_dir}/t_sys_readmem_4state_h.mem", "t/t_sys_readmem_4state_h.out"); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_4state.py b/test_regress/t/t_sys_readmem_4state.py new file mode 100755 index 000000000..3995ab993 --- /dev/null +++ b/test_regress/t/t_sys_readmem_4state.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-initial unique"]) + +test.execute(all_run_flags=["+verilator+rand+reset+1"]) + +test.files_identical(test.obj_dir + "/t_sys_readmem_4state_b.mem", "t/t_sys_readmem_4state_b.out") +test.files_identical(test.obj_dir + "/t_sys_readmem_4state_h.mem", "t/t_sys_readmem_4state_h.out") + +test.passes() diff --git a/test_regress/t/t_sys_readmem_assoc.pl b/test_regress/t/t_sys_readmem_assoc.pl deleted file mode 100755 index 493cedf7e..000000000 --- a/test_regress/t/t_sys_readmem_assoc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -files_identical("$Self->{obj_dir}/t_sys_writemem_c_b.mem", "t/t_sys_readmem_assoc_c_b.out"); -files_identical("$Self->{obj_dir}/t_sys_writemem_w_h.mem", "t/t_sys_readmem_assoc_w_h.out"); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_assoc.py b/test_regress/t/t_sys_readmem_assoc.py new file mode 100755 index 000000000..78cda062b --- /dev/null +++ b/test_regress/t/t_sys_readmem_assoc.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.files_identical(test.obj_dir + "/t_sys_writemem_c_b.mem", "t/t_sys_readmem_assoc_c_b.out") +test.files_identical(test.obj_dir + "/t_sys_writemem_w_h.mem", "t/t_sys_readmem_assoc_w_h.out") + +test.passes() diff --git a/test_regress/t/t_sys_readmem_assoc_bad.pl b/test_regress/t/t_sys_readmem_assoc_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_sys_readmem_assoc_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_assoc_bad.py b/test_regress/t/t_sys_readmem_assoc_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_sys_readmem_assoc_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_bad_addr.pl b/test_regress/t/t_sys_readmem_bad_addr.pl deleted file mode 100755 index d89f1290d..000000000 --- a/test_regress/t/t_sys_readmem_bad_addr.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_bad_addr.py b/test_regress/t/t_sys_readmem_bad_addr.py new file mode 100755 index 000000000..be2efa43f --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_addr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_bad_addr2.pl b/test_regress/t/t_sys_readmem_bad_addr2.pl deleted file mode 100755 index 0530bf7e8..000000000 --- a/test_regress/t/t_sys_readmem_bad_addr2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_bad_addr2.py b/test_regress/t/t_sys_readmem_bad_addr2.py new file mode 100755 index 000000000..be2efa43f --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_addr2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_bad_digit.pl b/test_regress/t/t_sys_readmem_bad_digit.pl deleted file mode 100755 index d89f1290d..000000000 --- a/test_regress/t/t_sys_readmem_bad_digit.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_bad_digit.py b/test_regress/t/t_sys_readmem_bad_digit.py new file mode 100755 index 000000000..be2efa43f --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_digit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_bad_end.pl b/test_regress/t/t_sys_readmem_bad_end.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_sys_readmem_bad_end.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_bad_end.py b/test_regress/t/t_sys_readmem_bad_end.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_end.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_bad_notfound.pl b/test_regress/t/t_sys_readmem_bad_notfound.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_sys_readmem_bad_notfound.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_bad_notfound.py b/test_regress/t/t_sys_readmem_bad_notfound.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_notfound.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_eof.pl b/test_regress/t/t_sys_readmem_eof.pl deleted file mode 100755 index 83e6e124b..000000000 --- a/test_regress/t/t_sys_readmem_eof.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -sub gen { - # Generate using file to avoid missing newline in repository - my $filename = shift; - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_vthread.pl\n"); - $fh->print("1\n"); - $fh->print("10\n"); - $fh->print("20\n"); - $fh->print("30"); # No newline -} - -gen($Self->{obj_dir} . "/dat.mem"); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_eof.py b/test_regress/t/t_sys_readmem_eof.py new file mode 100755 index 000000000..a34d539d0 --- /dev/null +++ b/test_regress/t/t_sys_readmem_eof.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + + +def gen(filename): + # Generate using file to avoid missing newline in repository + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_vthread.py\n") + fh.write("1\n") + fh.write("10\n") + fh.write("20\n") + fh.write("30") + # No newline + + +gen(test.obj_dir + "/dat.mem") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_sformat.pl b/test_regress/t/t_sys_sformat.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_sys_sformat.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_sformat.py b/test_regress/t/t_sys_sformat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_sformat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_sformat_noopt.pl b/test_regress/t/t_sys_sformat_noopt.pl deleted file mode 100755 index 569209da9..000000000 --- a/test_regress/t/t_sys_sformat_noopt.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_sys_sformat.v"); - -compile( - # Avoid inlining our simple example, to make sure verilated.h works right - verilator_flags2 => ["-O0"], - ); - -if ($Self->cxx_version =~ /clang/) { - skip("Known clang bug"); - #Here: if (VL_UNLIKELY(VL_NEQ_W(12, __Vtemp1, vlSymsp->TOP__t.__PVT__str))) -} else { - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_sys_sformat_noopt.py b/test_regress/t/t_sys_sformat_noopt.py new file mode 100755 index 000000000..ad41c3d45 --- /dev/null +++ b/test_regress/t/t_sys_sformat_noopt.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_sys_sformat.v" + +test.compile( + # Avoid inlining our simple example, to make sure verilated.h works right + verilator_flags2=["-O0"]) + +if re.search(r'clang', test.cxx_version): + test.skip("Known clang bug") + #Here: if (VL_UNLIKELY(VL_NEQ_W(12, __Vtemp1, vlSymsp->TOP__t.__PVT__str))) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_strobe.pl b/test_regress/t/t_sys_strobe.pl deleted file mode 100755 index 88b7809fc..000000000 --- a/test_regress/t/t_sys_strobe.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_sys_strobe.py b/test_regress/t/t_sys_strobe.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_sys_strobe.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_system.pl b/test_regress/t/t_sys_system.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_sys_system.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_system.py b/test_regress/t/t_sys_system.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_system.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_time.pl b/test_regress/t/t_sys_time.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_sys_time.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_time.py b/test_regress/t/t_sys_time.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_time.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_writemem.pl b/test_regress/t/t_sys_writemem.pl deleted file mode 100755 index d06bb642f..000000000 --- a/test_regress/t/t_sys_writemem.pl +++ /dev/null @@ -1,44 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_sys_readmem.v"); - -# Use random reset to ensure we're fully initializing arrays before -# $writememh, to avoid miscompares with X's on 4-state simulators. -$Self->{verilated_randReset} = 2; # 2 == truly random - -# TODO make test more generic to take the data type as a define -# then we can call test multiple times in different tests -compile(v_flags2 => [ - "+define+WRITEMEM_READ_BACK=1", - "+define+OUT_TMP1=\\\"$Self->{obj_dir}/tmp1.mem\\\"", - "+define+OUT_TMP2=\\\"$Self->{obj_dir}/tmp2.mem\\\"", - "+define+OUT_TMP3=\\\"$Self->{obj_dir}/tmp3.mem\\\"", - "+define+OUT_TMP4=\\\"$Self->{obj_dir}/tmp4.mem\\\"", - "+define+OUT_TMP5=\\\"$Self->{obj_dir}/tmp5.mem\\\"", - "+define+OUT_TMP6=\\\"$Self->{obj_dir}/tmp6.mem\\\"", - "+define+OUT_TMP7=\\\"$Self->{obj_dir}/tmp7.mem\\\"", - "+define+OUT_TMP8=\\\"$Self->{obj_dir}/tmp8.mem\\\"", - ]); - -execute( - check_finished => 1, - ); - -for (my $i = 1; $i <= 8; $i++) { - my $gold = "$Self->{t_dir}/t_sys_writemem.gold${i}.mem"; - my $out = "$Self->{obj_dir}/tmp${i}.mem"; - files_identical($out, $gold); -} - -ok(1); -1; diff --git a/test_regress/t/t_sys_writemem.py b/test_regress/t/t_sys_writemem.py new file mode 100755 index 000000000..27786c641 --- /dev/null +++ b/test_regress/t/t_sys_writemem.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_sys_readmem.v" + +# Use random reset to ensure we're fully initializing arrays before +# $writememh, to avoid miscompares with X's on 4-state simulators. +test.verilated_randReset = 2 # 2 == truly random + +# TODO make test more generic to take the data type as a define +# then we can call test multiple times in different tests +test.compile(v_flags2=[ + '+define+WRITEMEM_READ_BACK=1', + '\'+define+OUT_TMP1=\"' + test.obj_dir + '/tmp1.mem\"\'', + '\'+define+OUT_TMP2=\"' + test.obj_dir + '/tmp2.mem\"\'', + '\'+define+OUT_TMP3=\"' + test.obj_dir + '/tmp3.mem\"\'', + '\'+define+OUT_TMP4=\"' + test.obj_dir + '/tmp4.mem\"\'', + '\'+define+OUT_TMP5=\"' + test.obj_dir + '/tmp5.mem\"\'', + '\'+define+OUT_TMP6=\"' + test.obj_dir + '/tmp6.mem\"\'', + '\'+define+OUT_TMP7=\"' + test.obj_dir + '/tmp7.mem\"\'', + '\'+define+OUT_TMP8=\"' + test.obj_dir + '/tmp8.mem\"\'', +]) + +test.execute() + +for i in range(1, 9): + gold = test.t_dir + "/t_sys_writemem.gold" + str(i) + ".mem" + out = test.obj_dir + "/tmp" + str(i) + ".mem" + test.files_identical(out, gold) + +test.passes() diff --git a/test_regress/t/t_sys_writemem_b.pl b/test_regress/t/t_sys_writemem_b.pl deleted file mode 100755 index 140904bcb..000000000 --- a/test_regress/t/t_sys_writemem_b.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_sys_readmem.v"); - -# Use random reset to ensure we're fully initializing arrays before -# $writememh, to avoid miscompares with X's on 4-state simulators. -$Self->{verilated_randReset} = 2; # 2 == truly random - -compile(v_flags2 => [ - "+define+WRITEMEM_READ_BACK=1", - "+define+WRITEMEM_BIN=1", - "+define+OUT_TMP1=\\\"$Self->{obj_dir}/tmp1.mem\\\"", - "+define+OUT_TMP2=\\\"$Self->{obj_dir}/tmp2.mem\\\"", - "+define+OUT_TMP3=\\\"$Self->{obj_dir}/tmp3.mem\\\"", - "+define+OUT_TMP4=\\\"$Self->{obj_dir}/tmp4.mem\\\"", - "+define+OUT_TMP5=\\\"$Self->{obj_dir}/tmp5.mem\\\"", - "+define+OUT_TMP6=\\\"$Self->{obj_dir}/tmp6.mem\\\"", - "+define+OUT_TMP7=\\\"$Self->{obj_dir}/tmp7.mem\\\"", - "+define+OUT_TMP8=\\\"$Self->{obj_dir}/tmp8.mem\\\"", - ]); - -execute( - check_finished => 1, - ); - -for (my $i = 1; $i <= 8; $i++) { - my $gold = "$Self->{t_dir}/t_sys_writemem_b.gold${i}.mem"; - my $out = "$Self->{obj_dir}/tmp${i}.mem"; - files_identical($out, $gold); -} - -ok(1); -1; diff --git a/test_regress/t/t_sys_writemem_b.py b/test_regress/t/t_sys_writemem_b.py new file mode 100755 index 000000000..902f273e2 --- /dev/null +++ b/test_regress/t/t_sys_writemem_b.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_sys_readmem.v" + +# Use random reset to ensure we're fully initializing arrays before +# $writememh, to avoid miscompares with X's on 4-state simulators. +test.verilated_randReset = 2 # 2 == truly random + +test.compile(v_flags2=[ + "+define+WRITEMEM_READ_BACK=1", + "+define+WRITEMEM_BIN=1", + '+define+WRITEMEM_READ_BACK=1', + '\'+define+OUT_TMP1=\"' + test.obj_dir + '/tmp1.mem\"\'', + '\'+define+OUT_TMP2=\"' + test.obj_dir + '/tmp2.mem\"\'', + '\'+define+OUT_TMP3=\"' + test.obj_dir + '/tmp3.mem\"\'', + '\'+define+OUT_TMP4=\"' + test.obj_dir + '/tmp4.mem\"\'', + '\'+define+OUT_TMP5=\"' + test.obj_dir + '/tmp5.mem\"\'', + '\'+define+OUT_TMP6=\"' + test.obj_dir + '/tmp6.mem\"\'', + '\'+define+OUT_TMP7=\"' + test.obj_dir + '/tmp7.mem\"\'', + '\'+define+OUT_TMP8=\"' + test.obj_dir + '/tmp8.mem\"\'', +]) + +test.execute() + +for i in range(1, 9): + gold = test.t_dir + "/t_sys_writemem_b.gold" + str(i) + ".mem" + out = test.obj_dir + "/tmp" + str(i) + ".mem" + test.files_identical(out, gold) + +test.passes() diff --git a/test_regress/t/t_table_fsm.pl b/test_regress/t/t_table_fsm.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_table_fsm.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_table_fsm.py b/test_regress/t/t_table_fsm.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_table_fsm.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tagged.pl b/test_regress/t/t_tagged.pl deleted file mode 100755 index 877e6133a..000000000 --- a/test_regress/t/t_tagged.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tagged.py b/test_regress/t/t_tagged.py new file mode 100755 index 000000000..710a094ab --- /dev/null +++ b/test_regress/t/t_tagged.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_threads_counter_0.pl b/test_regress/t/t_threads_counter_0.pl deleted file mode 100755 index 6c3744eeb..000000000 --- a/test_regress/t/t_threads_counter_0.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_threads_counter.v"); - -compile( - verilator_flags2 => ['--cc'], - threads => 1, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_threads_counter_0.py b/test_regress/t/t_threads_counter_0.py new file mode 100755 index 000000000..0dfdcdbb2 --- /dev/null +++ b/test_regress/t/t_threads_counter_0.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_threads_counter.v" + +test.compile(verilator_flags2=['--cc'], threads=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_threads_counter_1.pl b/test_regress/t/t_threads_counter_1.pl deleted file mode 100755 index 95a607bfd..000000000 --- a/test_regress/t/t_threads_counter_1.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_threads_counter.v"); - -compile( - verilator_flags2 => ['--cc'], - threads => 1 - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_threads_counter_1.py b/test_regress/t/t_threads_counter_1.py new file mode 100755 index 000000000..7cbd7389e --- /dev/null +++ b/test_regress/t/t_threads_counter_1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_threads_counter.v" + +test.compile(verilator_flags2=['--cc'], threads=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_threads_counter_2.pl b/test_regress/t/t_threads_counter_2.pl deleted file mode 100755 index 3625322fe..000000000 --- a/test_regress/t/t_threads_counter_2.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_threads_counter.v"); - -compile( - verilator_flags2 => ['--cc'], - threads => 2 - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_threads_counter_2.py b/test_regress/t/t_threads_counter_2.py new file mode 100755 index 000000000..d4ab7e2ba --- /dev/null +++ b/test_regress/t/t_threads_counter_2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_threads_counter.v" + +test.compile(verilator_flags2=['--cc'], threads=2) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_threads_counter_4.pl b/test_regress/t/t_threads_counter_4.pl deleted file mode 100755 index 20ed3feb9..000000000 --- a/test_regress/t/t_threads_counter_4.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_threads_counter.v"); - -compile( - verilator_flags2 => ['--cc'], - threads => 4 - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_threads_counter_4.py b/test_regress/t/t_threads_counter_4.py new file mode 100755 index 000000000..50e637eae --- /dev/null +++ b/test_regress/t/t_threads_counter_4.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_threads_counter.v" + +test.compile(verilator_flags2=['--cc'], threads=4) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_threads_crazy.pl b/test_regress/t/t_threads_crazy.pl deleted file mode 100755 index c72858f2c..000000000 --- a/test_regress/t/t_threads_crazy.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -compile( - verilator_flags2 => ['--cc'], - threads => 4, - context_threads => 2 - ); - -execute( - fails => 1 - ); - -file_grep($Self->{run_log_filename}, qr/%Error: .*\/verilated\.cpp:\d+: VerilatedContext has 2 threads but model 'Vt_threads_crazy' \(instantiated as 'top'\) was Verilated with --threads 4\./); -ok(1); -1; diff --git a/test_regress/t/t_threads_crazy.py b/test_regress/t/t_threads_crazy.py new file mode 100755 index 000000000..625fc874d --- /dev/null +++ b/test_regress/t/t_threads_crazy.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') + +test.compile(verilator_flags2=['--cc'], threads=4, context_threads=2) + +test.execute(fails=True) + +test.file_grep( + test.run_log_filename, + r"%Error: .*\/verilated\.cpp:\d+: VerilatedContext has 2 threads but model 'Vt_threads_crazy' \(instantiated as 'top'\) was Verilated with --threads 4\." +) + +test.passes() diff --git a/test_regress/t/t_threads_crazy_context.pl b/test_regress/t/t_threads_crazy_context.pl deleted file mode 100755 index 73ba5c3b8..000000000 --- a/test_regress/t/t_threads_crazy_context.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_threads_crazy.v"); - -compile( - verilator_flags2 => ['--cc'], - threads => $Self->{vltmt} ? 2 : 1, - context_threads => 1024 - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vltmt}) { - file_grep($Self->{run_log_filename}, qr/System has \d+ hardware threads but simulation thread count set to 1024\. This will likely cause significant slowdown\./); -} - -ok(1); -1; diff --git a/test_regress/t/t_threads_crazy_context.py b/test_regress/t/t_threads_crazy_context.py new file mode 100755 index 000000000..6ef9e273d --- /dev/null +++ b/test_regress/t/t_threads_crazy_context.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_threads_crazy.v" + +test.compile(verilator_flags2=['--cc'], threads=(2 if test.vltmt else 1), context_threads=1024) + +test.execute() + +if test.vltmt: + test.file_grep( + test.run_log_filename, + r'System has \d+ hardware threads but simulation thread count set to 1024\. This will likely cause significant slowdown\.' + ) + +test.passes() diff --git a/test_regress/t/t_threads_nondeterminism.pl b/test_regress/t/t_threads_nondeterminism.pl deleted file mode 100755 index b584fa62d..000000000 --- a/test_regress/t/t_threads_nondeterminism.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_threads_counter.v"); - -compile( - verilator_flags2 => ['--cc --debug-nondeterminism --no-skip-identical'], - threads => 2 - ); - -execute( - check_finished => 1, - ); - -file_grep("$Self->{obj_dir}/vlt_compile.log", qr/hash of shape/i); - -ok(1); -1; diff --git a/test_regress/t/t_threads_nondeterminism.py b/test_regress/t/t_threads_nondeterminism.py new file mode 100755 index 000000000..51793a66a --- /dev/null +++ b/test_regress/t/t_threads_nondeterminism.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_threads_counter.v" + +test.compile(verilator_flags2=['--cc --debug-nondeterminism --no-skip-identical'], threads=2) + +test.execute() + +test.file_grep(test.compile_log_filename, r'Hash of shape') + +test.passes() diff --git a/test_regress/t/t_time.pl b/test_regress/t/t_time.pl deleted file mode 100755 index 47728df81..000000000 --- a/test_regress/t/t_time.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_time.py b/test_regress/t/t_time.py new file mode 100755 index 000000000..88cfbe63f --- /dev/null +++ b/test_regress/t/t_time.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_time_literals.pl b/test_regress/t/t_time_literals.pl deleted file mode 100755 index 1c5145af7..000000000 --- a/test_regress/t/t_time_literals.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_time_literals.py b/test_regress/t/t_time_literals.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_time_literals.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_time_passed.pl b/test_regress/t/t_time_passed.pl deleted file mode 100755 index 88b7809fc..000000000 --- a/test_regress/t/t_time_passed.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_passed.py b/test_regress/t/t_time_passed.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_time_passed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_print.pl b/test_regress/t/t_time_print.pl deleted file mode 100755 index 88b7809fc..000000000 --- a/test_regress/t/t_time_print.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_print.py b/test_regress/t/t_time_print.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_time_print.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_bad.pl b/test_regress/t/t_time_sc_bad.pl deleted file mode 100755 index 1c293ef05..000000000 --- a/test_regress/t/t_time_sc_bad.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_NS'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution - '+define+TEST_EXPECT=2us'], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_bad.py b/test_regress/t/t_time_sc_bad.py new file mode 100755 index 000000000..0ca15940f --- /dev/null +++ b/test_regress/t/t_time_sc_bad.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_NS' + +test.compile(verilator_flags2=[ + '-sc', + '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution + '+define+TEST_EXPECT=2us' +]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_bad_mt.pl b/test_regress/t/t_time_sc_bad_mt.pl deleted file mode 100755 index 6b6f6d637..000000000 --- a/test_regress/t/t_time_sc_bad_mt.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_NS'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution - '+define+TEST_EXPECT=2us'], - threads => 2, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_bad_mt.py b/test_regress/t/t_time_sc_bad_mt.py new file mode 100755 index 000000000..cf927d9fa --- /dev/null +++ b/test_regress/t/t_time_sc_bad_mt.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_NS' + +test.compile( + verilator_flags2=[ + '-sc', + '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution + '+define+TEST_EXPECT=2us' + ], + threads=2) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_fs.pl b/test_regress/t/t_time_sc_fs.pl deleted file mode 100755 index f3f22f608..000000000 --- a/test_regress/t/t_time_sc_fs.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_FS'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1fs/1fs', - '+define+TEST_EXPECT=20fs'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_fs.py b/test_regress/t/t_time_sc_fs.py new file mode 100755 index 000000000..70225625c --- /dev/null +++ b/test_regress/t/t_time_sc_fs.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_FS' + +test.compile(verilator_flags2=['-sc', '-timescale 1fs/1fs', '+define+TEST_EXPECT=20fs']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_ms.pl b/test_regress/t/t_time_sc_ms.pl deleted file mode 100755 index 3e90c0c36..000000000 --- a/test_regress/t/t_time_sc_ms.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_MS'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1ms/1ms', - '+define+TEST_EXPECT=20ms'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_ms.py b/test_regress/t/t_time_sc_ms.py new file mode 100755 index 000000000..8027dd32b --- /dev/null +++ b/test_regress/t/t_time_sc_ms.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_MS' + +test.compile(verilator_flags2=['-sc', '-timescale 1ms/1ms', '+define+TEST_EXPECT=20ms']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_ns.pl b/test_regress/t/t_time_sc_ns.pl deleted file mode 100755 index 76073b3f8..000000000 --- a/test_regress/t/t_time_sc_ns.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_NS'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1ns/1ns', - '+define+TEST_EXPECT=20ns'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_ns.py b/test_regress/t/t_time_sc_ns.py new file mode 100755 index 000000000..5db5c0710 --- /dev/null +++ b/test_regress/t/t_time_sc_ns.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_NS' + +test.compile(verilator_flags2=['-sc', '-timescale 1ns/1ns', '+define+TEST_EXPECT=20ns']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_sec.pl b/test_regress/t/t_time_sc_sec.pl deleted file mode 100755 index 8bc81ac97..000000000 --- a/test_regress/t/t_time_sc_sec.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_SEC'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1s/1s', - '+define+TEST_EXPECT=20s'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_sec.py b/test_regress/t/t_time_sc_sec.py new file mode 100755 index 000000000..4dc51c0c4 --- /dev/null +++ b/test_regress/t/t_time_sc_sec.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_SEC' + +test.compile(verilator_flags2=['-sc', '-timescale 1s/1s', '+define+TEST_EXPECT=20s']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_us.pl b/test_regress/t/t_time_sc_us.pl deleted file mode 100755 index e5533c631..000000000 --- a/test_regress/t/t_time_sc_us.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_US'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1us/1us', - '+define+TEST_EXPECT=20us'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_us.py b/test_regress/t/t_time_sc_us.py new file mode 100755 index 000000000..c93e31e4e --- /dev/null +++ b/test_regress/t/t_time_sc_us.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_US' + +test.compile(verilator_flags2=['-sc', '-timescale 1us/1us', '+define+TEST_EXPECT=20us']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_stamp64.pl b/test_regress/t/t_time_stamp64.pl deleted file mode 100755 index a3a332be9..000000000 --- a/test_regress/t/t_time_stamp64.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# Verilator before 4.033 had 'double sc_time_stamp()', make sure new form compiles -$self->{vl_time_stamp64} = 1; - -compile( - verilator_flags2 => ['-DVL_TIME_STAMP64=1'], - ); - -execute( - check_finished => 1, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_stamp64.py b/test_regress/t/t_time_stamp64.py new file mode 100755 index 000000000..b1ae8bfb1 --- /dev/null +++ b/test_regress/t/t_time_stamp64.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +# Verilator before 4.033 had 'double sc_time_stamp()', make sure new form compiles +test.vl_time_stamp64 = True + +test.compile(verilator_flags2=['-DVL_TIME_STAMP64=1']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_time_stamp_double.pl b/test_regress/t/t_time_stamp_double.pl deleted file mode 100755 index 2b7dbde51..000000000 --- a/test_regress/t/t_time_stamp_double.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename('t/t_time_stamp64.v'); - -# Verilator before 4.033 had 'double sc_time_stamp()', make sure this still compiles -$self->{vl_time_stamp64} = 0; - -compile( - verilator_flags2 => [], - ); - -execute( - check_finished => 1, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_stamp_double.py b/test_regress/t/t_time_stamp_double.py new file mode 100755 index 000000000..860803ab8 --- /dev/null +++ b/test_regress/t/t_time_stamp_double.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = 't/t_time_stamp64.v' + +# Verilator before 4.033 had 'double sc_time_stamp()', make sure this still compiles +test.vl_time_stamp64 = False + +test.compile(verilator_flags2=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_time_timeunit.pl b/test_regress/t/t_time_timeunit.pl deleted file mode 100755 index 4e42b8db0..000000000 --- a/test_regress/t/t_time_timeunit.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_timeunit.py b/test_regress/t/t_time_timeunit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_time_timeunit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_time_vpi_100s10ms.pl b/test_regress/t/t_time_vpi_100s10ms.pl deleted file mode 100755 index 34e5ba90e..000000000 --- a/test_regress/t/t_time_vpi_100s10ms.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 100e0 / 10e-6; - -compile( - v_flags2 => ['+define+time_scale_units=100s +define+time_scale_prec=10ms', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_100s10ms.py b/test_regress/t/t_time_vpi_100s10ms.py new file mode 100755 index 000000000..cfcf44e95 --- /dev/null +++ b/test_regress/t/t_time_vpi_100s10ms.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 100e0 / 10e-6 + +test.compile( + v_flags2=['+define+time_scale_units=100s +define+time_scale_prec=10ms', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_vpi_10ms10ns.pl b/test_regress/t/t_time_vpi_10ms10ns.pl deleted file mode 100755 index e6bf379c2..000000000 --- a/test_regress/t/t_time_vpi_10ms10ns.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 10e-3 / 10e-9; - -compile( - v_flags2 => ['+define+time_scale_units=10ms +define+time_scale_prec=10ns', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_10ms10ns.py b/test_regress/t/t_time_vpi_10ms10ns.py new file mode 100755 index 000000000..1851ccf3e --- /dev/null +++ b/test_regress/t/t_time_vpi_10ms10ns.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 10e-3 / 10e-9 + +test.compile( + v_flags2=['+define+time_scale_units=10ms +define+time_scale_prec=10ns', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_vpi_1fs1fs.pl b/test_regress/t/t_time_vpi_1fs1fs.pl deleted file mode 100755 index 84b0c95c1..000000000 --- a/test_regress/t/t_time_vpi_1fs1fs.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e-15 / 1e-15; - -compile( - v_flags2 => ['+define+time_scale_units=1fs +define+time_scale_prec=1fs', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1fs1fs.py b/test_regress/t/t_time_vpi_1fs1fs.py new file mode 100755 index 000000000..c95d44318 --- /dev/null +++ b/test_regress/t/t_time_vpi_1fs1fs.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e-15 / 1e-15 + +test.compile( + v_flags2=['+define+time_scale_units=1fs +define+time_scale_prec=1fs', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_vpi_1ms10ns.pl b/test_regress/t/t_time_vpi_1ms10ns.pl deleted file mode 100755 index 713f547c2..000000000 --- a/test_regress/t/t_time_vpi_1ms10ns.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e-3 / 10e-9; - -compile( - v_flags2 => ['+define+time_scale_units=1ms +define+time_scale_prec=10ns', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi --trace'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -file_grep("$Self->{obj_dir}/simx.vcd", qr!timescale +10ns!); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1ms10ns.py b/test_regress/t/t_time_vpi_1ms10ns.py new file mode 100755 index 000000000..b7460eb4e --- /dev/null +++ b/test_regress/t/t_time_vpi_1ms10ns.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e-3 / 10e-9 + +test.compile( + v_flags2=['+define+time_scale_units=1ms +define+time_scale_prec=10ns', test.pli_filename], + verilator_flags2=['--vpi --trace']) + +test.execute(expect_filename=test.golden_filename) + +test.file_grep(test.trace_filename, r'timescale +10ns') + +test.passes() diff --git a/test_regress/t/t_time_vpi_1ns1ns.pl b/test_regress/t/t_time_vpi_1ns1ns.pl deleted file mode 100755 index 32e10e69e..000000000 --- a/test_regress/t/t_time_vpi_1ns1ns.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e-9 / 1e-9; - -compile( - v_flags2 => ['+define+time_scale_units=1ns +define+time_scale_prec=1ns', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi --trace'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -file_grep("$Self->{obj_dir}/simx.vcd", qr!timescale +1ns!); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1ns1ns.py b/test_regress/t/t_time_vpi_1ns1ns.py new file mode 100755 index 000000000..ac7e49500 --- /dev/null +++ b/test_regress/t/t_time_vpi_1ns1ns.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e-9 / 1e-9 + +test.compile( + v_flags2=['+define+time_scale_units=1ns +define+time_scale_prec=1ns', test.pli_filename], + verilator_flags2=['--vpi --trace']) + +test.execute(expect_filename=test.golden_filename) + +test.file_grep(test.trace_filename, r'timescale +1ns') + +test.passes() diff --git a/test_regress/t/t_time_vpi_1ps1fs.pl b/test_regress/t/t_time_vpi_1ps1fs.pl deleted file mode 100755 index eb619bf9d..000000000 --- a/test_regress/t/t_time_vpi_1ps1fs.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e-12 / 10e-15; - -compile( - v_flags2 => ['+define+time_scale_units=1ps +define+time_scale_prec=1fs', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1ps1fs.py b/test_regress/t/t_time_vpi_1ps1fs.py new file mode 100755 index 000000000..a85054b1c --- /dev/null +++ b/test_regress/t/t_time_vpi_1ps1fs.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e-12 / 10e-15 + +test.compile( + v_flags2=['+define+time_scale_units=1ps +define+time_scale_prec=1fs', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_vpi_1s10ns.pl b/test_regress/t/t_time_vpi_1s10ns.pl deleted file mode 100755 index 88d513a8a..000000000 --- a/test_regress/t/t_time_vpi_1s10ns.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e0 / 10e-9; - -compile( - v_flags2 => ['+define+time_scale_units=1s +define+time_scale_prec=10ns', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1s10ns.py b/test_regress/t/t_time_vpi_1s10ns.py new file mode 100755 index 000000000..ebed040b9 --- /dev/null +++ b/test_regress/t/t_time_vpi_1s10ns.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e0 / 10e-9 + +test.compile( + v_flags2=['+define+time_scale_units=1s +define+time_scale_prec=10ns', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_vpi_1us1ns.pl b/test_regress/t/t_time_vpi_1us1ns.pl deleted file mode 100755 index e4b9adc38..000000000 --- a/test_regress/t/t_time_vpi_1us1ns.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e-6 / 1e-9; - -compile( - v_flags2 => ['+define+time_scale_units=1us +define+time_scale_prec=1ns', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1us1ns.py b/test_regress/t/t_time_vpi_1us1ns.py new file mode 100755 index 000000000..547804dae --- /dev/null +++ b/test_regress/t/t_time_vpi_1us1ns.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e-6 / 1e-9 + +test.compile( + v_flags2=['+define+time_scale_units=1us +define+time_scale_prec=1ns', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timescale_default.pl b/test_regress/t/t_timescale_default.pl deleted file mode 100755 index 88b7809fc..000000000 --- a/test_regress/t/t_timescale_default.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_timescale_default.py b/test_regress/t/t_timescale_default.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_timescale_default.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timescale_lint.pl b/test_regress/t/t_timescale_lint.pl deleted file mode 100755 index 051f08f78..000000000 --- a/test_regress/t/t_timescale_lint.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --timescale-override 1ns/1ns"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_timescale_lint.py b/test_regress/t/t_timescale_lint.py new file mode 100755 index 000000000..5e513aa7c --- /dev/null +++ b/test_regress/t/t_timescale_lint.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --timescale-override 1ns/1ns"]) + +test.passes() diff --git a/test_regress/t/t_timescale_lint2.pl b/test_regress/t/t_timescale_lint2.pl deleted file mode 100755 index 6a8798deb..000000000 --- a/test_regress/t/t_timescale_lint2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_timescale_lint.v"); - -lint( - verilator_flags2 => ["--lint-only --timescale 1ns/1ns"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_timescale_lint2.py b/test_regress/t/t_timescale_lint2.py new file mode 100755 index 000000000..6e393030b --- /dev/null +++ b/test_regress/t/t_timescale_lint2.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_timescale_lint.v" + +test.lint(verilator_flags2=["--lint-only --timescale 1ns/1ns"]) + +test.passes() diff --git a/test_regress/t/t_timescale_lint_bad.pl b/test_regress/t/t_timescale_lint_bad.pl deleted file mode 100755 index 022ca4683..000000000 --- a/test_regress/t/t_timescale_lint_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_timescale_lint.v"); - -lint( - verilator_flags2 => ["--lint-only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timescale_lint_bad.py b/test_regress/t/t_timescale_lint_bad.py new file mode 100755 index 000000000..8842c380b --- /dev/null +++ b/test_regress/t/t_timescale_lint_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_timescale_lint.v" + +test.lint(verilator_flags2=["--lint-only"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timescale_parse.pl b/test_regress/t/t_timescale_parse.pl deleted file mode 100755 index 334cd0451..000000000 --- a/test_regress/t/t_timescale_parse.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timescale_parse.py b/test_regress/t/t_timescale_parse.py new file mode 100755 index 000000000..9d1dcec8d --- /dev/null +++ b/test_regress/t/t_timescale_parse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timescale_parse_bad.pl b/test_regress/t/t_timescale_parse_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_timescale_parse_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timescale_parse_bad.py b/test_regress/t/t_timescale_parse_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_timescale_parse_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timescale_udp.pl b/test_regress/t/t_timescale_udp.pl deleted file mode 100755 index 4e42b8db0..000000000 --- a/test_regress/t/t_timescale_udp.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_timescale_udp.py b/test_regress/t/t_timescale_udp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_timescale_udp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timescale_unit.pl b/test_regress/t/t_timescale_unit.pl deleted file mode 100755 index 88b7809fc..000000000 --- a/test_regress/t/t_timescale_unit.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_timescale_unit.py b/test_regress/t/t_timescale_unit.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_timescale_unit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_always.pl b/test_regress/t/t_timing_always.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_always.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_always.py b/test_regress/t/t_timing_always.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_always.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_class.pl b/test_regress/t/t_timing_class.pl deleted file mode 100755 index ed3bac458..000000000 --- a/test_regress/t/t_timing_class.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_class.py b/test_regress/t/t_timing_class.py new file mode 100755 index 000000000..664ad3bec --- /dev/null +++ b/test_regress/t/t_timing_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_class_static_delay.pl b/test_regress/t/t_timing_class_static_delay.pl deleted file mode 100755 index ed3bac458..000000000 --- a/test_regress/t/t_timing_class_static_delay.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_class_static_delay.py b/test_regress/t/t_timing_class_static_delay.py new file mode 100755 index 000000000..664ad3bec --- /dev/null +++ b/test_regress/t/t_timing_class_static_delay.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_clkgen1.pl b/test_regress/t/t_timing_clkgen1.pl deleted file mode 100755 index a4a48a187..000000000 --- a/test_regress/t/t_timing_clkgen1.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing -Wno-MINTYPMAXDLY"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_clkgen1.py b/test_regress/t/t_timing_clkgen1.py new file mode 100755 index 000000000..19a494154 --- /dev/null +++ b/test_regress/t/t_timing_clkgen1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing -Wno-MINTYPMAXDLY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_clkgen2.pl b/test_regress/t/t_timing_clkgen2.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_clkgen2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_clkgen2.py b/test_regress/t/t_timing_clkgen2.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_clkgen2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_clkgen3.pl b/test_regress/t/t_timing_clkgen3.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_clkgen3.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_clkgen3.py b/test_regress/t/t_timing_clkgen3.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_clkgen3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_clkgen_sc.pl b/test_regress/t/t_timing_clkgen_sc.pl deleted file mode 100755 index 728e33f11..000000000 --- a/test_regress/t/t_timing_clkgen_sc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_clkgen2.v"); - -compile( - verilator_flags2 => ["--sc --exe --timing --timescale 10ps/1ps"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_clkgen_sc.py b/test_regress/t/t_timing_clkgen_sc.py new file mode 100755 index 000000000..f64e24169 --- /dev/null +++ b/test_regress/t/t_timing_clkgen_sc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_clkgen2.v" + +test.compile(verilator_flags2=["--sc --exe --timing --timescale 10ps/1ps"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_clkgen_unsup.pl b/test_regress/t/t_timing_clkgen_unsup.pl deleted file mode 100755 index b380d0484..000000000 --- a/test_regress/t/t_timing_clkgen_unsup.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_timing_clkgen1.v"); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_clkgen_unsup.py b/test_regress/t/t_timing_clkgen_unsup.py new file mode 100755 index 000000000..3d960dc96 --- /dev/null +++ b/test_regress/t/t_timing_clkgen_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_timing_clkgen1.v" + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_cmake.pl b/test_regress/t/t_timing_cmake.pl deleted file mode 100755 index acd0f0d36..000000000 --- a/test_regress/t/t_timing_cmake.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_coroutines) { - skip("No coroutine support"); -} elsif (!$Self->have_cmake) { - skip("cmake is not installed"); -} else { - top_filename("t/t_timing_events.v"); - - compile( - verilator_flags2 => ["--timescale 10ns/1ns --main --timing"], - verilator_make_gmake => 0, - verilator_make_cmake => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_timing_cmake.py b/test_regress/t/t_timing_cmake.py new file mode 100755 index 000000000..01e454245 --- /dev/null +++ b/test_regress/t/t_timing_cmake.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_events.v" + +if not test.have_coroutines: + test.skip("No coroutine support") +if not test.have_cmake: + test.skip("cmake is not installed") + +test.compile(verilator_flags2=["--timescale 10ns/1ns --main --timing"], + verilator_make_gmake=False, + verilator_make_cmake=True) + +test.passes() diff --git a/test_regress/t/t_timing_debug1.out b/test_regress/t/t_timing_debug1.out index fae5ac2e7..0d1f5f568 100644 --- a/test_regress/t/t_timing_debug1.out +++ b/test_regress/t/t_timing_debug1.out @@ -18,18 +18,30 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl -V{t#,#} 'stl' region trigger index 0 is active: Internal 'stl' trigger - first iteration --V{t#,#} 'stl' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#} 'stl' region trigger index 2 is active: @([hybrid] __VassignWtmp_t.clk2__0) --V{t#,#} 'stl' region trigger index 3 is active: @([hybrid] t.c1) +-V{t#,#} 'stl' region trigger index 1 is active: @([hybrid] t.clk1) +-V{t#,#} 'stl' region trigger index 2 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'stl' region trigger index 3 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#} 'stl' region trigger index 4 is active: @([hybrid] t.clk2) +-V{t#,#} 'stl' region trigger index 5 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'stl' region trigger index 6 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#} 'stl' region trigger index 7 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___eval_stl -V{t#,#}+ Vt_timing_debug1___024root___stl_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___stl_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___stl_sequent__TOP__2 --V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 --V{t#,#}+ Vt_timing_debug1___024root___stl_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___stl_comb__TOP__2 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__stl +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl +-V{t#,#} 'stl' region trigger index 2 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'stl' region trigger index 3 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#} 'stl' region trigger index 5 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'stl' region trigger index 6 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___eval_stl +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__stl -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl @@ -39,9 +51,13 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) --V{t#,#} 'act' region trigger index 2 is active: @([hybrid] t.c1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) +-V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 6 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 @@ -51,9 +67,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act @@ -76,33 +90,22 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 3: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 3: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -116,14 +119,25 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 @@ -142,14 +156,13 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 6: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 @@ -158,7 +171,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -167,6 +180,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -186,14 +208,13 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 @@ -224,13 +245,12 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 @@ -239,16 +259,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -258,10 +270,21 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -282,33 +305,23 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 5 is active: @(posedge t.clk2) +-V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) +-V{t#,#} 'act' region trigger index 9 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk2): @@ -321,16 +334,21 @@ -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 2 is active: @([hybrid] t.c1) +-V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 6 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act @@ -354,7 +372,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -372,7 +390,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:50 @@ -383,6 +401,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -402,7 +429,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -439,7 +466,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -453,16 +480,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -476,14 +495,25 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 @@ -502,7 +532,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -517,7 +547,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -526,6 +556,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -545,7 +584,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -582,7 +621,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -596,16 +635,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -615,10 +646,21 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -639,7 +681,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -654,7 +696,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) +-V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -663,6 +705,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -682,7 +733,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -697,7 +748,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -706,6 +757,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -725,7 +785,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -762,7 +822,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -776,16 +836,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -795,10 +847,21 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -819,7 +882,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -834,7 +897,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -843,6 +906,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -862,7 +934,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -899,7 +971,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -914,20 +986,10 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) --V{t#,#} 'act' region trigger index 5 is active: @(posedge t.clk2) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 9 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -945,16 +1007,26 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 2 is active: @([hybrid] t.c1) +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 6 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act @@ -979,7 +1051,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1017,7 +1089,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1032,7 +1104,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1041,6 +1113,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1060,7 +1141,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1097,7 +1178,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1111,16 +1192,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -1134,14 +1207,25 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 @@ -1160,7 +1244,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1175,7 +1259,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1184,6 +1268,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1203,7 +1296,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1240,7 +1333,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1254,7 +1347,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) +-V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1263,6 +1356,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1282,7 +1384,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1296,16 +1398,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -1315,10 +1409,21 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1339,7 +1444,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1354,7 +1459,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1363,6 +1468,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1382,7 +1496,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1419,7 +1533,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1433,16 +1547,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -1452,10 +1558,21 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1476,7 +1593,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1491,7 +1608,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1500,6 +1617,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1519,7 +1645,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1536,20 +1662,12 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) +-V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) +-V{t#,#} 'act' region trigger index 9 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 5 is active: @(posedge t.clk2) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:50 -V{t#,#} Ready processes waiting for @(posedge t.clk2): @@ -1560,16 +1678,21 @@ -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 2 is active: @([hybrid] t.c1) +-V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 6 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act @@ -1593,7 +1716,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1630,7 +1753,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1644,16 +1767,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -1667,14 +1782,25 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 @@ -1693,7 +1819,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1708,7 +1834,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1717,6 +1843,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1736,7 +1871,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1773,7 +1908,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1787,16 +1922,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -1806,10 +1933,21 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1830,7 +1968,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1846,8 +1984,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1858,6 +1996,18 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1877,7 +2027,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1914,7 +2064,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1928,16 +2078,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -1947,10 +2089,21 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1971,7 +2124,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -1986,7 +2139,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1995,6 +2148,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -2014,7 +2176,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -2051,7 +2213,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -2065,16 +2227,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) +-V{t#,#} 'act' region trigger index 7 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): @@ -2084,10 +2238,21 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -2108,7 +2273,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -2123,16 +2288,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 5 is active: @(posedge t.clk2) +-V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) +-V{t#,#} 'act' region trigger index 9 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk2): @@ -2145,16 +2302,21 @@ -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 2 is active: @([hybrid] t.c1) +-V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 6 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act @@ -2178,7 +2340,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#} 'act' region trigger index 8 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: @@ -2198,7 +2360,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:50 @@ -2209,6 +2371,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) +-V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba diff --git a/test_regress/t/t_timing_debug1.pl b/test_regress/t/t_timing_debug1.pl deleted file mode 100755 index 61ae92cc7..000000000 --- a/test_regress/t/t_timing_debug1.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_timing_sched.v"); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - all_run_flags => ["+verilator+debug"], - check_finished => 1, - ); - -if (!$Self->{vltmt}) { # vltmt output may vary between thread exec order - files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile"); -} - -ok(1); -1; diff --git a/test_regress/t/t_timing_debug1.py b/test_regress/t/t_timing_debug1.py new file mode 100755 index 000000000..edded70be --- /dev/null +++ b/test_regress/t/t_timing_debug1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_timing_sched.v" + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(all_run_flags=["+verilator+debug"]) + +if not test.vltmt: # vltmt output may vary between thread exec order + test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") + +test.passes() diff --git a/test_regress/t/t_timing_debug2.pl b/test_regress/t/t_timing_debug2.pl deleted file mode 100755 index aa8ec9485..000000000 --- a/test_regress/t/t_timing_debug2.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_timing_class.v"); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - all_run_flags => ["+verilator+debug"], - check_finished => 1, - ); - -if (!$Self->{vltmt}) { # vltmt output may vary between thread exec order - files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile"); -} - -ok(1); -1; diff --git a/test_regress/t/t_timing_debug2.py b/test_regress/t/t_timing_debug2.py new file mode 100755 index 000000000..e6f816ca2 --- /dev/null +++ b/test_regress/t/t_timing_debug2.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_timing_class.v" + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(all_run_flags=["+verilator+debug"]) + +if not test.vltmt: # vltmt output may vary between thread exec order + test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") + +test.passes() diff --git a/test_regress/t/t_timing_delay_callstack.pl b/test_regress/t/t_timing_delay_callstack.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_delay_callstack.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_delay_callstack.py b/test_regress/t/t_timing_delay_callstack.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_delay_callstack.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_dlyassign.pl b/test_regress/t/t_timing_dlyassign.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_dlyassign.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_dlyassign.py b/test_regress/t/t_timing_dlyassign.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_dlyassign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_dpi_unsup.pl b/test_regress/t/t_timing_dpi_unsup.pl deleted file mode 100755 index a6399f3f7..000000000 --- a/test_regress/t/t_timing_dpi_unsup.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_timing_dpi_unsup.v"); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_dpi_unsup.py b/test_regress/t/t_timing_dpi_unsup.py new file mode 100755 index 000000000..f0fcfa7f8 --- /dev/null +++ b/test_regress/t/t_timing_dpi_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_timing_dpi_unsup.v" + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_dynscope.pl b/test_regress/t/t_timing_dynscope.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_dynscope.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_dynscope.py b/test_regress/t/t_timing_dynscope.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_dynscope.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_events.pl b/test_regress/t/t_timing_events.pl deleted file mode 100755 index ed3bac458..000000000 --- a/test_regress/t/t_timing_events.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_events.py b/test_regress/t/t_timing_events.py new file mode 100755 index 000000000..664ad3bec --- /dev/null +++ b/test_regress/t/t_timing_events.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_finish.py b/test_regress/t/t_timing_finish.py new file mode 100755 index 000000000..671072f97 --- /dev/null +++ b/test_regress/t/t_timing_finish.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_finish.v b/test_regress/t/t_timing_finish.v new file mode 100644 index 000000000..a478269ab --- /dev/null +++ b/test_regress/t/t_timing_finish.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +program t; + initial begin + $write("*-* All Finished *-*\n"); + // No $finish + end +endprogram diff --git a/test_regress/t/t_timing_fork_comb.pl b/test_regress/t/t_timing_fork_comb.pl deleted file mode 100755 index c9e9158e8..000000000 --- a/test_regress/t/t_timing_fork_comb.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Should convert the first always into combo and detect cycle -compile( - fails => 1, - verilator_flags2 => ["--timing"], - expect => - '%Warning-UNOPTFLAT: t/t_timing_fork_comb.v:\d+:\d+: Signal unoptimizable: Circular combinational logic:' - ); - -compile( - verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_comb.py b/test_regress/t/t_timing_fork_comb.py new file mode 100755 index 000000000..cf21ef4d2 --- /dev/null +++ b/test_regress/t/t_timing_fork_comb.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing -Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_fork_comb_bad.py b/test_regress/t/t_timing_fork_comb_bad.py new file mode 100755 index 000000000..1b5d6f77c --- /dev/null +++ b/test_regress/t/t_timing_fork_comb_bad.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_timing_fork_comb.v" + +# Should convert the first always into combo and detect cycle +test.lint(fails=True, verilator_flags2=["--timing"]) + +test.file_grep( + test.compile_log_filename, + r'%Warning-UNOPTFLAT: t/t_timing_fork_comb.v:\d+:\d+: Signal unoptimizable: Circular combinational logic:' +) + +test.passes() diff --git a/test_regress/t/t_timing_fork_join.pl b/test_regress/t/t_timing_fork_join.pl deleted file mode 100755 index f686c3eec..000000000 --- a/test_regress/t/t_timing_fork_join.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_join.py b/test_regress/t/t_timing_fork_join.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_timing_fork_join.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_fork_join_forkproc.pl b/test_regress/t/t_timing_fork_join_forkproc.pl deleted file mode 100755 index e6d59ea75..000000000 --- a/test_regress/t/t_timing_fork_join_forkproc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_fork_join.v"); - -compile( - verilator_flags2 => ["--exe --main --timing --ftaskify-all-forked"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_join_forkproc.py b/test_regress/t/t_timing_fork_join_forkproc.py new file mode 100755 index 000000000..75f4712aa --- /dev/null +++ b/test_regress/t/t_timing_fork_join_forkproc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_fork_join.v" + +test.compile(verilator_flags2=["--exe --main --timing --ftaskify-all-forked"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_fork_many.pl b/test_regress/t/t_timing_fork_many.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_fork_many.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_many.py b/test_regress/t/t_timing_fork_many.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_fork_many.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_fork_nba.pl b/test_regress/t/t_timing_fork_nba.pl deleted file mode 100755 index e23c975f9..000000000 --- a/test_regress/t/t_timing_fork_nba.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --timing"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_nba.py b/test_regress/t/t_timing_fork_nba.py new file mode 100755 index 000000000..c12d9cce8 --- /dev/null +++ b/test_regress/t/t_timing_fork_nba.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --timing"]) + +test.passes() diff --git a/test_regress/t/t_timing_fork_no_timing_ctrl.pl b/test_regress/t/t_timing_fork_no_timing_ctrl.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_fork_no_timing_ctrl.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_no_timing_ctrl.py b/test_regress/t/t_timing_fork_no_timing_ctrl.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_fork_no_timing_ctrl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_fork_rec_method.pl b/test_regress/t/t_timing_fork_rec_method.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_fork_rec_method.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_rec_method.py b/test_regress/t/t_timing_fork_rec_method.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_fork_rec_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_fork_taskcall.pl b/test_regress/t/t_timing_fork_taskcall.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_fork_taskcall.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_taskcall.py b/test_regress/t/t_timing_fork_taskcall.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_fork_taskcall.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_func_bad.pl b/test_regress/t/t_timing_func_bad.pl deleted file mode 100755 index 0ee17366a..000000000 --- a/test_regress/t/t_timing_func_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--no-timing'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_func_bad.py b/test_regress/t/t_timing_func_bad.py new file mode 100755 index 000000000..7e3cbabde --- /dev/null +++ b/test_regress/t/t_timing_func_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename, verilator_flags2=['--no-timing']) + +test.passes() diff --git a/test_regress/t/t_timing_initial_always.pl b/test_regress/t/t_timing_initial_always.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_initial_always.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_initial_always.py b/test_regress/t/t_timing_initial_always.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_initial_always.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_intra_assign.out b/test_regress/t/t_timing_intra_assign.out index fc870d925..ea22e3418 100644 --- a/test_regress/t/t_timing_intra_assign.out +++ b/test_regress/t/t_timing_intra_assign.out @@ -1,15 +1,25 @@ -val[0]=0 val[1]=0 val[2]=0 -val[0]=1 val[1]=0 val[2]=0 -val[0]=2 val[1]=0 val[2]=15 -val[0]=3 val[1]=0 val[2]=15 -val[0]=4 val[1]=1 val[2]=14 -val[0]=5 val[1]=1 val[2]=14 -val[0]=6 val[1]=2 val[2]=13 -val[0]=7 val[1]=4 val[2]=11 -val[0]=8 val[1]=7 val[2]=8 -val[0]=9 val[1]=7 val[2]=8 -val[0]=10 val[1]=7 val[2]=8 -val[0]=11 val[1]=7 val[2]=8 -val[0]=12 val[1]=7 val[2]=8 -val[0]=13 val[1]=7 val[2]=8 +[0] val[0]=0 val[1]=0 val[2]=0 net[0]=0 net[1]=0 +[10] val[0]=1 val[1]=0 val[2]=0 net[0]=0 net[1]=15 +[14] val[0]=1 val[1]=1 val[2]=0 net[0]=0 net[1]=15 +[16] val[0]=1 val[1]=1 val[2]=1 net[0]=0 net[1]=15 +[20] val[0]=2 val[1]=1 val[2]=1 net[0]=1 net[1]=14 +[24] val[0]=2 val[1]=2 val[2]=1 net[0]=1 net[1]=14 +[25] val[0]=3 val[1]=2 val[2]=1 net[0]=1 net[1]=14 +[29] val[0]=3 val[1]=3 val[2]=1 net[0]=2 net[1]=13 +[30] val[0]=4 val[1]=3 val[2]=1 net[0]=2 net[1]=13 +[34] val[0]=4 val[1]=4 val[2]=1 net[0]=3 net[1]=12 +[35] val[0]=5 val[1]=4 val[2]=1 net[0]=3 net[1]=12 +[39] val[0]=5 val[1]=5 val[2]=1 net[0]=4 net[1]=11 +[40] val[0]=6 val[1]=5 val[2]=1 net[0]=4 net[1]=11 +[44] val[0]=6 val[1]=6 val[2]=1 net[0]=5 net[1]=10 +[46] val[0]=6 val[1]=6 val[2]=6 net[0]=5 net[1]=10 +[50] val[0]=7 val[1]=6 val[2]=6 net[0]=6 net[1]=9 +[54] val[0]=7 val[1]=7 val[2]=6 net[0]=6 net[1]=9 +[56] val[0]=7 val[1]=7 val[2]=7 net[0]=6 net[1]=9 +[75] val[0]=8 val[1]=7 val[2]=7 net[0]=7 net[1]=8 +[76] val[0]=9 val[1]=7 val[2]=7 net[0]=7 net[1]=8 +[78] val[0]=10 val[1]=7 val[2]=7 net[0]=7 net[1]=8 +[79] val[0]=11 val[1]=7 val[2]=7 net[0]=7 net[1]=8 +[80] val[0]=12 val[1]=7 val[2]=7 net[0]=7 net[1]=8 +[82] val[0]=13 val[1]=7 val[2]=7 net[0]=7 net[1]=8 *-* All Finished *-* diff --git a/test_regress/t/t_timing_intra_assign.pl b/test_regress/t/t_timing_intra_assign.pl deleted file mode 100755 index f625618ab..000000000 --- a/test_regress/t/t_timing_intra_assign.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -compile( - verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT -fno-localize"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_intra_assign.py b/test_regress/t/t_timing_intra_assign.py new file mode 100755 index 000000000..1407fff26 --- /dev/null +++ b/test_regress/t/t_timing_intra_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_intra_assign.v b/test_regress/t/t_timing_intra_assign.v index 35afe20a9..15f4f16fd 100644 --- a/test_regress/t/t_timing_intra_assign.v +++ b/test_regress/t/t_timing_intra_assign.v @@ -6,28 +6,35 @@ module t; logic[3:0] val[3]; + wire[3:0] #5 net[2]; logic[1:0] idx1 = 0; logic[1:0] idx2 = 0; logic[0:0] idx3 = 0; event e; - always @val[0] $write("val[0]=%0d val[1]=%0d val[2]=%0d\n", val[0], val[1], val[2]); + always @val $write("[%0t] val[0]=%0d val[1]=%0d val[2]=%0d net[0]=%0d net[1]=%0d\n", + $time, val[0], val[1], val[2], net[0], net[1]); - assign #10 {val[1], val[2]} = {val[0], 4'hf-val[0]}; + assign {net[0], net[1]} = {val[1], 4'hf-val[1]}; + assign #4 val[1] = val[0]; + assign #6 val[2] = val[0]; always #10 begin // always so we can use NBA val[0] = 1; #10 val[0] = 2; fork #5 val[0] = 3; join_none val[0] = #10 val[0] + 2; - val[idx1] <= #10 val[idx1] + 2; + val[0] <= #10 val[idx1] + 2; fork begin #5 val[0] = 5; - idx1 = 2; - idx2 = 3; - idx3 = 1; + idx1 = 0; + idx2 = 0; + idx3 = 0; #40 ->e; end join_none + idx1 = 2; + idx2 = 3; + idx3 = 1; val[idx1][idx2[idx3+:2]] = #20 1; @e val[0] = 8; fork begin diff --git a/test_regress/t/t_timing_intra_assign_nolocalize.py b/test_regress/t/t_timing_intra_assign_nolocalize.py new file mode 100755 index 000000000..1f097a2b0 --- /dev/null +++ b/test_regress/t/t_timing_intra_assign_nolocalize.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_intra_assign.v" +test.golden_filename = "t/t_timing_intra_assign.out" + +test.compile(verilator_flags2=["--binary -fno-localize"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_localevent.py b/test_regress/t/t_timing_localevent.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_localevent.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_localevent.v b/test_regress/t/t_timing_localevent.v new file mode 100644 index 000000000..69aaf8878 --- /dev/null +++ b/test_regress/t/t_timing_localevent.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +module t; + class Foo; + task sleep; + event e; + fork + @e; + #1 ->e; + join + endtask + task trigger_later1(event e); + fork #2 ->e; join_none + endtask + task trigger_later2(ref event e); + fork #3 ->e; join_none + endtask + task test; + for (int i = 0; i < 10; i++) begin + event e1, e2; + trigger_later1(e1); + trigger_later2(e2); + sleep; + @e1; @e2; + end + endtask + endclass + + initial begin + Foo foo = new; + foo.test; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_timing_localevent_unsup.out b/test_regress/t/t_timing_localevent_unsup.out deleted file mode 100644 index 01b2c9f44..000000000 --- a/test_regress/t/t_timing_localevent_unsup.out +++ /dev/null @@ -1,6 +0,0 @@ -%Error-UNSUPPORTED: t/t_timing_localevent_unsup.v:12:17: Unsupported: waiting on local event variables - : ... note: In instance 't::Sleeper' - 12 | @e; - | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: Exiting due to diff --git a/test_regress/t/t_timing_localevent_unsup.pl b/test_regress/t/t_timing_localevent_unsup.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_timing_localevent_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_localevent_unsup.v b/test_regress/t/t_timing_localevent_unsup.v deleted file mode 100644 index 8091e2a4b..000000000 --- a/test_regress/t/t_timing_localevent_unsup.v +++ /dev/null @@ -1,24 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. -// SPDX-License-Identifier: CC0-1.0 - -module t; - class Sleeper; - task sleep; - event e; - fork - @e; - #1 ->e; - join; - endtask - endclass - - initial begin - Sleeper sleeper = new; - sleeper.sleep; - $write("*-* All Finished *-*\n"); - $finish; - end -endmodule diff --git a/test_regress/t/t_timing_long.pl b/test_regress/t/t_timing_long.pl deleted file mode 100755 index 9c7fdc503..000000000 --- a/test_regress/t/t_timing_long.pl +++ /dev/null @@ -1,78 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; - -scenarios(simulator => 1); - -# Look for O(n^2) problems in process handling - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_timing_long.pl\n"); - - $fh->print("\n"); - $fh->print("`ifdef TEST_VERBOSE\n"); - $fh->print(" `define MSG(m) \$display m\n"); - $fh->print("`else\n"); - $fh->print(" `define MSG(m)\n"); - $fh->print("`endif\n"); - $fh->print("\n"); - - $fh->print("module t;\n"); - $fh->print("\n"); - $fh->print(" int cnt;\n"); - $fh->print("\n"); - $fh->print(" initial begin\n"); - - my $n = 100; - for (my $i = 1; $i < $n; ++$i) { - # If statement around the timing is important to make the code scheduling - # mostly unpredictable - $fh->printf(" if (cnt == %d) begin\n", $i - 1); - $fh->printf(" #1; ++cnt; `MSG((\"[%0t] cnt?=${i}\", \$time));" - . " if (cnt != %d) \$stop;\n", $i); - $fh->printf(" end\n"); - } - - $fh->print("\n"); - $fh->print(' $write("*-* All Finished *-*\n");', "\n"); - $fh->print(' $finish;', "\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_timing_long.v"); - -gen($Self->{top_filename}); - -if ($Self->have_coroutines) { - compile( - verilator_flags2 => ["--exe --build --main --tim" . "ing"], - make_top => 1, - ); - - execute( - check_finished => 1, - ); -} - -compile( - verilator_flags2 => ["--exe --build --main --no-timing -Wno-STMTDLY"], - make_top => 1, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_long.py b/test_regress/t/t_timing_long.py new file mode 100755 index 000000000..a523eb21d --- /dev/null +++ b/test_regress/t/t_timing_long.py @@ -0,0 +1,63 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = test.obj_dir + "/t_timing_long.v" + +# Look for O(n^2) problems in process handling + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_timing_long.py\n") + + fh.write("\n") + fh.write("`ifdef TEST_VERBOSE\n") + fh.write(" `define MSG(m) $display m\n") + fh.write("`else\n") + fh.write(" `define MSG(m)\n") + fh.write("`endif\n") + fh.write("\n") + + fh.write("module t;\n") + fh.write("\n") + fh.write(" int cnt;\n") + fh.write("\n") + fh.write(" initial begin\n") + + n = 100 + for i in range(1, n): + # If statement around the timing is important to make the code scheduling + # mostly unpredictable + fh.write(" if (cnt == " + str(i - 1) + ") begin\n") + fh.write(" #1; ++cnt; `MSG((\"[%0t] cnt?=" + str(i) + "\", $time));" + + " if (cnt != " + str(i) + ") $stop;\n") + fh.write(" end\n") + + fh.write("\n") + fh.write(' $write("*-* All Finished *-*\\n");' + "\n") + fh.write(" $finish;\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen(test.top_filename) + +if test.have_coroutines: + test.compile(verilator_flags2=["--exe --build --main --timing"], make_top=1) + + test.execute() + +test.compile(verilator_flags2=["--exe --build --main --no-timing -Wno-STMTDLY"], make_top=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_nba_1.pl b/test_regress/t/t_timing_nba_1.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_nba_1.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_nba_1.py b/test_regress/t/t_timing_nba_1.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_nba_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_nba_2.pl b/test_regress/t/t_timing_nba_2.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_nba_2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_nba_2.py b/test_regress/t/t_timing_nba_2.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_nba_2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_nested_assignment_on_lhs.pl b/test_regress/t/t_timing_nested_assignment_on_lhs.pl deleted file mode 100755 index 0ebdb8a45..000000000 --- a/test_regress/t/t_timing_nested_assignment_on_lhs.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_net_delay.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_nested_assignment_on_lhs.py b/test_regress/t/t_timing_nested_assignment_on_lhs.py new file mode 100755 index 000000000..bc41b20a9 --- /dev/null +++ b/test_regress/t/t_timing_nested_assignment_on_lhs.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_net_delay.v" + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_off.pl b/test_regress/t/t_timing_off.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_off.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_off.py b/test_regress/t/t_timing_off.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_off.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_osc.out b/test_regress/t/t_timing_osc.out index c5d5b92a2..afcbdeb10 100644 --- a/test_regress/t/t_timing_osc.out +++ b/test_regress/t/t_timing_osc.out @@ -1,27 +1,27 @@ $version Generated by VerilatedVcd $end $timescale 1fs $end - $scope module TOP $end - $scope module tb_osc $end - $var wire 1 # dco_out $end - $scope module dco $end - $var real 64 ' coarse_cw $end - $var real 64 ' medium_cw $end - $var real 64 ) fine_cw $end - $var wire 1 # rf_out $end - $var real 64 + coarse_ofst $end - $var real 64 - coarse_res $end - $var real 64 / medium_ofst $end - $var real 64 1 medium_res $end - $var real 64 3 fine_ofst $end - $var real 64 5 fine_res $end - $var real 64 7 coarse_delay $end - $var real 64 9 medium_delay $end - $var real 64 ; fine_delay $end - $var real 64 = jitter $end - $var wire 1 $ coarse_out $end - $var wire 1 % medium_out $end - $var wire 1 & fine_out $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module tb_osc $end + $var wire 1 # dco_out $end + $scope module dco $end + $var real 64 ' coarse_cw $end + $var real 64 ' medium_cw $end + $var real 64 ) fine_cw $end + $var wire 1 # rf_out $end + $var real 64 + coarse_ofst $end + $var real 64 - coarse_res $end + $var real 64 / medium_ofst $end + $var real 64 1 medium_res $end + $var real 64 3 fine_ofst $end + $var real 64 5 fine_res $end + $var real 64 7 coarse_delay $end + $var real 64 9 medium_delay $end + $var real 64 ; fine_delay $end + $var real 64 = jitter $end + $var wire 1 $ coarse_out $end + $var wire 1 % medium_out $end + $var wire 1 & fine_out $end $upscope $end $upscope $end $enddefinitions $end @@ -46,11038 +46,44 @@ r3.82e-11 ; r0 = #38200 1& -#50000 -#76400 #88200 1# #89000 1% -#100000 -#114600 -#126400 #127200 0& -#138200 -#139000 -#150000 -#152800 -#164600 -#165400 -#176400 #177200 0# -#178000 -#188200 -#189000 -#191000 -#200000 -#202800 -#203600 -#214600 -#215400 -#216200 -#226400 -#227200 -#228000 -#229200 -#238200 -#239000 -#241000 -#241800 -#250000 -#252800 -#253600 -#254400 -#264600 -#265400 -#266200 -#267000 -#267400 -#276400 -#277200 -#278000 -#279200 -#280000 -#288200 -#289000 -#291000 -#291800 -#292600 -#300000 -#302800 -#303600 -#304400 -#305200 -#305600 -#314600 -#315400 -#316200 -#317000 -#317400 -#318200 -#326400 -#327200 -#328000 -#329200 -#330000 -#330800 -#338200 -#339000 -#341000 -#341800 -#342600 -#343400 -#343800 -#350000 -#352800 -#353600 -#354400 -#355200 -#355600 -#356000 -#356400 -#364600 -#365400 -#366200 -#367000 -#367400 -#368200 -#369000 -#376400 -#377200 -#378000 -#379200 -#380000 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-#2995600 -#2995800 -#2996000 -#2996200 -#2996400 -#2996600 -#2996800 -#2997000 -#2997200 -#2997400 -#2997600 -#2997800 -#2998000 -#2998200 -#2998400 -#2998600 -#2998800 -#2999000 -#2999200 -#2999400 -#2999600 -#2999800 #3000000 diff --git a/test_regress/t/t_timing_osc.pl b/test_regress/t/t_timing_osc.pl deleted file mode 100755 index 63ec0902b..000000000 --- a/test_regress/t/t_timing_osc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing --trace"], - make_main => 0, - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_timing_osc.py b/test_regress/t/t_timing_osc.py new file mode 100755 index 000000000..bc97f4d76 --- /dev/null +++ b/test_regress/t/t_timing_osc.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing --trace"], make_main=False) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_pong.pl b/test_regress/t/t_timing_pong.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_pong.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_pong.py b/test_regress/t/t_timing_pong.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_pong.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_protect.pl b/test_regress/t/t_timing_protect.pl deleted file mode 100755 index 84a4c7ce0..000000000 --- a/test_regress/t/t_timing_protect.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->have_coroutines) { - skip("No coroutine support"); -} -else { - top_filename("t/t_timing_fork_join.v"); # Contains all relevant constructs - - compile( - verilator_flags2 => ["--exe --main --timing --protect-ids", - "--protect-key SECRET_KEY"], - ); - - execute( - check_finished => 1, - ); - - if ($Self->{vlt_all}) { - # Check for secret in any outputs - my $any; - foreach my $filename (glob $Self->{obj_dir} . "/*.[ch]*") { - file_grep_not($filename, qr/event[123]/i); - file_grep_not($filename, qr/t_timing_fork_join/i); - $any = 1; - } - $any or $Self->error("No outputs found"); - -} - -} - -ok(1); -1; diff --git a/test_regress/t/t_timing_protect.py b/test_regress/t/t_timing_protect.py new file mode 100755 index 000000000..9e828acb2 --- /dev/null +++ b/test_regress/t/t_timing_protect.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_timing_fork_join.v" # Contains all relevant constructs + +if not test.have_coroutines: + test.skip("No coroutine support") + +test.compile(verilator_flags2=["--exe --main --timing --protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +if test.vlt_all: + # Check for secret in any outputs + for filename in test.glob_some(test.obj_dir + "/*.[ch]*"): + test.file_grep_not(filename, r'event[123]') + test.file_grep_not(filename, r't_timing_fork_join') + +test.passes() diff --git a/test_regress/t/t_timing_reentry.pl b/test_regress/t/t_timing_reentry.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_reentry.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_reentry.py b/test_regress/t/t_timing_reentry.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_reentry.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_sched.pl b/test_regress/t/t_timing_sched.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_sched.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_sched.py b/test_regress/t/t_timing_sched.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_sched.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_sched_if.pl b/test_regress/t/t_timing_sched_if.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_sched_if.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_sched_if.py b/test_regress/t/t_timing_sched_if.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_sched_if.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_sched_nba.pl b/test_regress/t/t_timing_sched_nba.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_sched_nba.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_sched_nba.py b/test_regress/t/t_timing_sched_nba.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_sched_nba.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_split.pl b/test_regress/t/t_timing_split.pl deleted file mode 100755 index 2703f4761..000000000 --- a/test_regress/t/t_timing_split.pl +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing --output-split-cfuncs 1 -CFLAGS -Werror"], - ); - -execute( - check_finished => 1, - ); - -check_splits(); - -ok(1); -1; - -sub check_splits { - my $got1; - my $gotSyms1; - return if !$Self->have_coroutines; - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - if ($file =~ /Syms__1/) { - $gotSyms1 = 1; - } elsif ($file =~ /__1/) { - $got1 = 1; - } - } - $got1 or error("No __1 split file found"); - $gotSyms1 or error("No Syms__1 split file found"); -} diff --git a/test_regress/t/t_timing_split.py b/test_regress/t/t_timing_split.py new file mode 100755 index 000000000..54cfda002 --- /dev/null +++ b/test_regress/t/t_timing_split.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + + +def check_splits(): + got1 = False + gotSyms1 = False + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'Syms__1', filename): + gotSyms1 = True + elif re.search(r'__1', filename): + got1 = True + if not got1: + test.error("No __1 split file found") + if not gotSyms1: + test.error("No Syms__1 split file found") + + +test.compile(timing_loop=True, + verilator_flags2=["--timing --output-split-cfuncs 1 -CFLAGS -Werror"]) + +test.execute() + +if test.have_coroutines: + check_splits() + +test.passes() diff --git a/test_regress/t/t_timing_strobe.pl b/test_regress/t/t_timing_strobe.pl deleted file mode 100755 index f686c3eec..000000000 --- a/test_regress/t/t_timing_strobe.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_strobe.py b/test_regress/t/t_timing_strobe.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_timing_strobe.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_strobe.v b/test_regress/t/t_timing_strobe.v index 8c1057fb4..bc69c89e1 100644 --- a/test_regress/t/t_timing_strobe.v +++ b/test_regress/t/t_timing_strobe.v @@ -4,11 +4,8 @@ // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); + event e1; event e2; int v = 0; diff --git a/test_regress/t/t_timing_timescale.out b/test_regress/t/t_timing_timescale.out index 041fa0bc7..e28ab2ef6 100644 --- a/test_regress/t/t_timing_timescale.out +++ b/test_regress/t/t_timing_timescale.out @@ -20,7 +20,7 @@ [9e-06] clkb is 1 [9.5e-06] clkb is 0 [1e-05] clkb is 1 -[1e-05] Finishing (TOP.t.bot) +[1e-05] Finishing (t.bot) *-* All Finished *-* -[10500] final (TOP.t) -[1.05e-05] final (TOP.t.bot) count was 21 +[10500] final (t) +[1.05e-05] final (t.bot) count was 21 diff --git a/test_regress/t/t_timing_timescale.pl b/test_regress/t/t_timing_timescale.pl deleted file mode 100755 index f686c3eec..000000000 --- a/test_regress/t/t_timing_timescale.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_timescale.py b/test_regress/t/t_timing_timescale.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_timing_timescale.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_trace.out b/test_regress/t/t_timing_trace.out index c5a28236b..f5a47ca02 100644 --- a/test_regress/t/t_timing_trace.out +++ b/test_regress/t/t_timing_trace.out @@ -1,17 +1,17 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - $scope module TOP $end - $scope module t $end - $var wire 32 * CLK_PERIOD [31:0] $end - $var wire 32 + CLK_HALF_PERIOD [31:0] $end - $var wire 1 # rst $end - $var wire 1 ( clk $end - $var wire 1 $ a $end - $var wire 1 ) b $end - $var wire 1 % c $end - $var wire 1 & d $end - $var event 1 ' ev $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 32 * CLK_PERIOD [31:0] $end + $var wire 32 + CLK_HALF_PERIOD [31:0] $end + $var wire 1 # rst $end + $var wire 1 ( clk $end + $var wire 1 $ a $end + $var wire 1 ) b $end + $var wire 1 % c $end + $var wire 1 & d $end + $var event 1 ' ev $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_timing_trace.pl b/test_regress/t/t_timing_trace.pl deleted file mode 100755 index e968634de..000000000 --- a/test_regress/t/t_timing_trace.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing --trace -Wno-MINTYPMAXDLY"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_timing_trace.py b/test_regress/t/t_timing_trace.py new file mode 100755 index 000000000..6a9d5689d --- /dev/null +++ b/test_regress/t/t_timing_trace.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing --trace -Wno-MINTYPMAXDLY"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_trace_fst.out b/test_regress/t/t_timing_trace_fst.out index 0de0227ee..b95eb3cdb 100644 --- a/test_regress/t/t_timing_trace_fst.out +++ b/test_regress/t/t_timing_trace_fst.out @@ -1,5 +1,5 @@ $date - Sun Nov 5 12:08:16 2023 + Sun Sep 22 22:53:52 2024 $end $version @@ -8,7 +8,8 @@ $end $timescale 1ps $end -$scope module TOP $end +$scope module $rootio $end +$upscope $end $scope module t $end $var parameter 32 ! CLK_PERIOD [31:0] $end $var parameter 32 " CLK_HALF_PERIOD [31:0] $end @@ -20,7 +21,6 @@ $var logic 1 ' c $end $var logic 1 ( d $end $var event 1 ) ev $end $upscope $end -$upscope $end $enddefinitions $end #0 $dumpvars diff --git a/test_regress/t/t_timing_trace_fst.pl b/test_regress/t/t_timing_trace_fst.pl deleted file mode 100755 index 2e8d5f1f5..000000000 --- a/test_regress/t/t_timing_trace_fst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 Yves Mathieu. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_trace.v"); - -compile( - verilator_flags2 => ["--exe --main --timing --trace-fst -Wno-MINTYPMAXDLY"], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_timing_trace_fst.py b/test_regress/t/t_timing_trace_fst.py new file mode 100755 index 000000000..727cb9ff6 --- /dev/null +++ b/test_regress/t/t_timing_trace_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_trace.v" + +test.compile(verilator_flags2=["--exe --main --timing --trace-fst -Wno-MINTYPMAXDLY"]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_unset1.pl b/test_regress/t/t_timing_unset1.pl deleted file mode 100755 index 167a6cf70..000000000 --- a/test_regress/t/t_timing_unset1.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_notiming.v"); - -compile( - # --timing/--no-timing not specified - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_unset1.py b/test_regress/t/t_timing_unset1.py new file mode 100755 index 000000000..d50e1d8f9 --- /dev/null +++ b/test_regress/t/t_timing_unset1.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_notiming.v" + +test.compile( + # --timing/--no-timing not specified + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_unset2.pl b/test_regress/t/t_timing_unset2.pl deleted file mode 100755 index be9ccffa3..000000000 --- a/test_regress/t/t_timing_unset2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_off.v"); - -compile( - # --timing/--no-timing not specified - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_unset2.py b/test_regress/t/t_timing_unset2.py new file mode 100755 index 000000000..e19a52246 --- /dev/null +++ b/test_regress/t/t_timing_unset2.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_off.v" + +test.compile( + # --timing/--no-timing not specified + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_unset3.pl b/test_regress/t/t_timing_unset3.pl deleted file mode 100755 index 8c206a0f0..000000000 --- a/test_regress/t/t_timing_unset3.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clocking_notiming.v"); - -compile( - # --timing/--no-timing not specified - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_unset3.py b/test_regress/t/t_timing_unset3.py new file mode 100755 index 000000000..5ff23db31 --- /dev/null +++ b/test_regress/t/t_timing_unset3.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clocking_notiming.v" + +test.compile( + # --timing/--no-timing not specified + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_wait1.pl b/test_regress/t/t_timing_wait1.pl deleted file mode 100755 index 3f4a19511..000000000 --- a/test_regress/t/t_timing_wait1.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing -Wno-WAITCONST"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_wait1.py b/test_regress/t/t_timing_wait1.py new file mode 100755 index 000000000..d1f037fe6 --- /dev/null +++ b/test_regress/t/t_timing_wait1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing -Wno-WAITCONST"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_wait2.pl b/test_regress/t/t_timing_wait2.pl deleted file mode 100755 index f686c3eec..000000000 --- a/test_regress/t/t_timing_wait2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_wait2.py b/test_regress/t/t_timing_wait2.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_timing_wait2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_wait3.pl b/test_regress/t/t_timing_wait3.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_timing_wait3.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_wait3.py b/test_regress/t/t_timing_wait3.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_wait3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_wait_long.pl b/test_regress/t/t_timing_wait_long.pl deleted file mode 100755 index f686c3eec..000000000 --- a/test_regress/t/t_timing_wait_long.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_wait_long.py b/test_regress/t/t_timing_wait_long.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_timing_wait_long.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_write_expr.pl b/test_regress/t/t_timing_write_expr.pl deleted file mode 100755 index bc632ee01..000000000 --- a/test_regress/t/t_timing_write_expr.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - make_main => 0, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_write_expr.py b/test_regress/t/t_timing_write_expr.py new file mode 100755 index 000000000..d05629d98 --- /dev/null +++ b/test_regress/t/t_timing_write_expr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"], make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_zerodly.pl b/test_regress/t/t_timing_zerodly.pl deleted file mode 100755 index 9d615c1c3..000000000 --- a/test_regress/t/t_timing_zerodly.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_zerodly.py b/test_regress/t/t_timing_zerodly.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_zerodly.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_zerodly_consecutive.pl b/test_regress/t/t_timing_zerodly_consecutive.pl deleted file mode 100755 index 0d96fde8d..000000000 --- a/test_regress/t/t_timing_zerodly_consecutive.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_zerodly_consecutive.py b/test_regress/t/t_timing_zerodly_consecutive.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_zerodly_consecutive.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_zerodly_unsup.pl b/test_regress/t/t_timing_zerodly_unsup.pl deleted file mode 100755 index 5439c7838..000000000 --- a/test_regress/t/t_timing_zerodly_unsup.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_zerodly_unsup.py b/test_regress/t/t_timing_zerodly_unsup.py new file mode 100755 index 000000000..ea4425d51 --- /dev/null +++ b/test_regress/t/t_timing_zerodly_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_abort.pl b/test_regress/t/t_trace_abort.pl deleted file mode 100755 index 78c5ee50c..000000000 --- a/test_regress/t/t_trace_abort.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - fails => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_abort.py b/test_regress/t/t_trace_abort.py new file mode 100755 index 000000000..ed957bcf9 --- /dev/null +++ b/test_regress/t/t_trace_abort.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute(fails=True) + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_abort_fst.pl b/test_regress/t/t_trace_abort_fst.pl deleted file mode 100755 index a57dec132..000000000 --- a/test_regress/t/t_trace_abort_fst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_abort.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst'], - ); - -execute( - fails => 1, - ); - -fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_abort_fst.py b/test_regress/t/t_trace_abort_fst.py new file mode 100755 index 000000000..d3606912a --- /dev/null +++ b/test_regress/t/t_trace_abort_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_abort.v" + +test.compile(verilator_flags2=['--cc --trace-fst']) + +test.execute(fails=True) + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_abort_fst_sc.pl b/test_regress/t/t_trace_abort_fst_sc.pl deleted file mode 100755 index cef721403..000000000 --- a/test_regress/t/t_trace_abort_fst_sc.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_abort.v"); - - compile( - verilator_flags2 => ['--sc --trace-fst'], - ); - - execute( - fails => 1, - ); - - fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename}); -} -ok(1); -1; diff --git a/test_regress/t/t_trace_abort_fst_sc.py b/test_regress/t/t_trace_abort_fst_sc.py new file mode 100755 index 000000000..1e6f9c314 --- /dev/null +++ b/test_regress/t/t_trace_abort_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_abort.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst']) + +test.execute(fails=True) + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array.pl b/test_regress/t/t_trace_array.pl deleted file mode 100755 index ff327974a..000000000 --- a/test_regress/t/t_trace_array.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --trace --trace-structs'], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array.py b/test_regress/t/t_trace_array.py new file mode 100755 index 000000000..e178ccb9b --- /dev/null +++ b/test_regress/t/t_trace_array.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --trace --trace-structs']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst.pl b/test_regress/t/t_trace_array_fst.pl deleted file mode 100755 index f09bea826..000000000 --- a/test_regress/t/t_trace_array_fst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_array.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-structs'], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst.py b/test_regress/t/t_trace_array_fst.py new file mode 100755 index 000000000..7bb8aa3c4 --- /dev/null +++ b/test_regress/t/t_trace_array_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_portable.pl b/test_regress/t/t_trace_array_fst_portable.pl deleted file mode 100755 index 3a34b9113..000000000 --- a/test_regress/t/t_trace_array_fst_portable.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_array.v"); -golden_filename("t/t_trace_array_fst.out"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-structs', - '-CFLAGS -DVL_PORTABLE_ONLY'], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_portable.py b/test_regress/t/t_trace_array_fst_portable.py new file mode 100755 index 000000000..3942969f8 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_portable.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst.out" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_portable_sc.pl b/test_regress/t/t_trace_array_fst_portable_sc.pl deleted file mode 100755 index 2476e5765..000000000 --- a/test_regress/t/t_trace_array_fst_portable_sc.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_array.v"); - golden_filename("t/t_trace_array_fst_sc.out"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-structs', - '-CFLAGS -DVL_PORTABLE_ONLY'], - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_portable_sc.py b/test_regress/t/t_trace_array_fst_portable_sc.py new file mode 100755 index 000000000..024b64e9b --- /dev/null +++ b/test_regress/t/t_trace_array_fst_portable_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst_sc.out" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_sc.pl b/test_regress/t/t_trace_array_fst_sc.pl deleted file mode 100755 index dda6a138a..000000000 --- a/test_regress/t/t_trace_array_fst_sc.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_array.v"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-structs'], - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_sc.py b/test_regress/t/t_trace_array_fst_sc.py new file mode 100755 index 000000000..1f95faff6 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_1.pl b/test_regress/t/t_trace_array_fst_threads_1.pl deleted file mode 100755 index c75beb0ca..000000000 --- a/test_regress/t/t_trace_array_fst_threads_1.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_array.v"); -golden_filename("t/t_trace_array_fst.out"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-threads 1 --trace-structs'], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_threads_1.py b/test_regress/t/t_trace_array_fst_threads_1.py new file mode 100755 index 000000000..9c19b8e41 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_threads_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst.out" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 1 --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_1_sc.pl b/test_regress/t/t_trace_array_fst_threads_1_sc.pl deleted file mode 100755 index 5f7e2bb69..000000000 --- a/test_regress/t/t_trace_array_fst_threads_1_sc.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_array.v"); - golden_filename("t/t_trace_array_fst_sc.out"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-threads 1 --trace-structs'], - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_threads_1_sc.py b/test_regress/t/t_trace_array_fst_threads_1_sc.py new file mode 100755 index 000000000..b788ded44 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_threads_1_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst_sc.out" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 1 --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_2.pl b/test_regress/t/t_trace_array_fst_threads_2.pl deleted file mode 100755 index 75bbc7391..000000000 --- a/test_regress/t/t_trace_array_fst_threads_2.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_array.v"); -golden_filename("t/t_trace_array_fst.out"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-threads 2 --trace-structs'], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_threads_2.py b/test_regress/t/t_trace_array_fst_threads_2.py new file mode 100755 index 000000000..95c7a0913 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_threads_2.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst.out" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 2 --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_2_sc.pl b/test_regress/t/t_trace_array_fst_threads_2_sc.pl deleted file mode 100755 index 1cfe67da8..000000000 --- a/test_regress/t/t_trace_array_fst_threads_2_sc.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_array.v"); - golden_filename("t/t_trace_array_fst_sc.out"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-threads 2 --trace-structs'], - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_threads_2_sc.py b/test_regress/t/t_trace_array_fst_threads_2_sc.py new file mode 100755 index 000000000..34965a006 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_threads_2_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst_sc.out" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 2 --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_threads_1.pl b/test_regress/t/t_trace_array_threads_1.pl deleted file mode 100755 index 9f4332d28..000000000 --- a/test_regress/t/t_trace_array_threads_1.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_array.v"); -golden_filename("t/t_trace_array.out"); - -compile( - verilator_flags2 => ['--cc --trace --trace-threads 1 --trace-structs'], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_threads_1.py b/test_regress/t/t_trace_array_threads_1.py new file mode 100755 index 000000000..3400f7771 --- /dev/null +++ b/test_regress/t/t_trace_array_threads_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array.out" + +test.compile(verilator_flags2=['--cc --trace --trace-threads 1 --trace-structs']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_ascendingrange.pl b/test_regress/t/t_trace_ascendingrange.pl deleted file mode 100755 index aedb9ce36..000000000 --- a/test_regress/t/t_trace_ascendingrange.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# Strangely, asking for more threads makes it go away. -compile( - verilator_flags2 => ['--cc --trace --trace-params -Wno-ASCRANGE'], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_ascendingrange.py b/test_regress/t/t_trace_ascendingrange.py new file mode 100755 index 000000000..d90888a48 --- /dev/null +++ b/test_regress/t/t_trace_ascendingrange.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# Strangely, asking for more threads makes it go away. +test.compile(verilator_flags2=['--cc --trace --trace-params -Wno-ASCRANGE'], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_ascendingrange_fst.pl b/test_regress/t/t_trace_ascendingrange_fst.pl deleted file mode 100755 index 54e75cec9..000000000 --- a/test_regress/t/t_trace_ascendingrange_fst.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_ascendingrange.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# Strangely, asking for more threads makes it go away. -compile( - verilator_flags2 => ['--cc --trace-fst --trace-params -Wno-ASCRANGE'], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - check_finished => 1, - ); - -fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_ascendingrange_fst.py b/test_regress/t/t_trace_ascendingrange_fst.py new file mode 100755 index 000000000..2f812bb4c --- /dev/null +++ b/test_regress/t/t_trace_ascendingrange_fst.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ascendingrange.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# Strangely, asking for more threads makes it go away. +test.compile(verilator_flags2=['--cc --trace-fst --trace-params -Wno-ASCRANGE'], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_ascendingrange_fst_sc.pl b/test_regress/t/t_trace_ascendingrange_fst_sc.pl deleted file mode 100755 index 864a69b97..000000000 --- a/test_regress/t/t_trace_ascendingrange_fst_sc.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_ascendingrange.v"); - - # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. - # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. - # Strangely, asking for more threads makes it go away. - compile( - verilator_flags2 => ['--sc --trace-fst --trace-params -Wno-ASCRANGE'], - threads => $Self->{vltmt} ? 6 : 1 - ); - - execute( - check_finished => 1, - ); - - fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_ascendingrange_fst_sc.py b/test_regress/t/t_trace_ascendingrange_fst_sc.py new file mode 100755 index 000000000..a01e6692e --- /dev/null +++ b/test_regress/t/t_trace_ascendingrange_fst_sc.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ascendingrange.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# Strangely, asking for more threads makes it go away. +test.compile(verilator_flags2=['--sc --trace-fst --trace-params -Wno-ASCRANGE'], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_binary.out b/test_regress/t/t_trace_binary.out index 32d4f8ec5..6ba7d249c 100644 --- a/test_regress/t/t_trace_binary.out +++ b/test_regress/t/t_trace_binary.out @@ -1,11 +1,9 @@ $version Generated by VerilatedVcd $end -$date Sun Oct 9 14:08:37 2022 $end $timescale 1ps $end - - $scope module TOP $end - $scope module t $end - $var wire 32 # sig [31:0] $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 32 # sig [31:0] $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_binary.pl b/test_regress/t/t_trace_binary.pl deleted file mode 100755 index afc204bcb..000000000 --- a/test_regress/t/t_trace_binary.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--binary --trace'], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_binary.py b/test_regress/t/t_trace_binary.py new file mode 100755 index 000000000..2737cb863 --- /dev/null +++ b/test_regress/t/t_trace_binary.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir " + test.obj_dir, "--debug-check" + ], + verilator_flags2=['--binary --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_binary_flag_off.pl b/test_regress/t/t_trace_binary_flag_off.pl deleted file mode 100755 index 521677772..000000000 --- a/test_regress/t/t_trace_binary_flag_off.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_binary.v"); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--binary'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_binary_flag_off.py b/test_regress/t/t_trace_binary_flag_off.py new file mode 100755 index 000000000..2e846b7e1 --- /dev/null +++ b/test_regress/t/t_trace_binary_flag_off.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_binary.v" + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir " + test.obj_dir, "--debug-check" + ], + verilator_flags2=['--binary']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_cat.pl b/test_regress/t/t_trace_cat.pl deleted file mode 100755 index a34973212..000000000 --- a/test_regress/t/t_trace_cat.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_cat.cpp"], - ); - -execute( - check_finished => 1, - ); - -system("cat $Self->{obj_dir}/simpart_0000.vcd " - . " $Self->{obj_dir}/simpart_0000_cat*.vcd > $Self->{obj_dir}/simall.vcd"); - -vcd_identical("$Self->{obj_dir}/simall.vcd", - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_cat.py b/test_regress/t/t_trace_cat.py new file mode 100755 index 000000000..5b89b99fd --- /dev/null +++ b/test_regress/t/t_trace_cat.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +os.system("cat " + test.obj_dir + "/simpart_0000.vcd " + " " + test.obj_dir + + "/simpart_0000_cat*.vcd > " + test.obj_dir + "/simall.vcd") + +test.vcd_identical(test.obj_dir + "/simall.vcd", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_cat_fst.pl b/test_regress/t/t_trace_cat_fst.pl deleted file mode 100755 index 8715369c7..000000000 --- a/test_regress/t/t_trace_cat_fst.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace-fst --exe $Self->{t_dir}/t_trace_cat_fst.cpp"], - ); - -execute( - check_finished => 1, - ); - -fst_identical("$Self->{obj_dir}/simpart_0000.fst", - "t/$Self->{name}_0000.out"); -fst_identical("$Self->{obj_dir}/simpart_0100.fst", - "t/$Self->{name}_0100.out"); - -ok(1); -1; diff --git a/test_regress/t/t_trace_cat_fst.py b/test_regress/t/t_trace_cat_fst.py new file mode 100755 index 000000000..9f94e690c --- /dev/null +++ b/test_regress/t/t_trace_cat_fst.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["--trace-fst --exe", test.pli_filename]) + +test.execute() + +test.fst_identical(test.obj_dir + "/simpart_0000.fst", "t/" + test.name + "_0000.out") +test.fst_identical(test.obj_dir + "/simpart_0100.fst", "t/" + test.name + "_0100.out") + +test.passes() diff --git a/test_regress/t/t_trace_cat_renew.pl b/test_regress/t/t_trace_cat_renew.pl deleted file mode 100755 index 8ea59e856..000000000 --- a/test_regress/t/t_trace_cat_renew.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_cat.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_cat.cpp"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simpart_0000.vcd", - "t/$Self->{name}_0000.out"); -vcd_identical("$Self->{obj_dir}/simpart_0100.vcd", - "t/$Self->{name}_0100.out"); - -ok(1); -1; diff --git a/test_regress/t/t_trace_cat_renew.py b/test_regress/t/t_trace_cat_renew.py new file mode 100755 index 000000000..99db77d20 --- /dev/null +++ b/test_regress/t/t_trace_cat_renew.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_cat.cpp" +test.top_filename = "t/t_trace_cat.v" + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.obj_dir + "/simpart_0000.vcd", "t/" + test.name + "_0000.out") +test.vcd_identical(test.obj_dir + "/simpart_0100.vcd", "t/" + test.name + "_0100.out") + +test.passes() diff --git a/test_regress/t/t_trace_cat_reopen.pl b/test_regress/t/t_trace_cat_reopen.pl deleted file mode 100755 index 8ea59e856..000000000 --- a/test_regress/t/t_trace_cat_reopen.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_cat.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_cat.cpp"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simpart_0000.vcd", - "t/$Self->{name}_0000.out"); -vcd_identical("$Self->{obj_dir}/simpart_0100.vcd", - "t/$Self->{name}_0100.out"); - -ok(1); -1; diff --git a/test_regress/t/t_trace_cat_reopen.py b/test_regress/t/t_trace_cat_reopen.py new file mode 100755 index 000000000..99db77d20 --- /dev/null +++ b/test_regress/t/t_trace_cat_reopen.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_cat.cpp" +test.top_filename = "t/t_trace_cat.v" + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.obj_dir + "/simpart_0000.vcd", "t/" + test.name + "_0000.out") +test.vcd_identical(test.obj_dir + "/simpart_0100.vcd", "t/" + test.name + "_0100.out") + +test.passes() diff --git a/test_regress/t/t_trace_class.out b/test_regress/t/t_trace_class.out index 41b74f075..caa31e989 100644 --- a/test_regress/t/t_trace_class.out +++ b/test_regress/t/t_trace_class.out @@ -1,9 +1,9 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - $scope module TOP $end - $scope module $unit::Cls__P0__Vclpkg $end - $var wire 32 # PARAM [31:0] $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module $unit::Cls__P0__Vclpkg $end + $var wire 32 # PARAM [31:0] $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_class.pl b/test_regress/t/t_trace_class.pl deleted file mode 100755 index 7d0046bfc..000000000 --- a/test_regress/t/t_trace_class.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # verilator_flags2 => ['--binary --trace'], - verilator_flags2 => ['--binary --trace'], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_class.py b/test_regress/t/t_trace_class.py new file mode 100755 index 000000000..c57dc225f --- /dev/null +++ b/test_regress/t/t_trace_class.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # verilator_flags2 = ['--binary --trace'], + verilator_flags2=['--binary --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex.pl b/test_regress/t/t_trace_complex.pl deleted file mode 100755 index f02e405e8..000000000 --- a/test_regress/t/t_trace_complex.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - check_finished => 1, - ); - -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_strp_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arrp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_arrp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arru\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arrp\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_strp\[/); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex.py b/test_regress/t/t_trace_complex.py new file mode 100755 index 000000000..b7da0f5f5 --- /dev/null +++ b/test_regress/t/t_trace_complex.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute() + +test.file_grep(test.trace_filename, r' v_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_strp ') +test.file_grep(test.trace_filename, r' v_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arrp\[') +test.file_grep(test.trace_filename, r' v_arru_arru\[') +test.file_grep(test.trace_filename, r' v_arru_strp\[') +test.file_grep(test.trace_filename, r' v_strp ') +test.file_grep(test.trace_filename, r' v_strp_strp ') + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v index 763aef06c..354f83f57 100644 --- a/test_regress/t/t_trace_complex.v +++ b/test_regress/t/t_trace_complex.v @@ -8,11 +8,11 @@ bit global_bit; module t (clk); input clk; - integer cyc = 0; + integer cyc = 0; typedef struct packed { - bit b1; - bit b0; + bit b1; + bit b0; } strp_t; typedef struct packed { @@ -20,7 +20,7 @@ module t (clk); strp_t x0; } strp_strp_t; - typedef union packed { + typedef union packed { strp_t x1; strp_t x0; } unip_strp_t; @@ -30,7 +30,7 @@ module t (clk); typedef strp_t [4:3] arrp_strp_t; - typedef bit arru_t [2:1]; + typedef bit arru_t [2:1]; typedef arru_t arru_arru_t [4:3]; typedef arrp_t arru_arrp_t [4:3]; typedef strp_t arru_strp_t [4:3]; @@ -46,35 +46,35 @@ module t (clk); arru_arrp_t v_arru_arrp; arru_strp_t v_arru_strp; - real v_real; - real v_arr_real [2]; - string v_string; - chandle v_chandle; + real v_real; + real v_arr_real [2]; + string v_string; + chandle v_chandle; - string v_assoc[string]; + string v_assoc[string]; initial v_assoc["key"] = "value"; - typedef struct packed { - logic [31:0] data; + typedef struct packed { + logic [31:0] data; } str32_t; str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0 initial v_str32x2[0] = 32'hff; initial v_str32x2[1] = 0; - typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t; + typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t; enumed_t v_enumed; enumed_t v_enumed2; - typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t; + typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t; enumb_t v_enumb; - typedef struct packed { + typedef struct packed { enumb_t a; enumb_t b; } enumb2_str_t; enumb2_str_t v_enumb2_str; - logic [7:0] unpacked_array[-2:0]; + logic [7:0] unpacked_array[-2:0]; - bit LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; + bit LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; p #(.PARAM(2)) p2 (); p #(.PARAM(3)) p3 (); diff --git a/test_regress/t/t_trace_complex_fst.pl b/test_regress/t/t_trace_complex_fst.pl deleted file mode 100755 index 6ec35cae7..000000000 --- a/test_regress/t/t_trace_complex_fst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst'], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst.py b/test_regress/t/t_trace_complex_fst.py new file mode 100755 index 000000000..2d1104166 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +test.compile(verilator_flags2=['--cc --trace-fst']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_fst_sc.pl b/test_regress/t/t_trace_complex_fst_sc.pl deleted file mode 100755 index 054451209..000000000 --- a/test_regress/t/t_trace_complex_fst_sc.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_complex.v"); - - compile( - verilator_flags2 => ['--sc --trace-fst'], - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst_sc.py b/test_regress/t/t_trace_complex_fst_sc.py new file mode 100755 index 000000000..0e4fe6ff3 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_1.pl b/test_regress/t/t_trace_complex_fst_threads_1.pl deleted file mode 100755 index a43a89337..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_1.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); -golden_filename("t/t_trace_complex_fst.out"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-threads 1'], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst_threads_1.py b/test_regress/t/t_trace_complex_fst_threads_1.py new file mode 100755 index 000000000..b1a3f7e85 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_threads_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex_fst.out" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 1']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_1_sc.pl b/test_regress/t/t_trace_complex_fst_threads_1_sc.pl deleted file mode 100755 index 94b4913bd..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_1_sc.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_complex.v"); - golden_filename("t/t_trace_complex_fst_sc.out"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-threads 1'], - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst_threads_1_sc.py b/test_regress/t/t_trace_complex_fst_threads_1_sc.py new file mode 100755 index 000000000..6a62c90e9 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_threads_1_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex_fst_sc.out" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 1']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_2.pl b/test_regress/t/t_trace_complex_fst_threads_2.pl deleted file mode 100755 index b2c4721c7..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_2.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); -golden_filename("t/t_trace_complex_fst.out"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-threads 2'], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst_threads_2.py b/test_regress/t/t_trace_complex_fst_threads_2.py new file mode 100755 index 000000000..451fad715 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_threads_2.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex_fst.out" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 2']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_2_sc.pl b/test_regress/t/t_trace_complex_fst_threads_2_sc.pl deleted file mode 100755 index cb8a45396..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_2_sc.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_complex.v"); - golden_filename("t/t_trace_complex_fst_sc.out"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-threads 2'], - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst_threads_2_sc.py b/test_regress/t/t_trace_complex_fst_threads_2_sc.py new file mode 100755 index 000000000..7ddc967bd --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_threads_2_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex_fst_sc.out" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 2']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_params.pl b/test_regress/t/t_trace_complex_params.pl deleted file mode 100755 index 8f72740a0..000000000 --- a/test_regress/t/t_trace_complex_params.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); - -compile( - verilator_flags2 => ['--cc --trace --no-trace-structs --trace-params'], - ); - -execute( - check_finished => 1, - ); - -file_grep("$Self->{obj_dir}/simx.vcd", qr/ PARAM /); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_params.py b/test_regress/t/t_trace_complex_params.py new file mode 100755 index 000000000..566dc8a73 --- /dev/null +++ b/test_regress/t/t_trace_complex_params.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +test.compile(verilator_flags2=['--cc --trace --no-trace-structs --trace-params']) + +test.execute() + +test.file_grep(test.trace_filename, r' PARAM ') + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_params_fst.pl b/test_regress/t/t_trace_complex_params_fst.pl deleted file mode 100755 index aba062c24..000000000 --- a/test_regress/t/t_trace_complex_params_fst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst --no-trace-structs --trace-params'], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_params_fst.py b/test_regress/t/t_trace_complex_params_fst.py new file mode 100755 index 000000000..cd052c278 --- /dev/null +++ b/test_regress/t/t_trace_complex_params_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +test.compile(verilator_flags2=['--cc --trace-fst --no-trace-structs --trace-params']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_params_fst_sc.pl b/test_regress/t/t_trace_complex_params_fst_sc.pl deleted file mode 100755 index 6d12ba052..000000000 --- a/test_regress/t/t_trace_complex_params_fst_sc.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_complex.v"); - - compile( - verilator_flags2 => ['--sc --trace-fst --no-trace-structs --trace-params'], - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_params_fst_sc.py b/test_regress/t/t_trace_complex_params_fst_sc.py new file mode 100755 index 000000000..99007833e --- /dev/null +++ b/test_regress/t/t_trace_complex_params_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --no-trace-structs --trace-params']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_portable.pl b/test_regress/t/t_trace_complex_portable.pl deleted file mode 100755 index 8095d31aa..000000000 --- a/test_regress/t/t_trace_complex_portable.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Same test as t_trace_complex, but exercising the old VCD tracing API - -scenarios(vlt => 1); - -top_filename("t/t_trace_complex.v"); -golden_filename("t/t_trace_complex.out"); - -compile( - verilator_flags2 => ['--cc --trace -CFLAGS -DVL_PORTABLE_ONLY'], - ); - -execute( - check_finished => 1, - ); - -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_strp_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arrp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_arrp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arru\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arrp\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_strp\[/); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_portable.py b/test_regress/t/t_trace_complex_portable.py new file mode 100755 index 000000000..4e0bdcff1 --- /dev/null +++ b/test_regress/t/t_trace_complex_portable.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Same test as t_trace_complex, but exercising the old VCD tracing API + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex.out" + +test.compile(verilator_flags2=['--cc --trace -CFLAGS -DVL_PORTABLE_ONLY']) + +test.execute() + +test.file_grep(test.trace_filename, r' v_strp ') +test.file_grep(test.trace_filename, r' v_strp_strp ') +test.file_grep(test.trace_filename, r' v_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_strp ') +test.file_grep(test.trace_filename, r' v_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arrp\[') +test.file_grep(test.trace_filename, r' v_arru_strp\[') + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_structs.pl b/test_regress/t/t_trace_complex_structs.pl deleted file mode 100755 index 8bf726485..000000000 --- a/test_regress/t/t_trace_complex_structs.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); - -compile( - verilator_flags2 => ['--cc --trace --trace-structs --no-trace-params'], - ); - -execute( - check_finished => 1, - ); - -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_strp_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arrp /); -file_grep_not("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_arrp /); -file_grep_not("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arru\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arrp\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_strp\[/); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_structs.py b/test_regress/t/t_trace_complex_structs.py new file mode 100755 index 000000000..9e8df28e9 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +test.compile(verilator_flags2=['--cc --trace --trace-structs --no-trace-params']) + +test.execute() + +test.file_grep(test.trace_filename, r' v_strp ') +test.file_grep(test.trace_filename, r' v_strp_strp ') +test.file_grep(test.trace_filename, r' v_arrp ') +test.file_grep_not(test.trace_filename, r' v_arrp_arrp ') +test.file_grep_not(test.trace_filename, r' v_arrp_strp ') +test.file_grep(test.trace_filename, r' v_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arrp\[') +test.file_grep(test.trace_filename, r' v_arru_strp\[') + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_structs_fst.pl b/test_regress/t/t_trace_complex_structs_fst.pl deleted file mode 100755 index def4c9f46..000000000 --- a/test_regress/t/t_trace_complex_structs_fst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-structs --no-trace-params'], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_structs_fst.py b/test_regress/t/t_trace_complex_structs_fst.py new file mode 100755 index 000000000..879cd5e97 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-structs --no-trace-params']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.pl b/test_regress/t/t_trace_complex_structs_fst_sc.pl deleted file mode 100755 index dda24acc7..000000000 --- a/test_regress/t/t_trace_complex_structs_fst_sc.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_complex.v"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-structs --no-trace-params'], - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.py b/test_regress/t/t_trace_complex_structs_fst_sc.py new file mode 100755 index 000000000..4e88e7f62 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-structs --no-trace-params']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_threads_1.pl b/test_regress/t/t_trace_complex_threads_1.pl deleted file mode 100755 index ae50a144d..000000000 --- a/test_regress/t/t_trace_complex_threads_1.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); -golden_filename("t/t_trace_complex.out"); - -compile( - verilator_flags2 => ['--cc --trace --trace-threads 1'] - ); - -execute( - check_finished => 1, - ); - -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_strp_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arrp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_arrp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_strp /); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arru\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arrp\[/); -file_grep("$Self->{obj_dir}/simx.vcd", qr/ v_arru_strp\[/); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_threads_1.py b/test_regress/t/t_trace_complex_threads_1.py new file mode 100755 index 000000000..bf3e9e999 --- /dev/null +++ b/test_regress/t/t_trace_complex_threads_1.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex.out" + +test.compile(verilator_flags2=['--cc --trace --trace-threads 1']) + +test.execute() + +test.file_grep(test.trace_filename, r' v_strp ') +test.file_grep(test.trace_filename, r' v_strp_strp ') +test.file_grep(test.trace_filename, r' v_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_strp ') +test.file_grep(test.trace_filename, r' v_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arrp\[') +test.file_grep(test.trace_filename, r' v_arru_strp\[') + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_decoration.pl b/test_regress/t/t_trace_decoration.pl deleted file mode 100755 index e717c3d12..000000000 --- a/test_regress/t/t_trace_decoration.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --trace --no-decoration'], - ); - -execute( - check_finished => 1, - ); - -file_grep_not("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr!// Body!x); - -ok(1); -1; diff --git a/test_regress/t/t_trace_decoration.py b/test_regress/t/t_trace_decoration.py new file mode 100755 index 000000000..86750fc3c --- /dev/null +++ b/test_regress/t/t_trace_decoration.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --trace --no-decoration']) + +test.execute() + +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'// Body') + +test.passes() diff --git a/test_regress/t/t_trace_dumporder_bad.pl b/test_regress/t/t_trace_dumporder_bad.pl deleted file mode 100755 index df6f46881..000000000 --- a/test_regress/t/t_trace_dumporder_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-trace"], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_dumporder_bad.py b/test_regress/t/t_trace_dumporder_bad.py new file mode 100755 index 000000000..0e9c44d04 --- /dev/null +++ b/test_regress/t/t_trace_dumporder_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-trace"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn.cpp b/test_regress/t/t_trace_dumpvars_dyn.cpp index 1d3fbfab3..4123e95b7 100644 --- a/test_regress/t/t_trace_dumpvars_dyn.cpp +++ b/test_regress/t/t_trace_dumpvars_dyn.cpp @@ -10,9 +10,11 @@ #if VM_TRACE_FST #include #define TRACE_FILE_NAME "simx.fst" +#define TRACE_CLASS VerilatedFstC #elif VM_TRACE_VCD #include #define TRACE_FILE_NAME "simx.vcd" +#define TRACE_CLASS VerilatedVcdC #endif #include @@ -31,13 +33,7 @@ int main(int argc, char** argv) { std::unique_ptr top{new VM_PREFIX{"top"}}; -#if defined(T_TRACE_DUMPVARS_DYN_VCD_0) || defined(T_TRACE_DUMPVARS_DYN_VCD_1) - std::unique_ptr tfp{new VerilatedVcdC}; -#elif defined(T_TRACE_DUMPVARS_DYN_FST_0) || defined(T_TRACE_DUMPVARS_DYN_FST_1) - std::unique_ptr tfp{new VerilatedFstC}; -#else -#error "Bad test" -#endif + std::unique_ptr tfp{new TRACE_CLASS}; #if defined(T_TRACE_DUMPVARS_DYN_VCD_0) || defined(T_TRACE_DUMPVARS_DYN_FST_0) tfp->dumpvars(0, ""); diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_0.pl b/test_regress/t/t_trace_dumpvars_dyn_fst_0.pl deleted file mode 100755 index d22208347..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_fst_0.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_dumpvars_dyn.v"); - -compile( - make_main => 0, - verilator_flags2 => ["--trace-fst --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp"], - ); - -execute( - check_finished => 1, - ); - -fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_0.py b/test_regress/t/t_trace_dumpvars_dyn_fst_0.py new file mode 100755 index 000000000..00778c82c --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_fst_0.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" +test.top_filename = "t/t_trace_dumpvars_dyn.v" + +test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_1.out b/test_regress/t/t_trace_dumpvars_dyn_fst_1.out index 1a5eae60b..3da107403 100644 --- a/test_regress/t/t_trace_dumpvars_dyn_fst_1.out +++ b/test_regress/t/t_trace_dumpvars_dyn_fst_1.out @@ -15,6 +15,12 @@ $scope module sub1a $end $var parameter 32 " ADD [31:0] $end $var wire 32 ! cyc [31:0] $end $var wire 32 # value [31:0] $end +$scope module sub2a $end +$upscope $end +$scope module sub2b $end +$upscope $end +$scope module sub2c $end +$upscope $end $upscope $end $scope module sub1b $end $var parameter 32 $ ADD [31:0] $end diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_1.pl b/test_regress/t/t_trace_dumpvars_dyn_fst_1.pl deleted file mode 100755 index d22208347..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_fst_1.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_dumpvars_dyn.v"); - -compile( - make_main => 0, - verilator_flags2 => ["--trace-fst --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp"], - ); - -execute( - check_finished => 1, - ); - -fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_1.py b/test_regress/t/t_trace_dumpvars_dyn_fst_1.py new file mode 100755 index 000000000..00778c82c --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_fst_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" +test.top_filename = "t/t_trace_dumpvars_dyn.v" + +test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.pl b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.pl deleted file mode 100755 index 31354ab6a..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_dumpvars_dyn.v"); - -compile( - make_main => 0, - verilator_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py new file mode 100755 index 000000000..17f76e69b --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" +test.top_filename = "t/t_trace_dumpvars_dyn.v" + +test.compile(make_main=False, verilator_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.out b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.out index dd46b59b0..d740ec55c 100644 --- a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.out +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.out @@ -1,7 +1,5 @@ $version Generated by VerilatedVcd $end -$date Sat Mar 5 13:47:52 2022 $end $timescale 1ps $end - $scope module top $end $scope module t $end $var wire 32 # cyc [31:0] $end @@ -9,6 +7,12 @@ $timescale 1ps $end $var wire 32 - ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end + $scope module sub2a $end + $upscope $end + $scope module sub2b $end + $upscope $end + $scope module sub2c $end + $upscope $end $upscope $end $scope module sub1b $end $var wire 32 1 ADD [31:0] $end diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.pl b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.pl deleted file mode 100755 index 70ccefe3c..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_dumpvars_dyn.v"); - -compile( - make_main => 0, - verilator_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp -CFLAGS -DVL_DEBUG"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py new file mode 100755 index 000000000..9e369b46e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" +test.top_filename = "t/t_trace_dumpvars_dyn.v" + +test.compile(make_main=False, + verilator_flags2=["--trace --exe", test.pli_filename, "-CFLAGS -DVL_DEBUG"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_empty.pl b/test_regress/t/t_trace_empty.pl deleted file mode 100755 index fae46614d..000000000 --- a/test_regress/t/t_trace_empty.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--trace'], - ); - -execute( - check_finished => 1, - ); - -file_grep_not("$Self->{obj_dir}/simx.vcd", qr/var/); - -ok(1); -1; diff --git a/test_regress/t/t_trace_empty.py b/test_regress/t/t_trace_empty.py new file mode 100755 index 000000000..317f700bc --- /dev/null +++ b/test_regress/t/t_trace_empty.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--trace']) + +test.execute() + +test.file_grep_not(test.trace_filename, r'var') + +test.passes() diff --git a/test_regress/t/t_trace_ena_cc.pl b/test_regress/t/t_trace_ena_cc.pl deleted file mode 100755 index 94c44cb0d..000000000 --- a/test_regress/t/t_trace_ena_cc.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_ena.v"); - -compile( - verilator_flags2 => ['-trace'], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/V$Self->{name}__Trace__0__Slow.cpp", qr/c_trace_on\"/x); - file_grep_not("$Self->{obj_dir}/V$Self->{name}__Trace__0__Slow.cpp", qr/_trace_off\"/x); - file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); - file_grep_not("$Self->{obj_dir}/simx.vcd", qr/inside_sub/x); - - vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_ena_cc.py b/test_regress/t/t_trace_ena_cc.py new file mode 100755 index 000000000..925abfaf4 --- /dev/null +++ b/test_regress/t/t_trace_ena_cc.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ena.v" + +test.compile(verilator_flags2=['-trace']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.obj_dir + "/V" + test.name + "__Trace__0__Slow.cpp", r'c_trace_on\"') + test.file_grep_not(test.obj_dir + "/V" + test.name + "__Trace__0__Slow.cpp", r'_trace_off\"') + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.file_grep_not(test.trace_filename, r'inside_sub') + + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_ena_sc.pl b/test_regress/t/t_trace_ena_sc.pl deleted file mode 100755 index 73e694095..000000000 --- a/test_regress/t/t_trace_ena_sc.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_ena.v"); - - compile( - verilator_flags2 => ['-trace -sc'], - ); - - execute( - check_finished => 1, - ); - - if ($Self->{vlt_all}) { - # Note more checks in _cc.pl - file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); - - vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_ena_sc.py b/test_regress/t/t_trace_ena_sc.py new file mode 100755 index 000000000..7b26b4db3 --- /dev/null +++ b/test_regress/t/t_trace_ena_sc.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ena.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['-trace -sc']) + +test.execute() + +if test.vlt_all: + # Note more checks in _cc.py + test.file_grep(test.trace_filename, r'\$enddefinitions') + + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_enum_fst.pl b/test_regress/t/t_trace_enum_fst.pl deleted file mode 100755 index d59b6459d..000000000 --- a/test_regress/t/t_trace_enum_fst.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_enum.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst --output-split-ctrace 1'], - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -# Five $attrbegin expected: -# - state_t declaration -# - t.v_enumed -# - t.sink.state -# - other_state_t declaration -# - t.v_other_enumed -file_grep_count($Self->{golden_filename}, qr/attrbegin/, 5); - -ok(1); -1; diff --git a/test_regress/t/t_trace_enum_fst.py b/test_regress/t/t_trace_enum_fst.py new file mode 100755 index 000000000..1f9a54afa --- /dev/null +++ b/test_regress/t/t_trace_enum_fst.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_enum.v" + +test.compile(verilator_flags2=['--cc --trace-fst --output-split-ctrace 1']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +# Five $attrbegin expected: +# - state_t declaration +# - t.v_enumed +# - t.sink.state +# - other_state_t declaration +# - t.v_other_enumed +test.file_grep_count(test.golden_filename, r'attrbegin', 5) + +test.passes() diff --git a/test_regress/t/t_trace_event.out b/test_regress/t/t_trace_event.out new file mode 100644 index 000000000..33f528708 --- /dev/null +++ b/test_regress/t/t_trace_event.out @@ -0,0 +1,71 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var event 1 # ev_test $end + $var wire 32 $ i [31:0] $end + $var wire 1 % toggle $end + $var wire 1 & clk $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 $ +0% +0& +#10 +b00000000000000000000000000000001 $ +1& +#20 +0& +#30 +b00000000000000000000000000000010 $ +1& +#40 +0& +#50 +b00000000000000000000000000000011 $ +1& +#60 +0& +#70 +b00000000000000000000000000000100 $ +1& +#80 +0& +#90 +b00000000000000000000000000000101 $ +1& +#100 +0& +#110 +1# +b00000000000000000000000000000110 $ +1% +1& +#120 +0& +#130 +b00000000000000000000000000000111 $ +1& +#140 +0& +#150 +b00000000000000000000000000001000 $ +1& +#160 +0& +#170 +b00000000000000000000000000001001 $ +1& +#180 +0& +#190 +b00000000000000000000000000001010 $ +1& +#200 +0& +#210 +1& diff --git a/test_regress/t/t_trace_event.py b/test_regress/t/t_trace_event.py new file mode 100755 index 000000000..215c5d6dc --- /dev/null +++ b/test_regress/t/t_trace_event.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--trace --binary']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_event.v b/test_regress/t/t_trace_event.v new file mode 100644 index 000000000..64950188b --- /dev/null +++ b/test_regress/t/t_trace_event.v @@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t(/*AUTOARG*/); + + event ev_test; + + int i; + + bit toggle = 1'b0; + + bit clk; + always #10 clk = ~clk; + + initial begin + @(posedge clk); + + @(ev_test); + toggle = ~toggle; + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(0, top); + for(i=0; i < 10; i++) begin + @(posedge clk); + + if (i == 5) + ->ev_test; + end + + @(posedge clk); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_trace_event_fst.out b/test_regress/t/t_trace_event_fst.out new file mode 100644 index 000000000..bda112149 --- /dev/null +++ b/test_regress/t/t_trace_event_fst.out @@ -0,0 +1,79 @@ +$date + Sun Sep 22 22:54:12 2024 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module $rootio $end +$upscope $end +$scope module t $end +$var event 1 ! ev_test $end +$var int 32 " i [31:0] $end +$var bit 1 # toggle $end +$var bit 1 $ clk $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0$ +0# +b00000000000000000000000000000000 " +$end +#10 +b00000000000000000000000000000001 " +1$ +#20 +0$ +#30 +1$ +b00000000000000000000000000000010 " +#40 +0$ +#50 +1$ +b00000000000000000000000000000011 " +#60 +0$ +#70 +1$ +b00000000000000000000000000000100 " +#80 +0$ +#90 +1$ +b00000000000000000000000000000101 " +#100 +0$ +#110 +1$ +b00000000000000000000000000000110 " +1# +1! +#120 +0$ +#130 +1$ +b00000000000000000000000000000111 " +#140 +0$ +#150 +1$ +b00000000000000000000000000001000 " +#160 +0$ +#170 +1$ +b00000000000000000000000000001001 " +#180 +0$ +#190 +1$ +b00000000000000000000000000001010 " +#200 +0$ +#210 +1$ diff --git a/test_regress/t/t_trace_event_fst.py b/test_regress/t/t_trace_event_fst.py new file mode 100755 index 000000000..a0f87c134 --- /dev/null +++ b/test_regress/t/t_trace_event_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_event.v" + +test.compile(verilator_flags2=['--trace-fst --binary']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_flag_off.pl b/test_regress/t/t_trace_flag_off.pl deleted file mode 100755 index 32a214e08..000000000 --- a/test_regress/t/t_trace_flag_off.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test that without --trace we get a message when turning on traces -scenarios(vlt => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_flag_off.py b/test_regress/t/t_trace_flag_off.py new file mode 100755 index 000000000..d0074dd4a --- /dev/null +++ b/test_regress/t/t_trace_flag_off.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test that without --trace we get a message when turning on traces +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_fst.pl b/test_regress/t/t_trace_fst.pl deleted file mode 100755 index 42029ba72..000000000 --- a/test_regress/t/t_trace_fst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--trace-fst"], -); - -execute( - check_finished => 1, -); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_fst.py b/test_regress/t/t_trace_fst.py new file mode 100755 index 000000000..c1d629013 --- /dev/null +++ b/test_regress/t/t_trace_fst.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--trace-fst"]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_fst_cmake.pl b/test_regress/t/t_trace_fst_cmake.pl deleted file mode 100755 index 4a00d2fb6..000000000 --- a/test_regress/t/t_trace_fst_cmake.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--trace-fst"], - verilator_make_gmake => 0, - verilator_make_cmake => 1, -); - -execute( - check_finished => 1, -); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_fst_cmake.py b/test_regress/t/t_trace_fst_cmake.py new file mode 100755 index 000000000..8e70813e5 --- /dev/null +++ b/test_regress/t/t_trace_fst_cmake.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--trace-fst"], verilator_make_gmake=False, verilator_make_cmake=1) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_fst_sc.pl b/test_regress/t/t_trace_fst_sc.pl deleted file mode 100755 index ebe177afd..000000000 --- a/test_regress/t/t_trace_fst_sc.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(vlt_all => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - compile( - verilator_flags2 => ["--trace-fst --sc"], - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} -ok(1); -1; diff --git a/test_regress/t/t_trace_fst_sc.py b/test_regress/t/t_trace_fst_sc.py new file mode 100755 index 000000000..70d59dba1 --- /dev/null +++ b/test_regress/t/t_trace_fst_sc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=["--trace-fst --sc"]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_fst_sc_cmake.pl b/test_regress/t/t_trace_fst_sc_cmake.pl deleted file mode 100755 index 9764d6bf0..000000000 --- a/test_regress/t/t_trace_fst_sc_cmake.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(vlt_all => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - compile( - verilator_flags2 => ["--trace-fst --sc"], - verilator_make_gmake => 0, - verilator_make_cmake => 1, - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} -ok(1); -1; diff --git a/test_regress/t/t_trace_fst_sc_cmake.py b/test_regress/t/t_trace_fst_sc_cmake.py new file mode 100755 index 000000000..b5d8f5f0e --- /dev/null +++ b/test_regress/t/t_trace_fst_sc_cmake.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=["--trace-fst --sc"], + verilator_make_gmake=False, + verilator_make_cmake=1) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_iface.pl b/test_regress/t/t_trace_iface.pl deleted file mode 100755 index a17d59021..000000000 --- a/test_regress/t/t_trace_iface.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--trace'], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_iface.py b/test_regress/t/t_trace_iface.py new file mode 100755 index 000000000..de8cf58ff --- /dev/null +++ b/test_regress/t/t_trace_iface.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_no_top_name.out b/test_regress/t/t_trace_no_top_name.out index 2905133f4..5eef24e61 100644 --- a/test_regress/t/t_trace_no_top_name.out +++ b/test_regress/t/t_trace_no_top_name.out @@ -1,5 +1,7 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end + $scope module $rootio $end + $upscope $end $scope module another_top $end $var wire 1 # b $end $upscope $end diff --git a/test_regress/t/t_trace_no_top_name.pl b/test_regress/t/t_trace_no_top_name.pl deleted file mode 100755 index 6acf255d1..000000000 --- a/test_regress/t/t_trace_no_top_name.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --main-top-name '-' --trace -Wno-MULTITOP"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_no_top_name.py b/test_regress/t/t_trace_no_top_name.py new file mode 100755 index 000000000..e3e6887f1 --- /dev/null +++ b/test_regress/t/t_trace_no_top_name.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --main-top-name '-' --trace -Wno-MULTITOP"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_no_top_name2.cpp b/test_regress/t/t_trace_no_top_name2.cpp new file mode 100644 index 000000000..ce05129eb --- /dev/null +++ b/test_regress/t/t_trace_no_top_name2.cpp @@ -0,0 +1,53 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include +#if VM_TRACE_FST +#include +#define TRACE_FILE_NAME "simx.fst" +#define TRACE_CLASS VerilatedFstC +#elif VM_TRACE_VCD +#include +#define TRACE_FILE_NAME "simx.vcd" +#define TRACE_CLASS VerilatedVcdC +#endif + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // This test is to specifically check "" as the below upper model name + std::unique_ptr top{new VM_PREFIX{""}}; + + std::unique_ptr tfp{new TRACE_CLASS}; + + top->trace(tfp.get(), 99); + tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/" TRACE_FILE_NAME); + top->clk = 0; + + while (main_time <= 20) { + top->eval(); + tfp->dump((unsigned int)(main_time)); + ++main_time; + top->clk = !top->clk; + } + tfp->close(); + top->final(); + tfp.reset(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_no_top_name2.v b/test_regress/t/t_trace_no_top_name2.v new file mode 100644 index 000000000..b1f408cb6 --- /dev/null +++ b/test_regress/t/t_trace_no_top_name2.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module sub; + int a = 1212; +endmodule + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + int cyc; + + sub sub(); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_trace_no_top_name2_fst.out b/test_regress/t/t_trace_no_top_name2_fst.out new file mode 100644 index 000000000..81393e41f --- /dev/null +++ b/test_regress/t/t_trace_no_top_name2_fst.out @@ -0,0 +1,77 @@ +$date + Sat Sep 21 08:10:39 2024 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module $rootio $end +$var wire 1 ! clk $end +$upscope $end +$scope module t $end +$var wire 1 ! clk $end +$var int 32 " cyc [31:0] $end +$scope module sub $end +$var int 32 # a [31:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b00000000000000000000010010111100 # +b00000000000000000000000000000000 " +0! +$end +#1 +1! +b00000000000000000000000000000001 " +#2 +0! +#3 +1! +b00000000000000000000000000000010 " +#4 +0! +#5 +1! +b00000000000000000000000000000011 " +#6 +0! +#7 +1! +b00000000000000000000000000000100 " +#8 +0! +#9 +1! +b00000000000000000000000000000101 " +#10 +0! +#11 +1! +b00000000000000000000000000000110 " +#12 +0! +#13 +1! +b00000000000000000000000000000111 " +#14 +0! +#15 +1! +b00000000000000000000000000001000 " +#16 +0! +#17 +1! +b00000000000000000000000000001001 " +#18 +0! +#19 +1! +b00000000000000000000000000001010 " +#20 +0! diff --git a/test_regress/t/t_trace_no_top_name2_fst.py b/test_regress/t/t_trace_no_top_name2_fst.py new file mode 100755 index 000000000..bedb57f89 --- /dev/null +++ b/test_regress/t/t_trace_no_top_name2_fst.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_trace_no_top_name2.cpp" +test.top_filename = "t/t_trace_no_top_name2.v" + +test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_no_top_name2_vcd.out b/test_regress/t/t_trace_no_top_name2_vcd.out new file mode 100644 index 000000000..45e6e891c --- /dev/null +++ b/test_regress/t/t_trace_no_top_name2_vcd.out @@ -0,0 +1,69 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $var wire 1 # clk $end + $upscope $end + $scope module t $end + $var wire 1 # clk $end + $var wire 32 $ cyc [31:0] $end + $scope module sub $end + $var wire 32 % a [31:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +0# +b00000000000000000000000000000000 $ +b00000000000000000000010010111100 % +#1 +1# +b00000000000000000000000000000001 $ +#2 +0# +#3 +1# +b00000000000000000000000000000010 $ +#4 +0# +#5 +1# +b00000000000000000000000000000011 $ +#6 +0# +#7 +1# +b00000000000000000000000000000100 $ +#8 +0# +#9 +1# +b00000000000000000000000000000101 $ +#10 +0# +#11 +1# +b00000000000000000000000000000110 $ +#12 +0# +#13 +1# +b00000000000000000000000000000111 $ +#14 +0# +#15 +1# +b00000000000000000000000000001000 $ +#16 +0# +#17 +1# +b00000000000000000000000000001001 $ +#18 +0# +#19 +1# +b00000000000000000000000000001010 $ +#20 +0# diff --git a/test_regress/t/t_trace_no_top_name2_vcd.py b/test_regress/t/t_trace_no_top_name2_vcd.py new file mode 100755 index 000000000..06a524d42 --- /dev/null +++ b/test_regress/t/t_trace_no_top_name2_vcd.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_trace_no_top_name2.cpp" +test.top_filename = "t/t_trace_no_top_name2.v" + +test.compile(make_main=False, verilator_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_noflag_bad.pl b/test_regress/t/t_trace_noflag_bad.pl deleted file mode 100755 index 8271fa41d..000000000 --- a/test_regress/t/t_trace_noflag_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # We need to list verilated_vcd_c.cpp because without --trace Verilator - # won't build it itself automatically. - verilator_flags2 => ["--cc --exe $Self->{t_dir}/$Self->{name}_c.cpp verilated_vcd_c.cpp"], - make_top_shell => 0, - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_noflag_bad.py b/test_regress/t/t_trace_noflag_bad.py new file mode 100755 index 000000000..a61eb9bdd --- /dev/null +++ b/test_regress/t/t_trace_noflag_bad.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # We need to list verilated_vcd_c.cpp because without --trace Verilator + # won't build it itself automatically. + verilator_flags2=["--cc --exe", test.t_dir + "/" + test.name + "_c.cpp verilated_vcd_c.cpp"], + make_top_shell=False, + make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_off_cc.pl b/test_regress/t/t_trace_off_cc.pl deleted file mode 100755 index 0aa901413..000000000 --- a/test_regress/t/t_trace_off_cc.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_ena.v"); - -compile( - verilator_flags2 => ['-notrace'], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - !-r "$Self->{obj_dir}/simx.vcd" or error("Tracing should be off\n"); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_off_cc.py b/test_regress/t/t_trace_off_cc.py new file mode 100755 index 000000000..27f02bff7 --- /dev/null +++ b/test_regress/t/t_trace_off_cc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ena.v" + +test.compile(verilator_flags2=['-notrace']) + +test.execute() + +if test.vlt_all: + if os.path.exists(test.trace_filename): + test.error("Tracing should be off") + +test.passes() diff --git a/test_regress/t/t_trace_off_sc.pl b/test_regress/t/t_trace_off_sc.pl deleted file mode 100755 index fb6a3392e..000000000 --- a/test_regress/t/t_trace_off_sc.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_ena.v"); - -compile( - verilator_flags2 => ['-notrace -sc'], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - !-r "$Self->{obj_dir}/simx.vcd" or error("Tracing should be off\n"); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_off_sc.py b/test_regress/t/t_trace_off_sc.py new file mode 100755 index 000000000..44a184b75 --- /dev/null +++ b/test_regress/t/t_trace_off_sc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ena.v" + +test.compile(verilator_flags2=['-notrace -sc']) + +test.execute() + +if test.vlt_all: + if os.path.exists(test.trace_filename): + test.error("Tracing should be off") + +test.passes() diff --git a/test_regress/t/t_trace_open_wrong_order_bad.cpp b/test_regress/t/t_trace_open_wrong_order_bad.cpp index fa899b799..2a8f4cad9 100644 --- a/test_regress/t/t_trace_open_wrong_order_bad.cpp +++ b/test_regress/t/t_trace_open_wrong_order_bad.cpp @@ -12,13 +12,14 @@ #include VM_PREFIX_INCLUDE int main(int argc, char** argv) { - VerilatedContext ctx; - VerilatedVcdC tfp; - Vt_trace_open_wrong_order_bad dut; - ctx.traceEverOn(true); - tfp.open(VL_STRINGIFY(TEST_OBJ_DIR) "/dump.vcd"); // Error! shall put to the next line! - dut.trace(&tfp, 99); // Error! - tfp.dump(0); - tfp.close(); + std::unique_ptr contextp{new VerilatedContext}; + std::unique_ptr tfp{new VerilatedVcdC}; + std::unique_ptr top{new VM_PREFIX{contextp.get(), "top"}}; + + contextp->traceEverOn(true); + tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/dump.vcd"); // Error! shall put to the next line! + top->trace(tfp.get(), 99); // Error! + tfp->dump(0); + tfp->close(); return 0; } diff --git a/test_regress/t/t_trace_open_wrong_order_bad.pl b/test_regress/t/t_trace_open_wrong_order_bad.pl deleted file mode 100755 index 0d55a8647..000000000 --- a/test_regress/t/t_trace_open_wrong_order_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--cc --trace --exe $Self->{t_dir}/$Self->{name}.cpp"], - make_top_shell => 0, - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_open_wrong_order_bad.py b/test_regress/t/t_trace_open_wrong_order_bad.py new file mode 100755 index 000000000..691cb579b --- /dev/null +++ b/test_regress/t/t_trace_open_wrong_order_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--cc --trace --exe", test.pli_filename], + make_top_shell=False, + make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_packed_struct.pl b/test_regress/t/t_trace_packed_struct.pl deleted file mode 100755 index 795f3673b..000000000 --- a/test_regress/t/t_trace_packed_struct.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--trace"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_packed_struct.py b/test_regress/t/t_trace_packed_struct.py new file mode 100755 index 000000000..66b2dd8cd --- /dev/null +++ b/test_regress/t/t_trace_packed_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--trace"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_packed_struct_fst.pl b/test_regress/t/t_trace_packed_struct_fst.pl deleted file mode 100755 index 394fb3efd..000000000 --- a/test_regress/t/t_trace_packed_struct_fst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_packed_struct.v"); - -compile( - v_flags2 => ["--trace-fst"] - ); - -execute( - check_finished => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_packed_struct_fst.py b/test_regress/t/t_trace_packed_struct_fst.py new file mode 100755 index 000000000..4add1a2b6 --- /dev/null +++ b/test_regress/t/t_trace_packed_struct_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_packed_struct.v" + +test.compile(v_flags2=["--trace-fst"]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_packed_struct_fst_sc.pl b/test_regress/t/t_trace_packed_struct_fst_sc.pl deleted file mode 100755 index f5acc5403..000000000 --- a/test_regress/t/t_trace_packed_struct_fst_sc.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_packed_struct.v"); - - compile( - v_flags2 => ["--sc --trace-fst"] - ); - - execute( - check_finished => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_packed_struct_fst_sc.py b/test_regress/t/t_trace_packed_struct_fst_sc.py new file mode 100755 index 000000000..e329e22e9 --- /dev/null +++ b/test_regress/t/t_trace_packed_struct_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_packed_struct.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(v_flags2=["--sc --trace-fst"]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_param.pl b/test_regress/t/t_trace_param.pl deleted file mode 100755 index 71022a7d7..000000000 --- a/test_regress/t/t_trace_param.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--trace"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_param.py b/test_regress/t/t_trace_param.py new file mode 100755 index 000000000..7ed3e770d --- /dev/null +++ b/test_regress/t/t_trace_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--trace"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_param_fst.pl b/test_regress/t/t_trace_param_fst.pl deleted file mode 100755 index 38e46c0b8..000000000 --- a/test_regress/t/t_trace_param_fst.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_param.v"); - -compile( - v_flags2 => ["--trace-fst"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_param_fst.py b/test_regress/t/t_trace_param_fst.py new file mode 100755 index 000000000..863328841 --- /dev/null +++ b/test_regress/t/t_trace_param_fst.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_param.v" + +test.compile(v_flags2=["--trace-fst"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_param_override.out b/test_regress/t/t_trace_param_override.out index 92ff7f265..c139f47f0 100644 --- a/test_regress/t/t_trace_param_override.out +++ b/test_regress/t/t_trace_param_override.out @@ -1,12 +1,10 @@ $version Generated by VerilatedVcd $end -$date Thu Nov 10 19:19:51 2022 $end $timescale 1ps $end - - $scope module TOP $end - $scope module t $end - $var wire 32 $ PORIG [31:0] $end - $var wire 32 # POVERRODE [31:0] $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 32 # POVERRODE [31:0] $end + $var wire 32 $ PORIG [31:0] $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_param_override.pl b/test_regress/t/t_trace_param_override.pl deleted file mode 100755 index 51a8874fe..000000000 --- a/test_regress/t/t_trace_param_override.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --trace -GPOVERRODE=31"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_param_override.py b/test_regress/t/t_trace_param_override.py new file mode 100755 index 000000000..928c0acde --- /dev/null +++ b/test_regress/t/t_trace_param_override.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --trace -GPOVERRODE=31"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_primitive.pl b/test_regress/t/t_trace_primitive.pl deleted file mode 100755 index dc8c69b4c..000000000 --- a/test_regress/t/t_trace_primitive.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--trace"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/simx.vcd", "sub_t_i"); -}; - -ok(1); -1; diff --git a/test_regress/t/t_trace_primitive.py b/test_regress/t/t_trace_primitive.py new file mode 100755 index 000000000..7d9702fd0 --- /dev/null +++ b/test_regress/t/t_trace_primitive.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--trace"]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, "sub_t_i") + +test.passes() diff --git a/test_regress/t/t_trace_primitive.v b/test_regress/t/t_trace_primitive.v index 176c053ca..fe08ff8ca 100644 --- a/test_regress/t/t_trace_primitive.v +++ b/test_regress/t/t_trace_primitive.v @@ -30,9 +30,17 @@ module t endmodule primitive CINV (a, b); -output b; -input a; -assign b = ~a; + output b; + input a; +`ifdef VERILATOR + assign b = ~a; +`else + table + //b a + 0 : ? : 1; + 1 : ? : 0; + endtable +`endif endprimitive diff --git a/test_regress/t/t_trace_primitive_fst.pl b/test_regress/t/t_trace_primitive_fst.pl deleted file mode 100755 index 2c52884c2..000000000 --- a/test_regress/t/t_trace_primitive_fst.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_primitive.v"); - -compile( - v_flags2 => ["--trace-fst"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_primitive_fst.py b/test_regress/t/t_trace_primitive_fst.py new file mode 100755 index 000000000..186eb317d --- /dev/null +++ b/test_regress/t/t_trace_primitive_fst.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_primitive.v" + +test.compile(v_flags2=["--trace-fst"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_primitive_fst_sc.pl b/test_regress/t/t_trace_primitive_fst_sc.pl deleted file mode 100755 index b9a8fe2bb..000000000 --- a/test_regress/t/t_trace_primitive_fst_sc.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_primitive.v"); - - compile( - v_flags2 => ["--sc --trace-fst"], - ); - - execute( - check_finished => 1, - ); -} -ok(1); -1; diff --git a/test_regress/t/t_trace_primitive_fst_sc.py b/test_regress/t/t_trace_primitive_fst_sc.py new file mode 100755 index 000000000..2c19efdfe --- /dev/null +++ b/test_regress/t/t_trace_primitive_fst_sc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_primitive.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(v_flags2=["--sc --trace-fst"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_public_func.pl b/test_regress/t/t_trace_public_func.pl deleted file mode 100755 index 519178385..000000000 --- a/test_regress/t/t_trace_public_func.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_public.v"); -golden_filename("t/t_trace_public.out"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["-DATTRIBUTES -DPUB_FUNC --trace --exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_public_func.py b/test_regress/t/t_trace_public_func.py new file mode 100755 index 000000000..415f64bc3 --- /dev/null +++ b/test_regress/t/t_trace_public_func.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_public.v" +test.golden_filename = "t/t_trace_public.out" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["-DATTRIBUTES -DPUB_FUNC --trace --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_public_func_vlt.pl b/test_regress/t/t_trace_public_func_vlt.pl deleted file mode 100755 index f532f19d0..000000000 --- a/test_regress/t/t_trace_public_func_vlt.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_public.v"); -golden_filename("t/t_trace_public.out"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["-DPUB_FUNC --trace --exe $Self->{t_dir}/t_trace_public_func.cpp $Self->{t_dir}/t_trace_public_func.vlt"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_public_func_vlt.py b/test_regress/t/t_trace_public_func_vlt.py new file mode 100755 index 000000000..da815dcdd --- /dev/null +++ b/test_regress/t/t_trace_public_func_vlt.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_public_func.cpp" +test.top_filename = "t/t_trace_public.v" +test.golden_filename = "t/t_trace_public.out" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=[ + "-DPUB_FUNC --trace --exe", test.pli_filename, + test.t_dir + "/t_trace_public_func.vlt" + ]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_public_sig.pl b/test_regress/t/t_trace_public_sig.pl deleted file mode 100755 index edb8bf2c4..000000000 --- a/test_regress/t/t_trace_public_sig.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_public.v"); -golden_filename("t/t_trace_public.out"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["-DATTRIBUTES --trace --exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -# vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" -file_grep("$Self->{obj_dir}/simx.vcd", qr/module glbl/i); - -ok(1); -1; diff --git a/test_regress/t/t_trace_public_sig.py b/test_regress/t/t_trace_public_sig.py new file mode 100755 index 000000000..21f4444c9 --- /dev/null +++ b/test_regress/t/t_trace_public_sig.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_public.v" +test.golden_filename = "t/t_trace_public.out" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["-DATTRIBUTES --trace --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +# vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" +test.file_grep(test.trace_filename, r'module glbl') + +test.passes() diff --git a/test_regress/t/t_trace_public_sig_vlt.pl b/test_regress/t/t_trace_public_sig_vlt.pl deleted file mode 100755 index ceb9db1af..000000000 --- a/test_regress/t/t_trace_public_sig_vlt.pl +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_public.v"); -golden_filename("t/t_trace_public.out"); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_public_sig.cpp $Self->{t_dir}/t_trace_public_sig.vlt --no-json-edit-nums"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"GSR",.*"loc":"f,47:[^"]*",.*"origName":"GSR",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true.*"isSigUserRWPublic":true/); -} - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -# vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" -file_grep("$Self->{obj_dir}/simx.vcd", qr/module glbl/i); - -ok(1); -1; diff --git a/test_regress/t/t_trace_public_sig_vlt.py b/test_regress/t/t_trace_public_sig_vlt.py new file mode 100755 index 000000000..743751fa9 --- /dev/null +++ b/test_regress/t/t_trace_public_sig_vlt.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_public_sig.cpp" +test.top_filename = "t/t_trace_public.v" +test.golden_filename = "t/t_trace_public.out" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=[ + "--trace --exe", test.pli_filename, + test.t_dir + "/t_trace_public_sig.vlt --no-json-edit-nums" + ]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"GSR",.*"loc":"f,47:[^"]*",.*"origName":"GSR",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true.*"isSigUserRWPublic":true' + ) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +# vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" +test.file_grep(test.trace_filename, r'module glbl') + +test.passes() diff --git a/test_regress/t/t_trace_rollover.pl b/test_regress/t/t_trace_rollover.pl deleted file mode 100755 index ea462b851..000000000 --- a/test_regress/t/t_trace_rollover.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_cat.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_rollover.cpp"], - ); - -execute( - check_finished => 1, - ); - -system("cat $Self->{obj_dir}/simrollover_cat*.vcd " - . " > $Self->{obj_dir}/simall.vcd"); - -vcd_identical("$Self->{obj_dir}/simall.vcd", - $Self->{golden_filename}); - -file_grep_not("$Self->{obj_dir}/simrollover_cat0000.vcd", qr/^#/i); -file_grep("$Self->{obj_dir}/simrollover_cat0001.vcd", qr/^#/i); -file_grep("$Self->{obj_dir}/simrollover_cat0002.vcd", qr/^#/i); - -ok(1); -1; diff --git a/test_regress/t/t_trace_rollover.py b/test_regress/t/t_trace_rollover.py new file mode 100755 index 000000000..4764e4ba6 --- /dev/null +++ b/test_regress/t/t_trace_rollover.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_cat.v" + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +os.system("cat " + test.obj_dir + "/simrollover_cat*.vcd " + " > " + test.obj_dir + "/simall.vcd") + +test.vcd_identical(test.obj_dir + "/simall.vcd", test.golden_filename) + +test.file_grep_not(test.obj_dir + "/simrollover_cat0000.vcd", r'^#') +test.file_grep(test.obj_dir + "/simrollover_cat0001.vcd", r'^#') +test.file_grep(test.obj_dir + "/simrollover_cat0002.vcd", r'^#') + +test.passes() diff --git a/test_regress/t/t_trace_sc_empty.pl b/test_regress/t/t_trace_sc_empty.pl deleted file mode 100755 index e8d7ccc84..000000000 --- a/test_regress/t/t_trace_sc_empty.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-sc', '--trace'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_sc_empty.py b/test_regress/t/t_trace_sc_empty.py new file mode 100755 index 000000000..ae5b13494 --- /dev/null +++ b/test_regress/t/t_trace_sc_empty.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-sc', '--trace']) + +test.passes() diff --git a/test_regress/t/t_trace_scope_no_inline.pl b/test_regress/t/t_trace_scope_no_inline.pl deleted file mode 100755 index ee66c75a5..000000000 --- a/test_regress/t/t_trace_scope_no_inline.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--cc --trace -fno-inline t/$Self->{name}.vlt"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_scope_no_inline.py b/test_regress/t/t_trace_scope_no_inline.py new file mode 100755 index 000000000..0944e381c --- /dev/null +++ b/test_regress/t/t_trace_scope_no_inline.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--cc --trace -fno-inline t/" + test.name + ".vlt"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_scope_vlt.pl b/test_regress/t/t_trace_scope_vlt.pl deleted file mode 100755 index 9847c375d..000000000 --- a/test_regress/t/t_trace_scope_vlt.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_scope_vlt.v"); - -compile( - v_flags2 => ["--trace t/t_trace_scope_vlt.vlt"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_scope_vlt.py b/test_regress/t/t_trace_scope_vlt.py new file mode 100755 index 000000000..7c58f9479 --- /dev/null +++ b/test_regress/t/t_trace_scope_vlt.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_scope_vlt.v" + +test.compile(v_flags2=["--trace t/t_trace_scope_vlt.vlt"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_scstruct.pl b/test_regress/t/t_trace_scstruct.pl deleted file mode 100755 index fb375c474..000000000 --- a/test_regress/t/t_trace_scstruct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--sc --trace --trace-structs --pins-bv 2'], - ); - -#execute(); # didn't bother with top shell - -ok(1); -1; diff --git a/test_regress/t/t_trace_scstruct.py b/test_regress/t/t_trace_scstruct.py new file mode 100755 index 000000000..3dd077924 --- /dev/null +++ b/test_regress/t/t_trace_scstruct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--sc --trace --trace-structs --pins-bv 2']) + +#test.execute() # didn't bother with top shell + +test.passes() diff --git a/test_regress/t/t_trace_split_cfuncs.pl b/test_regress/t/t_trace_split_cfuncs.pl deleted file mode 100755 index 4959ee710..000000000 --- a/test_regress/t/t_trace_split_cfuncs.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--trace", "--output-split-cfuncs", "1"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_split_cfuncs.py b/test_regress/t/t_trace_split_cfuncs.py new file mode 100755 index 000000000..b1b588c76 --- /dev/null +++ b/test_regress/t/t_trace_split_cfuncs.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--trace", "--output-split-cfuncs", "1"]) + +test.passes() diff --git a/test_regress/t/t_trace_split_cfuncs_dpi_export.pl b/test_regress/t/t_trace_split_cfuncs_dpi_export.pl deleted file mode 100755 index 4959ee710..000000000 --- a/test_regress/t/t_trace_split_cfuncs_dpi_export.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--trace", "--output-split-cfuncs", "1"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_split_cfuncs_dpi_export.py b/test_regress/t/t_trace_split_cfuncs_dpi_export.py new file mode 100755 index 000000000..b1b588c76 --- /dev/null +++ b/test_regress/t/t_trace_split_cfuncs_dpi_export.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--trace", "--output-split-cfuncs", "1"]) + +test.passes() diff --git a/test_regress/t/t_trace_string.pl b/test_regress/t/t_trace_string.pl deleted file mode 100755 index 544c5a7a4..000000000 --- a/test_regress/t/t_trace_string.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_string.py b/test_regress/t/t_trace_string.py new file mode 100755 index 000000000..f9c1f82de --- /dev/null +++ b/test_regress/t/t_trace_string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_string_fst.pl b/test_regress/t/t_trace_string_fst.pl deleted file mode 100755 index cfd82a08d..000000000 --- a/test_regress/t/t_trace_string_fst.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_string.v"); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_string_fst.py b/test_regress/t/t_trace_string_fst.py new file mode 100755 index 000000000..cf926f0d2 --- /dev/null +++ b/test_regress/t/t_trace_string_fst.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_string.v" + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_string_fst_sc.pl b/test_regress/t/t_trace_string_fst_sc.pl deleted file mode 100755 index b1298449b..000000000 --- a/test_regress/t/t_trace_string_fst_sc.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_string.v"); - - compile( - verilator_flags2 => ['--sc --trace'], - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_string_fst_sc.py b/test_regress/t/t_trace_string_fst_sc.py new file mode 100755 index 000000000..dc56e4069 --- /dev/null +++ b/test_regress/t/t_trace_string_fst_sc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_string.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_timescale.pl b/test_regress/t/t_trace_timescale.pl deleted file mode 100755 index ed4a3b3e4..000000000 --- a/test_regress/t/t_trace_timescale.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--trace"], - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_timescale.py b/test_regress/t/t_trace_timescale.py new file mode 100755 index 000000000..8c2aacbfb --- /dev/null +++ b/test_regress/t/t_trace_timescale.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--trace"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_timing1.out b/test_regress/t/t_trace_timing1.out index 5d7ee2f0d..b829e1aca 100644 --- a/test_regress/t/t_trace_timing1.out +++ b/test_regress/t/t_trace_timing1.out @@ -1,12 +1,11 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - - $scope module TOP $end - $scope module t $end - $var wire 32 % CLOCK_CYCLE [31:0] $end - $var wire 1 # rst $end - $var wire 1 $ clk $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 32 % CLOCK_CYCLE [31:0] $end + $var wire 1 # rst $end + $var wire 1 $ clk $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_timing1.pl b/test_regress/t/t_trace_timing1.pl deleted file mode 100755 index 4c3233d88..000000000 --- a/test_regress/t/t_trace_timing1.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--binary --trace'], - make_main => 0, - ); - -execute( - check_finished => 1, - ); - -vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_timing1.py b/test_regress/t/t_trace_timing1.py new file mode 100755 index 000000000..1ddc50dab --- /dev/null +++ b/test_regress/t/t_trace_timing1.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir", test.obj_dir, "--debug-check" + ], + verilator_flags2=['--binary --trace'], + make_main=False) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_dump_cc.pl b/test_regress/t/t_trace_two_dump_cc.pl deleted file mode 100755 index b12ff1c88..000000000 --- a/test_regress/t/t_trace_two_dump_cc.pl +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-trace'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-exe', '-trace', "$Self->{t_dir}/t_trace_two_cc.cpp"], - v_flags2 => ['+define+TEST_DUMP'], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); - vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_dump_cc.py b/test_regress/t/t_trace_two_dump_cc.py new file mode 100755 index 000000000..6170a75b7 --- /dev/null +++ b/test_regress/t/t_trace_two_dump_cc.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-trace']) + +test.run( + logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=['-exe', '-trace', test.t_dir + "/t_trace_two_cc.cpp"], + v_flags2=['+define+TEST_DUMP']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_dump_sc.pl b/test_regress/t/t_trace_two_dump_sc.pl deleted file mode 100755 index 68e985871..000000000 --- a/test_regress/t/t_trace_two_dump_sc.pl +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t_trace_two_a.v"); - - compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-sc -trace'], - ); - - run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - - compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-sc', '-exe', '-trace', - "$Self->{t_dir}/t_trace_two_sc.cpp"], - v_flags2 => ['+define+TEST_DUMP'], - ); - - execute( - check_finished => 1, - ); - - if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); - vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_dump_sc.py b/test_regress/t/t_trace_two_dump_sc.py new file mode 100755 index 000000000..1dc86e098 --- /dev/null +++ b/test_regress/t/t_trace_two_dump_sc.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t_trace_two_a.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-sc -trace']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=['-sc', '-exe', '-trace', test.t_dir + "/t_trace_two_sc.cpp"], + v_flags2=['+define+TEST_DUMP']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_dumpfst_cc.pl b/test_regress/t/t_trace_two_dumpfst_cc.pl deleted file mode 100755 index e672f49c0..000000000 --- a/test_regress/t/t_trace_two_dumpfst_cc.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['--trace-fst --trace-threads 1 -DTEST_FST'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-exe', '--trace-fst --trace-threads 1', - '-DTEST_FST', - "$Self->{t_dir}/t_trace_two_cc.cpp"], - v_flags2 => ['+define+TEST_DUMP'], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_dumpfst_cc.py b/test_regress/t/t_trace_two_dumpfst_cc.py new file mode 100755 index 000000000..525c4698a --- /dev/null +++ b/test_regress/t/t_trace_two_dumpfst_cc.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['--trace-fst --trace-threads 1 -DTEST_FST']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=[ + '-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', + test.t_dir + "/t_trace_two_cc.cpp" + ], + v_flags2=['+define+TEST_DUMP']) + +test.execute() + +if test.vlt_all: + test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_hdr_cc.pl b/test_regress/t/t_trace_two_hdr_cc.pl deleted file mode 100755 index 665808c3b..000000000 --- a/test_regress/t/t_trace_two_hdr_cc.pl +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-trace'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - make_flags => 'CPPFLAGS_ADD=-DTEST_HDR_TRACE=1', - verilator_flags2 => ['-exe', '-trace', "$Self->{t_dir}/t_trace_two_cc.cpp"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); - vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_hdr_cc.py b/test_regress/t/t_trace_two_hdr_cc.py new file mode 100755 index 000000000..3aef38dc9 --- /dev/null +++ b/test_regress/t/t_trace_two_hdr_cc.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-trace']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + make_flags=['CPPFLAGS_ADD=-DTEST_HDR_TRACE=1'], + verilator_flags2=['-exe', '-trace', test.t_dir + "/t_trace_two_cc.cpp"]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_hdr_sc.pl b/test_regress/t/t_trace_two_hdr_sc.pl deleted file mode 100755 index 89776af8b..000000000 --- a/test_regress/t/t_trace_two_hdr_sc.pl +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t_trace_two_a.v"); - - compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-sc -trace'], - ); - - run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - - compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - make_flags => 'CPPFLAGS_ADD=-DTEST_HDR_TRACE', - verilator_flags2 => ['-sc', '-exe', '-trace', - "$Self->{t_dir}/t_trace_two_sc.cpp"], - ); - - execute( - check_finished => 1, - ); - - if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); - vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_hdr_sc.py b/test_regress/t/t_trace_two_hdr_sc.py new file mode 100755 index 000000000..5f2557ce7 --- /dev/null +++ b/test_regress/t/t_trace_two_hdr_sc.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t_trace_two_a.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-sc -trace']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + make_flags=['CPPFLAGS_ADD=-DTEST_HDR_TRACE'], + verilator_flags2=['-sc', '-exe', '-trace', test.t_dir + "/t_trace_two_sc.cpp"]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_hdrfst_cc.pl b/test_regress/t/t_trace_two_hdrfst_cc.pl deleted file mode 100755 index e6b4a6008..000000000 --- a/test_regress/t/t_trace_two_hdrfst_cc.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['--trace-fst --trace-threads 1'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - make_flags => 'CPPFLAGS_ADD="-DTEST_HDR_TRACE=1 -DTEST_FST=1"', - verilator_flags2 => ['-exe', '--trace-fst --trace-threads 1', - '-DTEST_FST', - "$Self->{t_dir}/t_trace_two_cc.cpp"], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_hdrfst_cc.py b/test_regress/t/t_trace_two_hdrfst_cc.py new file mode 100755 index 000000000..8b0157b74 --- /dev/null +++ b/test_regress/t/t_trace_two_hdrfst_cc.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['--trace-fst --trace-threads 1']) + +test.run( + logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + make_flags=['CPPFLAGS_ADD="-DTEST_HDR_TRACE=1 -DTEST_FST=1"'], + verilator_flags2=[ + '-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', + test.t_dir + "/t_trace_two_cc.cpp" + ]) + +test.execute() + +if test.vlt_all: + test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_port_cc.pl b/test_regress/t/t_trace_two_port_cc.pl deleted file mode 100755 index 1bc4268b2..000000000 --- a/test_regress/t/t_trace_two_port_cc.pl +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-trace'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-exe', '-trace', "$Self->{t_dir}/t_trace_two_cc.cpp"], - v_flags2 => ['+define+TEST_DUMPPORTS'], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); - vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_port_cc.py b/test_regress/t/t_trace_two_port_cc.py new file mode 100755 index 000000000..4c3461f0d --- /dev/null +++ b/test_regress/t/t_trace_two_port_cc.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-trace']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=['-exe', '-trace', test.t_dir + "/t_trace_two_cc.cpp"], + v_flags2=['+define+TEST_DUMPPORTS']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_port_sc.pl b/test_regress/t/t_trace_two_port_sc.pl deleted file mode 100755 index 1bc1d29af..000000000 --- a/test_regress/t/t_trace_two_port_sc.pl +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t_trace_two_a.v"); - - compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-sc -trace'], - ); - - run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - - compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-sc', '-exe', '-trace', - "$Self->{t_dir}/t_trace_two_sc.cpp"], - v_flags2 => ['+define+TEST_DUMPPORTS'], - ); - - execute( - check_finished => 1, - ); - - if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); - vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_port_sc.py b/test_regress/t/t_trace_two_port_sc.py new file mode 100755 index 000000000..051ed305b --- /dev/null +++ b/test_regress/t/t_trace_two_port_sc.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_sc: + test.skip("No SystemC installed") + +top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-sc -trace']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=['-sc', '-exe', '-trace', test.t_dir + "/t_trace_two_sc.cpp"], + v_flags2=['+define+TEST_DUMPPORTS']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_portfst_cc.pl b/test_regress/t/t_trace_two_portfst_cc.pl deleted file mode 100755 index f9782d372..000000000 --- a/test_regress/t/t_trace_two_portfst_cc.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['--trace-fst --trace-threads 1'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-exe', '--trace-fst --trace-threads 1', - '-DTEST_FST', - "$Self->{t_dir}/t_trace_two_cc.cpp"], - v_flags2 => ['+define+TEST_DUMPPORTS'], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_portfst_cc.py b/test_regress/t/t_trace_two_portfst_cc.py new file mode 100755 index 000000000..060eda528 --- /dev/null +++ b/test_regress/t/t_trace_two_portfst_cc.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['--trace-fst --trace-threads 1']) + +test.run( + logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=[ + '-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', + test.t_dir + "/t_trace_two_cc.cpp" + ], + v_flags2=['+define+TEST_DUMPPORTS']) + +test.execute() + +if test.vlt_all: + test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_ub_misaligned_address.pl b/test_regress/t/t_trace_ub_misaligned_address.pl deleted file mode 100755 index a9ee0f201..000000000 --- a/test_regress/t/t_trace_ub_misaligned_address.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_ub_misaligned_address.v"); - -compile( - verilator_flags2 => ["--binary --trace", - "-CFLAGS -fsanitize=address,undefined", - "-LDFLAGS -fsanitize=address,undefined"], - ); - -execute( - check_finished => 1, - aslr_off => 1, # Some GCC versions hit an address-sanitizer bug otherwise - ); - -# Make sure that there are no additional messages (such as runtime messages -# regarding undefined behavior). -files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile"); - -ok(1); -1; diff --git a/test_regress/t/t_trace_ub_misaligned_address.py b/test_regress/t/t_trace_ub_misaligned_address.py new file mode 100755 index 000000000..b86a92b34 --- /dev/null +++ b/test_regress/t/t_trace_ub_misaligned_address.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ub_misaligned_address.v" + +test.compile(verilator_flags2=[ + "--binary --trace", "-CFLAGS -fsanitize=address,undefined", + "-LDFLAGS -fsanitize=address,undefined" +]) + +test.execute( + # Some GCC versions hit an address-sanitizer bug otherwise) + aslr_off=True) + +# Make sure that there are no additional messages (such as runtime messages +# regarding undefined behavior).test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") + +test.passes() diff --git a/test_regress/t/t_trace_ub_misaligned_address.v b/test_regress/t/t_trace_ub_misaligned_address.v index 379412d3a..40b351aa7 100644 --- a/test_regress/t/t_trace_ub_misaligned_address.v +++ b/test_regress/t/t_trace_ub_misaligned_address.v @@ -55,7 +55,7 @@ module t; end Test test(.out(out), .in(in), - .clk(clk), .rst(rst)); + .clk(clk), .rst(rst)); endmodule diff --git a/test_regress/t/t_trace_wide_struct.pl b/test_regress/t/t_trace_wide_struct.pl deleted file mode 100755 index 7914ddcc8..000000000 --- a/test_regress/t/t_trace_wide_struct.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile (verilator_flags2 => ['--trace --trace-structs'],); - -ok(1); -1; diff --git a/test_regress/t/t_trace_wide_struct.py b/test_regress/t/t_trace_wide_struct.py new file mode 100755 index 000000000..89f022528 --- /dev/null +++ b/test_regress/t/t_trace_wide_struct.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--trace --trace-structs']) + +test.passes() diff --git a/test_regress/t/t_tri_and_eqcase.pl b/test_regress/t/t_tri_and_eqcase.pl deleted file mode 100755 index 48bf31461..000000000 --- a/test_regress/t/t_tri_and_eqcase.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_and_eqcase.py b/test_regress/t/t_tri_and_eqcase.py new file mode 100755 index 000000000..6585af685 --- /dev/null +++ b/test_regress/t/t_tri_and_eqcase.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_array.pl b/test_regress/t/t_tri_array.pl deleted file mode 100755 index dd6bb1a0b..000000000 --- a/test_regress/t/t_tri_array.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - check_finished => 1, - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_tri_array.py b/test_regress/t/t_tri_array.py new file mode 100755 index 000000000..d0b1f865e --- /dev/null +++ b/test_regress/t/t_tri_array.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_array_bufif.pl b/test_regress/t/t_tri_array_bufif.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_tri_array_bufif.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_array_bufif.py b/test_regress/t/t_tri_array_bufif.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_array_bufif.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_array_pull.pl b/test_regress/t/t_tri_array_pull.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_tri_array_pull.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_array_pull.py b/test_regress/t/t_tri_array_pull.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_array_pull.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_compass_bad.pl b/test_regress/t/t_tri_compass_bad.pl deleted file mode 100755 index da8086e04..000000000 --- a/test_regress/t/t_tri_compass_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_compass_bad.py b/test_regress/t/t_tri_compass_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_tri_compass_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_cond_eqcase_with_1.pl b/test_regress/t/t_tri_cond_eqcase_with_1.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_tri_cond_eqcase_with_1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_cond_eqcase_with_1.py b/test_regress/t/t_tri_cond_eqcase_with_1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_cond_eqcase_with_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_dangle.pl b/test_regress/t/t_tri_dangle.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_tri_dangle.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_dangle.py b/test_regress/t/t_tri_dangle.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_dangle.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_eqcase.pl b/test_regress/t/t_tri_eqcase.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_tri_eqcase.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_eqcase.py b/test_regress/t/t_tri_eqcase.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_eqcase.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_eqcase_input.pl b/test_regress/t/t_tri_eqcase_input.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_tri_eqcase_input.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_eqcase_input.py b/test_regress/t/t_tri_eqcase_input.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_eqcase_input.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_bufif0.pl b/test_regress/t/t_tri_gate_bufif0.pl deleted file mode 100755 index fe60c4a2d..000000000 --- a/test_regress/t/t_tri_gate_bufif0.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_BUFIF0',], - make_flags => 'CPPFLAGS_ADD=-DT_BUFIF0', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_bufif0.py b/test_regress/t/t_tri_gate_bufif0.py new file mode 100755 index 000000000..4634d4e76 --- /dev/null +++ b/test_regress/t/t_tri_gate_bufif0.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_BUFIF0'], + make_flags=['CPPFLAGS_ADD=-DT_BUFIF0'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_bufif0_pins_inout.pl b/test_regress/t/t_tri_gate_bufif0_pins_inout.pl deleted file mode 100755 index 4c2e9c21c..000000000 --- a/test_regress/t/t_tri_gate_bufif0_pins_inout.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_BUFIF0',], - make_flags => 'CPPFLAGS_ADD=-DT_BUFIF0', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_bufif0_pins_inout.py b/test_regress/t/t_tri_gate_bufif0_pins_inout.py new file mode 100755 index 000000000..76fc851c5 --- /dev/null +++ b/test_regress/t/t_tri_gate_bufif0_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_BUFIF0'], + make_flags=['CPPFLAGS_ADD=-DT_BUFIF0'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_bufif1.pl b/test_regress/t/t_tri_gate_bufif1.pl deleted file mode 100755 index 2d48b6683..000000000 --- a/test_regress/t/t_tri_gate_bufif1.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_BUFIF1',], - make_flags => 'CPPFLAGS_ADD=-DT_BUFIF1', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_bufif1.py b/test_regress/t/t_tri_gate_bufif1.py new file mode 100755 index 000000000..1a14c142e --- /dev/null +++ b/test_regress/t/t_tri_gate_bufif1.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_BUFIF1'], + make_flags=['CPPFLAGS_ADD=-DT_BUFIF1'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_bufif1_pins_inout.pl b/test_regress/t/t_tri_gate_bufif1_pins_inout.pl deleted file mode 100755 index d6895bc6e..000000000 --- a/test_regress/t/t_tri_gate_bufif1_pins_inout.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_BUFIF1',], - make_flags => 'CPPFLAGS_ADD=-DT_BUFIF1', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_bufif1_pins_inout.py b/test_regress/t/t_tri_gate_bufif1_pins_inout.py new file mode 100755 index 000000000..6a4dce294 --- /dev/null +++ b/test_regress/t/t_tri_gate_bufif1_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_BUFIF1'], + make_flags=['CPPFLAGS_ADD=-DT_BUFIF1'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_cond.pl b/test_regress/t/t_tri_gate_cond.pl deleted file mode 100755 index 9dd84b300..000000000 --- a/test_regress/t/t_tri_gate_cond.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_COND',], - make_flags => 'CPPFLAGS_ADD=-DT_COND', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_cond.py b/test_regress/t/t_tri_gate_cond.py new file mode 100755 index 000000000..c4b5851c4 --- /dev/null +++ b/test_regress/t/t_tri_gate_cond.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_COND'], + make_flags=['CPPFLAGS_ADD=-DT_COND'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_cond_pins_inout.pl b/test_regress/t/t_tri_gate_cond_pins_inout.pl deleted file mode 100755 index 270654454..000000000 --- a/test_regress/t/t_tri_gate_cond_pins_inout.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_COND',], - make_flags => 'CPPFLAGS_ADD=-DT_COND', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_cond_pins_inout.py b/test_regress/t/t_tri_gate_cond_pins_inout.py new file mode 100755 index 000000000..20ffe23ea --- /dev/null +++ b/test_regress/t/t_tri_gate_cond_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_COND'], + make_flags=['CPPFLAGS_ADD=-DT_COND'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_nmos.pl b/test_regress/t/t_tri_gate_nmos.pl deleted file mode 100755 index f5398c4e2..000000000 --- a/test_regress/t/t_tri_gate_nmos.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NMOS',], - make_flags => 'CPPFLAGS_ADD=-DT_NMOS', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_nmos.py b/test_regress/t/t_tri_gate_nmos.py new file mode 100755 index 000000000..8b8c924f2 --- /dev/null +++ b/test_regress/t/t_tri_gate_nmos.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NMOS'], + make_flags=['CPPFLAGS_ADD=-DT_NMOS'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_nmos_pins_inout.pl b/test_regress/t/t_tri_gate_nmos_pins_inout.pl deleted file mode 100755 index 6e2b110b8..000000000 --- a/test_regress/t/t_tri_gate_nmos_pins_inout.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NMOS',], - make_flags => 'CPPFLAGS_ADD=-DT_NMOS', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_nmos_pins_inout.py b/test_regress/t/t_tri_gate_nmos_pins_inout.py new file mode 100755 index 000000000..fc4bbaa5c --- /dev/null +++ b/test_regress/t/t_tri_gate_nmos_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NMOS'], + make_flags=['CPPFLAGS_ADD=-DT_NMOS'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_notif0.pl b/test_regress/t/t_tri_gate_notif0.pl deleted file mode 100755 index 500b4c300..000000000 --- a/test_regress/t/t_tri_gate_notif0.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NOTIF0',], - make_flags => 'CPPFLAGS_ADD=-DT_NOTIF0', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_notif0.py b/test_regress/t/t_tri_gate_notif0.py new file mode 100755 index 000000000..a9dd77046 --- /dev/null +++ b/test_regress/t/t_tri_gate_notif0.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NOTIF0'], + make_flags=['CPPFLAGS_ADD=-DT_NOTIF0'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_notif0_pins_inout.pl b/test_regress/t/t_tri_gate_notif0_pins_inout.pl deleted file mode 100755 index 51c24c753..000000000 --- a/test_regress/t/t_tri_gate_notif0_pins_inout.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NOTIF0',], - make_flags => 'CPPFLAGS_ADD=-DT_NOTIF0', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_notif0_pins_inout.py b/test_regress/t/t_tri_gate_notif0_pins_inout.py new file mode 100755 index 000000000..797e8d163 --- /dev/null +++ b/test_regress/t/t_tri_gate_notif0_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NOTIF0'], + make_flags=['CPPFLAGS_ADD=-DT_NOTIF0'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_notif1.pl b/test_regress/t/t_tri_gate_notif1.pl deleted file mode 100755 index 3d319380c..000000000 --- a/test_regress/t/t_tri_gate_notif1.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NOTIF1',], - make_flags => 'CPPFLAGS_ADD=-DT_NOTIF1', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_notif1.py b/test_regress/t/t_tri_gate_notif1.py new file mode 100755 index 000000000..09350a74e --- /dev/null +++ b/test_regress/t/t_tri_gate_notif1.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NOTIF1'], + make_flags=['CPPFLAGS_ADD=-DT_NOTIF1'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_notif1_pins_inout.pl b/test_regress/t/t_tri_gate_notif1_pins_inout.pl deleted file mode 100755 index 40ad8dc8c..000000000 --- a/test_regress/t/t_tri_gate_notif1_pins_inout.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NOTIF1',], - make_flags => 'CPPFLAGS_ADD=-DT_NOTIF1', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_notif1_pins_inout.py b/test_regress/t/t_tri_gate_notif1_pins_inout.py new file mode 100755 index 000000000..c03f247c7 --- /dev/null +++ b/test_regress/t/t_tri_gate_notif1_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NOTIF1'], + make_flags=['CPPFLAGS_ADD=-DT_NOTIF1'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_pmos.pl b/test_regress/t/t_tri_gate_pmos.pl deleted file mode 100755 index 2d3352e29..000000000 --- a/test_regress/t/t_tri_gate_pmos.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_PMOS',], - make_flags => 'CPPFLAGS_ADD=-DT_PMOS', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_pmos.py b/test_regress/t/t_tri_gate_pmos.py new file mode 100755 index 000000000..9f23ab621 --- /dev/null +++ b/test_regress/t/t_tri_gate_pmos.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_PMOS'], + make_flags=['CPPFLAGS_ADD=-DT_PMOS'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_pmos_pins_inout.pl b/test_regress/t/t_tri_gate_pmos_pins_inout.pl deleted file mode 100755 index ce203edaa..000000000 --- a/test_regress/t/t_tri_gate_pmos_pins_inout.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_PMOS',], - make_flags => 'CPPFLAGS_ADD=-DT_PMOS', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_pmos_pins_inout.py b/test_regress/t/t_tri_gate_pmos_pins_inout.py new file mode 100755 index 000000000..c9177fd57 --- /dev/null +++ b/test_regress/t/t_tri_gate_pmos_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_PMOS'], + make_flags=['CPPFLAGS_ADD=-DT_PMOS'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gen.pl b/test_regress/t/t_tri_gen.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_tri_gen.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gen.py b/test_regress/t/t_tri_gen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_gen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_graph.pl b/test_regress/t/t_tri_graph.pl deleted file mode 100755 index 079bb20a8..000000000 --- a/test_regress/t/t_tri_graph.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile only test -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_graph.py b/test_regress/t/t_tri_graph.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_tri_graph.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_tri_ifbegin.pl b/test_regress/t/t_tri_ifbegin.pl deleted file mode 100755 index dd4fed003..000000000 --- a/test_regress/t/t_tri_ifbegin.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -# No execution - -ok(1); -1; diff --git a/test_regress/t/t_tri_ifbegin.py b/test_regress/t/t_tri_ifbegin.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_tri_ifbegin.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_inout.pl b/test_regress/t/t_tri_inout.pl deleted file mode 100755 index ce5a6dd80..000000000 --- a/test_regress/t/t_tri_inout.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_inout.py b/test_regress/t/t_tri_inout.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_tri_inout.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_inout2.pl b/test_regress/t/t_tri_inout2.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_tri_inout2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_inout2.py b/test_regress/t/t_tri_inout2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_inout2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_inout_pins_inout.pl b/test_regress/t/t_tri_inout_pins_inout.pl deleted file mode 100755 index f116af7d3..000000000 --- a/test_regress/t/t_tri_inout_pins_inout.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_tri_inout.v"); - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_inout.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_inout_pins_inout.py b/test_regress/t/t_tri_inout_pins_inout.py new file mode 100755 index 000000000..1d13da5b0 --- /dev/null +++ b/test_regress/t/t_tri_inout_pins_inout.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +test.top_filename = "t/t_tri_inout.v" + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_inout.cpp" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_inz.pl b/test_regress/t/t_tri_inz.pl deleted file mode 100755 index 544de0c93..000000000 --- a/test_regress/t/t_tri_inz.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2018 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_inz.py b/test_regress/t/t_tri_inz.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_tri_inz.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_no_top.pl b/test_regress/t/t_tri_no_top.pl deleted file mode 100755 index c0c2e7b13..000000000 --- a/test_regress/t/t_tri_no_top.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --pins-inout-enables --timing --main", "$Self->{t_dir}/t_tri_top_en_out.v"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_no_top.py b/test_regress/t/t_tri_no_top.py new file mode 100755 index 000000000..22d83a776 --- /dev/null +++ b/test_regress/t/t_tri_no_top.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + "--exe --pins-inout-enables --timing --main", test.t_dir + "/t_tri_top_en_out.v" + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_public.pl b/test_regress/t/t_tri_public.pl deleted file mode 100755 index 079bb20a8..000000000 --- a/test_regress/t/t_tri_public.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile only test -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_public.py b/test_regress/t/t_tri_public.py new file mode 100755 index 000000000..c23e16d62 --- /dev/null +++ b/test_regress/t/t_tri_public.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +# Compile only test + +test.passes() diff --git a/test_regress/t/t_tri_pull01.pl b/test_regress/t/t_tri_pull01.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_tri_pull01.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pull01.py b/test_regress/t/t_tri_pull01.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_pull01.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_pull2_bad.pl b/test_regress/t/t_tri_pull2_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_tri_pull2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pull2_bad.py b/test_regress/t/t_tri_pull2_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_tri_pull2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_pull_bad.pl b/test_regress/t/t_tri_pull_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_tri_pull_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pull_bad.py b/test_regress/t/t_tri_pull_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_tri_pull_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_pull_implicit.pl b/test_regress/t/t_tri_pull_implicit.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_tri_pull_implicit.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pull_implicit.py b/test_regress/t/t_tri_pull_implicit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_pull_implicit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_pullup.pl b/test_regress/t/t_tri_pullup.pl deleted file mode 100755 index ce5a6dd80..000000000 --- a/test_regress/t/t_tri_pullup.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pullup.py b/test_regress/t/t_tri_pullup.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_tri_pullup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_pullup_pins_inout.pl b/test_regress/t/t_tri_pullup_pins_inout.pl deleted file mode 100755 index dd6fb477a..000000000 --- a/test_regress/t/t_tri_pullup_pins_inout.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_pullup.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_pullup.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pullup_pins_inout.py b/test_regress/t/t_tri_pullup_pins_inout.py new file mode 100755 index 000000000..fcfabc5fe --- /dev/null +++ b/test_regress/t/t_tri_pullup_pins_inout.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_pullup.cpp" +test.top_filename = "t/t_tri_pullup.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_pullvec_bad.pl b/test_regress/t/t_tri_pullvec_bad.pl deleted file mode 100755 index 48bf31461..000000000 --- a/test_regress/t/t_tri_pullvec_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pullvec_bad.py b/test_regress/t/t_tri_pullvec_bad.py new file mode 100755 index 000000000..6585af685 --- /dev/null +++ b/test_regress/t/t_tri_pullvec_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_select.pl b/test_regress/t/t_tri_select.pl deleted file mode 100755 index ce5a6dd80..000000000 --- a/test_regress/t/t_tri_select.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_select.py b/test_regress/t/t_tri_select.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_tri_select.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_select_eqcase.pl b/test_regress/t/t_tri_select_eqcase.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_tri_select_eqcase.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_select_eqcase.py b/test_regress/t/t_tri_select_eqcase.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_select_eqcase.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_select_pins_inout.pl b/test_regress/t/t_tri_select_pins_inout.pl deleted file mode 100755 index dd9a102c8..000000000 --- a/test_regress/t/t_tri_select_pins_inout.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_select.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_select.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_select_pins_inout.py b/test_regress/t/t_tri_select_pins_inout.py new file mode 100755 index 000000000..da7c9bb9c --- /dev/null +++ b/test_regress/t/t_tri_select_pins_inout.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_select.cpp" +test.top_filename = "t/t_tri_select.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_select_unsized.pl b/test_regress/t/t_tri_select_unsized.pl deleted file mode 100755 index 11a648d2d..000000000 --- a/test_regress/t/t_tri_select_unsized.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile only test -compile( - verilator_flags2 => ["-Wno-WIDTH"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_select_unsized.py b/test_regress/t/t_tri_select_unsized.py new file mode 100755 index 000000000..55e4826e3 --- /dev/null +++ b/test_regress/t/t_tri_select_unsized.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-WIDTH"]) + +test.passes() diff --git a/test_regress/t/t_tri_struct.pl b/test_regress/t/t_tri_struct.pl deleted file mode 100755 index 69c1098d4..000000000 --- a/test_regress/t/t_tri_struct.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -compile( - verilator_flags2 => ['--exe --main --timing'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_struct.py b/test_regress/t/t_tri_struct.py new file mode 100755 index 000000000..2ffd2b3e0 --- /dev/null +++ b/test_regress/t/t_tri_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile(verilator_flags2=['--exe --main --timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_struct_packed.pl b/test_regress/t/t_tri_struct_packed.pl deleted file mode 100755 index 680393eab..000000000 --- a/test_regress/t/t_tri_struct_packed.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--exe --main --timing'], - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_struct_packed.py b/test_regress/t/t_tri_struct_packed.py new file mode 100755 index 000000000..b5b4b8643 --- /dev/null +++ b/test_regress/t/t_tri_struct_packed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--exe --main --timing']) + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_struct_pins_inout.pl b/test_regress/t/t_tri_struct_pins_inout.pl deleted file mode 100755 index 9241088e9..000000000 --- a/test_regress/t/t_tri_struct_pins_inout.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_tri_struct.v"); - -compile( - verilator_flags2 => ['--exe --pins-inout-enables --main --timing'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_struct_pins_inout.py b/test_regress/t/t_tri_struct_pins_inout.py new file mode 100755 index 000000000..3bcf9231a --- /dev/null +++ b/test_regress/t/t_tri_struct_pins_inout.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.top_filename = "t/t_tri_struct.v" + +test.compile(verilator_flags2=['--exe --pins-inout-enables --main --timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_top_en_out.pl b/test_regress/t/t_tri_top_en_out.pl deleted file mode 100755 index 20f49dc28..000000000 --- a/test_regress/t/t_tri_top_en_out.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --timing --pins-inout-enables", "$Self->{t_dir}/$Self->{name}.cpp"], -); - -execute( - check_finished => 1, -); -ok(1); -1; diff --git a/test_regress/t/t_tri_top_en_out.py b/test_regress/t/t_tri_top_en_out.py new file mode 100755 index 000000000..da6e614c5 --- /dev/null +++ b/test_regress/t/t_tri_top_en_out.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --timing --pins-inout-enables", test.pli_filename]) + +test.execute() +test.passes() diff --git a/test_regress/t/t_tri_top_en_out_bad.pl b/test_regress/t/t_tri_top_en_out_bad.pl deleted file mode 100755 index 54537bf8c..000000000 --- a/test_regress/t/t_tri_top_en_out_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 1, - verilator_make_gmake => 1, - verilator_flags2 => ["--exe --pins-inout-enables --no-timing -Wno-STMTDLY"] -); -file_grep_not("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/internal_sub_io__out/); -file_grep_not("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/internal_sub_io__en/); - -ok(1); -1; diff --git a/test_regress/t/t_tri_top_en_out_bad.py b/test_regress/t/t_tri_top_en_out_bad.py new file mode 100755 index 000000000..6b0e5e228 --- /dev/null +++ b/test_regress/t/t_tri_top_en_out_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=1, + verilator_make_gmake=True, + verilator_flags2=["--exe --pins-inout-enables --no-timing -Wno-STMTDLY"]) + +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'internal_sub_io__out') +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'internal_sub_io__en') + +test.passes() diff --git a/test_regress/t/t_tri_unconn.pl b/test_regress/t/t_tri_unconn.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_tri_unconn.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_unconn.py b/test_regress/t/t_tri_unconn.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_unconn.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_various.pl b/test_regress/t/t_tri_various.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_tri_various.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_various.py b/test_regress/t/t_tri_various.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_various.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_type.pl b/test_regress/t/t_type.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_type.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_type.py b/test_regress/t/t_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_type_compare.pl b/test_regress/t/t_type_compare.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_type_compare.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_compare.py b/test_regress/t/t_type_compare.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_type_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_type_compare_bad.pl b/test_regress/t/t_type_compare_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_type_compare_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_compare_bad.py b/test_regress/t/t_type_compare_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_type_compare_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_type_match.pl b/test_regress/t/t_type_match.pl deleted file mode 100755 index 122290bdc..000000000 --- a/test_regress/t/t_type_match.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_match.py b/test_regress/t/t_type_match.py new file mode 100755 index 000000000..c37bc018e --- /dev/null +++ b/test_regress/t/t_type_match.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_type_match.v b/test_regress/t/t_type_match.v index 7c91d571c..b6560e3ce 100644 --- a/test_regress/t/t_type_match.v +++ b/test_regress/t/t_type_match.v @@ -1,10 +1,5 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This module takes a single clock input, and should either -// $write("*-* All Finished *-*\n"); -// $finish; -// on success, or $stop. -// // issue #5125 // type used for __Vtrigprevexpr signal do not match type used for i/o port // @@ -26,58 +21,58 @@ module t (clk); initial cnt=1; always @ (posedge clk) - begin - cnt <= cnt + 1; + begin + cnt <= cnt + 1; - a <= cnt[0]; - $display("%d %d %d", cnt, a, d); - if (d != a) - $stop; + a <= cnt[0]; + $display("%d %d %d", cnt, a, d); + if (d != a) + $stop; - if (cnt == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cnt == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module top ( -input a, -output d -); + input a, + output d + ); -logic b; -logic c[1]; -assign c[0] = b; + logic b; + logic c[1]; + assign c[0] = b; -unit i_unit -( -.a (a), -.b (b), -.c (c), -.d (d) -); + unit i_unit + ( + .a (a), + .b (b), + .c (c), + .d (d) + ); endmodule module unit -( -input a, -input c[1], -output logic b, -output logic d -); + ( + input a, + input c[1], + output logic b, + output logic d + ); -// no_inline required to prevent optimising away the interesing part ... -/*verilator no_inline_module*/ + // no_inline required to prevent optimising away the interesing part ... + /*verilator no_inline_module*/ -always_comb -begin - b = a; - d = b && c[0]; -end + always_comb + begin + b = a; + d = b && c[0]; + end endmodule diff --git a/test_regress/t/t_type_param.pl b/test_regress/t/t_type_param.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_type_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_param.py b/test_regress/t/t_type_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_type_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_type_param_circ_bad.pl b/test_regress/t/t_type_param_circ_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_type_param_circ_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_param_circ_bad.py b/test_regress/t/t_type_param_circ_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_type_param_circ_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_type_param_collision.pl b/test_regress/t/t_type_param_collision.pl deleted file mode 100755 index 247c1e80b..000000000 --- a/test_regress/t/t_type_param_collision.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_type_param.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_param_collision.py b/test_regress/t/t_type_param_collision.py new file mode 100755 index 000000000..a4337c4ed --- /dev/null +++ b/test_regress/t/t_type_param_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_type_param.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef.pl b/test_regress/t/t_typedef.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_typedef.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef.py b/test_regress/t/t_typedef.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_array.pl b/test_regress/t/t_typedef_array.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_typedef_array.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_array.py b/test_regress/t/t_typedef_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_circ_bad.pl b/test_regress/t/t_typedef_circ_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_typedef_circ_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_circ_bad.py b/test_regress/t/t_typedef_circ_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_typedef_circ_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_typedef_consistency_0.pl b/test_regress/t/t_typedef_consistency_0.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_typedef_consistency_0.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_consistency_0.py b/test_regress/t/t_typedef_consistency_0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_consistency_0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_id_bad.out b/test_regress/t/t_typedef_id_bad.out new file mode 100644 index 000000000..f970a5c97 --- /dev/null +++ b/test_regress/t/t_typedef_id_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_typedef_id_bad.v:9:34: Expecting a data type: 'i' + 9 | class Cls #(parameter type P_T = i); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_typedef_id_bad.py b/test_regress/t/t_typedef_id_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_typedef_id_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_typedef_id_bad.v b/test_regress/t/t_typedef_id_bad.v new file mode 100644 index 000000000..fd4482a5f --- /dev/null +++ b/test_regress/t/t_typedef_id_bad.v @@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +int i; + +class Cls #(parameter type P_T = i); +endclass diff --git a/test_regress/t/t_typedef_no_bad.out b/test_regress/t/t_typedef_no_bad.out new file mode 100644 index 000000000..1d17e5fc6 --- /dev/null +++ b/test_regress/t/t_typedef_no_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_typedef_no_bad.v:10:4: Can't find typedef: 'sometype' + 10 | sometype p; + | ^~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_typedef_no_bad.py b/test_regress/t/t_typedef_no_bad.py new file mode 100755 index 000000000..33cb398b7 --- /dev/null +++ b/test_regress/t/t_typedef_no_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--json-only"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_no_typedef_bad.v b/test_regress/t/t_typedef_no_bad.v similarity index 100% rename from test_regress/t/t_no_typedef_bad.v rename to test_regress/t/t_typedef_no_bad.v diff --git a/test_regress/t/t_typedef_package.pl b/test_regress/t/t_typedef_package.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_typedef_package.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_package.py b/test_regress/t/t_typedef_package.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_package.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_param.pl b/test_regress/t/t_typedef_param.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_typedef_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_param.py b/test_regress/t/t_typedef_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_port.pl b/test_regress/t/t_typedef_port.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_typedef_port.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_port.py b/test_regress/t/t_typedef_port.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_signed.pl b/test_regress/t/t_typedef_signed.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_typedef_signed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_signed.py b/test_regress/t/t_typedef_signed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_unused_bad.pl b/test_regress/t/t_typedef_unused_bad.pl deleted file mode 100755 index eb5a450f9..000000000 --- a/test_regress/t/t_typedef_unused_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--Wpedantic"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_unused_bad.py b/test_regress/t/t_typedef_unused_bad.py new file mode 100755 index 000000000..285f30e23 --- /dev/null +++ b/test_regress/t/t_typedef_unused_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--Wpedantic"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_typename.pl b/test_regress/t/t_typename.pl deleted file mode 100755 index eab33bfc9..000000000 --- a/test_regress/t/t_typename.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typename.py b/test_regress/t/t_typename.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_typename.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_typename_min.pl b/test_regress/t/t_typename_min.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_typename_min.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typename_min.py b/test_regress/t/t_typename_min.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typename_min.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typename_min.v b/test_regress/t/t_typename_min.v index d497283f2..8d39ce5cc 100644 --- a/test_regress/t/t_typename_min.v +++ b/test_regress/t/t_typename_min.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 `define stop $stop -`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; int unsigned array[3] = {1, 2, 3}; diff --git a/test_regress/t/t_udp.pl b/test_regress/t/t_udp.pl deleted file mode 100755 index 4f8c004cf..000000000 --- a/test_regress/t/t_udp.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_udp.v"); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_udp.py b/test_regress/t/t_udp.py new file mode 100755 index 000000000..204d47313 --- /dev/null +++ b/test_regress/t/t_udp.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_udp.v" + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_udp_bad.pl b/test_regress/t/t_udp_bad.pl deleted file mode 100755 index fc220ea47..000000000 --- a/test_regress/t/t_udp_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-unsup"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_bad.py b/test_regress/t/t_udp_bad.py new file mode 100755 index 000000000..a0f699e19 --- /dev/null +++ b/test_regress/t/t_udp_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --bbox-unsup"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_udp_lint.pl b/test_regress/t/t_udp_lint.pl deleted file mode 100755 index bce98ae52..000000000 --- a/test_regress/t/t_udp_lint.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_udp.v"); - -lint( - # Unsupported: UDP Tables - verilator_flags2 => ["--lint-only --bbox-unsup"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_lint.py b/test_regress/t/t_udp_lint.py new file mode 100755 index 000000000..c817fb894 --- /dev/null +++ b/test_regress/t/t_udp_lint.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_udp.v" + +test.lint( + # Unsupported: UDP Tables + verilator_flags2=["--lint-only --bbox-unsup"]) + +test.passes() diff --git a/test_regress/t/t_udp_noname.pl b/test_regress/t/t_udp_noname.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_udp_noname.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_noname.py b/test_regress/t/t_udp_noname.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_udp_noname.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_udp_param_bad.pl b/test_regress/t/t_udp_param_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_udp_param_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_param_bad.py b/test_regress/t/t_udp_param_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_udp_param_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_udp_tableend_bad.pl b/test_regress/t/t_udp_tableend_bad.pl deleted file mode 100755 index fc220ea47..000000000 --- a/test_regress/t/t_udp_tableend_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-unsup"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_tableend_bad.py b/test_regress/t/t_udp_tableend_bad.py new file mode 100755 index 000000000..a0f699e19 --- /dev/null +++ b/test_regress/t/t_udp_tableend_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --bbox-unsup"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_udp_tableeof_bad.pl b/test_regress/t/t_udp_tableeof_bad.pl deleted file mode 100755 index 677258838..000000000 --- a/test_regress/t/t_udp_tableeof_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-unsup"], - fails => $Self->{vlt_all}, - # Cannot use .out, get "$end" or "end of file" depending on bison version - expect => qr/EOF in 'table'/, - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_tableeof_bad.py b/test_regress/t/t_udp_tableeof_bad.py new file mode 100755 index 000000000..6b41e2961 --- /dev/null +++ b/test_regress/t/t_udp_tableeof_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --bbox-unsup"], fails=test.vlt_all) + +# Cannot use .out, get "$end" or "end of file" depending on bison version +test.file_grep(test.compile_log_filename, r"EOF in 'table'") + +test.passes() diff --git a/test_regress/t/t_unbounded.pl b/test_regress/t/t_unbounded.pl deleted file mode 100755 index f60fd309f..000000000 --- a/test_regress/t/t_unbounded.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unbounded.py b/test_regress/t/t_unbounded.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unbounded.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unbounded_bad.pl b/test_regress/t/t_unbounded_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_unbounded_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unbounded_bad.py b/test_regress/t/t_unbounded_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_unbounded_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unconnected.pl b/test_regress/t/t_unconnected.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_unconnected.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unconnected.py b/test_regress/t/t_unconnected.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unconnected.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unconnected_bad.pl b/test_regress/t/t_unconnected_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_unconnected_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unconnected_bad.py b/test_regress/t/t_unconnected_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_unconnected_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unicode.pl b/test_regress/t/t_unicode.pl deleted file mode 100755 index 2708b48d1..000000000 --- a/test_regress/t/t_unicode.pl +++ /dev/null @@ -1,57 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; -#use Data::Dumper; -use strict; -use vars qw($Self); - -scenarios(simulator => 1); - -# Greek Hi -my $hi = "Greek: " . c(0xce) . c(0xb3) . c(0xce) . c(0xb5) . c(0xce) . c(0xb9) . c(0xce) . c(0xb1); -sub c { - # Appease https://www.virustotal.com NANO-Antivirus gives Trojan.Script.Vbs-heuristic flag - my $code = shift; - return eval("c" . "h" . "r(" . $code . ")"); -} - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print(c(0xEF)); - $fh->print(c(0xBB)); - $fh->print(c(0xBF)); # BOM - $fh->print("// Bom\n"); - $fh->print("// Generated by t_unicode.pl\n"); - $fh->print("module t;\n"); - $fh->print(" // " . $hi . "\n"); - $fh->print(" initial begin\n"); - $fh->print(" \$write(\"" . $hi . "\\n\");\n"); - $fh->print(" \$write(\"*-* All Finished *-*\\n\");\n"); - $fh->print(" \$finish;\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_unicode.v"); - -gen($Self->{top_filename}); - -compile( - ); - -execute( - check_finished => 1, - expect => $hi, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unicode.py b/test_regress/t/t_unicode.py new file mode 100755 index 000000000..61dc58004 --- /dev/null +++ b/test_regress/t/t_unicode.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = test.obj_dir + "/t_unicode.v" + + +def c(code): + # Appease https://www.virustotal.com NANO-Antivirus gives Trojan.Script.Vbs-heuristic flag + return eval("c" + "h" + "r(" + str(code) + ")") # pylint: disable=eval-used + + +# Greek Hi +hi = "Greek: " + c(0xce) + c(0xb3) + c(0xce) + c(0xb5) + c(0xce) + c(0xb9) + c(0xce) + c(0xb1) + + +def gen(filename): + with open(filename, 'w', encoding="latin-1") as fh: + fh.write(c(0xEF)) + fh.write(c(0xBB)) + fh.write(c(0xBF)) # BOM + fh.write("// Bom\n") + fh.write("// Generated by t_unicode.py\n") + fh.write("module t;\n") + fh.write(" // " + hi + "\n") + fh.write(" initial begin\n") + fh.write(" $write(\"" + hi + "\\n\");\n") + fh.write(" $write(\"*-* All Finished *-*\\n\");\n") + fh.write(" $finish;\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen(test.top_filename) + +test.compile() + +test.execute() + +test.file_grep(test.run_log_filename, hi) + +test.passes() diff --git a/test_regress/t/t_union_soft.pl b/test_regress/t/t_union_soft.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_union_soft.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_union_soft.py b/test_regress/t/t_union_soft.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_union_soft.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_union_unpacked.pl b/test_regress/t/t_union_unpacked.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_union_unpacked.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_union_unpacked.py b/test_regress/t/t_union_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_union_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_uniqueif.pl b/test_regress/t/t_uniqueif.pl deleted file mode 100755 index 59aeed76c..000000000 --- a/test_regress/t/t_uniqueif.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_uniqueif.py b/test_regress/t/t_uniqueif.py new file mode 100755 index 000000000..d97aaff01 --- /dev/null +++ b/test_regress/t/t_uniqueif.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_uniqueif_fail1.pl b/test_regress/t/t_uniqueif_fail1.pl deleted file mode 100755 index 0b8089a46..000000000 --- a/test_regress/t/t_uniqueif_fail1.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_uniqueif.v"); - -compile( - v_flags2 => ['+define+FAILING_ASSERTION1'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - fails => $Self->{nc}, - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_uniqueif_fail1.py b/test_regress/t/t_uniqueif_fail1.py new file mode 100755 index 000000000..8eeaeefee --- /dev/null +++ b/test_regress/t/t_uniqueif_fail1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_uniqueif.v" + +test.compile(v_flags2=['+define+FAILING_ASSERTION1'], + verilator_flags2=['--assert'], + nc_flags2=['+assert'], + fails=test.nc) + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_uniqueif_fail2.pl b/test_regress/t/t_uniqueif_fail2.pl deleted file mode 100755 index 0f3406ade..000000000 --- a/test_regress/t/t_uniqueif_fail2.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_uniqueif.v"); - -compile( - v_flags2 => ['+define+FAILING_ASSERTION2'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - fails => $Self->{nc}, - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_uniqueif_fail2.py b/test_regress/t/t_uniqueif_fail2.py new file mode 100755 index 000000000..f94dedc48 --- /dev/null +++ b/test_regress/t/t_uniqueif_fail2.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_uniqueif.v" + +test.compile(v_flags2=['+define+FAILING_ASSERTION2'], + verilator_flags2=['--assert'], + nc_flags2=['+assert'], + fails=test.nc) + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_uniqueif_fail3.pl b/test_regress/t/t_uniqueif_fail3.pl deleted file mode 100755 index eb8c557ae..000000000 --- a/test_regress/t/t_uniqueif_fail3.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_uniqueif.v"); - -compile( - v_flags2 => ['+define+FAILING_ASSERTION3'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - fails => $Self->{nc}, - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_uniqueif_fail3.py b/test_regress/t/t_uniqueif_fail3.py new file mode 100755 index 000000000..e52b3e975 --- /dev/null +++ b/test_regress/t/t_uniqueif_fail3.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_uniqueif.v" + +test.compile(v_flags2=['+define+FAILING_ASSERTION3'], + verilator_flags2=['--assert'], + nc_flags2=['+assert'], + fails=test.nc) + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_uniqueif_fail4.pl b/test_regress/t/t_uniqueif_fail4.pl deleted file mode 100755 index 6f236b834..000000000 --- a/test_regress/t/t_uniqueif_fail4.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_uniqueif.v"); - -compile( - v_flags2 => ['+define+FAILING_ASSERTION4'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - fails => $Self->{nc}, - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_uniqueif_fail4.py b/test_regress/t/t_uniqueif_fail4.py new file mode 100755 index 000000000..ee0e4f768 --- /dev/null +++ b/test_regress/t/t_uniqueif_fail4.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_uniqueif.v" + +test.compile(v_flags2=['+define+FAILING_ASSERTION4'], + verilator_flags2=['--assert'], + nc_flags2=['+assert'], + fails=test.nc) + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unopt_array.pl b/test_regress/t/t_unopt_array.pl deleted file mode 100755 index 6bef1be6c..000000000 --- a/test_regress/t/t_unopt_array.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_array.py b/test_regress/t/t_unopt_array.py new file mode 100755 index 000000000..c37bc018e --- /dev/null +++ b/test_regress/t/t_unopt_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_array_csplit.pl b/test_regress/t/t_unopt_array_csplit.pl deleted file mode 100755 index eae29afb9..000000000 --- a/test_regress/t/t_unopt_array_csplit.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_unopt_array.v"); -compile( - v_flags2 => ["--trace --output-split 1 --output-split-cfuncs 1 -Wno-UNOPTFLAT"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_array_csplit.py b/test_regress/t/t_unopt_array_csplit.py new file mode 100755 index 000000000..26fd8b3d1 --- /dev/null +++ b/test_regress/t/t_unopt_array_csplit.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_unopt_array.v" + +test.compile(v_flags2=["--trace --output-split 1 --output-split-cfuncs 1 -Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_array_typedef.pl b/test_regress/t/t_unopt_array_typedef.pl deleted file mode 100755 index ecce1d841..000000000 --- a/test_regress/t/t_unopt_array_typedef.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_array.v"); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT +define+USE_TYPEDEF"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_array_typedef.py b/test_regress/t/t_unopt_array_typedef.py new file mode 100755 index 000000000..809e92873 --- /dev/null +++ b/test_regress/t/t_unopt_array_typedef.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_array.v" + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT +define+USE_TYPEDEF"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_bound.pl b/test_regress/t/t_unopt_bound.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_unopt_bound.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_bound.py b/test_regress/t/t_unopt_bound.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unopt_bound.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_combo.pl b/test_regress/t/t_unopt_combo.pl deleted file mode 100755 index 16e6f0588..000000000 --- a/test_regress/t/t_unopt_combo.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['+define+ALLOW_UNOPT'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_combo.py b/test_regress/t/t_unopt_combo.py new file mode 100755 index 000000000..64265ff66 --- /dev/null +++ b/test_regress/t/t_unopt_combo.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['+define+ALLOW_UNOPT']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_combo_bad.pl b/test_regress/t/t_unopt_combo_bad.pl deleted file mode 100755 index 5590ecd32..000000000 --- a/test_regress/t/t_unopt_combo_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_combo.v"); - -compile( - v_flags2 => ['+define+ATTRIBUTES'], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_unopt_combo_bad.py b/test_regress/t/t_unopt_combo_bad.py new file mode 100755 index 000000000..1592b6d48 --- /dev/null +++ b/test_regress/t/t_unopt_combo_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_combo.v" + +test.compile(v_flags2=['+define+ATTRIBUTES'], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_combo_isolate.pl b/test_regress/t/t_unopt_combo_isolate.pl deleted file mode 100755 index 8eccab6d3..000000000 --- a/test_regress/t/t_unopt_combo_isolate.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_combo.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["--no-json-edit-nums +define+ISOLATE --stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+3/i); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.b",.*"loc":"e,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__Vfuncout",.*"loc":"e,99:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__t_crc",.*"loc":"e,100:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_crc",.*"loc":"e,112:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_c",.*"loc":"e,113:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_c",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_combo_isolate.py b/test_regress/t/t_unopt_combo_isolate.py new file mode 100755 index 000000000..c7f9f968d --- /dev/null +++ b/test_regress/t/t_unopt_combo_isolate.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_combo.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=["--no-json-edit-nums +define+ISOLATE --stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+3') + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.b",.*"loc":"e,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__Vfuncout",.*"loc":"e,99:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__t_crc",.*"loc":"e,100:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_crc",.*"loc":"e,112:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_c",.*"loc":"e,113:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_c",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_combo_isolate_vlt.pl b/test_regress/t/t_unopt_combo_isolate_vlt.pl deleted file mode 100755 index 523a49945..000000000 --- a/test_regress/t/t_unopt_combo_isolate_vlt.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_combo.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["--no-json-edit-nums --stats $Self->{t_dir}/t_unopt_combo_isolate.vlt"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+3/i); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.b",.*"loc":"f,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__Vfuncout",.*"loc":"f,104:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__t_crc",.*"loc":"f,105:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_crc",.*"loc":"f,115:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_c",.*"loc":"f,116:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_c",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_combo_isolate_vlt.py b/test_regress/t/t_unopt_combo_isolate_vlt.py new file mode 100755 index 000000000..eab58591c --- /dev/null +++ b/test_regress/t/t_unopt_combo_isolate_vlt.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_combo.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile( + verilator_flags2=["--no-json-edit-nums --stats", test.t_dir + "/t_unopt_combo_isolate.vlt"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+3') + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.b",.*"loc":"f,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__Vfuncout",.*"loc":"f,104:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__t_crc",.*"loc":"f,105:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_crc",.*"loc":"f,115:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_c",.*"loc":"f,116:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_c",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_combo_waive.pl b/test_regress/t/t_unopt_combo_waive.pl deleted file mode 100755 index 99f3041e4..000000000 --- a/test_regress/t/t_unopt_combo_waive.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_unopt_combo.v"); - -compile( - v_flags2 => ['+define+ATTRIBUTES', "t/t_unopt_combo.vlt"], - # Passes, as we waived - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_combo_waive.py b/test_regress/t/t_unopt_combo_waive.py new file mode 100755 index 000000000..508a70141 --- /dev/null +++ b/test_regress/t/t_unopt_combo_waive.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_unopt_combo.v" + +test.compile(v_flags2=['+define+ATTRIBUTES', "t/t_unopt_combo.vlt"], + # Passes, as we waived + ) + +test.passes() diff --git a/test_regress/t/t_unopt_converge_initial_run_bad.pl b/test_regress/t/t_unopt_converge_initial_run_bad.pl deleted file mode 100755 index 8825ddf1e..000000000 --- a/test_regress/t/t_unopt_converge_initial_run_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2007 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_converge_initial.v"); - -compile( - v_flags2 => ['+define+ALLOW_UNOPT --output-split 0'], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ) if $Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_unopt_converge_initial_run_bad.py b/test_regress/t/t_unopt_converge_initial_run_bad.py new file mode 100755 index 000000000..ebc9607d7 --- /dev/null +++ b/test_regress/t/t_unopt_converge_initial_run_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_converge_initial.v" + +test.compile(v_flags2=['+define+ALLOW_UNOPT --output-split 0']) + +if test.vlt_all: + test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unopt_converge_ndbg_bad.pl b/test_regress/t/t_unopt_converge_ndbg_bad.pl deleted file mode 100755 index 929013cbc..000000000 --- a/test_regress/t/t_unopt_converge_ndbg_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2007 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_converge.v"); - -compile( - v_flags2 => ['+define+ALLOW_UNOPT'], - make_flags => 'CPPFLAGS_ADD=-UVL_DEBUG', - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ) if $Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_unopt_converge_ndbg_bad.py b/test_regress/t/t_unopt_converge_ndbg_bad.py new file mode 100755 index 000000000..65b34b60c --- /dev/null +++ b/test_regress/t/t_unopt_converge_ndbg_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_converge.v" + +test.compile(v_flags2=['+define+ALLOW_UNOPT'], make_flags=['CPPFLAGS_ADD=-UVL_DEBUG']) + +if test.vlt_all: + test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unopt_converge_print_bad.pl b/test_regress/t/t_unopt_converge_print_bad.pl deleted file mode 100755 index c20b4c98f..000000000 --- a/test_regress/t/t_unopt_converge_print_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2007 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_converge.v"); -#$Self->{verilated_debug} = 1; - -compile( - v_flags2 => ['+define+ALLOW_UNOPT --output-split 0'], - make_flags => 'CPPFLAGS_ADD=-DVL_DEBUG', - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ) if $Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_unopt_converge_print_bad.py b/test_regress/t/t_unopt_converge_print_bad.py new file mode 100755 index 000000000..d38fcc4a0 --- /dev/null +++ b/test_regress/t/t_unopt_converge_print_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_converge.v" +#test.verilated_debug = 1 + +test.compile(v_flags2=['+define+ALLOW_UNOPT --output-split 0'], + make_flags=['CPPFLAGS_ADD=-DVL_DEBUG']) + +if test.vlt_all: + test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unopt_converge_run_bad.pl b/test_regress/t/t_unopt_converge_run_bad.pl deleted file mode 100755 index ce55a1d72..000000000 --- a/test_regress/t/t_unopt_converge_run_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2007 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_converge.v"); - -compile( - v_flags2 => ['+define+ALLOW_UNOPT --output-split 0'], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ) if $Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_unopt_converge_run_bad.py b/test_regress/t/t_unopt_converge_run_bad.py new file mode 100755 index 000000000..846df0093 --- /dev/null +++ b/test_regress/t/t_unopt_converge_run_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_converge.v" + +test.compile(v_flags2=['+define+ALLOW_UNOPT --output-split 0']) + +if test.vlt_all: + test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unopt_converge_unopt_bad.pl b/test_regress/t/t_unopt_converge_unopt_bad.pl deleted file mode 100755 index cd6d7d7c5..000000000 --- a/test_regress/t/t_unopt_converge_unopt_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2007 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_unopt_converge.v"); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_converge_unopt_bad.py b/test_regress/t/t_unopt_converge_unopt_bad.py new file mode 100755 index 000000000..23a3f47d2 --- /dev/null +++ b/test_regress/t/t_unopt_converge_unopt_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_unopt_converge.v" + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unoptflat_simple_2_bad.pl b/test_regress/t/t_unoptflat_simple_2_bad.pl deleted file mode 100755 index 285d1dffd..000000000 --- a/test_regress/t/t_unoptflat_simple_2_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unoptflat_simple_2.v"); - -# Compile only -compile( - verilator_flags3 => [], - verilator_flags2 => ["--report-unoptflat"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - -ok(1); -1; diff --git a/test_regress/t/t_unoptflat_simple_2_bad.py b/test_regress/t/t_unoptflat_simple_2_bad.py new file mode 100755 index 000000000..5c6e4b955 --- /dev/null +++ b/test_regress/t/t_unoptflat_simple_2_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unoptflat_simple_2.v" + +# Compile only +test.compile(verilator_flags3=[], + verilator_flags2=["--report-unoptflat"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unoptflat_simple_3_bad.pl b/test_regress/t/t_unoptflat_simple_3_bad.pl deleted file mode 100755 index b838ad45f..000000000 --- a/test_regress/t/t_unoptflat_simple_3_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unoptflat_simple_3.v"); - -# Compile only -compile( - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_unoptflat_simple_3_bad.py b/test_regress/t/t_unoptflat_simple_3_bad.py new file mode 100755 index 000000000..7c3da3bf6 --- /dev/null +++ b/test_regress/t/t_unoptflat_simple_3_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unoptflat_simple_3.v" + +# Compile only +test.compile(fails=True) + +test.passes() diff --git a/test_regress/t/t_unoptflat_simple_bad.pl b/test_regress/t/t_unoptflat_simple_bad.pl deleted file mode 100755 index 2a9c4d934..000000000 --- a/test_regress/t/t_unoptflat_simple_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unoptflat_simple.v"); - -# Compile only -compile( - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_unoptflat_simple_bad.py b/test_regress/t/t_unoptflat_simple_bad.py new file mode 100755 index 000000000..85da89728 --- /dev/null +++ b/test_regress/t/t_unoptflat_simple_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unoptflat_simple.v" + +# Compile only +test.compile(fails=True) + +test.passes() diff --git a/test_regress/t/t_unpack_array_direct_assignment.pl b/test_regress/t/t_unpack_array_direct_assignment.pl deleted file mode 100755 index 29a73f42a..000000000 --- a/test_regress/t/t_unpack_array_direct_assignment.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unpack_array_no_expand.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpack_array_direct_assignment.py b/test_regress/t/t_unpack_array_direct_assignment.py new file mode 100755 index 000000000..dd7cd31de --- /dev/null +++ b/test_regress/t/t_unpack_array_direct_assignment.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unpack_array_no_expand.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpack_array_no_expand.pl b/test_regress/t/t_unpack_array_no_expand.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_unpack_array_no_expand.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpack_array_no_expand.py b/test_regress/t/t_unpack_array_no_expand.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpack_array_no_expand.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_array_order.pl b/test_regress/t/t_unpacked_array_order.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_unpacked_array_order.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_array_order.py b/test_regress/t/t_unpacked_array_order.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_array_order.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_array_p_fmt.pl b/test_regress/t/t_unpacked_array_p_fmt.pl deleted file mode 100755 index 6e4e9e231..000000000 --- a/test_regress/t/t_unpacked_array_p_fmt.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_array_p_fmt.py b/test_regress/t/t_unpacked_array_p_fmt.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_unpacked_array_p_fmt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unpacked_concat.pl b/test_regress/t/t_unpacked_concat.pl deleted file mode 100755 index 354bf40cc..000000000 --- a/test_regress/t/t_unpacked_concat.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); -execute( - check_finished => 1, - ); - - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_concat.py b/test_regress/t/t_unpacked_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_concat.v b/test_regress/t/t_unpacked_concat.v index 1c73f8ffd..468518ab2 100644 --- a/test_regress/t/t_unpacked_concat.v +++ b/test_regress/t/t_unpacked_concat.v @@ -4,12 +4,7 @@ // without warranty, 2023 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); typedef int AI3[1:3]; AI3 A3; diff --git a/test_regress/t/t_unpacked_concat_bad.out b/test_regress/t/t_unpacked_concat_bad.out index e2c0f4797..6b736d415 100644 --- a/test_regress/t/t_unpacked_concat_bad.out +++ b/test_regress/t/t_unpacked_concat_bad.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_unpacked_concat_bad.v:17:46: Unsupported: Non-1 replication to form 'bit[31:0]$[1:0]' data type +%Error-UNSUPPORTED: t/t_unpacked_concat_bad.v:12:46: Unsupported: Non-1 replication to form 'bit[31:0]$[1:0]' data type : ... note: In instance 't' - 17 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; + 12 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_unpacked_concat_bad.pl b/test_regress/t/t_unpacked_concat_bad.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_unpacked_concat_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_concat_bad.py b/test_regress/t/t_unpacked_concat_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_unpacked_concat_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unpacked_concat_bad.v b/test_regress/t/t_unpacked_concat_bad.v index 70cb5c37a..bcd1780cc 100644 --- a/test_regress/t/t_unpacked_concat_bad.v +++ b/test_regress/t/t_unpacked_concat_bad.v @@ -4,12 +4,7 @@ // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); typedef logic [15:0] count_t; typedef bit [31:0] bit_int_t; diff --git a/test_regress/t/t_unpacked_concat_bad2.out b/test_regress/t/t_unpacked_concat_bad2.out index 1a5e93630..bc664a764 100644 --- a/test_regress/t/t_unpacked_concat_bad2.out +++ b/test_regress/t/t_unpacked_concat_bad2.out @@ -1,13 +1,13 @@ -%Error: t/t_unpacked_concat_bad2.v:25:15: Array initialization has too many elements. 2 elements are expected, but at least 5 elements exist. - 25 | s1 = {s0, s2}; +%Error: t/t_unpacked_concat_bad2.v:20:15: Array initialization has too many elements. 2 elements are expected, but at least 5 elements exist. + 20 | s1 = {s0, s2}; | ^ -%Error: t/t_unpacked_concat_bad2.v:26:23: Array initialization has too many elements. 4 elements are expected, but at least 5 elements exist. - 26 | s2 = {s1, s0, s0, s0}; +%Error: t/t_unpacked_concat_bad2.v:21:23: Array initialization has too many elements. 4 elements are expected, but at least 5 elements exist. + 21 | s2 = {s1, s0, s0, s0}; | ^ -%Error: t/t_unpacked_concat_bad2.v:28:17: Item is incompatible with the array type. - 28 | s2 = {s0, s3}; +%Error: t/t_unpacked_concat_bad2.v:23:17: Item is incompatible with the array type. + 23 | s2 = {s0, s3}; | ^~ -%Error: t/t_unpacked_concat_bad2.v:30:19: Item is incompatible with the array type. - 30 | A9_logic = {A3, 4, 5, A3, 6}; +%Error: t/t_unpacked_concat_bad2.v:25:19: Item is incompatible with the array type. + 25 | A9_logic = {A3, 4, 5, A3, 6}; | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_unpacked_concat_bad2.pl b/test_regress/t/t_unpacked_concat_bad2.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_unpacked_concat_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_concat_bad2.py b/test_regress/t/t_unpacked_concat_bad2.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_unpacked_concat_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unpacked_concat_bad2.v b/test_regress/t/t_unpacked_concat_bad2.v index ba3800237..c487916f3 100644 --- a/test_regress/t/t_unpacked_concat_bad2.v +++ b/test_regress/t/t_unpacked_concat_bad2.v @@ -4,12 +4,7 @@ // without warranty, 2023 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t (/*AUTOARG*/); logic [7:0] s0; logic [7:0] s1[1:2]; diff --git a/test_regress/t/t_unpacked_concat_bad3.out b/test_regress/t/t_unpacked_concat_bad3.out new file mode 100644 index 000000000..4bd30ce0c --- /dev/null +++ b/test_regress/t/t_unpacked_concat_bad3.out @@ -0,0 +1,4 @@ +%Error: Internal Error: t/t_unpacked_concat_bad3.v:9:41: ../V3EmitCConstInit.h:#: Missing array init element + 9 | localparam logic [7:0] TOO_FEW [5] = '{0, 1, 2**8-1}; + | ^~ + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_unpacked_concat_bad3.py b/test_regress/t/t_unpacked_concat_bad3.py new file mode 100755 index 000000000..88e1a07b1 --- /dev/null +++ b/test_regress/t/t_unpacked_concat_bad3.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# Not lint, crashes in V3EmitCConstInit.h +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unpacked_concat_bad3.v b/test_regress/t/t_unpacked_concat_bad3.v new file mode 100644 index 000000000..1efdb08a5 --- /dev/null +++ b/test_regress/t/t_unpacked_concat_bad3.v @@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Driss Hafdi. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + localparam logic [7:0] TOO_FEW [5] = '{0, 1, 2**8-1}; // Bad + + initial begin + $display("%p", TOO_FEW); + $stop; + end +endmodule diff --git a/test_regress/t/t_unpacked_init.pl b/test_regress/t/t_unpacked_init.pl deleted file mode 100755 index 9a15dd2cc..000000000 --- a/test_regress/t/t_unpacked_init.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_init.py b/test_regress/t/t_unpacked_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_slice.pl b/test_regress/t/t_unpacked_slice.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_unpacked_slice.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_slice.py b/test_regress/t/t_unpacked_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_slice_range.pl b/test_regress/t/t_unpacked_slice_range.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_unpacked_slice_range.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_slice_range.py b/test_regress/t/t_unpacked_slice_range.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_slice_range.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_str_init.pl b/test_regress/t/t_unpacked_str_init.pl deleted file mode 100755 index baf0745f9..000000000 --- a/test_regress/t/t_unpacked_str_init.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -# No execute, not self-checking - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_str_init.py b/test_regress/t/t_unpacked_str_init.py new file mode 100755 index 000000000..e77872b79 --- /dev/null +++ b/test_regress/t/t_unpacked_str_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +# No execute, not self-checking + +test.passes() diff --git a/test_regress/t/t_unpacked_str_init2.pl b/test_regress/t/t_unpacked_str_init2.pl deleted file mode 100755 index bd862f553..000000000 --- a/test_regress/t/t_unpacked_str_init2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_str_init2.py b/test_regress/t/t_unpacked_str_init2.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_unpacked_str_init2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unpacked_str_pair.pl b/test_regress/t/t_unpacked_str_pair.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_unpacked_str_pair.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_str_pair.py b/test_regress/t/t_unpacked_str_pair.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_str_pair.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_struct_eq.pl b/test_regress/t/t_unpacked_struct_eq.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_unpacked_struct_eq.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_struct_eq.py b/test_regress/t/t_unpacked_struct_eq.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_struct_eq.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_struct_redef.pl b/test_regress/t/t_unpacked_struct_redef.pl deleted file mode 100755 index 859050d63..000000000 --- a/test_regress/t/t_unpacked_struct_redef.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_struct_redef.py b/test_regress/t/t_unpacked_struct_redef.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_struct_redef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_struct_sel.pl b/test_regress/t/t_unpacked_struct_sel.pl deleted file mode 100755 index 1aa73f80a..000000000 --- a/test_regress/t/t_unpacked_struct_sel.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_struct_sel.py b/test_regress/t/t_unpacked_struct_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_struct_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unroll_complexcond.pl b/test_regress/t/t_unroll_complexcond.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_unroll_complexcond.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_complexcond.py b/test_regress/t/t_unroll_complexcond.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unroll_complexcond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unroll_delay.pl b/test_regress/t/t_unroll_delay.pl deleted file mode 100755 index a9298001e..000000000 --- a/test_regress/t/t_unroll_delay.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --timing --trace'], - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_delay.py b/test_regress/t/t_unroll_delay.py new file mode 100755 index 000000000..47049c4c4 --- /dev/null +++ b/test_regress/t/t_unroll_delay.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --timing --trace']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unroll_forfor.pl b/test_regress/t/t_unroll_forfor.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_unroll_forfor.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_forfor.py b/test_regress/t/t_unroll_forfor.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unroll_forfor.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unroll_genf.pl b/test_regress/t/t_unroll_genf.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_unroll_genf.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_genf.py b/test_regress/t/t_unroll_genf.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unroll_genf.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unroll_pragma_disable.pl b/test_regress/t/t_unroll_pragma_disable.pl deleted file mode 100755 index be362c068..000000000 --- a/test_regress/t/t_unroll_pragma_disable.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_unroll_pragma.v"); - -compile( - verilator_flags2 => ['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_DISABLE'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -file_grep($Self->{stats}, qr/Optimizations, Unrolled Loops\s+(\d+)/i, 1); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_pragma_disable.py b/test_regress/t/t_unroll_pragma_disable.py new file mode 100755 index 000000000..62b1b7832 --- /dev/null +++ b/test_regress/t/t_unroll_pragma_disable.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_unroll_pragma.v" + +test.compile(verilator_flags2=['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_DISABLE'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.file_grep(test.stats, r'Optimizations, Unrolled Loops\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_unroll_pragma_full.pl b/test_regress/t/t_unroll_pragma_full.pl deleted file mode 100755 index 0b58b01a9..000000000 --- a/test_regress/t/t_unroll_pragma_full.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_unroll_pragma.v"); - -compile( - verilator_flags2 => ['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_FULL'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -file_grep($Self->{stats}, qr/Optimizations, Unrolled Loops\s+(\d+)/i, 5); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_pragma_full.py b/test_regress/t/t_unroll_pragma_full.py new file mode 100755 index 000000000..6018f47de --- /dev/null +++ b/test_regress/t/t_unroll_pragma_full.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_unroll_pragma.v" + +test.compile(verilator_flags2=['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_FULL'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.file_grep(test.stats, r'Optimizations, Unrolled Loops\s+(\d+)', 5) + +test.passes() diff --git a/test_regress/t/t_unroll_pragma_none.pl b/test_regress/t/t_unroll_pragma_none.pl deleted file mode 100755 index 933e315a3..000000000 --- a/test_regress/t/t_unroll_pragma_none.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_unroll_pragma.v"); - -compile( - verilator_flags2 => ['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_NONE'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -file_grep($Self->{stats}, qr/Optimizations, Unrolled Loops\s+(\d+)/i, 3); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_pragma_none.py b/test_regress/t/t_unroll_pragma_none.py new file mode 100755 index 000000000..34fedcad9 --- /dev/null +++ b/test_regress/t/t_unroll_pragma_none.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_unroll_pragma.v" + +test.compile(verilator_flags2=['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_NONE'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.file_grep(test.stats, r'Optimizations, Unrolled Loops\s+(\d+)', 3) + +test.passes() diff --git a/test_regress/t/t_unroll_signed.pl b/test_regress/t/t_unroll_signed.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_unroll_signed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_signed.py b/test_regress/t/t_unroll_signed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unroll_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unroll_unopt_io.pl b/test_regress/t/t_unroll_unopt_io.pl deleted file mode 100755 index 1df6afd70..000000000 --- a/test_regress/t/t_unroll_unopt_io.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--x-assign fast'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_unopt_io.py b/test_regress/t/t_unroll_unopt_io.py new file mode 100755 index 000000000..af1f37c0c --- /dev/null +++ b/test_regress/t/t_unroll_unopt_io.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--x-assign fast']) + +test.passes() diff --git a/test_regress/t/t_urandom.pl b/test_regress/t/t_urandom.pl deleted file mode 100755 index aabcde63e..000000000 --- a/test_regress/t/t_urandom.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_urandom.py b/test_regress/t/t_urandom.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_urandom.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_user_type_xassign.py b/test_regress/t/t_user_type_xassign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_user_type_xassign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_user_type_xassign.v b/test_regress/t/t_user_type_xassign.v new file mode 100644 index 000000000..9cfc02cd9 --- /dev/null +++ b/test_regress/t/t_user_type_xassign.v @@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Demonstrate complex user typea problem with --x-assign +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + typedef logic [31:0] int_t; + typedef int_t [6:0] bar_t; + bar_t the_bar; + + logic [31:0] thing_one; + always_comb begin + for (int sel = 0; sel < 1; sel++) + thing_one = the_bar[sel]; + end + + virtual class SomeClass; + static function logic compare(int a, int b); + return a > b; + endfunction + endclass + + logic [31:0] thing_two; + always_comb begin + for (int sel_a = 0; sel_a < 1; sel_a++) + thing_two = the_bar[sel_a]; + end + + // finish report + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + +endmodule diff --git a/test_regress/t/t_uvm_all.pl b/test_regress/t/t_uvm_all.pl deleted file mode 100755 index 77aac6e6b..000000000 --- a/test_regress/t/t_uvm_all.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--binary --timing", - "-Wno-PKGNODECL -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT", - "-Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-CASTCONST -Wno-REALCVT", - "--error-limit 200 --debug-exit-uvm"], - verilator_make_gmake => 0, - ); - -#execute( -# check_finished => 1, -# ); - -ok(1); -1; diff --git a/test_regress/t/t_uvm_all.py b/test_regress/t/t_uvm_all.py new file mode 100755 index 000000000..790de6b74 --- /dev/null +++ b/test_regress/t/t_uvm_all.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + v_flags2=[ + "--binary --timing", # + "-Wno-PKGNODECL -Wno-IMPLICITSTATIC -Wno-MISINDENT", + "-Wno-CASEINCOMPLETE -Wno-CASTCONST -Wno-SYMRSVDWORD -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC", + "-Wno-REALCVT", # TODO note mostly related to $realtime - could suppress or fix upstream + "--error-limit 200 --debug-exit-uvm" + ], + verilator_make_gmake=False) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_uvm_pkg_all.vh b/test_regress/t/t_uvm_pkg_all.vh index 2c97fecb3..362e714b8 100644 --- a/test_regress/t/t_uvm_pkg_all.vh +++ b/test_regress/t/t_uvm_pkg_all.vh @@ -3,7 +3,7 @@ //------------------------------------------------------------------------------ // To recreate: // Using verilator_ext_tests -// t/t_uvm_parse.pl --debug --no-dump-tree +// t/t_uvm_parse.py --debug --no-dump-tree // Copy to here t/obj_vlt/Vt_uvm_parse/Vt_uvm_parse__inputs.vpp // M-x untabify // (global-replace-regexp "[ ]+$" "") diff --git a/test_regress/t/t_uvm_pkg_todo.vh b/test_regress/t/t_uvm_pkg_todo.vh index 58823aa81..888258fa2 100644 --- a/test_regress/t/t_uvm_pkg_todo.vh +++ b/test_regress/t/t_uvm_pkg_todo.vh @@ -3,7 +3,7 @@ //------------------------------------------------------------------------------ // To recreate: // Using verilator_ext_tests -// t/t_uvm_parse.pl --debug --no-dump-tree +// t/t_uvm_parse.py --debug --no-dump-tree // Copy to here t/obj_vlt/Vt_uvm_parse/Vt_uvm_parse__inputs.vpp // M-x untabify // (global-replace-regexp "[ ]+$" "") @@ -20256,9 +20256,7 @@ virtual class uvm_sequence_base extends uvm_sequence_item; if (is_rel_default != wait_rel_default) uvm_report_fatal("RELMSM", "is_relevant() was implemented without defining wait_for_relevant()", UVM_NONE); -//TODO issue #4495 - unsupported local event - may want to model the larger context where is used - might be case where edit upstream? -//TODO %Error-UNSUPPORTED: t/t_uvm_pkg_todo.vh:20247:5: Unsupported: waiting on local event variables -//TODO @e; + @e; endtask task lock(uvm_sequencer_base sequencer = null); if (sequencer == null) @@ -21074,21 +21072,15 @@ typedef class uvm_tlm_extension_base; class uvm_tlm_generic_payload extends uvm_sequence_item; rand bit [63:0] m_address; rand uvm_tlm_command_e m_command; - //TODO issue-4625 - Rand fields of dynamic array types - //TODO %Error-UNSUPPORTED: t/t_uvm_pkg_todo.vh:21081:35: Unsupported: random member variable with type 'byte[]' - /*TODO rand*/ byte unsigned m_data[]; + rand byte unsigned m_data[]; rand int unsigned m_length; rand uvm_tlm_response_status_e m_response_status; bit m_dmi; - //TODO issue-4625 - Rand fields of dynamic array types - //TODO %Error-UNSUPPORTED: t/t_uvm_pkg_todo.vh:21081:35: Unsupported: random member variable with type 'byte[]' - /*TODO rand*/ byte unsigned m_byte_enable[]; + rand byte unsigned m_byte_enable[]; rand int unsigned m_byte_enable_length; rand int unsigned m_streaming_width; protected uvm_tlm_extension_base m_extensions [uvm_tlm_extension_base]; - //TODO issue-4625 - Rand fields of dynamic array types - //TODO %Error-UNSUPPORTED: t/t_uvm_pkg_todo.vh:21081:35: Unsupported: random member variable with type 'CLASSREFDTYPE 'uvm_tlm_extension_base'[]' - local /*rand*/ uvm_tlm_extension_base m_rand_exts[]; + local rand uvm_tlm_extension_base m_rand_exts[]; typedef uvm_object_registry#(uvm_tlm_generic_payload,"uvm_tlm_generic_payload") type_id; static function uvm_tlm_generic_payload type_id_create (string name="", uvm_component parent=null, diff --git a/test_regress/t/t_uvm_todo.pl b/test_regress/t/t_uvm_todo.pl deleted file mode 100755 index 5d005a5d2..000000000 --- a/test_regress/t/t_uvm_todo.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--timing", - "-Wno-PKGNODECL -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT", - "-Wno-CASEINCOMPLETE -Wno-CASTCONST -Wno-SYMRSVDWORD -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC", - "-Wno-REALCVT", # TODO note mostly related to $realtime - could suppress or fix upstream - "-Wno-ZERODLY", # TODO issue #4494, add support - ], - make_flags => '-k -j ' . ::max_procs(), - verilator_make_gmake => 0, - ); - -#execute( -# check_finished => 1, -# ); - -ok(1); -1; diff --git a/test_regress/t/t_uvm_todo.py b/test_regress/t/t_uvm_todo.py new file mode 100755 index 000000000..91773036f --- /dev/null +++ b/test_regress/t/t_uvm_todo.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import multiprocessing + +test.scenarios('vlt') + +test.compile( + v_flags2=[ + "--timing", # + "-Wno-PKGNODECL -Wno-IMPLICITSTATIC -Wno-MISINDENT", + "-Wno-CASEINCOMPLETE -Wno-CASTCONST -Wno-SYMRSVDWORD -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC", + "-Wno-REALCVT" # TODO note mostly related to $realtime - could suppress or fix upstream + ], + make_flags=['-k -j ' + str(multiprocessing.cpu_count())], + verilator_make_gmake=False) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_vams_basic.pl b/test_regress/t/t_vams_basic.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_vams_basic.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vams_basic.py b/test_regress/t/t_vams_basic.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_vams_basic.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vams_basic.v b/test_regress/t/t_vams_basic.v index 5b567f738..624eb2bb5 100644 --- a/test_regress/t/t_vams_basic.v +++ b/test_regress/t/t_vams_basic.v @@ -6,11 +6,7 @@ `begin_keywords "VAMS-2.3" -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t (/*AUTOARG*/); task check (integer line, real got, real expec); real delta; diff --git a/test_regress/t/t_vams_kwd_bad.out b/test_regress/t/t_vams_kwd_bad.out index 9e3a97617..0d6fac32e 100644 --- a/test_regress/t/t_vams_kwd_bad.out +++ b/test_regress/t/t_vams_kwd_bad.out @@ -2,7 +2,7 @@ 12 | int above; | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_vams_kwd_bad.v:12:13: syntax error, unexpected ';', expecting IDENTIFIER or '(' or randomize +%Error: t/t_vams_kwd_bad.v:12:13: syntax error, unexpected ';', expecting IDENTIFIER or randomize 12 | int above; | ^ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:13:8: Unsupported: AMS reserved word not implemented: 'abs' diff --git a/test_regress/t/t_vams_kwd_bad.pl b/test_regress/t/t_vams_kwd_bad.pl deleted file mode 100755 index 623dba016..000000000 --- a/test_regress/t/t_vams_kwd_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ["--error-limit 1000"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vams_kwd_bad.py b/test_regress/t/t_vams_kwd_bad.py new file mode 100755 index 000000000..45a114b8a --- /dev/null +++ b/test_regress/t/t_vams_kwd_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, + verilator_flags2=["--error-limit 1000"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vams_wreal.pl b/test_regress/t/t_vams_wreal.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_vams_wreal.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vams_wreal.py b/test_regress/t/t_vams_wreal.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_vams_wreal.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_assign_landr.pl b/test_regress/t/t_var_assign_landr.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_var_assign_landr.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_assign_landr.py b/test_regress/t/t_var_assign_landr.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_assign_landr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_assign_landr_noexpand.pl b/test_regress/t/t_var_assign_landr_noexpand.pl deleted file mode 100755 index e616f77c3..000000000 --- a/test_regress/t/t_var_assign_landr_noexpand.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_assign_landr.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_assign_landr_noexpand.py b/test_regress/t/t_var_assign_landr_noexpand.py new file mode 100755 index 000000000..5b4129fff --- /dev/null +++ b/test_regress/t/t_var_assign_landr_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_var_assign_landr.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_bad_hide.pl b/test_regress/t/t_var_bad_hide.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_var_bad_hide.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_bad_hide.py b/test_regress/t/t_var_bad_hide.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_var_bad_hide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_bad_hide2.pl b/test_regress/t/t_var_bad_hide2.pl deleted file mode 100755 index fc5822886..000000000 --- a/test_regress/t/t_var_bad_hide2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_bad_hide2.py b/test_regress/t/t_var_bad_hide2.py new file mode 100755 index 000000000..d546b464e --- /dev/null +++ b/test_regress/t/t_var_bad_hide2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_bad_hide_docs.pl b/test_regress/t/t_var_bad_hide_docs.pl deleted file mode 100755 index c683326f1..000000000 --- a/test_regress/t/t_var_bad_hide_docs.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_VARHIDDEN_faulty.rst", - regexp => qr/(module t|integer|endmodule)/); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_VARHIDDEN_msg.rst", - lineno_adjust => -6, - regexp => qr/(var_bad_hide)/); -} - -ok(1); -1; diff --git a/test_regress/t/t_var_bad_hide_docs.py b/test_regress/t/t_var_bad_hide_docs.py new file mode 100755 index 000000000..fea969814 --- /dev/null +++ b/test_regress/t/t_var_bad_hide_docs.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_VARHIDDEN_faulty.rst", + regexp=r'(module t|integer|endmodule)') + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_VARHIDDEN_msg.rst", + lineno_adjust=-6, + regexp=r'(var_bad_hide)') + +test.passes() diff --git a/test_regress/t/t_var_bad_sameas.pl b/test_regress/t/t_var_bad_sameas.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_bad_sameas.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_bad_sameas.py b/test_regress/t/t_var_bad_sameas.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_bad_sameas.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_bad_sv.pl b/test_regress/t/t_var_bad_sv.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_var_bad_sv.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_bad_sv.py b/test_regress/t/t_var_bad_sv.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_var_bad_sv.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_const.pl b/test_regress/t/t_var_const.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_var_const.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_const.py b/test_regress/t/t_var_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_const_bad.pl b/test_regress/t/t_var_const_bad.pl deleted file mode 100755 index 5e419b352..000000000 --- a/test_regress/t/t_var_const_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_const_bad.py b/test_regress/t/t_var_const_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_const_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_dotted1_inl0.pl b/test_regress/t/t_var_dotted1_inl0.pl deleted file mode 100755 index d56ca9496..000000000 --- a/test_regress/t/t_var_dotted1_inl0.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_var_dotted1.v"); - -compile( - v_flags2 => ['+define+NOUSE_INLINE',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted1_inl0.py b/test_regress/t/t_var_dotted1_inl0.py new file mode 100755 index 000000000..4fc10fede --- /dev/null +++ b/test_regress/t/t_var_dotted1_inl0.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_var_dotted1.v" + +test.compile(v_flags2=['+define+NOUSE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_dotted1_inl1.pl b/test_regress/t/t_var_dotted1_inl1.pl deleted file mode 100755 index f5992fa03..000000000 --- a/test_regress/t/t_var_dotted1_inl1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_var_dotted1.v"); - -compile( - v_flags2 => ['+define+USE_INLINE',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted1_inl1.py b/test_regress/t/t_var_dotted1_inl1.py new file mode 100755 index 000000000..e2a6573e0 --- /dev/null +++ b/test_regress/t/t_var_dotted1_inl1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_var_dotted1.v" + +test.compile(v_flags2=['+define+USE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_dotted1_inl2.pl b/test_regress/t/t_var_dotted1_inl2.pl deleted file mode 100755 index 7fad5e056..000000000 --- a/test_regress/t/t_var_dotted1_inl2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_var_dotted1.v"); - -compile( - v_flags2 => ['+define+USE_INLINE_MID',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted1_inl2.py b/test_regress/t/t_var_dotted1_inl2.py new file mode 100755 index 000000000..9af70f709 --- /dev/null +++ b/test_regress/t/t_var_dotted1_inl2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_var_dotted1.v" + +test.compile(v_flags2=['+define+USE_INLINE_MID']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_dotted2_inl0.pl b/test_regress/t/t_var_dotted2_inl0.pl deleted file mode 100755 index dce5f07b8..000000000 --- a/test_regress/t/t_var_dotted2_inl0.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_var_dotted2.v"); - -compile( - v_flags2 => ['+define+NOUSE_INLINE',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted2_inl0.py b/test_regress/t/t_var_dotted2_inl0.py new file mode 100755 index 000000000..d1929af8d --- /dev/null +++ b/test_regress/t/t_var_dotted2_inl0.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_var_dotted2.v" + +test.compile(v_flags2=['+define+NOUSE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_dotted2_inl1.pl b/test_regress/t/t_var_dotted2_inl1.pl deleted file mode 100755 index b4f57957e..000000000 --- a/test_regress/t/t_var_dotted2_inl1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_var_dotted2.v"); - -compile( - v_flags2 => ['+define+USE_INLINE',], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted2_inl1.py b/test_regress/t/t_var_dotted2_inl1.py new file mode 100755 index 000000000..1638e3047 --- /dev/null +++ b/test_regress/t/t_var_dotted2_inl1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_var_dotted2.v" + +test.compile(v_flags2=['+define+USE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_dotted_dup_bad.pl b/test_regress/t/t_var_dotted_dup_bad.pl deleted file mode 100755 index f25e38708..000000000 --- a/test_regress/t/t_var_dotted_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted_dup_bad.py b/test_regress/t/t_var_dotted_dup_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_var_dotted_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_dup2.pl b/test_regress/t/t_var_dup2.pl deleted file mode 100755 index 09b2ce4eb..000000000 --- a/test_regress/t/t_var_dup2.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dup2.py b/test_regress/t/t_var_dup2.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_var_dup2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_var_dup2_bad.pl b/test_regress/t/t_var_dup2_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_dup2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dup2_bad.py b/test_regress/t/t_var_dup2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_dup2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_dup3.pl b/test_regress/t/t_var_dup3.pl deleted file mode 100755 index 09b2ce4eb..000000000 --- a/test_regress/t/t_var_dup3.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dup3.py b/test_regress/t/t_var_dup3.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_var_dup3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_var_dup_bad.pl b/test_regress/t/t_var_dup_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_var_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dup_bad.py b/test_regress/t/t_var_dup_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_var_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_escape.pl b/test_regress/t/t_var_escape.pl deleted file mode 100755 index cb56ec58b..000000000 --- a/test_regress/t/t_var_escape.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Access is so we can dump waves - v_flags2 => [$Self->{vlt_all} ? '-trace' : ' +access+rwc'], - ); - -execute( - check_finished => 1, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); - my $sig = quotemeta("bra[ket]slash/dash-colon:9"); - file_grep("$Self->{obj_dir}/simx.vcd", qr/ $sig/); - file_grep("$Self->{obj_dir}/simx.vcd", qr/ other\.cyc /); - file_grep("$Self->{obj_dir}/simx.vcd", qr/ module mod\.with_dot /); - vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_var_escape.py b/test_regress/t/t_var_escape.py new file mode 100755 index 000000000..c4d5794db --- /dev/null +++ b/test_regress/t/t_var_escape.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # Access is so we can dump waves + v_flags2=['-trace' if test.vlt_all else ' +access+rwc']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + sigre = re.escape("bra[ket]slash/dash-colon:9") + test.file_grep(test.trace_filename, sigre) + test.file_grep(test.trace_filename, r' other\.cyc ') + test.file_grep(test.trace_filename, r' module mod\.with_dot ') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_extern_method_lifetime.pl b/test_regress/t/t_var_extern_method_lifetime.pl deleted file mode 100755 index 929ae897c..000000000 --- a/test_regress/t/t_var_extern_method_lifetime.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_extern_method_lifetime.py b/test_regress/t/t_var_extern_method_lifetime.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_var_extern_method_lifetime.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_in_assign.pl b/test_regress/t/t_var_in_assign.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_var_in_assign.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_in_assign.py b/test_regress/t/t_var_in_assign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_in_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_in_assign_bad.pl b/test_regress/t/t_var_in_assign_bad.pl deleted file mode 100755 index 4fa14760f..000000000 --- a/test_regress/t/t_var_in_assign_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --Mdir obj_lint_only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -(!-d "obj_lint_only") or error("%Error: lint-only shouldn't make output directory"); - -ok(1); -1; diff --git a/test_regress/t/t_var_in_assign_bad.py b/test_regress/t/t_var_in_assign_bad.py new file mode 100755 index 000000000..b7ddcf7bd --- /dev/null +++ b/test_regress/t/t_var_in_assign_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --Mdir obj_lint_only"], + fails=True, + expect_filename=test.golden_filename) + +if os.path.exists("obj_lint_only"): + test.error("%Error: lint-only shouldn't make output directory") + +test.passes() diff --git a/test_regress/t/t_var_in_assign_pedantic.pl b/test_regress/t/t_var_in_assign_pedantic.pl deleted file mode 100755 index 205a9bca8..000000000 --- a/test_regress/t/t_var_in_assign_pedantic.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_in_assign_bad.v"); - -lint( - verilator_flags2 => ['-Wpedantic -Wno-fatal'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_in_assign_pedantic.py b/test_regress/t/t_var_in_assign_pedantic.py new file mode 100755 index 000000000..7b97942aa --- /dev/null +++ b/test_regress/t/t_var_in_assign_pedantic.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_var_in_assign_bad.v" + +test.lint(verilator_flags2=['-Wpedantic -Wno-fatal']) + +test.passes() diff --git a/test_regress/t/t_var_in_fork.pl b/test_regress/t/t_var_in_fork.pl deleted file mode 100755 index fec4c2942..000000000 --- a/test_regress/t/t_var_in_fork.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_in_fork.py b/test_regress/t/t_var_in_fork.py new file mode 100755 index 000000000..7bd93561b --- /dev/null +++ b/test_regress/t/t_var_in_fork.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_init.pl b/test_regress/t/t_var_init.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_var_init.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_init.py b/test_regress/t/t_var_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_life.pl b/test_regress/t/t_var_life.pl deleted file mode 100755 index 1c174883c..000000000 --- a/test_regress/t/t_var_life.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Lifetime assign deletions\s+(\d+)/i, 4); - file_grep($Self->{stats}, qr/Optimizations, Lifetime constant prop\s+(\d+)/i, 2); -} - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_life.py b/test_regress/t/t_var_life.py new file mode 100755 index 000000000..09d396a1b --- /dev/null +++ b/test_regress/t/t_var_life.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Lifetime assign deletions\s+(\d+)', 4) + test.file_grep(test.stats, r'Optimizations, Lifetime constant prop\s+(\d+)', 2) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_local.pl b/test_regress/t/t_var_local.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_var_local.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_local.py b/test_regress/t/t_var_local.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_nonamebegin.pl b/test_regress/t/t_var_nonamebegin.pl deleted file mode 100755 index 9082e34d3..000000000 --- a/test_regress/t/t_var_nonamebegin.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-trace'], - ); - -execute( - expect_filename => "t/$Self->{name}__log.out" - ); - -if ($Self->{vlt_all}) { - vcd_identical("$Self->{obj_dir}/simx.vcd", - $Self->{golden_filename}); -} -ok(1); -1; diff --git a/test_regress/t/t_var_nonamebegin.py b/test_regress/t/t_var_nonamebegin.py new file mode 100755 index 000000000..a6754718f --- /dev/null +++ b/test_regress/t/t_var_nonamebegin.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-trace']) + +test.execute(expect_filename="t/" + test.name + "__log.out") + +if test.vlt_all: + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_notfound_bad.pl b/test_regress/t/t_var_notfound_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_notfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_notfound_bad.py b/test_regress/t/t_var_notfound_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_notfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_outoforder.pl b/test_regress/t/t_var_outoforder.pl deleted file mode 100755 index a17622844..000000000 --- a/test_regress/t/t_var_outoforder.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_outoforder.py b/test_regress/t/t_var_outoforder.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_outoforder.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_overcmp.pl b/test_regress/t/t_var_overcmp.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_var_overcmp.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_overcmp.py b/test_regress/t/t_var_overcmp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_overcmp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_overwidth_bad.pl b/test_regress/t/t_var_overwidth_bad.pl deleted file mode 100755 index cecc640a5..000000000 --- a/test_regress/t/t_var_overwidth_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_var_overwidth_bad.cpp"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_overwidth_bad.py b/test_regress/t/t_var_overwidth_bad.py new file mode 100755 index 000000000..8f9635a27 --- /dev/null +++ b/test_regress/t/t_var_overwidth_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_overzero.pl b/test_regress/t/t_var_overzero.pl deleted file mode 100755 index 657dda6f3..000000000 --- a/test_regress/t/t_var_overzero.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--x-initial fast"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_overzero.py b/test_regress/t/t_var_overzero.py new file mode 100755 index 000000000..a2adc5082 --- /dev/null +++ b/test_regress/t/t_var_overzero.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-initial fast"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_cc.pl b/test_regress/t/t_var_pins_cc.pl deleted file mode 100755 index e8330324e..000000000 --- a/test_regress/t/t_var_pins_cc.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ['-cc'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN8 \(&i1,0,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN8 \(&i8,7,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN16 \(&i16,15,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN \(&i32,31,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN64 \(&i64,63,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_INW \(&i65,64,0,3\);/x); - - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT8 \(&o1,0,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT8 \(&o8,7,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT16\(&o16,15,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT \(&o32,31,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT64\(&o64,63,0\);/x); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUTW \(&o65,64,0,3\);/x); -} - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_cc.py b/test_regress/t/t_var_pins_cc.py new file mode 100755 index 000000000..1912bf071 --- /dev/null +++ b/test_regress/t/t_var_pins_cc.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=['-cc'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'VL_IN8\(&i1,0,0\);') +hgrep(r'VL_IN8\(&i8,7,0\);') +hgrep(r'VL_IN16\(&i16,15,0\);') +hgrep(r'VL_IN\(&i32,31,0\);') +hgrep(r'VL_IN64\(&i64,63,0\);') +hgrep(r'VL_INW\(&i65,64,0,3\);') + +hgrep(r'VL_OUT8\(&o1,0,0\);') +hgrep(r'VL_OUT8\(&o8,7,0\);') +hgrep(r'VL_OUT16\(&o16,15,0\);') +hgrep(r'VL_OUT\(&o32,31,0\);') +hgrep(r'VL_OUT64\(&o64,63,0\);') +hgrep(r'VL_OUTW\(&o65,64,0,3\);') + +test.passes() diff --git a/test_regress/t/t_var_pins_sc1.pl b/test_regress/t/t_var_pins_sc1.pl deleted file mode 100755 index c7e21f8f3..000000000 --- a/test_regress/t/t_var_pins_sc1.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc -pins-bv 1 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], - make_main => 0, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1_vlt;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16_vlt;/x); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1_vlt;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16_vlt;/x); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc1.py b/test_regress/t/t_var_pins_sc1.py new file mode 100755 index 000000000..69d66746d --- /dev/null +++ b/test_regress/t/t_var_pins_sc1.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=[ + "-sc -pins-bv 1 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" +], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s>\s+&i1;') +hgrep(r'sc_core::sc_in\s>\s+&i8;') +hgrep(r'sc_core::sc_in\s>\s+&i16;') +hgrep(r'sc_core::sc_in\s>\s+&i32;') +hgrep(r'sc_core::sc_in\s>\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') + +hgrep(r'sc_core::sc_out\s>\s+&o1;') +hgrep(r'sc_core::sc_out\s>\s+&o8;') +hgrep(r'sc_core::sc_out\s>\s+&o16;') +hgrep(r'sc_core::sc_out\s>\s+&o32;') +hgrep(r'sc_core::sc_out\s>\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') +hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc2.pl b/test_regress/t/t_var_pins_sc2.pl deleted file mode 100755 index 4380d3993..000000000 --- a/test_regress/t/t_var_pins_sc2.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc -pins-bv 2 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1_vlt;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16_vlt;/x); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1_vlt;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16_vlt;/x); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc2.py b/test_regress/t/t_var_pins_sc2.py new file mode 100755 index 000000000..ef358bd83 --- /dev/null +++ b/test_regress/t/t_var_pins_sc2.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=[ + "-sc -pins-bv 2 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" +], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s>\s+&i8;') +hgrep(r'sc_core::sc_in\s>\s+&i16;') +hgrep(r'sc_core::sc_in\s>\s+&i32;') +hgrep(r'sc_core::sc_in\s>\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s>\s+&o8;') +hgrep(r'sc_core::sc_out\s>\s+&o16;') +hgrep(r'sc_core::sc_out\s>\s+&o32;') +hgrep(r'sc_core::sc_out\s>\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') +hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc32.pl b/test_regress/t/t_var_pins_sc32.pl deleted file mode 100755 index 350d5227c..000000000 --- a/test_regress/t/t_var_pins_sc32.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc -no-pins64 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1_vlt;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16_vlt;/x); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1_vlt;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16_vlt;/x); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc32.py b/test_regress/t/t_var_pins_sc32.py new file mode 100755 index 000000000..184ba2d2b --- /dev/null +++ b/test_regress/t/t_var_pins_sc32.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=[ + "-sc -no-pins64 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" +], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s+&i8;') +hgrep(r'sc_core::sc_in\s+&i16;') +hgrep(r'sc_core::sc_in\s+&i32;') +hgrep(r'sc_core::sc_in\s>\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s+&o8;') +hgrep(r'sc_core::sc_out\s+&o16;') +hgrep(r'sc_core::sc_out\s+&o32;') +hgrep(r'sc_core::sc_out\s>\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') +hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc64.pl b/test_regress/t/t_var_pins_sc64.pl deleted file mode 100755 index 500f57ae4..000000000 --- a/test_regress/t/t_var_pins_sc64.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc -pins64 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], - make_main => 0, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1_vlt;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16_vlt;/x); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1_vlt;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16_vlt;/x); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc64.py b/test_regress/t/t_var_pins_sc64.py new file mode 100755 index 000000000..4dca57a9d --- /dev/null +++ b/test_regress/t/t_var_pins_sc64.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=[ + "-sc -pins64 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" +], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s+&i8;') +hgrep(r'sc_core::sc_in\s+&i16;') +hgrep(r'sc_core::sc_in\s+&i32;') +hgrep(r'sc_core::sc_in\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s+&o8;') +hgrep(r'sc_core::sc_out\s+&o16;') +hgrep(r'sc_core::sc_out\s+&o32;') +hgrep(r'sc_core::sc_out\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') +hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc_biguint.pl b/test_regress/t/t_var_pins_sc_biguint.pl deleted file mode 100755 index ad87f7295..000000000 --- a/test_regress/t/t_var_pins_sc_biguint.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc --pins-sc-biguint --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], - make_main => 0, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i128;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i513;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16;/x); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o128;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o513;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16;/x); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc_biguint.py b/test_regress/t/t_var_pins_sc_biguint.py new file mode 100755 index 000000000..a50232864 --- /dev/null +++ b/test_regress/t/t_var_pins_sc_biguint.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=["-sc --pins-sc-biguint --trace --exe", test.pli_filename], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s+&i8;') +hgrep(r'sc_core::sc_in\s+&i16;') +hgrep(r'sc_core::sc_in\s+&i32;') +hgrep(r'sc_core::sc_in\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&i128;') +hgrep(r'sc_core::sc_in\s>\s+&i513;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s+&o8;') +hgrep(r'sc_core::sc_out\s+&o16;') +hgrep(r'sc_core::sc_out\s+&o32;') +hgrep(r'sc_core::sc_out\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&o128;') +hgrep(r'sc_core::sc_out\s>\s+&o513;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc_uint.pl b/test_regress/t/t_var_pins_sc_uint.pl deleted file mode 100755 index 70333a0b5..000000000 --- a/test_regress/t/t_var_pins_sc_uint.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc --pins-sc-uint --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i128;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i513;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16;/x); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o128;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o513;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16;/x); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc_uint.py b/test_regress/t/t_var_pins_sc_uint.py new file mode 100755 index 000000000..42602c6d0 --- /dev/null +++ b/test_regress/t/t_var_pins_sc_uint.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=["-sc --pins-sc-uint --trace --exe", test.pli_filename], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s>\s+&i8;') +hgrep(r'sc_core::sc_in\s>\s+&i16;') +hgrep(r'sc_core::sc_in\s>\s+&i32;') +hgrep(r'sc_core::sc_in\s>\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&i128;') +hgrep(r'sc_core::sc_in\s>\s+&i513;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s>\s+&o8;') +hgrep(r'sc_core::sc_out\s>\s+&o16;') +hgrep(r'sc_core::sc_out\s>\s+&o32;') +hgrep(r'sc_core::sc_out\s>\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&o128;') +hgrep(r'sc_core::sc_out\s>\s+&o513;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc_uint_biguint.pl b/test_regress/t/t_var_pins_sc_uint_biguint.pl deleted file mode 100755 index 480eca2b4..000000000 --- a/test_regress/t/t_var_pins_sc_uint_biguint.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc --pins-sc-uint --pins-sc-biguint --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i128;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i513;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16;/x); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o128;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o513;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16;/x); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc_uint_biguint.py b/test_regress/t/t_var_pins_sc_uint_biguint.py new file mode 100755 index 000000000..c480b6b87 --- /dev/null +++ b/test_regress/t/t_var_pins_sc_uint_biguint.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile( + verilator_flags2=["-sc --pins-sc-uint --pins-sc-biguint --trace --exe", test.pli_filename], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s>\s+&i8;') +hgrep(r'sc_core::sc_in\s>\s+&i16;') +hgrep(r'sc_core::sc_in\s>\s+&i32;') +hgrep(r'sc_core::sc_in\s>\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&i128;') +hgrep(r'sc_core::sc_in\s>\s+&i513;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s>\s+&o8;') +hgrep(r'sc_core::sc_out\s>\s+&o16;') +hgrep(r'sc_core::sc_out\s>\s+&o32;') +hgrep(r'sc_core::sc_out\s>\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&o128;') +hgrep(r'sc_core::sc_out\s>\s+&o513;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc_uint_bool.pl b/test_regress/t/t_var_pins_sc_uint_bool.pl deleted file mode 100755 index 05a4dd4d3..000000000 --- a/test_regress/t/t_var_pins_sc_uint_bool.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc --pins-sc-uint-bool --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i128;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i513;/x); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o128;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o513;/x); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc_uint_bool.py b/test_regress/t/t_var_pins_sc_uint_bool.py new file mode 100755 index 000000000..20acac5fe --- /dev/null +++ b/test_regress/t/t_var_pins_sc_uint_bool.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=["-sc --pins-sc-uint-bool --trace --exe", test.pli_filename], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s>\s+&i1;') +hgrep(r'sc_core::sc_in\s+&i8;') +hgrep(r'sc_core::sc_in\s+&i16;') +hgrep(r'sc_core::sc_in\s+&i32;') +hgrep(r'sc_core::sc_in\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&i128;') +hgrep(r'sc_core::sc_in\s>\s+&i513;') + +hgrep(r'sc_core::sc_out\s>\s+&o1;') +hgrep(r'sc_core::sc_out\s+&o8;') +hgrep(r'sc_core::sc_out\s+&o16;') +hgrep(r'sc_core::sc_out\s+&o32;') +hgrep(r'sc_core::sc_out\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&o128;') +hgrep(r'sc_core::sc_out\s>\s+&o513;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc_uint_bool_nomain.pl b/test_regress/t/t_var_pins_sc_uint_bool_nomain.pl deleted file mode 100755 index 6b27f802f..000000000 --- a/test_regress/t/t_var_pins_sc_uint_bool_nomain.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# This test runs the very first time we've executed Verilator --sc -# after building so we make sure to run with --gdbbt, so if it dumps we'll -# get a trace. - -scenarios(simulator => 1); - -top_filename("t/t_a1_first_cc.v"); - -$DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree"; - -compile( - verilator_flags2 => [$DEBUG_QUIET, "-sc --trace --pins-sc-uint-bool"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc_uint_bool_nomain.py b/test_regress/t/t_var_pins_sc_uint_bool_nomain.py new file mode 100755 index 000000000..a6e5a22f5 --- /dev/null +++ b/test_regress/t/t_var_pins_sc_uint_bool_nomain.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# This test runs the very first time we've executed Verilator --sc +# after building so we make sure to run with --gdbbt, so if it dumps we'll +# get a trace. + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_a1_first_cc.v" + +DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree" + +test.compile(verilator_flags2=[DEBUG_QUIET, "-sc --trace --pins-sc-uint-bool"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_scui.pl b/test_regress/t/t_var_pins_scui.pl deleted file mode 100755 index 124313eea..000000000 --- a/test_regress/t/t_var_pins_scui.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc -pins-uint8 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], - make_main => 0, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in \s+ &i64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &i65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s> \s+ &ibv16;/x); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o8;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o16;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out \s+ &o64;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &o65;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv1;/x); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s> \s+ &obv16;/x); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_scui.py b/test_regress/t/t_var_pins_scui.py new file mode 100755 index 000000000..0f9beb9a2 --- /dev/null +++ b/test_regress/t/t_var_pins_scui.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=["-sc -pins-uint8 --trace --exe", test.pli_filename], + make_main=False) + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i1;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i8;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i16;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i32;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i64;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_in\s>\s+&i65;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_in\s>\s+&ibv1;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_in\s>\s+&ibv16;') + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o1;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o8;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o16;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o32;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o64;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_out\s>\s+&o65;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_out\s>\s+&obv1;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_out\s>\s+&obv16;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_port2_bad.pl b/test_regress/t/t_var_port2_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_port2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_port2_bad.py b/test_regress/t/t_var_port2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_port2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_port_bad.pl b/test_regress/t/t_var_port_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_port_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_port_bad.py b/test_regress/t/t_var_port_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_port_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_port_json_only.pl b/test_regress/t/t_var_port_json_only.pl deleted file mode 100755 index 0230deada..000000000 --- a/test_regress/t/t_var_port_json_only.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical($out_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_var_port_json_only.py b/test_regress/t/t_var_port_json_only.py new file mode 100755 index 000000000..5fa0ddc00 --- /dev/null +++ b/test_regress/t/t_var_port_json_only.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_port_xml.pl b/test_regress/t/t_var_port_xml.pl deleted file mode 100755 index fe03f41d4..000000000 --- a/test_regress/t/t_var_port_xml.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical($out_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_var_port_xml.py b/test_regress/t/t_var_port_xml.py new file mode 100755 index 000000000..e24dca19d --- /dev/null +++ b/test_regress/t/t_var_port_xml.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_ref.pl b/test_regress/t/t_var_ref.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_var_ref.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref.py b/test_regress/t/t_var_ref.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_ref.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_ref_bad1.pl b/test_regress/t/t_var_ref_bad1.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_var_ref_bad1.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref_bad1.py b/test_regress/t/t_var_ref_bad1.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_var_ref_bad1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_ref_bad2.pl b/test_regress/t/t_var_ref_bad2.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_ref_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref_bad2.py b/test_regress/t/t_var_ref_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_ref_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_ref_bad3.pl b/test_regress/t/t_var_ref_bad3.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_var_ref_bad3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref_bad3.py b/test_regress/t/t_var_ref_bad3.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_var_ref_bad3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_ref_noinline.pl b/test_regress/t/t_var_ref_noinline.pl deleted file mode 100755 index 9ba333659..000000000 --- a/test_regress/t/t_var_ref_noinline.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_var_ref.v"); - -scenarios(simulator => 1); - -compile( - v_flags2 => ['+define+T_NOINLINE'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref_noinline.py b/test_regress/t/t_var_ref_noinline.py new file mode 100755 index 000000000..f5064fa95 --- /dev/null +++ b/test_regress/t/t_var_ref_noinline.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +test.top_filename = "t/t_var_ref.v" + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['+define+T_NOINLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_ref_static.pl b/test_regress/t/t_var_ref_static.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_var_ref_static.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref_static.py b/test_regress/t/t_var_ref_static.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_var_ref_static.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_rsvd.pl b/test_regress/t/t_var_rsvd.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_var_rsvd.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_rsvd.py b/test_regress/t/t_var_rsvd.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_rsvd.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_rsvd_bad.pl b/test_regress/t/t_var_rsvd_bad.pl deleted file mode 100755 index a034e8fa8..000000000 --- a/test_regress/t/t_var_rsvd_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_var_rsvd_port.v"); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_rsvd_bad.py b/test_regress/t/t_var_rsvd_bad.py new file mode 100755 index 000000000..113352b72 --- /dev/null +++ b/test_regress/t/t_var_rsvd_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_var_rsvd_port.v" + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_rsvd_port.pl b/test_regress/t/t_var_rsvd_port.pl deleted file mode 100755 index 76a08e9aa..000000000 --- a/test_regress/t/t_var_rsvd_port.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-SYMRSVDWORD"], - ); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_rsvd_port.py b/test_regress/t/t_var_rsvd_port.py new file mode 100755 index 000000000..13c220107 --- /dev/null +++ b/test_regress/t/t_var_rsvd_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-SYMRSVDWORD"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_sc_bv.pl b/test_regress/t/t_var_sc_bv.pl deleted file mode 100755 index 32ebabeb3..000000000 --- a/test_regress/t/t_var_sc_bv.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_var_sc_bv.cpp --sc -fno-inline"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_sc_bv.py b/test_regress/t/t_var_sc_bv.py new file mode 100755 index 000000000..fb4049cf1 --- /dev/null +++ b/test_regress/t/t_var_sc_bv.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "--sc -fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_set_link.pl b/test_regress/t/t_var_set_link.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_var_set_link.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_set_link.py b/test_regress/t/t_var_set_link.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_set_link.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_static.pl b/test_regress/t/t_var_static.pl deleted file mode 100755 index efb3d2dfc..000000000 --- a/test_regress/t/t_var_static.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wno-IMPLICITSTATIC'], - ); - -execute( - check_finished => 1, - all_run_flags => ['+plusarg=value'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_static.py b/test_regress/t/t_var_static.py new file mode 100755 index 000000000..df3c5c280 --- /dev/null +++ b/test_regress/t/t_var_static.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wno-IMPLICITSTATIC']) + +test.execute(all_run_flags=['+plusarg=value']) + +test.passes() diff --git a/test_regress/t/t_var_static_assign_decl_bad.pl b/test_regress/t/t_var_static_assign_decl_bad.pl deleted file mode 100755 index dbc037440..000000000 --- a/test_regress/t/t_var_static_assign_decl_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_static_assign_decl_bad.py b/test_regress/t/t_var_static_assign_decl_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_var_static_assign_decl_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_static_assign_decl_bad.v b/test_regress/t/t_var_static_assign_decl_bad.v index 2c4217372..db25de778 100644 --- a/test_regress/t/t_var_static_assign_decl_bad.v +++ b/test_regress/t/t_var_static_assign_decl_bad.v @@ -139,7 +139,7 @@ module t(input clk); endfunction iface iface(); - prog prog; + prog prog(); logic in; no_warn no_warn(.in(in), .clk(clk)); diff --git a/test_regress/t/t_var_static_param.pl b/test_regress/t/t_var_static_param.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_var_static_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_static_param.py b/test_regress/t/t_var_static_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_static_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_suggest_bad.pl b/test_regress/t/t_var_suggest_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_var_suggest_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_suggest_bad.py b/test_regress/t/t_var_suggest_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_var_suggest_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_tieout.pl b/test_regress/t/t_var_tieout.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_var_tieout.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_tieout.py b/test_regress/t/t_var_tieout.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_tieout.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_top_struct.pl b/test_regress/t/t_var_top_struct.pl deleted file mode 100755 index 157d7a50b..000000000 --- a/test_regress/t/t_var_top_struct.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_top_struct.py b/test_regress/t/t_var_top_struct.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_var_top_struct.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_var_types.pl b/test_regress/t/t_var_types.pl deleted file mode 100755 index 191ac69aa..000000000 --- a/test_regress/t/t_var_types.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{verilated_randReset} = 1; # allow checking if we initialize vars to zero only when needed - -compile( - verilator_flags2 => ["--x-assign 1"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_types.py b/test_regress/t/t_var_types.py new file mode 100755 index 000000000..9964558dd --- /dev/null +++ b/test_regress/t/t_var_types.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.verilated_randReset = 1 # allow checking if we initialize vars to zero only when needed + +test.compile(verilator_flags2=["--x-assign 1"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_types_bad.pl b/test_regress/t/t_var_types_bad.pl deleted file mode 100755 index d2715e7c7..000000000 --- a/test_regress/t/t_var_types_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -$Self->{verilated_randReset} = 1; # allow checking if we initialize vars to zero only when needed - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_types_bad.py b/test_regress/t/t_var_types_bad.py new file mode 100755 index 000000000..8e9543a6c --- /dev/null +++ b/test_regress/t/t_var_types_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.verilated_randReset = 1 # allow checking if we initialize vars to zero only when needed + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_vec_sel.pl b/test_regress/t/t_var_vec_sel.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_var_vec_sel.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_var_vec_sel.py b/test_regress/t/t_var_vec_sel.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_var_vec_sel.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_var_xref_bad.pl b/test_regress/t/t_var_xref_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_var_xref_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_xref_bad.py b/test_regress/t/t_var_xref_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_var_xref_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_xref_gen.pl b/test_regress/t/t_var_xref_gen.pl deleted file mode 100755 index d862fcf2e..000000000 --- a/test_regress/t/t_var_xref_gen.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--debug-check"], - ); - -ok(1); - -1; diff --git a/test_regress/t/t_var_xref_gen.py b/test_regress/t/t_var_xref_gen.py new file mode 100755 index 000000000..75684187a --- /dev/null +++ b/test_regress/t/t_var_xref_gen.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--debug-check"]) + +test.passes() diff --git a/test_regress/t/t_verilated_all.pl b/test_regress/t/t_verilated_all.pl deleted file mode 100755 index 990e34c5d..000000000 --- a/test_regress/t/t_verilated_all.pl +++ /dev/null @@ -1,66 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -my $root = ".."; - -compile( - # Can't use --coverage and --savable together, so cheat and compile inline - verilator_flags2 => ["--cc", - "--coverage-toggle --coverage-line --coverage-user", - "--trace --vpi ", - "--trace-threads 1", - $Self->have_coroutines ? "--timing" : "--no-timing -Wno-STMTDLY", - "--prof-exec", "--prof-pgo", - "$root/include/verilated_save.cpp"], - threads => 2 - ); - -execute( - all_run_flags => [" +verilator+prof+exec+file+/dev/null", - " +verilator+prof+vlt+file+/dev/null", - ], - check_finished => 1, - ); - -my %hit; -foreach my $file (glob("$root/include/*.cpp $root/include/*.h")) { - $file =~ s!.*/!!; - - # This file isn't actually used by the runtime (though - # it might be in the future? hence it's under include/) - # It is used to build verilator. - if ($file =~ /verilated_unordered_set_map\.h/) { next; } - - print "NEED: $file\n" if $Self->{verbose}; - $hit{$file} = 0; -} -foreach my $dfile (glob("$Self->{obj_dir}/*.d")) { - my $wholefile = file_contents($dfile); - foreach my $file (split /\s+/, $wholefile) { - $file =~ s!.*/!!; - print "USED: $file\n" if $Self->{verbose}; - $hit{$file} = 1; - } -} - -foreach my $file (sort keys %hit) { - if (!$hit{$file} - && $file !~ /_sc/ - && $file !~ /_fst/ - && ($file !~ /_timing/ || $Self->have_coroutines) - && ($file !~ /_thread/)) { - error("Include file not covered by t_verilated_all test: ", $file); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_verilated_all.py b/test_regress/t/t_verilated_all.py new file mode 100755 index 000000000..14301bd7b --- /dev/null +++ b/test_regress/t/t_verilated_all.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.compile( + # Can't use --coverage and --savable together, so cheat and compile inline + verilator_flags2=[ + "--cc", "--coverage-toggle --coverage-line --coverage-user", + "--trace --vpi ", "--trace-threads 1", + ("--timing" if test.have_coroutines else "--no-timing -Wno-STMTDLY"), "--prof-exec", + "--prof-pgo", root + "/include/verilated_save.cpp" + ], + threads=2) + +test.execute( + all_run_flags=[" +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+/dev/null"]) + +hit = {} +for filename in (test.glob_some(root + "/include/*.cpp") + test.glob_some(root + "/include/*.h")): + filename = os.path.basename(filename) + if test.verbose: + print("NEED: " + filename) + hit[filename] = False + +for dfile in test.glob_some(test.obj_dir + "/*.d"): + wholefile = test.file_contents(dfile) + for filename in wholefile.split(): + filename = os.path.basename(filename) + if test.verbose: + print("USED: " + filename) + hit[filename] = True + +for filename in sorted(hit.keys()): + if (not hit[filename] and not re.search(r'_sc', filename) and not re.search(r'_fst', filename) + and not re.search(r'_thread', filename) + and (not re.search(r'_timing', filename) or test.have_coroutines)): + test.error("Include file not covered by t_verilated_all test: ", filename) + +test.passes() diff --git a/test_regress/t/t_verilated_all_newest.pl b/test_regress/t/t_verilated_all_newest.pl deleted file mode 100755 index 7ea15b92d..000000000 --- a/test_regress/t/t_verilated_all_newest.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_verilated_all.v"); - -my $root = ".."; - -compile( - # Can't use --coverage and --savable together, so cheat and compile inline - verilator_flags2 => ["--cc --coverage-toggle --coverage-line --coverage-user --trace --prof-exec --prof-pgo --vpi $root/include/verilated_save.cpp", - $Self->have_coroutines ? "--timing" : "--no-timing -Wno-STMTDLY"], - make_flags => 'DRIVER_STD=newest', - ); - -execute( - all_run_flags => [" +verilator+prof+exec+file+/dev/null", - " +verilator+prof+vlt+file+/dev/null", - ], - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_verilated_all_newest.py b/test_regress/t/t_verilated_all_newest.py new file mode 100755 index 000000000..3a22434c1 --- /dev/null +++ b/test_regress/t/t_verilated_all_newest.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_verilated_all.v" + +root = ".." + +test.compile( + # Can't use --coverage and --savable together, so cheat and compile inline + verilator_flags2=[ + "--cc --coverage-toggle --coverage-line --coverage-user --trace --prof-exec --prof-pgo --vpi " + + root + "/include/verilated_save.cpp", + ("--timing" if test.have_coroutines else "--no-timing -Wno-STMTDLY") + ], + make_flags=['DRIVER_STD=newest']) + +test.execute( + all_run_flags=[" +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+/dev/null"]) + +test.passes() diff --git a/test_regress/t/t_verilated_all_oldest.pl b/test_regress/t/t_verilated_all_oldest.pl deleted file mode 100755 index 103e2e197..000000000 --- a/test_regress/t/t_verilated_all_oldest.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -# This test now does nothing, because using DRIVER_STD=oldest tends to blow up glibc. -# Support for DRIVER_STD=oldest was removed from makefiles. This file remains for commentary. - -ok(1); -1; diff --git a/test_regress/t/t_verilated_all_oldest.py b/test_regress/t/t_verilated_all_oldest.py new file mode 100755 index 000000000..c07c374b9 --- /dev/null +++ b/test_regress/t/t_verilated_all_oldest.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +# This test now does nothing, because using DRIVER_STD=oldest tends to blow up glibc. +# Support for DRIVER_STD=oldest was removed from makefiles. This file remains for commentary. + +test.passes() diff --git a/test_regress/t/t_verilated_debug.pl b/test_regress/t/t_verilated_debug.pl deleted file mode 100755 index 04964e29f..000000000 --- a/test_regress/t/t_verilated_debug.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -$Self->{verilated_debug} = 1; - -compile( - verilator_flags2 => [], - ); - -execute( - check_finished => 1, - ); - -if (!$Self->{vltmt}) { # vltmt output may vary between thread exec order - files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile"); -} - -ok(1); -1; diff --git a/test_regress/t/t_verilated_debug.py b/test_regress/t/t_verilated_debug.py new file mode 100755 index 000000000..221a3478d --- /dev/null +++ b/test_regress/t/t_verilated_debug.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.verilated_debug = True + +test.compile(verilator_flags2=[]) + +test.execute() + +if not test.vltmt: # vltmt output may vary between thread exec order + test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") + +test.passes() diff --git a/test_regress/t/t_verilated_header.pl b/test_regress/t/t_verilated_header.pl deleted file mode 100755 index bf07f8abd..000000000 --- a/test_regress/t/t_verilated_header.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -compile( - verilator_flags2 => ["+incdir+$ENV{VERILATOR_ROOT}/include"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_verilated_header.py b/test_regress/t/t_verilated_header.py new file mode 100755 index 000000000..64fff6852 --- /dev/null +++ b/test_regress/t/t_verilated_header.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile(verilator_flags2=["+incdir+" + os.environ["VERILATOR_ROOT"] + "/include"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_verilated_threaded.pl b/test_regress/t/t_verilated_threaded.pl deleted file mode 100755 index a012b4529..000000000 --- a/test_regress/t/t_verilated_threaded.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_verilated_all.v"); - -my $root = ".."; - -compile( - # Can't use --coverage and --savable together, so cheat and compile inline - verilator_flags2 => ["--cc --coverage-toggle --coverage-line --coverage-user --trace --vpi $root/include/verilated_save.cpp", - $Self->have_coroutines ? "--timing" : "--no-timing -Wno-STMTDLY"], - threads => 1 - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_verilated_threaded.py b/test_regress/t/t_verilated_threaded.py new file mode 100755 index 000000000..af80be73f --- /dev/null +++ b/test_regress/t/t_verilated_threaded.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_verilated_all.v" + +root = ".." + +test.compile( + # Can't use --coverage and --savable together, so cheat and compile inline + verilator_flags2=[ + "--cc --coverage-toggle --coverage-line --coverage-user --trace --vpi " + root + + "/include/verilated_save.cpp", + ("--timing" if test.have_coroutines else "--no-timing -Wno-STMTDLY") + ], + threads=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_virtual_interface_method.pl b/test_regress/t/t_virtual_interface_method.pl deleted file mode 100755 index 9a53332e0..000000000 --- a/test_regress/t/t_virtual_interface_method.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--binary"], - verilator_make_gmake => 0, - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_virtual_interface_method.py b/test_regress/t/t_virtual_interface_method.py new file mode 100755 index 000000000..d2e0fe791 --- /dev/null +++ b/test_regress/t/t_virtual_interface_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--binary"], verilator_make_gmake=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_virtual_interface_method_bad.pl b/test_regress/t/t_virtual_interface_method_bad.pl deleted file mode 100755 index 85114ac5d..000000000 --- a/test_regress/t/t_virtual_interface_method_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2017"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_virtual_interface_method_bad.py b/test_regress/t/t_virtual_interface_method_bad.py new file mode 100755 index 000000000..54f436672 --- /dev/null +++ b/test_regress/t/t_virtual_interface_method_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1800-2017"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vl_assign_sbw.pl b/test_regress/t/t_vl_assign_sbw.pl deleted file mode 100755 index da724aa21..000000000 --- a/test_regress/t/t_vl_assign_sbw.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --pins-sc-biguint --sc $Self->{t_dir}/t_vl_assign_sbw.cpp"], -); - -execute( - check_finished => 1 -); - -ok(1); -1; diff --git a/test_regress/t/t_vl_assign_sbw.py b/test_regress/t/t_vl_assign_sbw.py new file mode 100755 index 000000000..1a06f784b --- /dev/null +++ b/test_regress/t/t_vl_assign_sbw.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --pins-sc-biguint --sc", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vlcov_debugi.pl b/test_regress/t/t_vlcov_debugi.pl deleted file mode 100755 index 5e6046a73..000000000 --- a/test_regress/t/t_vlcov_debugi.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -foreach my $basename ("t_vlcov_data_a.dat", - "t_vlcov_data_b.dat", - "t_vlcov_data_c.dat", - "t_vlcov_data_d.dat", - ) { - run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "t/${basename}", - "--debug", - "--debugi 9", - ], - tee => $Self->{verbose}, - verilator_run => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_debugi.py b/test_regress/t/t_vlcov_debugi.py new file mode 100755 index 000000000..b3d310b71 --- /dev/null +++ b/test_regress/t/t_vlcov_debugi.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +for basename in [ + "t_vlcov_data_a.dat", "t_vlcov_data_b.dat", "t_vlcov_data_c.dat", "t_vlcov_data_d.dat" +]: + test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "t/" + basename, "--debug", + "--debugi 9" + ], + tee=test.verbose, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_vlcov_flag_invalid_bad.pl b/test_regress/t/t_vlcov_flag_invalid_bad.pl deleted file mode 100755 index 18ad2d42b..000000000 --- a/test_regress/t/t_vlcov_flag_invalid_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", '--invalid-dash'], - logfile => $Self->{run_log_filename}, - fails => 1, - expect_filename => $Self->{golden_filename}, - verilator_run => 1, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_vlcov_flag_invalid_bad.py b/test_regress/t/t_vlcov_flag_invalid_bad.py new file mode 100755 index 000000000..8e3fec647 --- /dev/null +++ b/test_regress/t/t_vlcov_flag_invalid_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", '--invalid-dash'], + logfile=test.run_log_filename, + fails=True, + expect_filename=test.golden_filename, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_vlcov_info.info.out b/test_regress/t/t_vlcov_info.info.out new file mode 100644 index 000000000..9e041cf5f --- /dev/null +++ b/test_regress/t/t_vlcov_info.info.out @@ -0,0 +1,13 @@ +TN:verilator_coverage +SF:file1.sp +DA:159,22 +BRDA:159,0,0,0 +BRDA:159,0,1,1 +BRDA:159,0,2,20 +BRDA:159,0,3,0 +BRDA:159,0,4,1 +BRDA:159,0,5,9 +BRDA:159,0,6,22 +BRF:7 +BRH:2 +end_of_record diff --git a/test_regress/t/t_vlcov_info.pl b/test_regress/t/t_vlcov_info.pl deleted file mode 100755 index 919215a12..000000000 --- a/test_regress/t/t_vlcov_info.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--write-info", "$Self->{obj_dir}/coverage.info", - "t/t_vlcov_data_a.dat", - "t/t_vlcov_data_b.dat", - "t/t_vlcov_data_c.dat", - "t/t_vlcov_data_d.dat", - ], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/coverage.info", $Self->{name} . ".info.out"); - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_info.py b/test_regress/t/t_vlcov_info.py new file mode 100755 index 000000000..19def3282 --- /dev/null +++ b/test_regress/t/t_vlcov_info.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "t/t_vlcov_data_a.dat", "t/t_vlcov_data_b.dat", + "t/t_vlcov_data_c.dat", "t/t_vlcov_data_d.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_vlcov_merge.pl b/test_regress/t/t_vlcov_merge.pl deleted file mode 100755 index 0671dde4b..000000000 --- a/test_regress/t/t_vlcov_merge.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--no-unlink", "--nounlink", - "--write", "$Self->{obj_dir}/coverage.dat", - "t/t_vlcov_data_a.dat", - "t/t_vlcov_data_b.dat", - "t/t_vlcov_data_c.dat", - "t/t_vlcov_data_d.dat", - ], - verilator_run => 1, - ); - -# Not deleted e.g. parsed --no-unlink properly -files_identical("$Self->{t_dir}/t_vlcov_data_a.dat", - "$Self->{t_dir}/t_vlcov_data_a.dat"); - -# Older clib's didn't properly sort maps, but the coverage data doesn't -# really care about ordering. So avoid false failures by sorting. -files_identical_sorted("$Self->{obj_dir}/coverage.dat", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_merge.py b/test_regress/t/t_vlcov_merge.py new file mode 100755 index 000000000..271a8d1c7 --- /dev/null +++ b/test_regress/t/t_vlcov_merge.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--no-unlink", + "--nounlink", + "--write", + test.obj_dir + "/coverage.dat", + "t/t_vlcov_data_a.dat", + "t/t_vlcov_data_b.dat", + "t/t_vlcov_data_c.dat", + "t/t_vlcov_data_d.dat", +], + verilator_run=True) + +# Not deleted e.g. parsed --no-unlink properlytest.files_identical(test.t_dir + "/t_vlcov_data_a.dat", test.t_dir + "/t_vlcov_data_a.dat") + +# Older clib's didn't properly sort maps, but the coverage data doesn't +# really care about ordering. So avoid false failures by sorting.test.files_identical_sorted(test.obj_dir + "/coverage.dat", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlcov_nfound_bad.pl b/test_regress/t/t_vlcov_nfound_bad.pl deleted file mode 100755 index 6a4a9be42..000000000 --- a/test_regress/t/t_vlcov_nfound_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(fails => 1, - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "t/t_NOT_FOUND",], - logfile => $Self->{run_log_filename}, - expect_filename => $Self->{golden_filename}, - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_nfound_bad.py b/test_regress/t/t_vlcov_nfound_bad.py new file mode 100755 index 000000000..d435f38ee --- /dev/null +++ b/test_regress/t/t_vlcov_nfound_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(fails=True, + cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "t/t_NOT_FOUND"], + logfile=test.run_log_filename, + expect_filename=test.golden_filename, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_vlcov_rank.pl b/test_regress/t/t_vlcov_rank.pl deleted file mode 100755 index 703de90d5..000000000 --- a/test_regress/t/t_vlcov_rank.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--rank", - "t/t_vlcov_data_a.dat", - "t/t_vlcov_data_b.dat", - "t/t_vlcov_data_c.dat", - "t/t_vlcov_data_d.dat", - ], - logfile => "$Self->{obj_dir}/vlcov.log", - tee => 0, - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/vlcov.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_rank.py b/test_regress/t/t_vlcov_rank.py new file mode 100755 index 000000000..6013b047c --- /dev/null +++ b/test_regress/t/t_vlcov_rank.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--rank", "t/t_vlcov_data_a.dat", + "t/t_vlcov_data_b.dat", "t/t_vlcov_data_c.dat", "t/t_vlcov_data_d.dat" +], + logfile=test.obj_dir + "/vlcov.log", + tee=False, + verilator_run=True) + +test.files_identical(test.obj_dir + "/vlcov.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlcov_rewrite.pl b/test_regress/t/t_vlcov_rewrite.pl deleted file mode 100755 index 0affb5b9c..000000000 --- a/test_regress/t/t_vlcov_rewrite.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -foreach my $basename ("t_vlcov_data_a.dat", - "t_vlcov_data_b.dat", - "t_vlcov_data_c.dat", - "t_vlcov_data_d.dat", - ) { - run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "t/${basename}", - "--write", "$Self->{obj_dir}/${basename}" - ], - tee => 0, - verilator_run => 1, - ); - files_identical("$Self->{obj_dir}/${basename}", "t/${basename}"); -} - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_rewrite.py b/test_regress/t/t_vlcov_rewrite.py new file mode 100755 index 000000000..91fdfa1d0 --- /dev/null +++ b/test_regress/t/t_vlcov_rewrite.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +for basename in [ + "t_vlcov_data_a.dat", "t_vlcov_data_b.dat", "t_vlcov_data_c.dat", "t_vlcov_data_d.dat" +]: + test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "t/" + basename, "--write", + test.obj_dir + "/" + basename + ], + tee=False, + verilator_run=True) + + test.files_identical(test.obj_dir + "/" + basename, "t/" + basename) + +test.passes() diff --git a/test_regress/t/t_vlcov_unlink.pl b/test_regress/t/t_vlcov_unlink.pl deleted file mode 100755 index e2a054967..000000000 --- a/test_regress/t/t_vlcov_unlink.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use File::Copy; - -scenarios(dist => 1); - -my $tmp = "$Self->{obj_dir}/copied.dat"; -File::Copy::copy("$Self->{t_dir}/t_vlcov_data_a.dat", $tmp); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--unlink", - $tmp, - "--write", "$Self->{obj_dir}/output.dat"], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/output.dat", "t/t_vlcov_data_a.dat"); - -# --unlink should have removed it -!-r $tmp or error("Not unlinked"); - -ok(1); - -1; diff --git a/test_regress/t/t_vlcov_unlink.py b/test_regress/t/t_vlcov_unlink.py new file mode 100755 index 000000000..90f9428f4 --- /dev/null +++ b/test_regress/t/t_vlcov_unlink.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import shutil + +test.scenarios('dist') + +tmp = test.obj_dir + "/copied.dat" +shutil.copy(test.t_dir + "/t_vlcov_data_a.dat", tmp) + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--unlink", tmp, "--write", + test.obj_dir + "/output.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/output.dat", "t/t_vlcov_data_a.dat") + +# --unlink should have removed it +if os.path.exists(tmp): + test.error("Wan't unlinked") + +test.passes() diff --git a/test_regress/t/t_vlt_match_error_1.out b/test_regress/t/t_vlt_match_error_1.out index ffd388fbb..1971bca8e 100644 --- a/test_regress/t/t_vlt_match_error_1.out +++ b/test_regress/t/t_vlt_match_error_1.out @@ -1,7 +1,3 @@ -%Error-PKGNODECL: t/t_vlt_match_error.v:17:12: Package/class 'hi' not found, and needs to be predeclared (IEEE 1800-2023 26.3) - 17 | import hi::*; - | ^~ - ... For error description see https://verilator.org/warn/PKGNODECL?v=latest %Error: t/t_vlt_match_error.v:17:12: Importing from missing package 'hi' 17 | import hi::*; | ^~ diff --git a/test_regress/t/t_vlt_match_error_1.pl b/test_regress/t/t_vlt_match_error_1.pl deleted file mode 100755 index 7de7b8d1b..000000000 --- a/test_regress/t/t_vlt_match_error_1.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder and Ethan Sifferman. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_vlt_match_error.v"); - -lint( - verilator_flags2 => ["-DT_VLT_MATCH_ERROR_1 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_match_error_1.py b/test_regress/t/t_vlt_match_error_1.py new file mode 100755 index 000000000..14c18fda5 --- /dev/null +++ b/test_regress/t/t_vlt_match_error_1.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_vlt_match_error.v" + +test.lint(verilator_flags2=[ + "-DT_VLT_MATCH_ERROR_1 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt" +], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_match_error_2.pl b/test_regress/t/t_vlt_match_error_2.pl deleted file mode 100755 index 0e046489a..000000000 --- a/test_regress/t/t_vlt_match_error_2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder and Ethan Sifferman. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_vlt_match_error.v"); - -lint( - verilator_flags2 => ["-DT_VLT_MATCH_ERROR_2 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_match_error_2.py b/test_regress/t/t_vlt_match_error_2.py new file mode 100755 index 000000000..98c8b2327 --- /dev/null +++ b/test_regress/t/t_vlt_match_error_2.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_vlt_match_error.v" + +test.lint(verilator_flags2=[ + "-DT_VLT_MATCH_ERROR_2 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt" +], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_match_error_3.pl b/test_regress/t/t_vlt_match_error_3.pl deleted file mode 100755 index 43093cc2e..000000000 --- a/test_regress/t/t_vlt_match_error_3.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder and Ethan Sifferman. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_vlt_match_error.v"); - -lint( - verilator_flags2 => ["-DT_VLT_MATCH_ERROR_3 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_match_error_3.py b/test_regress/t/t_vlt_match_error_3.py new file mode 100755 index 000000000..53a1dae32 --- /dev/null +++ b/test_regress/t/t_vlt_match_error_3.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_vlt_match_error.v" + +test.lint(verilator_flags2=[ + "-DT_VLT_MATCH_ERROR_3 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt" +], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_syntax_bad.pl b/test_regress/t/t_vlt_syntax_bad.pl deleted file mode 100755 index 5d79360fb..000000000 --- a/test_regress/t/t_vlt_syntax_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["t/t_vlt_syntax_bad.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_syntax_bad.py b/test_regress/t/t_vlt_syntax_bad.py new file mode 100755 index 000000000..90b3aecba --- /dev/null +++ b/test_regress/t/t_vlt_syntax_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["t/t_vlt_syntax_bad.vlt"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_timing.pl b/test_regress/t/t_vlt_timing.pl deleted file mode 100755 index 78679cf79..000000000 --- a/test_regress/t/t_vlt_timing.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_off.v"); - -compile( - verilator_flags2 => ["--exe --main --timing t/t_vlt_timing.vlt"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_timing.py b/test_regress/t/t_vlt_timing.py new file mode 100755 index 000000000..0feac9429 --- /dev/null +++ b/test_regress/t/t_vlt_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_off.v" + +test.compile(verilator_flags2=["--exe --main --timing t/t_vlt_timing.vlt"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vlt_warn.pl b/test_regress/t/t_vlt_warn.pl deleted file mode 100755 index 32163cf4e..000000000 --- a/test_regress/t/t_vlt_warn.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall t/t_vlt_warn.vlt"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_warn.py b/test_regress/t/t_vlt_warn.py new file mode 100755 index 000000000..58ef49915 --- /dev/null +++ b/test_regress/t/t_vlt_warn.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall t/t_vlt_warn.vlt"]) + +test.passes() diff --git a/test_regress/t/t_vlt_warn_bad.pl b/test_regress/t/t_vlt_warn_bad.pl deleted file mode 100755 index 43047c39e..000000000 --- a/test_regress/t/t_vlt_warn_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_vlt_warn.v"); - -lint( - verilator_flags2 => ["--lint-only t/t_vlt_warn_bad.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_warn_bad.py b/test_regress/t/t_vlt_warn_bad.py new file mode 100755 index 000000000..b55f59369 --- /dev/null +++ b/test_regress/t/t_vlt_warn_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_vlt_warn.v" + +test.lint(verilator_flags2=["--lint-only t/t_vlt_warn_bad.vlt"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_warn_ecode_bad.pl b/test_regress/t/t_vlt_warn_ecode_bad.pl deleted file mode 100755 index ebf322c30..000000000 --- a/test_regress/t/t_vlt_warn_ecode_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_vlt_warn.v"); - -lint( - verilator_flags2 => ["--lint-only t/t_vlt_warn_ecode_bad.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_warn_ecode_bad.py b/test_regress/t/t_vlt_warn_ecode_bad.py new file mode 100755 index 000000000..28f9b6683 --- /dev/null +++ b/test_regress/t/t_vlt_warn_ecode_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_vlt_warn.v" + +test.lint(verilator_flags2=["--lint-only t/t_vlt_warn_ecode_bad.vlt"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_warn_file_bad.pl b/test_regress/t/t_vlt_warn_file_bad.pl deleted file mode 100755 index 83d974461..000000000 --- a/test_regress/t/t_vlt_warn_file_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # See also t/t_lint_warn_incfile1_bad - # See also t/t_lint_warn_incfile2_bad - verilator_flags2 => ["--no-std t/t_vlt_warn_file_bad.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_warn_file_bad.py b/test_regress/t/t_vlt_warn_file_bad.py new file mode 100755 index 000000000..35484f938 --- /dev/null +++ b/test_regress/t/t_vlt_warn_file_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # See also t/t_lint_warn_incfile1_bad + # See also t/t_lint_warn_incfile2_bad + verilator_flags2=["--no-std t/t_vlt_warn_file_bad.vlt"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vpi_cb_iter.pl b/test_regress/t/t_vpi_cb_iter.pl deleted file mode 100755 index 0d8f23641..000000000 --- a/test_regress/t/t_vpi_cb_iter.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --vpi $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_cb_iter.py b/test_regress/t/t_vpi_cb_iter.py new file mode 100755 index 000000000..663e45330 --- /dev/null +++ b/test_regress/t/t_vpi_cb_iter.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --vpi", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vpi_const_type.pl b/test_regress/t/t_vpi_const_type.pl deleted file mode 100755 index 31a37c26f..000000000 --- a/test_regress/t/t_vpi_const_type.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_const_type.cpp"], - ); - -execute( - use_libvpi => 1, - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_const_type.py b/test_regress/t/t_vpi_const_type.py new file mode 100755 index 000000000..61cf61c9e --- /dev/null +++ b/test_regress/t/t_vpi_const_type.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_dump.pl b/test_regress/t/t_vpi_dump.pl deleted file mode 100755 index 0ea513860..000000000 --- a/test_regress/t/t_vpi_dump.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["--exe --vpi --public-flat-rw --no-l2name $Self->{t_dir}/t_vpi_dump.cpp $Self->{t_dir}/TestVpiMain.cpp"], - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - use_libvpi => 1, - check_finished => 1, - expect_filename => $Self->{golden_filename}, - xrun_run_expect_filename => ($Self->{golden_filename} =~ s/\.out$/.xrun.out/r), - iv_run_expect_filename => ($Self->{golden_filename} =~ s/\.out$/.iv.out/r), - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_dump.py b/test_regress/t/t_vpi_dump.py new file mode 100755 index 000000000..6a54e966f --- /dev/null +++ b/test_regress/t/t_vpi_dump.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=[ + "--exe --vpi --public-flat-rw --no-l2name", test.pli_filename, + test.t_dir + "/TestVpiMain.cpp" + ], + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute(use_libvpi=True, + expect_filename=test.golden_filename, + xrun_run_expect_filename=re.sub(r'\.out$', '.xrun.out', test.golden_filename), + iv_run_expect_filename=re.sub(r'\.out$', '.iv.out', test.golden_filename)) + +test.passes() diff --git a/test_regress/t/t_vpi_dump_missing_scopes.pl b/test_regress/t/t_vpi_dump_missing_scopes.pl deleted file mode 100755 index dbf39c31e..000000000 --- a/test_regress/t/t_vpi_dump_missing_scopes.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => "t_vpi_dump.cpp", - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["--exe --vpi --public-flat-rw --no-l2name $Self->{t_dir}/t_vpi_dump.cpp $Self->{t_dir}/TestVpiMain.cpp"], - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - use_libvpi => 1, - check_finished => 1, - expect_filename => $Self->{golden_filename}, - xrun_run_expect_filename => ($Self->{golden_filename} =~ s/\.out$/.xrun.out/r), - iv_run_expect_filename => ($Self->{golden_filename} =~ s/\.out$/.iv.out/r), - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_dump_missing_scopes.py b/test_regress/t/t_vpi_dump_missing_scopes.py new file mode 100755 index 000000000..6c016e888 --- /dev/null +++ b/test_regress/t/t_vpi_dump_missing_scopes.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_dump.cpp" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=[ + "--exe --vpi --public-flat-rw --no-l2name", test.pli_filename, + test.t_dir + "/TestVpiMain.cpp" + ], + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute(use_libvpi=True, + expect_filename=test.golden_filename, + xrun_run_expect_filename=re.sub(r'\.out$', '.xrun.out', test.golden_filename), + iv_run_expect_filename=re.sub(r'\.out$', '.iv.out', test.golden_filename)) + +test.passes() diff --git a/test_regress/t/t_vpi_escape.pl b/test_regress/t/t_vpi_escape.pl deleted file mode 100755 index 111934bb1..000000000 --- a/test_regress/t/t_vpi_escape.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -pli_filename("t_vpi_escape.cpp"); -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - sim_time => 100, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name --public-flat-rw $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - # run_env => "VPI_TRACE=" . Cwd::getcwd() . "/$Self->{obj_dir}/$Self->{name}_vpi.log", - # run_env => "VPI_TRACE=/tmp/$Self->{name}_vpi.log", - use_libvpi => 1, - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_escape.py b/test_regress/t/t_vpi_escape.py new file mode 100755 index 000000000..e216188d9 --- /dev/null +++ b/test_regress/t/t_vpi_escape.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_escape.cpp" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + sim_time=100, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name --public-flat-rw", test.pli_filename]) + +test.execute( + # run_env = "VPI_TRACE=" . Cwd::getcwd() . "/" + test.obj_dir + "/" + test.name + "_vpi.log", + # run_env = "VPI_TRACE=/tmp/"+test.name+"_vpi.log", + use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_finish.pl b/test_regress/t/t_vpi_finish.pl deleted file mode 100755 index 77affd6a5..000000000 --- a/test_regress/t/t_vpi_finish.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_vpi_finish_c.cpp"], - verilator_flags2 => ["--vpi"], - ); - -execute( - check_finished => 1, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_vpi_finish.py b/test_regress/t/t_vpi_finish.py new file mode 100755 index 000000000..34a4cc6f1 --- /dev/null +++ b/test_regress/t/t_vpi_finish.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_vpi_finish_c.cpp"], verilator_flags2=["--vpi"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vpi_get.pl b/test_regress/t/t_vpi_get.pl deleted file mode 100755 index faf3e678c..000000000 --- a/test_regress/t/t_vpi_get.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_get.cpp"], - make_pli => 1, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], - v_flags2 => ["+define+USE_VPI_NOT_DPI +define+VERILATOR_COMMENTS"], -); - -execute( - use_libvpi => 1, - check_finished => 1 -); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_get.py b/test_regress/t/t_vpi_get.py new file mode 100755 index 000000000..9f7ed1832 --- /dev/null +++ b/test_regress/t/t_vpi_get.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename], + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], + v_flags2=["+define+USE_VPI_NOT_DPI +define+VERILATOR_COMMENTS"]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_get_public_rw_switch.pl b/test_regress/t/t_vpi_get_public_rw_switch.pl deleted file mode 100755 index 203665b14..000000000 --- a/test_regress/t/t_vpi_get_public_rw_switch.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -vm_prefix("Vt_vpi_get"); -top_filename("t/t_vpi_get.v"); -pli_filename("t_vpi_get.cpp"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --vpi" - . " --public-flat-rw --prefix Vt_vpi_get --no-l2name" - . " $Self->{t_dir}/t_vpi_get.cpp"], - make_pli => 1, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], -); - -execute( - use_libvpi => 1, - check_finished => 1 -); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_get_public_rw_switch.py b/test_regress/t/t_vpi_get_public_rw_switch.py new file mode 100755 index 000000000..88e7cd71c --- /dev/null +++ b/test_regress/t/t_vpi_get_public_rw_switch.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.vm_prefix = "Vt_vpi_get" +test.top_filename = "t/t_vpi_get.v" +test.pli_filename = "t/t_vpi_get.cpp" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=[ + "--exe --vpi --public-flat-rw --prefix Vt_vpi_get --no-l2name", + test.t_dir + "/t_vpi_get.cpp" + ], + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], + v_flags2=["+define+USE_VPI_NOT_DPI"]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_memory.pl b/test_regress/t/t_vpi_memory.pl deleted file mode 100755 index c806cf940..000000000 --- a/test_regress/t/t_vpi_memory.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_memory.cpp"], - ); - -execute( - use_libvpi => 1, - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_memory.py b/test_regress/t/t_vpi_memory.py new file mode 100755 index 000000000..31a4ce4b1 --- /dev/null +++ b/test_regress/t/t_vpi_memory.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_module.pl b/test_regress/t/t_vpi_module.pl deleted file mode 100755 index fe539483b..000000000 --- a/test_regress/t/t_vpi_module.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_module.cpp"], - ); - -execute( - use_libvpi => 1, - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_module.py b/test_regress/t/t_vpi_module.py new file mode 100755 index 000000000..ef8a5d334 --- /dev/null +++ b/test_regress/t/t_vpi_module.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_module_dpi.pl b/test_regress/t/t_vpi_module_dpi.pl deleted file mode 100755 index 3dcaa1ef1..000000000 --- a/test_regress/t/t_vpi_module_dpi.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -vm_prefix("Vt_vpi_module"); -top_filename("t/t_vpi_module.v"); -pli_filename("t_vpi_module.cpp"); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_module.cpp"], - ); - -execute( - use_libvpi => 1, - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_module_dpi.py b/test_regress/t/t_vpi_module_dpi.py new file mode 100755 index 000000000..879bda0ca --- /dev/null +++ b/test_regress/t/t_vpi_module_dpi.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_vpi_module.v" +test.pli_filename = "t/t_vpi_module.cpp" +test.vm_prefix = "Vt_vpi_module" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_module_empty.pl b/test_regress/t/t_vpi_module_empty.pl deleted file mode 100755 index d9362b696..000000000 --- a/test_regress/t/t_vpi_module_empty.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_module_empty.cpp"], - ); - -execute( - use_libvpi => 1, - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_module_empty.py b/test_regress/t/t_vpi_module_empty.py new file mode 100755 index 000000000..ef8a5d334 --- /dev/null +++ b/test_regress/t/t_vpi_module_empty.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_onetime_cbs.pl b/test_regress/t/t_vpi_onetime_cbs.pl deleted file mode 100755 index b4c84aee4..000000000 --- a/test_regress/t/t_vpi_onetime_cbs.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{sanitize} = 0; # Test neads cleanup to reclaim all callbacks - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - verilator_flags2 => ["--exe --vpi $Self->{t_dir}/$Self->{name}.cpp"], - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DIVERILOG"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - ); - -execute( - check_finished => 1, - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_onetime_cbs.py b/test_regress/t/t_vpi_onetime_cbs.py new file mode 100755 index 000000000..2a2646bfd --- /dev/null +++ b/test_regress/t/t_vpi_onetime_cbs.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.sanitize = False # Test neads cleanup to reclaim all callbacks + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["--exe --vpi", test.pli_filename], + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DIVERILOG"], + v_flags2=["+define+USE_VPI_NOT_DPI"]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_package.pl b/test_regress/t/t_vpi_package.pl deleted file mode 100755 index 4cb6a2780..000000000 --- a/test_regress/t/t_vpi_package.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_package.cpp"], - ); - -execute( - use_libvpi => 1, - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_package.py b/test_regress/t/t_vpi_package.py new file mode 100755 index 000000000..61cf61c9e --- /dev/null +++ b/test_regress/t/t_vpi_package.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_param.pl b/test_regress/t/t_vpi_param.pl deleted file mode 100755 index feea273d1..000000000 --- a/test_regress/t/t_vpi_param.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_param.cpp"], - ); - -execute( - use_libvpi => 1, - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_param.py b/test_regress/t/t_vpi_param.py new file mode 100755 index 000000000..31a4ce4b1 --- /dev/null +++ b/test_regress/t/t_vpi_param.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_public_depth.pl b/test_regress/t/t_vpi_public_depth.pl deleted file mode 100755 index 930a82c94..000000000 --- a/test_regress/t/t_vpi_public_depth.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_public_depth.cpp --public-depth 3"], - make_flags => 'CPPFLAGS_ADD=-DTEST_VPI_PUBLIC_DEPTH', - ); - -execute( - use_libvpi => 1, - check_finished => 1, - v_flags2, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_public_depth.py b/test_regress/t/t_vpi_public_depth.py new file mode 100755 index 000000000..d5766b917 --- /dev/null +++ b/test_regress/t/t_vpi_public_depth.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=[ + "+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename, + "--public-depth 3" + ], + make_flags=['CPPFLAGS_ADD=-DTEST_VPI_PUBLIC_DEPTH']) + +test.execute(use_libvpi=True, v_flags2=[]) + +test.passes() diff --git a/test_regress/t/t_vpi_public_depth_off.pl b/test_regress/t/t_vpi_public_depth_off.pl deleted file mode 100755 index 64de60c4d..000000000 --- a/test_regress/t/t_vpi_public_depth_off.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -pli_filename("t_vpi_public_depth.cpp"); -top_filename("t/t_vpi_public_depth.v"); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_public_depth.cpp --public-depth 2"], - make_flags => 'CPPFLAGS_ADD=-DTEST_VPI_PUBLIC_DEPTH_OFF', - ); - -execute( - use_libvpi => 1, - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_public_depth_off.py b/test_regress/t/t_vpi_public_depth_off.py new file mode 100755 index 000000000..925b535de --- /dev/null +++ b/test_regress/t/t_vpi_public_depth_off.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_public_depth.cpp" +test.top_filename = "t/t_vpi_public_depth.v" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=[ + "+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename, + "--public-depth 2" + ], + make_flags=['CPPFLAGS_ADD=-DTEST_VPI_PUBLIC_DEPTH_OFF']) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_public_params.pl b/test_regress/t/t_vpi_public_params.pl deleted file mode 100755 index 34224a797..000000000 --- a/test_regress/t/t_vpi_public_params.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# same vpi script should work with --public-params instead of inline publics -pli_filename("t_vpi_param.cpp"); - -skip("Known compiler limitation") - if $Self->cxx_version =~ /\(GCC\) 4.4/; - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_param.cpp --public-params "], - ); - -execute( - use_libvpi => 1, - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_public_params.py b/test_regress/t/t_vpi_public_params.py new file mode 100755 index 000000000..43d10bc97 --- /dev/null +++ b/test_regress/t/t_vpi_public_params.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_param.cpp" + +# same vpi script should work with --public-params instead of inline publics + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename, "--public-params"]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_release_dup_bad.pl b/test_regress/t/t_vpi_release_dup_bad.pl deleted file mode 100755 index 2fa1154c0..000000000 --- a/test_regress/t/t_vpi_release_dup_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["t/$Self->{name}_c.cpp"], - verilator_flags2 => ['--vpi'], - ); - -execute( - fails => 1, - ); - -file_grep($Self->{run_log_filename}, qr/vpi_release_handle.*called on same object twice/i); - -ok(1); - -1; diff --git a/test_regress/t/t_vpi_release_dup_bad.py b/test_regress/t/t_vpi_release_dup_bad.py new file mode 100755 index 000000000..f49cdbdec --- /dev/null +++ b/test_regress/t/t_vpi_release_dup_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["t/" + test.name + "_c.cpp"], verilator_flags2=['--vpi']) + +test.execute(fails=True) + +test.file_grep(test.run_log_filename, r'vpi_release_handle.*called on same object twice') + +test.passes() diff --git a/test_regress/t/t_vpi_repetitive_cbs.pl b/test_regress/t/t_vpi_repetitive_cbs.pl deleted file mode 100755 index 8dab7fd6d..000000000 --- a/test_regress/t/t_vpi_repetitive_cbs.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - verilator_flags2 => ["--exe --vpi $Self->{t_dir}/$Self->{name}.cpp"], - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DIVERILOG"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - ); - -execute( - check_finished => 1, - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_repetitive_cbs.py b/test_regress/t/t_vpi_repetitive_cbs.py new file mode 100755 index 000000000..620a74cde --- /dev/null +++ b/test_regress/t/t_vpi_repetitive_cbs.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["--exe --vpi", test.pli_filename], + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DIVERILOG"], + v_flags2=["+define+USE_VPI_NOT_DPI"]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_sc.pl b/test_regress/t/t_vpi_sc.pl deleted file mode 100755 index b4f453e63..000000000 --- a/test_regress/t/t_vpi_sc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Must not make shell/main or hides bug - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --vpi --sc $Self->{t_dir}/t_vpi_sc.cpp"], -); - -execute( - check_finished => 1 -); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_sc.py b/test_regress/t/t_vpi_sc.py new file mode 100755 index 000000000..cf18f768b --- /dev/null +++ b/test_regress/t/t_vpi_sc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # Must not make shell/main or hides bug + make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --vpi --sc", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vpi_stop_bad.pl b/test_regress/t/t_vpi_stop_bad.pl deleted file mode 100755 index 061b4561c..000000000 --- a/test_regress/t/t_vpi_stop_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_vpi_stop_bad_c.cpp"], - verilator_flags2 => ["--vpi"], - ); - -execute( - fails => $Self->{vlt_all}, - check_finished => 0, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_vpi_stop_bad.py b/test_regress/t/t_vpi_stop_bad.py new file mode 100755 index 000000000..fb9404ffa --- /dev/null +++ b/test_regress/t/t_vpi_stop_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_vpi_stop_bad_c.cpp"], verilator_flags2=["--vpi"]) + +test.execute(fails=test.vlt_all, check_finished=False, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vpi_time_cb.pl b/test_regress/t/t_vpi_time_cb.pl deleted file mode 100755 index ab1608097..000000000 --- a/test_regress/t/t_vpi_time_cb.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - sim_time => 2100, - v_flags2 => ["t/t_vpi_time_cb_c.cpp"], - iv_flags2 => ["-g2005-sv -DWAVES -DIVERILOG"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_time_cb.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_time_cb.py b/test_regress/t/t_vpi_time_cb.py new file mode 100755 index 000000000..a0b1ae435 --- /dev/null +++ b/test_regress/t/t_vpi_time_cb.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + sim_time=2100, + v_flags2=["t/t_vpi_time_cb_c.cpp"], + iv_flags2=["-g2005-sv -DWAVES -DIVERILOG"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vpi_unimpl.pl b/test_regress/t/t_vpi_unimpl.pl deleted file mode 100755 index 2fdc5f638..000000000 --- a/test_regress/t/t_vpi_unimpl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_unimpl.cpp"], - ); - -execute( - check_finished => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_unimpl.py b/test_regress/t/t_vpi_unimpl.py new file mode 100755 index 000000000..24ecd0ed9 --- /dev/null +++ b/test_regress/t/t_vpi_unimpl.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vpi_var.pl b/test_regress/t/t_vpi_var.pl deleted file mode 100755 index 1788e06cd..000000000 --- a/test_regress/t/t_vpi_var.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - sim_time => 2100, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_var.cpp"], - ); - -execute( - use_libvpi => 1, - check_finished => 1, - all_run_flags => ['+PLUS +INT=1234 +STRSTR'] - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_var.py b/test_regress/t/t_vpi_var.py new file mode 100755 index 000000000..14985718b --- /dev/null +++ b/test_regress/t/t_vpi_var.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + sim_time=2100, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) + +test.passes() diff --git a/test_regress/t/t_vpi_var2.pl b/test_regress/t/t_vpi_var2.pl deleted file mode 100755 index cb4a3acb8..000000000 --- a/test_regress/t/t_vpi_var2.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -pli_filename("t_vpi_var.cpp"); -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - sim_time => 2100, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DT_VPI_VAR2"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_var.cpp"], - ); - -execute( - use_libvpi => 1, - check_finished => 1, - all_run_flags => ['+PLUS +INT=1234 +STRSTR'] - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_var2.py b/test_regress/t/t_vpi_var2.py new file mode 100755 index 000000000..478afcebb --- /dev/null +++ b/test_regress/t/t_vpi_var2.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_var.cpp" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + sim_time=2100, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DT_VPI_VAR2"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) + +test.passes() diff --git a/test_regress/t/t_vpi_var3.pl b/test_regress/t/t_vpi_var3.pl deleted file mode 100755 index 3ffa3323e..000000000 --- a/test_regress/t/t_vpi_var3.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -pli_filename("t_vpi_var.cpp"); -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - sim_time => 2100, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DT_VPI_VAR3"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name --public-flat-rw $Self->{t_dir}/t_vpi_var.cpp"], - ); - -execute( - use_libvpi => 1, - check_finished => 1, - all_run_flags => ['+PLUS +INT=1234 +STRSTR'] - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_var3.py b/test_regress/t/t_vpi_var3.py new file mode 100755 index 000000000..f4a2b3cc4 --- /dev/null +++ b/test_regress/t/t_vpi_var3.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_var.cpp" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + sim_time=2100, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DT_VPI_VAR3"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name --public-flat-rw", test.pli_filename]) + +test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) + +test.passes() diff --git a/test_regress/t/t_vpi_zero_time_cb.pl b/test_regress/t/t_vpi_zero_time_cb.pl deleted file mode 100755 index d29050de0..000000000 --- a/test_regress/t/t_vpi_zero_time_cb.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_main => 0, - make_pli => 1, - sim_time => 2100, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DIVERILOG"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_zero_time_cb.cpp -LDFLAGS '-ldl -rdynamic'"], - ); - -execute( - use_libvpi => 1, - check_finished => 1, - all_run_flags => ['+PLUS +INT=1234 +STRSTR'] - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_zero_time_cb.py b/test_regress/t/t_vpi_zero_time_cb.py new file mode 100755 index 000000000..aff674d1e --- /dev/null +++ b/test_regress/t/t_vpi_zero_time_cb.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + make_main=False, + make_pli=True, + sim_time=2100, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DIVERILOG"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename, "-LDFLAGS '-ldl -rdynamic'"]) + +test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) + +test.passes() diff --git a/test_regress/t/t_vthread.pl b/test_regress/t/t_vthread.pl deleted file mode 100755 index f3050d635..000000000 --- a/test_regress/t/t_vthread.pl +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; - -scenarios(vlt => 1); - -$Self->{sanitize} = 0; # GCC takes too long otherwise - -sub gen { - my $filename = shift; - my $n = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_vthread.pl\n"); - $fh->print("module genmod #(int val = 0)(clk, o);\n"); - $fh->print(" input clk;\n"); - $fh->print(" output int o;\n"); - $fh->print(" always @ (posedge clk) begin\n"); - $fh->print(" o <= val;\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); - $fh->print("module t (clk, o);\n"); - $fh->print(" input clk;\n"); - $fh->print(" output int o;\n"); - for (my $i = 0; $i < ($n + 1); ++$i) { - $fh->print(" int r$i;\n"); - $fh->print(" genmod #(.val($i)) rm$i (.clk(clk), .o(r$i));\n"); - } - $fh->print(" always @ (posedge clk) begin\n"); - $fh->print(" o <= r$n;\n"); - $fh->print(' $write("*-* All Finished *-*\n");', "\n"); - $fh->print(' $finish;', "\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_vthread.v"); - -gen($Self->{top_filename}, 6000); - -compile( - # use --trace to generate trace files that can be parallelized - verilator_flags2=>["--stats --trace --verilate-jobs 2"], - ); - -execute( - check_finished => 1, - ); - -file_grep($Self->{stats}, qr/Verilate jobs: 2/); - -ok(1); -1; diff --git a/test_regress/t/t_vthread.py b/test_regress/t/t_vthread.py new file mode 100755 index 000000000..f0c0d547c --- /dev/null +++ b/test_regress/t/t_vthread.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_vthread.v" +test.sanitize = False # GCC takes too long otherwise + + +def gen(filename, n): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_vthread.py\n") + fh.write("module genmod #(int val = 0)(clk, o);\n") + fh.write(" input clk;\n") + fh.write(" output int o;\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(" o <= val;\n") + fh.write(" end\n") + fh.write("endmodule\n") + fh.write("module t (clk, o);\n") + fh.write(" input clk;\n") + fh.write(" output int o;\n") + for i in range(0, n + 1): + fh.write(" int r" + str(i) + ";\n") + fh.write(" genmod #(.val(" + str(i) + ")) rm" + str(i) + " (.clk, .o(r" + str(i) + + "));\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(" o <= r" + str(n) + ";\n") + fh.write(' $write("*-* All Finished *-*\\n");' + "\n") + fh.write(' $finish;' + "\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen(test.top_filename, 6000) + +test.compile( + # use --trace to generate trace files that can be parallelized + verilator_flags2=["--stats --trace --verilate-jobs 2"]) + +test.execute() + +test.file_grep(test.stats, r'Verilate jobs: 2') + +test.passes() diff --git a/test_regress/t/t_wait.pl b/test_regress/t/t_wait.pl deleted file mode 100755 index c586a8d47..000000000 --- a/test_regress/t/t_wait.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--lint-only --no-timing'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wait.py b/test_regress/t/t_wait.py new file mode 100755 index 000000000..c2eb14c07 --- /dev/null +++ b/test_regress/t/t_wait.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only --no-timing'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wait_const.pl b/test_regress/t/t_wait_const.pl deleted file mode 100755 index 901ee7e8b..000000000 --- a/test_regress/t/t_wait_const.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--binary"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wait_const.py b/test_regress/t/t_wait_const.py new file mode 100755 index 000000000..a1700c6d9 --- /dev/null +++ b/test_regress/t/t_wait_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wait_fork.pl b/test_regress/t/t_wait_fork.pl deleted file mode 100755 index 47728df81..000000000 --- a/test_regress/t/t_wait_fork.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wait_fork.py b/test_regress/t/t_wait_fork.py new file mode 100755 index 000000000..88cfbe63f --- /dev/null +++ b/test_regress/t/t_wait_fork.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wait_order.pl b/test_regress/t/t_wait_order.pl deleted file mode 100755 index eba12604c..000000000 --- a/test_regress/t/t_wait_order.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--binary --timing'], - fails => $Self->{vlt_all}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wait_order.py b/test_regress/t/t_wait_order.py new file mode 100755 index 000000000..f65962575 --- /dev/null +++ b/test_regress/t/t_wait_order.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(expect_filename=test.golden_filename, + verilator_flags2=['--binary --timing'], + fails=test.vlt_all) + +test.passes() diff --git a/test_regress/t/t_wait_timing.pl b/test_regress/t/t_wait_timing.pl deleted file mode 100755 index 8791bb4a2..000000000 --- a/test_regress/t/t_wait_timing.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_wait.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--binary --timing -Wno-WAITCONST"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wait_timing.py b/test_regress/t/t_wait_timing.py new file mode 100755 index 000000000..eb0a58c0b --- /dev/null +++ b/test_regress/t/t_wait_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_wait.v" + +test.compile(timing_loop=True, verilator_flags2=["--binary --timing -Wno-WAITCONST"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_waiveroutput.pl b/test_regress/t/t_waiveroutput.pl deleted file mode 100755 index c995f2cde..000000000 --- a/test_regress/t/t_waiveroutput.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.out"; -my $waiver_filename = "t/$Self->{name}.vlt"; - -top_filename("t/t_waiveroutput.v"); - -compile( - v_flags2 => [$waiver_filename, '--waiver-output', $out_filename], - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_waiveroutput.py b/test_regress/t/t_waiveroutput.py new file mode 100755 index 000000000..67b6355da --- /dev/null +++ b/test_regress/t/t_waiveroutput.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_waiveroutput.v" + +out_filename = test.obj_dir + "/" + test.name + ".waiver_gen.out" +waiver_filename = "t/" + test.name + ".vlt" + +test.compile(v_flags2=[waiver_filename, '--waiver-output', out_filename]) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_waiveroutput_allgood.pl b/test_regress/t/t_waiveroutput_allgood.pl deleted file mode 100755 index 8a1846a0d..000000000 --- a/test_regress/t/t_waiveroutput_allgood.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.vlt"; -my $waiver_filename = "t/$Self->{name}.vlt"; - -top_filename("t/t_waiveroutput.v"); - -compile( - v_flags2 => [$waiver_filename, '--waiver-output', $out_filename], - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_waiveroutput_allgood.py b/test_regress/t/t_waiveroutput_allgood.py new file mode 100755 index 000000000..fd20a2c37 --- /dev/null +++ b/test_regress/t/t_waiveroutput_allgood.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_waiveroutput.v" + +out_filename = test.obj_dir + "/" + test.name + ".waiver_gen.vlt" +waiver_filename = "t/" + test.name + ".vlt" + +test.compile(v_flags2=[waiver_filename, '--waiver-output', out_filename]) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_waiveroutput_wall.pl b/test_regress/t/t_waiveroutput_wall.pl deleted file mode 100755 index ff30db361..000000000 --- a/test_regress/t/t_waiveroutput_wall.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.out"; -my $waiver_filename = "t/$Self->{name}.vlt"; - -top_filename("t/t_waiveroutput.v"); - -compile( - v_flags2 => ['-Wall', $waiver_filename, '--waiver-output', $out_filename], - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_waiveroutput_wall.py b/test_regress/t/t_waiveroutput_wall.py new file mode 100755 index 000000000..9128c7d89 --- /dev/null +++ b/test_regress/t/t_waiveroutput_wall.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_waiveroutput.v" + +out_filename = test.obj_dir + "/" + test.name + ".waiver_gen.out" +waiver_filename = "t/" + test.name + ".vlt" + +test.compile(v_flags2=['-Wall', waiver_filename, '--waiver-output', out_filename]) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_while_cond_is_stmt.pl b/test_regress/t/t_while_cond_is_stmt.pl deleted file mode 100755 index b3335ee60..000000000 --- a/test_regress/t/t_while_cond_is_stmt.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_while_cond_is_stmt.py b/test_regress/t/t_while_cond_is_stmt.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_while_cond_is_stmt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_while_timing_control.pl b/test_regress/t/t_while_timing_control.pl deleted file mode 100755 index c6aaa67e5..000000000 --- a/test_regress/t/t_while_timing_control.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 10e-7 / 10e-9; - -compile( - timing_loop => 1, - verilator_flags2 => ['--binary --timing -Wno-ZERODLY'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_while_timing_control.py b/test_regress/t/t_while_timing_control.py new file mode 100755 index 000000000..5a15b96a8 --- /dev/null +++ b/test_regress/t/t_while_timing_control.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.main_time_multiplier = 10e-7 / 10e-9 + +test.compile(timing_loop=True, verilator_flags2=['--binary --timing -Wno-ZERODLY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wire_beh1364_bad.pl b/test_regress/t/t_wire_beh1364_bad.pl deleted file mode 100755 index 6a33667e2..000000000 --- a/test_regress/t/t_wire_beh1364_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $waiver_filename = "$Self->{obj_dir}/$Self->{name}_waiver.vlt"; - -lint( - verilator_flags2 => ["--lint-only --language 1364-2001 --waiver-output ${waiver_filename}"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -if (-e $waiver_filename) { - error("Waiver file generated, not expected"); -} - -ok(1); -1; diff --git a/test_regress/t/t_wire_beh1364_bad.py b/test_regress/t/t_wire_beh1364_bad.py new file mode 100755 index 000000000..9e2f7e267 --- /dev/null +++ b/test_regress/t/t_wire_beh1364_bad.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +waiver_filename = test.obj_dir + "/" + test.name + "_waiver.vlt" + +test.lint(verilator_flags2=["--lint-only --language 1364-2001 --waiver-output", waiver_filename], + fails=True, + expect_filename=test.golden_filename) + +if os.path.exists(waiver_filename): + test.error("Waiver file generated, not expected") + +test.passes() diff --git a/test_regress/t/t_wire_beh1800_bad.pl b/test_regress/t/t_wire_beh1800_bad.pl deleted file mode 100755 index 85114ac5d..000000000 --- a/test_regress/t/t_wire_beh1800_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2017"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_beh1800_bad.py b/test_regress/t/t_wire_beh1800_bad.py new file mode 100755 index 000000000..54f436672 --- /dev/null +++ b/test_regress/t/t_wire_beh1800_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1800-2017"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wire_behp1364_bad.pl b/test_regress/t/t_wire_behp1364_bad.pl deleted file mode 100755 index 77f34c903..000000000 --- a/test_regress/t/t_wire_behp1364_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1364-2001"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_behp1364_bad.py b/test_regress/t/t_wire_behp1364_bad.py new file mode 100755 index 000000000..773f8b8e1 --- /dev/null +++ b/test_regress/t/t_wire_behp1364_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1364-2001"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wire_behp1800_bad.pl b/test_regress/t/t_wire_behp1800_bad.pl deleted file mode 100755 index 85114ac5d..000000000 --- a/test_regress/t/t_wire_behp1800_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2017"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_behp1800_bad.py b/test_regress/t/t_wire_behp1800_bad.py new file mode 100755 index 000000000..54f436672 --- /dev/null +++ b/test_regress/t/t_wire_behp1800_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1800-2017"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wire_self_bad.pl b/test_regress/t/t_wire_self_bad.pl deleted file mode 100755 index 85114ac5d..000000000 --- a/test_regress/t/t_wire_self_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2017"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_self_bad.py b/test_regress/t/t_wire_self_bad.py new file mode 100755 index 000000000..54f436672 --- /dev/null +++ b/test_regress/t/t_wire_self_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1800-2017"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wire_triand.out b/test_regress/t/t_wire_triand.out deleted file mode 100644 index c64acb3a9..000000000 --- a/test_regress/t/t_wire_triand.out +++ /dev/null @@ -1,8 +0,0 @@ -%Error-UNSUPPORTED: t/t_wire_triand.v:11:4: Unsupported: triand - 11 | triand ta; - | ^~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_wire_triand.v:12:4: Unsupported: trior - 12 | trior to; - | ^~~~~ -%Error: Exiting due to diff --git a/test_regress/t/t_wire_triand.pl b/test_regress/t/t_wire_triand.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_wire_triand.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_triand.v b/test_regress/t/t_wire_triand.v deleted file mode 100644 index dcd94f310..000000000 --- a/test_regress/t/t_wire_triand.v +++ /dev/null @@ -1,14 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' -// -// Simple bi-directional alias test. -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/); - - triand ta; - trior to; - -endmodule diff --git a/test_regress/t/t_wire_types.pl b/test_regress/t/t_wire_types.pl deleted file mode 100755 index 174d78f53..000000000 --- a/test_regress/t/t_wire_types.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{verilated_randReset} = 1; # allow checking if we initialize vars to zero only when needed - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_types.py b/test_regress/t/t_wire_types.py new file mode 100755 index 000000000..8b49c4409 --- /dev/null +++ b/test_regress/t/t_wire_types.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.verilated_randReset = 1 # allow checking if we initialize vars to zero only when needed + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wired_net_test.py b/test_regress/t/t_wired_net_test.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_wired_net_test.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wired_net_test.v b/test_regress/t/t_wired_net_test.v new file mode 100755 index 000000000..741c558a1 --- /dev/null +++ b/test_regress/t/t_wired_net_test.v @@ -0,0 +1,71 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); + +module t( +clk +/*AUTOARG*/); + input clk; + wor [3:0] ptrior1; + trior [3:0] ptrior2; + wand [3:0] ptriand1; + triand [3:0] ptriand2; + wire [3:0] z1; + wire [3:0] z2; + wire [3:0] tri_z1; + wire [3:0] tri_z2; + logic [3:0] x; + logic [3:0] y; + logic [3:0] tri_x; + logic [3:0] tri_y; + logic [3:0] tri_x_dat; + logic [3:0] tri_y_dat; + logic [3:0] tri_x_en; + logic [3:0] tri_y_en; + assign ptrior1 = x & y; + assign ptrior1 = x + y; + assign ptrior2 = tri_x & tri_y; + assign ptrior2 = tri_x + tri_y; + assign ptriand1 = x & y; + assign ptriand1 = x + y; + assign ptriand2 = tri_x & tri_y; + assign ptriand2 = tri_x + tri_y; + assign z1 = (x & y) | (x + y); + assign z2 = (x & y) & (x + y); + assign tri_z1 = (tri_x & tri_y) | (tri_x + tri_y); + assign tri_z2 = (tri_x & tri_y) & (tri_x + tri_y); + integer cyc = 0; + integer xz_index = 0; + integer xz_num = 0; + integer i; + assign tri_x[0] = tri_x_en[0] ? tri_x_dat[0] : 1'bz; + assign tri_x[1] = tri_x_en[1] ? tri_x_dat[1] : 1'bz; + assign tri_x[2] = tri_x_en[2] ? tri_x_dat[2] : 1'bz; + assign tri_x[3] = tri_x_en[3] ? tri_x_dat[3] : 1'bz; + assign tri_y[0] = tri_y_en[0] ? tri_y_dat[0] : 1'bz; + assign tri_y[1] = tri_y_en[1] ? tri_y_dat[1] : 1'bz; + assign tri_y[2] = tri_y_en[2] ? tri_y_dat[2] : 1'bz; + assign tri_y[3] = tri_y_en[3] ? tri_y_dat[3] : 1'bz; + always @ (posedge clk) begin + cyc <= cyc + 1; + x = {$random}[3:0]; + y = {$random}[3:0]; + tri_x_dat = {$random}[3:0]; + tri_y_dat = {$random}[3:0]; + tri_x_en = {$random}[3:0]; + tri_y_en = {$random}[3:0]; + `checkb(ptrior1, z1); + `checkb(ptrior2, tri_z1); + `checkb(ptriand1, z2); + `checkb(ptriand2, tri_z2); + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_with.pl b/test_regress/t/t_with.pl deleted file mode 100755 index c81275cdf..000000000 --- a/test_regress/t/t_with.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_with.py b/test_regress/t/t_with.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_with.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_with_suggest_bad.pl b/test_regress/t/t_with_suggest_bad.pl deleted file mode 100755 index 85114ac5d..000000000 --- a/test_regress/t/t_with_suggest_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2017"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_with_suggest_bad.py b/test_regress/t/t_with_suggest_bad.py new file mode 100755 index 000000000..54f436672 --- /dev/null +++ b/test_regress/t/t_with_suggest_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1800-2017"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wrapper_clone.pl b/test_regress/t/t_wrapper_clone.pl deleted file mode 100755 index 54682086b..000000000 --- a/test_regress/t/t_wrapper_clone.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test module for prepareClone/atClone APIs -# -# This file ONLY is placed into the Public Domain, for any use, -# without warranty, 2023 by Yinan Xu. -# SPDX-License-Identifier: CC0-1.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp", - "-cc"], - threads => $Self->{vltmt} ? 2 : 1, - ); - -execute( - check_finished => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_clone.py b/test_regress/t/t_wrapper_clone.py new file mode 100755 index 000000000..123fd2a37 --- /dev/null +++ b/test_regress/t/t_wrapper_clone.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test module for prepareClone/atClone APIs +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "-cc"], + threads=(2 if test.vltmt else 1)) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wrapper_context.pl b/test_regress/t/t_wrapper_context.pl deleted file mode 100755 index 30c3a78a3..000000000 --- a/test_regress/t/t_wrapper_context.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Multiple Model Test Module -# -# Copyright 2020-2021 by Andreas Kuster. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - # link threads library, add custom .cpp code, add tracing & coverage support - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp", - "--trace --coverage -cc"], - threads => 1, - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - check_finished => 1, - ); - -files_identical_sorted("$Self->{obj_dir}/coverage_top0.dat", "t/t_wrapper_context_top0.out"); -files_identical_sorted("$Self->{obj_dir}/coverage_top1.dat", "t/t_wrapper_context_top1.out"); - -vcd_identical("$Self->{obj_dir}/trace0.vcd", "t/t_wrapper_context_trace0.out"); -vcd_identical("$Self->{obj_dir}/trace1.vcd", "t/t_wrapper_context_trace1.out"); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_context.py b/test_regress/t/t_wrapper_context.py new file mode 100755 index 000000000..62943d1c4 --- /dev/null +++ b/test_regress/t/t_wrapper_context.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Multiple Model Test Module +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile( + make_top_shell=False, + make_main=False, + # link threads library, add custom .cpp code, add tracing & coverage support + verilator_flags2=["--exe", test.pli_filename, "--trace --coverage -cc"], + threads=1, + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute() +test.files_identical_sorted(test.obj_dir + "/coverage_top0.dat", "t/t_wrapper_context_top0.out") +test.files_identical_sorted(test.obj_dir + "/coverage_top1.dat", "t/t_wrapper_context_top1.out") + +test.vcd_identical(test.obj_dir + "/trace0.vcd", "t/t_wrapper_context_trace0.out") +test.vcd_identical(test.obj_dir + "/trace1.vcd", "t/t_wrapper_context_trace1.out") + +test.passes() diff --git a/test_regress/t/t_wrapper_context_fst.pl b/test_regress/t/t_wrapper_context_fst.pl deleted file mode 100755 index 98b3ceb5a..000000000 --- a/test_regress/t/t_wrapper_context_fst.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Multiple Model Test Module -# -# Copyright 2020-2021 by Andreas Kuster. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_wrapper_context.v"); - -compile( - make_top_shell => 0, - make_main => 0, - # link threads library, add custom .cpp code, add tracing & coverage support - verilator_flags2 => ["--exe $Self->{t_dir}/t_wrapper_context.cpp", - "--trace-fst --coverage -cc"], - threads => 1, - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_context_fst.py b/test_regress/t/t_wrapper_context_fst.py new file mode 100755 index 000000000..16290df42 --- /dev/null +++ b/test_regress/t/t_wrapper_context_fst.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Multiple Model Test Module +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_wrapper_context.cpp" +test.top_filename = "t/t_wrapper_context.v" + +test.compile( + make_top_shell=False, + make_main=False, + # link threads library, add custom .cpp code, add tracing & coverage support + verilator_flags2=["--exe", test.pli_filename, "--trace-fst --coverage -cc"], + threads=1, + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wrapper_context_seq.pl b/test_regress/t/t_wrapper_context_seq.pl deleted file mode 100755 index 162a0c596..000000000 --- a/test_regress/t/t_wrapper_context_seq.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Multiple Model Test Module -# -# Copyright 2020-2021 by Andreas Kuster. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_wrapper_context.v"); - -compile( - make_top_shell => 0, - make_main => 0, - # link threads library, add custom .cpp code, add tracing & coverage support - verilator_flags2 => ["--exe $Self->{t_dir}/t_wrapper_context.cpp", - "--trace --coverage -cc"], - threads => 1, - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_context_seq.py b/test_regress/t/t_wrapper_context_seq.py new file mode 100755 index 000000000..94fe6aa28 --- /dev/null +++ b/test_regress/t/t_wrapper_context_seq.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Multiple Model Test Module +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_wrapper_context.cpp" +test.top_filename = "t/t_wrapper_context.v" + +test.compile( + make_top_shell=False, + make_main=False, + # link threads library, add custom .cpp code, add tracing & coverage support + verilator_flags2=["--exe", test.pli_filename, "--trace --coverage -cc"], + threads=1, + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wrapper_del_context_bad.pl b/test_regress/t/t_wrapper_del_context_bad.pl deleted file mode 100755 index 82a4ea9cf..000000000 --- a/test_regress/t/t_wrapper_del_context_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Multiple Model Test Module -# -# Copyright 2020-2021 by Andreas Kuster. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_del_context_bad.py b/test_regress/t/t_wrapper_del_context_bad.py new file mode 100755 index 000000000..a7310eb61 --- /dev/null +++ b/test_regress/t/t_wrapper_del_context_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Multiple Model Test Module +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wrapper_legacy.pl b/test_regress/t/t_wrapper_legacy.pl deleted file mode 100755 index bdcde3470..000000000 --- a/test_regress/t/t_wrapper_legacy.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - make_flags => 'CPPFLAGS_ADD=-DVL_TIME_CONTEXT', - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_legacy.py b/test_regress/t/t_wrapper_legacy.py new file mode 100755 index 000000000..5aaf32d75 --- /dev/null +++ b/test_regress/t/t_wrapper_legacy.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename], + make_flags=['CPPFLAGS_ADD=-DVL_TIME_CONTEXT']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wrapper_legacy_time64.pl b/test_regress/t/t_wrapper_legacy_time64.pl deleted file mode 100755 index ad170fa1e..000000000 --- a/test_regress/t/t_wrapper_legacy_time64.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_wrapper_legacy.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_wrapper_legacy.cpp"], - make_flags => 'CPPFLAGS_ADD=-DVL_TIME_STAMP64', - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_legacy_time64.py b/test_regress/t/t_wrapper_legacy_time64.py new file mode 100755 index 000000000..1e14ef94a --- /dev/null +++ b/test_regress/t/t_wrapper_legacy_time64.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_wrapper_legacy.cpp" +test.top_filename = "t/t_wrapper_legacy.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename], + make_flags=['CPPFLAGS_ADD=-DVL_TIME_STAMP64']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wrapper_legacy_timed.pl b/test_regress/t/t_wrapper_legacy_timed.pl deleted file mode 100755 index edde6839d..000000000 --- a/test_regress/t/t_wrapper_legacy_timed.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_wrapper_legacy.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_wrapper_legacy.cpp"], - make_flags => 'CPPFLAGS_ADD=-UVL_TIME_CONTEXT', - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_legacy_timed.py b/test_regress/t/t_wrapper_legacy_timed.py new file mode 100755 index 000000000..74ebc2c1b --- /dev/null +++ b/test_regress/t/t_wrapper_legacy_timed.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_wrapper_legacy.cpp" +test.top_filename = "t/t_wrapper_legacy.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename], + make_flags=['CPPFLAGS_ADD=-UVL_TIME_CONTEXT']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wrapper_reuse_context_bad.pl b/test_regress/t/t_wrapper_reuse_context_bad.pl deleted file mode 100755 index 2aedd72bc..000000000 --- a/test_regress/t/t_wrapper_reuse_context_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Multiple Model Test Module -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_reuse_context_bad.py b/test_regress/t/t_wrapper_reuse_context_bad.py new file mode 100755 index 000000000..a7310eb61 --- /dev/null +++ b/test_regress/t/t_wrapper_reuse_context_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Multiple Model Test Module +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_x_assign_0.pl b/test_regress/t/t_x_assign_0.pl deleted file mode 100755 index aa0614025..000000000 --- a/test_regress/t/t_x_assign_0.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_x_assign.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--x-assign 0 --exe $Self->{t_dir}/t_x_assign.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_x_assign_0.py b/test_regress/t/t_x_assign_0.py new file mode 100755 index 000000000..37663b85c --- /dev/null +++ b/test_regress/t/t_x_assign_0.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_x_assign.cpp" +test.top_filename = "t/t_x_assign.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--x-assign 0 --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_x_assign_1.pl b/test_regress/t/t_x_assign_1.pl deleted file mode 100755 index d55fbc7a0..000000000 --- a/test_regress/t/t_x_assign_1.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_x_assign.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--x-assign 1 --exe $Self->{t_dir}/t_x_assign.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_x_assign_1.py b/test_regress/t/t_x_assign_1.py new file mode 100755 index 000000000..97778b4f0 --- /dev/null +++ b/test_regress/t/t_x_assign_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_x_assign.cpp" +test.top_filename = "t/t_x_assign.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--x-assign 1 --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_x_assign_unique_0.pl b/test_regress/t/t_x_assign_unique_0.pl deleted file mode 100755 index 675fbbd33..000000000 --- a/test_regress/t/t_x_assign_unique_0.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_x_assign.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--x-assign unique --exe $Self->{t_dir}/t_x_assign.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_x_assign_unique_0.py b/test_regress/t/t_x_assign_unique_0.py new file mode 100755 index 000000000..22aa92b35 --- /dev/null +++ b/test_regress/t/t_x_assign_unique_0.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_x_assign.cpp" +test.top_filename = "t/t_x_assign.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--x-assign unique --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_x_assign_unique_1.pl b/test_regress/t/t_x_assign_unique_1.pl deleted file mode 100755 index 675fbbd33..000000000 --- a/test_regress/t/t_x_assign_unique_1.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_x_assign.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--x-assign unique --exe $Self->{t_dir}/t_x_assign.cpp"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_x_assign_unique_1.py b/test_regress/t/t_x_assign_unique_1.py new file mode 100755 index 000000000..22aa92b35 --- /dev/null +++ b/test_regress/t/t_x_assign_unique_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_x_assign.cpp" +test.top_filename = "t/t_x_assign.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--x-assign unique --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_xml_begin_hier.pl b/test_regress/t/t_xml_begin_hier.pl deleted file mode 100755 index d25c191ff..000000000 --- a/test_regress/t/t_xml_begin_hier.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_begin_hier.py b/test_regress/t/t_xml_begin_hier.py new file mode 100755 index 000000000..e24dca19d --- /dev/null +++ b/test_regress/t/t_xml_begin_hier.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_debugcheck.out b/test_regress/t/t_xml_debugcheck.out index 67ac81eb4..d962b2382 100644 --- a/test_regress/t/t_xml_debugcheck.out +++ b/test_regress/t/t_xml_debugcheck.out @@ -61,7 +61,7 @@ - + @@ -69,10 +69,10 @@ - - - - + + + + @@ -82,10 +82,10 @@ - - - - + + + + @@ -99,14 +99,14 @@ - - - - - - - - + + + + + + + + @@ -118,14 +118,14 @@ - - - - - - - - + + + + + + + + @@ -141,14 +141,14 @@ - - - - - - - - + + + + + + + + @@ -160,14 +160,14 @@ - - - - - - - - + + + + + + + + @@ -183,18 +183,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -208,18 +208,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -237,18 +237,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -262,18 +262,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -291,18 +291,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -316,18 +316,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -345,10 +345,10 @@ - + - - + + @@ -358,10 +358,10 @@ - + - - + + @@ -375,10 +375,10 @@ - + - - + + @@ -388,10 +388,10 @@ - + - - + + @@ -405,14 +405,14 @@ - + - - - + + + - - + + @@ -424,14 +424,14 @@ - + - - - + + + - - + + @@ -447,14 +447,14 @@ - + - - - + + + - - + + @@ -466,14 +466,14 @@ - + - - - + + + - - + + @@ -487,12 +487,12 @@ - - - - - - + + + + + + @@ -500,24 +500,24 @@ - - - - - - - + + + + + + + - + - - - + + + - + @@ -541,31 +541,27 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + - - - - + + + + @@ -580,26 +576,24 @@ - - - - - - + + + + - - + + - - - + + + - + @@ -701,13 +695,13 @@ - - + + - + @@ -716,16 +710,16 @@ - - - - - - + + + + + + - - - + + + @@ -755,12 +749,12 @@ - - - - - - + + + + + + @@ -768,33 +762,33 @@ - - - - - - - + + + + + + + - + - - - + + + - + - - - - + + + + @@ -804,10 +798,10 @@ - - - - + + + + @@ -821,10 +815,10 @@ - - - - + + + + @@ -834,10 +828,10 @@ - - - - + + + + @@ -851,14 +845,14 @@ - - - - - - - - + + + + + + + + @@ -870,14 +864,14 @@ - - - - - - - - + + + + + + + + @@ -893,10 +887,10 @@ - + - - + + @@ -906,10 +900,10 @@ - + - - + + @@ -923,10 +917,10 @@ - + - - + + @@ -936,10 +930,10 @@ - + - - + + @@ -953,14 +947,14 @@ - + - - - + + + - - + + @@ -972,14 +966,14 @@ - + - - - + + + - - + + @@ -1005,12 +999,12 @@ - - - - - - + + + + + + @@ -1018,33 +1012,33 @@ - - - - - - - + + + + + + + - + - - - + + + - + - - - - + + + + @@ -1054,10 +1048,10 @@ - - - - + + + + @@ -1071,10 +1065,10 @@ - - - - + + + + @@ -1084,10 +1078,10 @@ - - - - + + + + @@ -1101,14 +1095,14 @@ - - - - - - - - + + + + + + + + @@ -1120,14 +1114,14 @@ - - - - - - - - + + + + + + + + @@ -1143,10 +1137,10 @@ - + - - + + @@ -1156,10 +1150,10 @@ - + - - + + @@ -1173,10 +1167,10 @@ - + - - + + @@ -1186,10 +1180,10 @@ - + - - + + @@ -1203,14 +1197,14 @@ - + - - - + + + - - + + @@ -1222,14 +1216,14 @@ - + - - - + + + - - + + @@ -1255,12 +1249,12 @@ - - - - - - + + + + + + @@ -1268,33 +1262,33 @@ - - - - - - - + + + + + + + - + - - - + + + - + - - - - + + + + @@ -1304,10 +1298,10 @@ - - - - + + + + @@ -1321,10 +1315,10 @@ - - - - + + + + @@ -1334,10 +1328,10 @@ - - - - + + + + @@ -1351,14 +1345,14 @@ - - - - - - - - + + + + + + + + @@ -1370,14 +1364,14 @@ - - - - - - - - + + + + + + + + @@ -1393,10 +1387,10 @@ - + - - + + @@ -1406,10 +1400,10 @@ - + - - + + @@ -1423,10 +1417,10 @@ - + - - + + @@ -1436,10 +1430,10 @@ - + - - + + @@ -1453,14 +1447,14 @@ - + - - - + + + - - + + @@ -1472,14 +1466,14 @@ - + - - - + + + - - + + @@ -1518,13 +1512,13 @@ - - - + + + - - - + + + @@ -1735,7 +1729,7 @@ - + @@ -1761,7 +1755,7 @@ - + @@ -1777,13 +1771,13 @@ - + - + @@ -1846,7 +1840,7 @@ - + diff --git a/test_regress/t/t_xml_debugcheck.pl b/test_regress/t/t_xml_debugcheck.pl deleted file mode 100755 index 1894252fe..000000000 --- a/test_regress/t/t_xml_debugcheck.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -top_filename("t/t_enum_type_methods.v"); - -compile( - verilator_flags2 => ['--no-std', '--debug-check', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}, 'logfile'); - -# make sure that certain tags are present in --debug-check -# that would not be present in --xml-only -file_grep("$out_filename", qr//x); # for and -file_grep("$out_filename", qr/ signed=/x); # for -file_grep("$out_filename", qr/ func=/x); # for - -ok(1); -1; diff --git a/test_regress/t/t_xml_debugcheck.py b/test_regress/t/t_xml_debugcheck.py new file mode 100755 index 000000000..c88859559 --- /dev/null +++ b/test_regress/t/t_xml_debugcheck.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_enum_type_methods.v" + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--debug-check', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename, 'logfile') + +# make sure that certain tags are present in --debug-check +# that would not be present in --xml-only +test.file_grep(out_filename, r'') # for and +test.file_grep(out_filename, r' signed=') # for +test.file_grep(out_filename, r' func=') # for + +test.passes() diff --git a/test_regress/t/t_xml_first.pl b/test_regress/t/t_xml_first.pl deleted file mode 100755 index d25c191ff..000000000 --- a/test_regress/t/t_xml_first.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_first.py b/test_regress/t/t_xml_first.py new file mode 100755 index 000000000..e24dca19d --- /dev/null +++ b/test_regress/t/t_xml_first.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_flat.pl b/test_regress/t/t_xml_flat.pl deleted file mode 100755 index 9d4890c52..000000000 --- a/test_regress/t/t_xml_flat.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -top_filename("t/t_xml_first.v"); - -compile( - verilator_flags2 => ['--no-std', '--xml-only', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_flat.py b/test_regress/t/t_xml_flat.py new file mode 100755 index 000000000..39b3babd7 --- /dev/null +++ b/test_regress/t/t_xml_flat.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_xml_first.v" + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_flat_no_inline_mod.pl b/test_regress/t/t_xml_flat_no_inline_mod.pl deleted file mode 100755 index 9763b0cc1..000000000 --- a/test_regress/t/t_xml_flat_no_inline_mod.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_flat_no_inline_mod.py b/test_regress/t/t_xml_flat_no_inline_mod.py new file mode 100755 index 000000000..d011198ac --- /dev/null +++ b/test_regress/t/t_xml_flat_no_inline_mod.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_flat_pub_mod.pl b/test_regress/t/t_xml_flat_pub_mod.pl deleted file mode 100755 index 9763b0cc1..000000000 --- a/test_regress/t/t_xml_flat_pub_mod.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_flat_pub_mod.py b/test_regress/t/t_xml_flat_pub_mod.py new file mode 100755 index 000000000..d011198ac --- /dev/null +++ b/test_regress/t/t_xml_flat_pub_mod.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_flat_vlvbound.pl b/test_regress/t/t_xml_flat_vlvbound.pl deleted file mode 100755 index 9763b0cc1..000000000 --- a/test_regress/t/t_xml_flat_vlvbound.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_flat_vlvbound.py b/test_regress/t/t_xml_flat_vlvbound.py new file mode 100755 index 000000000..d011198ac --- /dev/null +++ b/test_regress/t/t_xml_flat_vlvbound.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_output.pl b/test_regress/t/t_xml_output.pl deleted file mode 100755 index 8f7f7dc3e..000000000 --- a/test_regress/t/t_xml_output.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/renamed-$Self->{name}.xml"; - -compile( - verilator_flags2 => ["--no-std", "--xml-only --xml-output $out_filename"], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -foreach my $file (glob("$Self->{obj_dir}/*")) { - next if $file =~ /\.log/; # Made by driver.pl, not Verilator - next if $file =~ /\.status/; # Made by driver.pl, not Verilator - next if $file =~ /renamed-/; # Requested output - error("%Error: Created $file, but --xml-only shouldn't create files"); -} - -ok(1); -1; diff --git a/test_regress/t/t_xml_output.py b/test_regress/t/t_xml_output.py new file mode 100755 index 000000000..640e36eca --- /dev/null +++ b/test_regress/t/t_xml_output.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/renamed-" + test.name + ".xml" + +test.compile(verilator_flags2=["--no-std", "--xml-only --xml-output", out_filename], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +for filename in test.glob_some(test.obj_dir + "/*"): + if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources + or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources + or re.search(r'renamed-', filename)): # Requested output + continue + test.error("%Error: Created '" + filename + "', but --xml-only shouldn't create files") + +test.passes() diff --git a/test_regress/t/t_xml_tag.pl b/test_regress/t/t_xml_tag.pl deleted file mode 100755 index d25c191ff..000000000 --- a/test_regress/t/t_xml_tag.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_tag.py b/test_regress/t/t_xml_tag.py new file mode 100755 index 000000000..e24dca19d --- /dev/null +++ b/test_regress/t/t_xml_tag.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/vltest_bootstrap.py b/test_regress/t/vltest_bootstrap.py new file mode 100755 index 000000000..b299e9207 --- /dev/null +++ b/test_regress/t/vltest_bootstrap.py @@ -0,0 +1,17 @@ +# DESCRIPTION: Verilator: Verilog Test bootstrap loader +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import os +import re +import sys + +os.chdir(os.path.dirname(os.path.realpath(__file__)) + "/..") +# Avoid chdir leaving the .. which confuses later commands +os.environ['PWD'] = os.getcwd() +args = list(map(lambda arg: re.sub(r'.*/test_regress/', '', arg), sys.argv)) +os.execl("./driver.py", "driver.py", *args) diff --git a/test_regress/t_cover_line_cc.info.out b/test_regress/t_cover_line_cc.info.out deleted file mode 100644 index d02a0b274..000000000 --- a/test_regress/t_cover_line_cc.info.out +++ /dev/null @@ -1,87 +0,0 @@ -TN:verilator_coverage -SF:t/t_cover_line.v -DA:15,1 -DA:18,1 -DA:47,10 -DA:48,0 -DA:49,10 -DA:50,10 -DA:52,1 -DA:53,1 -DA:54,1 -DA:55,1 -DA:58,1 -DA:59,1 -DA:61,9 -DA:62,9 -DA:65,1 -DA:66,1 -DA:67,1 -DA:68,1 -DA:71,9 -DA:72,9 -DA:75,1 -DA:76,1 -DA:77,1 -DA:79,1 -DA:80,1 -DA:81,1 -DA:83,1 -DA:84,1 -DA:85,1 -DA:88,7 -DA:89,7 -DA:92,0 -DA:93,0 -DA:94,0 -DA:96,0 -DA:97,0 -DA:98,0 -DA:99,0 -DA:102,1 -DA:103,1 -DA:105,1 -DA:107,1 -DA:112,1 -DA:113,1 -DA:114,1 -DA:119,1 -DA:121,1 -DA:132,20 -DA:133,2 -DA:134,2 -DA:137,18 -DA:156,20 -DA:157,20 -DA:158,0 -DA:160,0 -DA:162,2 -DA:164,2 -DA:166,18 -DA:180,1 -DA:181,1 -DA:182,0 -DA:183,1 -DA:186,11 -DA:187,0 -DA:188,11 -DA:191,11 -DA:192,0 -DA:193,11 -DA:207,10 -DA:208,10 -DA:211,11 -DA:213,11 -DA:214,1 -DA:215,1 -DA:217,1 -DA:218,1 -DA:221,11 -DA:222,1 -DA:223,11 -DA:224,11 -DA:245,10 -DA:246,1 -DA:248,1 -DA:249,0 -end_of_record diff --git a/test_regress/t_cover_toggle_min.info.out b/test_regress/t_cover_toggle_min.info.out deleted file mode 100644 index 7608c5284..000000000 --- a/test_regress/t_cover_toggle_min.info.out +++ /dev/null @@ -1,6 +0,0 @@ -TN:verilator_coverage -SF:t/t_cover_toggle_min.v -DA:10,0 -DA:11,0 -DA:12,1 -end_of_record diff --git a/test_regress/t_vlcov_info.info.out b/test_regress/t_vlcov_info.info.out deleted file mode 100644 index f34103ee6..000000000 --- a/test_regress/t_vlcov_info.info.out +++ /dev/null @@ -1,4 +0,0 @@ -TN:verilator_coverage -SF:file1.sp -DA:159,0 -end_of_record diff --git a/verilator-config-version.cmake.in b/verilator-config-version.cmake.in index 55a9ae285..92160d8fc 100644 --- a/verilator-config-version.cmake.in +++ b/verilator-config-version.cmake.in @@ -5,7 +5,7 @@ # This allows specifying a minimum Verilator version. # Include it in your CMakeLists.txt using: # -# find_package(verilate 4.0) +# find_package(verilator 4.0) # # Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU @@ -18,10 +18,10 @@ set(PACKAGE_VERSION "@PACKAGE_VERSION_NUMBER@") if(PACKAGE_VERSION VERSION_LESS PACKAGE_FIND_VERSION) - set(PACKAGE_VERSION_COMPATIBLE FALSE) + set(PACKAGE_VERSION_COMPATIBLE FALSE) else() - set(PACKAGE_VERSION_COMPATIBLE TRUE) - if(PACKAGE_FIND_VERSION STREQUAL PACKAGE_VERSION) - set(PACKAGE_VERSION_EXACT TRUE) - endif() + set(PACKAGE_VERSION_COMPATIBLE TRUE) + if(PACKAGE_FIND_VERSION STREQUAL PACKAGE_VERSION) + set(PACKAGE_VERSION_EXACT TRUE) + endif() endif() diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in index ebf14380b..3c00e1d86 100644 --- a/verilator-config.cmake.in +++ b/verilator-config.cmake.in @@ -4,7 +4,7 @@ # # Include it in your CMakeLists.txt using: # -# find_package(verilate) +# find_package(verilator) # # This script adds a verilate function. # @@ -22,410 +22,570 @@ cmake_minimum_required(VERSION 3.13) # Prefer VERILATOR_ROOT from environment -if (DEFINED ENV{VERILATOR_ROOT}) - set(VERILATOR_ROOT "$ENV{VERILATOR_ROOT}" CACHE PATH "VERILATOR_ROOT") +if(DEFINED ENV{VERILATOR_ROOT}) + set(VERILATOR_ROOT "$ENV{VERILATOR_ROOT}" CACHE PATH "VERILATOR_ROOT") endif() set(VERILATOR_ROOT "${CMAKE_CURRENT_LIST_DIR}" CACHE PATH "VERILATOR_ROOT") -find_program(VERILATOR_BIN NAMES verilator_bin verilator_bin.exe - HINTS ${VERILATOR_ROOT}/bin ENV VERILATOR_ROOT - NO_CMAKE_PATH NO_CMAKE_ENVIRONMENT_PATH NO_CMAKE_SYSTEM_PATH) +find_program( + VERILATOR_BIN + NAMES verilator_bin verilator_bin.exe + HINTS ${VERILATOR_ROOT}/bin + ENV VERILATOR_ROOT + NO_CMAKE_PATH + NO_CMAKE_ENVIRONMENT_PATH + NO_CMAKE_SYSTEM_PATH +) -if (NOT VERILATOR_ROOT) - message(FATAL_ERROR "VERILATOR_ROOT cannot be detected. Set it to the appropriate directory (e.g. /usr/share/verilator) as an environment variable or CMake define.") +if(NOT VERILATOR_ROOT) + message( + FATAL_ERROR + "VERILATOR_ROOT cannot be detected. Set it to the appropriate directory (e.g. /usr/share/verilator) as an environment variable or CMake define." + ) endif() -if (NOT VERILATOR_BIN) - message(FATAL_ERROR "Cannot find verilator_bin excecutable.") +if(NOT VERILATOR_BIN) + message(FATAL_ERROR "Cannot find verilator_bin excecutable.") endif() set(verilator_FOUND 1) include(CheckCXXSourceCompiles) function(_verilator_check_cxx_libraries LIBRARIES RESVAR) - # Check whether a particular link option creates a valid executable - set(_VERILATOR_CHECK_CXX_LINK_OPTIONS_SRC "int main() {return 0;}\n") - set(CMAKE_REQUIRED_FLAGS) - set(CMAKE_REQUIRED_DEFINITIONS) - set(CMAKE_REQUIRED_INCLUDES) - set(CMAKE_REQUIRED_LINK_OPTIONS) - set(CMAKE_REQUIRED_LIBRARIES ${LIBRARIES}) - set(CMAKE_REQUIRED_QUIET) - check_cxx_source_compiles("${_VERILATOR_CHECK_CXX_LINK_OPTIONS_SRC}" "${RESVAR}") - set("${RESVAR}" "${${RESVAR}}" PARENT_SCOPE) + # Check whether a particular link option creates a valid executable + set(_VERILATOR_CHECK_CXX_LINK_OPTIONS_SRC "int main() {return 0;}\n") + set(CMAKE_REQUIRED_FLAGS) + set(CMAKE_REQUIRED_DEFINITIONS) + set(CMAKE_REQUIRED_INCLUDES) + set(CMAKE_REQUIRED_LINK_OPTIONS) + set(CMAKE_REQUIRED_LIBRARIES ${LIBRARIES}) + set(CMAKE_REQUIRED_QUIET) + check_cxx_source_compiles( + "${_VERILATOR_CHECK_CXX_LINK_OPTIONS_SRC}" + "${RESVAR}" + ) + set("${RESVAR}" "${${RESVAR}}" PARENT_SCOPE) endfunction() # Check compiler flag support. Skip on MSVC, these are all GCC flags. -if (NOT CMAKE_CXX_COMPILER_ID MATCHES MSVC) - if (NOT DEFINED VERILATOR_CFLAGS OR NOT DEFINED VERILATOR_MT_CFLAGS) - include(CheckCXXCompilerFlag) - foreach (FLAG @CFG_CXX_FLAGS_CMAKE@) - string(MAKE_C_IDENTIFIER ${FLAG} FLAGNAME) - check_cxx_compiler_flag(${FLAG} ${FLAGNAME}) - if (${FLAGNAME}) - list(APPEND VERILATOR_CFLAGS ${FLAG}) - endif() - endforeach() - foreach (FLAG @CFG_LDFLAGS_THREADS_CMAKE@) - string(MAKE_C_IDENTIFIER ${FLAG} FLAGNAME) - _verilator_check_cxx_libraries("${FLAG}" ${FLAGNAME}) - if (${FLAGNAME}) - list(APPEND VERILATOR_MT_CFLAGS ${FLAG}) - endif() - endforeach() - endif() +if(NOT CMAKE_CXX_COMPILER_ID MATCHES MSVC) + if(NOT DEFINED VERILATOR_CFLAGS OR NOT DEFINED VERILATOR_MT_CFLAGS) + include(CheckCXXCompilerFlag) + foreach(FLAG @CFG_CXX_FLAGS_CMAKE@) + string(MAKE_C_IDENTIFIER ${FLAG} FLAGNAME) + check_cxx_compiler_flag(${FLAG} ${FLAGNAME}) + if(${FLAGNAME}) + list(APPEND VERILATOR_CFLAGS ${FLAG}) + endif() + endforeach() + foreach(FLAG @CFG_LDFLAGS_THREADS_CMAKE@) + string(MAKE_C_IDENTIFIER ${FLAG} FLAGNAME) + _verilator_check_cxx_libraries("${FLAG}" ${FLAGNAME}) + if(${FLAGNAME}) + list(APPEND VERILATOR_MT_CFLAGS ${FLAG}) + endif() + endforeach() + endif() endif() -if (${CMAKE_CXX_COMPILER_ID} STREQUAL "AppleClang") - add_link_options(-Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv) +if(${CMAKE_CXX_COMPILER_ID} STREQUAL "AppleClang") + add_link_options(-Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv) endif() -define_property(TARGET - PROPERTY VERILATOR_THREADED - BRIEF_DOCS "Deprecated and has no effect (ignored)" - FULL_DOCS "Deprecated and has no effect (ignored)" +define_property( + TARGET + PROPERTY VERILATOR_THREADED + BRIEF_DOCS "Deprecated and has no effect (ignored)" + FULL_DOCS "Deprecated and has no effect (ignored)" ) -define_property(TARGET - PROPERTY VERILATOR_TRACE_THREADED - BRIEF_DOCS "Verilator multithread tracing enabled" - FULL_DOCS "Verilator multithread tracing enabled" +define_property( + TARGET + PROPERTY VERILATOR_TRACE_THREADED + BRIEF_DOCS "Verilator multithread tracing enabled" + FULL_DOCS "Verilator multithread tracing enabled" ) -define_property(TARGET - PROPERTY VERILATOR_TIMING - BRIEF_DOCS "Verilator timing enabled" - FULL_DOCS "Verilator timing enabled" +define_property( + TARGET + PROPERTY VERILATOR_TIMING + BRIEF_DOCS "Verilator timing enabled" + FULL_DOCS "Verilator timing enabled" ) -define_property(TARGET - PROPERTY VERILATOR_COVERAGE - BRIEF_DOCS "Verilator coverage enabled" - FULL_DOCS "Verilator coverage enabled" +define_property( + TARGET + PROPERTY VERILATOR_COVERAGE + BRIEF_DOCS "Verilator coverage enabled" + FULL_DOCS "Verilator coverage enabled" ) -define_property(TARGET - PROPERTY VERILATOR_TRACE - BRIEF_DOCS "Verilator trace enabled" - FULL_DOCS "Verilator trace enabled" +define_property( + TARGET + PROPERTY VERILATOR_TRACE + BRIEF_DOCS "Verilator trace enabled" + FULL_DOCS "Verilator trace enabled" ) -define_property(TARGET - PROPERTY VERILATOR_TRACE_VCD - BRIEF_DOCS "Verilator VCD trace enabled" - FULL_DOCS "Verilator VCD trace enabled" +define_property( + TARGET + PROPERTY VERILATOR_TRACE_VCD + BRIEF_DOCS "Verilator VCD trace enabled" + FULL_DOCS "Verilator VCD trace enabled" ) -define_property(TARGET - PROPERTY VERILATOR_TRACE_FST - BRIEF_DOCS "Verilator FST trace enabled" - FULL_DOCS "Verilator FST trace enabled" +define_property( + TARGET + PROPERTY VERILATOR_TRACE_FST + BRIEF_DOCS "Verilator FST trace enabled" + FULL_DOCS "Verilator FST trace enabled" ) -define_property(TARGET - PROPERTY VERILATOR_SYSTEMC - BRIEF_DOCS "Verilator SystemC enabled" - FULL_DOCS "Verilator SystemC enabled" +define_property( + TARGET + PROPERTY VERILATOR_SYSTEMC + BRIEF_DOCS "Verilator SystemC enabled" + FULL_DOCS "Verilator SystemC enabled" ) -define_property(TARGET +define_property( + TARGET PROPERTY VERILATOR_TRACE_STRUCTS BRIEF_DOCS "Verilator trace structs enabled" FULL_DOCS "Verilator trace structs enabled" ) - function(verilate TARGET) - cmake_parse_arguments(VERILATE "COVERAGE;TRACE;TRACE_FST;SYSTEMC;TRACE_STRUCTS" - "PREFIX;TOP_MODULE;THREADS;TRACE_THREADS;DIRECTORY" - "SOURCES;VERILATOR_ARGS;INCLUDE_DIRS;OPT_SLOW;OPT_FAST;OPT_GLOBAL" - ${ARGN}) - if (NOT VERILATE_SOURCES) - message(FATAL_ERROR "Need at least one source") - endif() - - if (NOT VERILATE_PREFIX) - list(LENGTH VERILATE_SOURCES NUM_SOURCES) - if (${NUM_SOURCES} GREATER 1) - message(WARNING "Specify PREFIX if there are multiple SOURCES") + cmake_parse_arguments( + VERILATE + "COVERAGE;TRACE;TRACE_FST;SYSTEMC;TRACE_STRUCTS" + "PREFIX;TOP_MODULE;THREADS;TRACE_THREADS;DIRECTORY" + "SOURCES;VERILATOR_ARGS;INCLUDE_DIRS;OPT_SLOW;OPT_FAST;OPT_GLOBAL" + ${ARGN} + ) + if(NOT VERILATE_SOURCES) + message(FATAL_ERROR "Need at least one source") endif() - list(GET VERILATE_SOURCES 0 TOPSRC) - get_filename_component(_SRC_NAME ${TOPSRC} NAME_WE) - string(MAKE_C_IDENTIFIER V${_SRC_NAME} VERILATE_PREFIX) - endif() - if (VERILATE_TOP_MODULE) - list(APPEND VERILATOR_ARGS --top ${VERILATE_TOP_MODULE}) - endif() - - if (VERILATE_THREADS) - list(APPEND VERILATOR_ARGS --threads ${VERILATE_THREADS}) - endif() - - if (VERILATE_TRACE_THREADS) - list(APPEND VERILATOR_ARGS --trace-threads ${VERILATE_TRACE_THREADS}) - endif() - - if (VERILATE_COVERAGE) - list(APPEND VERILATOR_ARGS --coverage) - endif() - - if (VERILATE_TRACE AND VERILATE_TRACE_FST) - message(FATAL_ERROR "Cannot have both TRACE and TRACE_FST") - endif() - - if (VERILATE_TRACE) - list(APPEND VERILATOR_ARGS --trace) - endif() - - if (VERILATE_TRACE_FST) - list(APPEND VERILATOR_ARGS --trace-fst) - endif() - - if (VERILATE_SYSTEMC) - list(APPEND VERILATOR_ARGS --sc) - else() - list(APPEND VERILATOR_ARGS --cc) - endif() - - if (VERILATE_TRACE_STRUCTS) - list(APPEND VERILATOR_ARGS --trace-structs) - endif() - - foreach(INC ${VERILATE_INCLUDE_DIRS}) - list(APPEND VERILATOR_ARGS -y "${INC}") - endforeach() - - string(TOLOWER ${CMAKE_CXX_COMPILER_ID} COMPILER) - if (COMPILER STREQUAL "appleclang") - set(COMPILER clang) - elseif (NOT COMPILER MATCHES "^msvc$|^clang$") - set(COMPILER gcc) - endif() - - get_target_property(BINARY_DIR "${TARGET}" BINARY_DIR) - get_target_property(TARGET_NAME "${TARGET}" NAME) - set(VDIR "${BINARY_DIR}/CMakeFiles/${TARGET_NAME}.dir/${VERILATE_PREFIX}.dir") - - if (VERILATE_DIRECTORY) - set(VDIR "${VERILATE_DIRECTORY}") - endif() - - file(MAKE_DIRECTORY ${VDIR}) - - set(VERILATOR_COMMAND "${CMAKE_COMMAND}" -E env "VERILATOR_ROOT=${VERILATOR_ROOT}" - "${VERILATOR_BIN}" --compiler ${COMPILER} - --prefix ${VERILATE_PREFIX} --Mdir ${VDIR} --make cmake - ${VERILATOR_ARGS} ${VERILATE_VERILATOR_ARGS} - ${VERILATE_SOURCES}) - - set(VARGS_FILE "${VDIR}/verilator_args.txt") - set(VCMAKE "${VDIR}/${VERILATE_PREFIX}.cmake") - set(VCMAKE_COPY "${VDIR}/${VERILATE_PREFIX}_copy.cmake") - - if (NOT EXISTS "${VARGS_FILE}" OR NOT EXISTS "${VCMAKE_COPY}") - set(VERILATOR_OUTDATED ON) - else() - file(READ "${VARGS_FILE}" PREVIOUS_VERILATOR_COMMAND) - if(NOT VERILATOR_COMMAND STREQUAL PREVIOUS_VERILATOR_COMMAND) - set(VERILATOR_OUTDATED ON) + if(NOT VERILATE_PREFIX) + list(LENGTH VERILATE_SOURCES NUM_SOURCES) + if(${NUM_SOURCES} GREATER 1) + message(WARNING "Specify PREFIX if there are multiple SOURCES") + endif() + list(GET VERILATE_SOURCES 0 TOPSRC) + get_filename_component(_SRC_NAME ${TOPSRC} NAME_WE) + string(MAKE_C_IDENTIFIER V${_SRC_NAME} VERILATE_PREFIX) endif() - endif() - if (VERILATOR_OUTDATED) - message(STATUS "Executing Verilator...") - execute_process( - COMMAND ${VERILATOR_COMMAND} - WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" - RESULT_VARIABLE _VERILATOR_RC - OUTPUT_VARIABLE _VERILATOR_OUTPUT - ERROR_VARIABLE _VERILATOR_OUTPUT) - if (_VERILATOR_RC) - string(REPLACE ";" " " VERILATOR_COMMAND_READABLE "${VERILATOR_COMMAND}") - message("Verilator command: \"${VERILATOR_COMMAND_READABLE}\"") - message("Output:\n${_VERILATOR_OUTPUT}") - message(FATAL_ERROR "Verilator command failed (return code=${_VERILATOR_RC})") + if(VERILATE_TOP_MODULE) + list(APPEND VERILATOR_ARGS --top ${VERILATE_TOP_MODULE}) endif() - execute_process(COMMAND "${CMAKE_COMMAND}" -E copy "${VCMAKE}" "${VCMAKE_COPY}") - endif() - file(WRITE "${VARGS_FILE}" "${VERILATOR_COMMAND}") - include("${VCMAKE_COPY}") + if(VERILATE_THREADS) + list(APPEND VERILATOR_ARGS --threads ${VERILATE_THREADS}) + endif() - set(GENERATED_C_SOURCES ${${VERILATE_PREFIX}_CLASSES_FAST} - ${${VERILATE_PREFIX}_CLASSES_SLOW} - ${${VERILATE_PREFIX}_SUPPORT_FAST} - ${${VERILATE_PREFIX}_SUPPORT_SLOW}) - # No need for .h's as the .cpp will get written same time - set(GENERATED_SOURCES ${GENERATED_C_SOURCES}) + if(VERILATE_TRACE_THREADS) + list(APPEND VERILATOR_ARGS --trace-threads ${VERILATE_TRACE_THREADS}) + endif() - add_custom_command(OUTPUT ${GENERATED_SOURCES} "${VCMAKE}" - COMMAND ${VERILATOR_COMMAND} - WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" - DEPENDS "${VERILATOR_BIN}" ${${VERILATE_PREFIX}_DEPS} VERBATIM) - # Reconfigure if file list has changed - # (check contents rather than modified time to avoid unnecessary reconfiguration) - add_custom_command(OUTPUT "${VCMAKE_COPY}" - COMMAND "${CMAKE_COMMAND}" -E copy_if_different - "${VCMAKE}" "${VCMAKE_COPY}" - DEPENDS "${VCMAKE}" VERBATIM) + if(VERILATE_COVERAGE) + list(APPEND VERILATOR_ARGS --coverage) + endif() - if (${VERILATE_PREFIX}_COVERAGE) - # If any verilate() call specifies COVERAGE, define VM_COVERAGE in the final build - set_property(TARGET ${TARGET} PROPERTY VERILATOR_COVERAGE ON) - endif() + if(VERILATE_TRACE AND VERILATE_TRACE_FST) + message(FATAL_ERROR "Cannot have both TRACE and TRACE_FST") + endif() - if (${VERILATE_PREFIX}_TRACE_VCD) - # If any verilate() call specifies TRACE, define VM_TRACE in the final build - set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) - set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_VCD ON) - endif() + if(VERILATE_TRACE) + list(APPEND VERILATOR_ARGS --trace) + endif() - if (${VERILATE_PREFIX}_TRACE_FST) - # If any verilate() call specifies TRACE_FST, define VM_TRACE_FST in the final build - set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) - set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_FST ON) - endif() + if(VERILATE_TRACE_FST) + list(APPEND VERILATOR_ARGS --trace-fst) + endif() - if (${VERILATE_PREFIX}_SC) - # If any verilate() call specifies SYSTEMC, define VM_SC in the final build - set_property(TARGET ${TARGET} PROPERTY VERILATOR_SYSTEMC ON) - endif() + if(VERILATE_SYSTEMC) + list(APPEND VERILATOR_ARGS --sc) + else() + list(APPEND VERILATOR_ARGS --cc) + endif() - if (${VERILATE_PREFIX}_TRACE_STRUCTS) - set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_STRUCTS ON) - endif() + if(VERILATE_TRACE_STRUCTS) + list(APPEND VERILATOR_ARGS --trace-structs) + endif() + + foreach(INC ${VERILATE_INCLUDE_DIRS}) + list(APPEND VERILATOR_ARGS -y "${INC}") + endforeach() + + string(TOLOWER ${CMAKE_CXX_COMPILER_ID} COMPILER) + if(COMPILER STREQUAL "appleclang") + set(COMPILER clang) + elseif(NOT COMPILER MATCHES "^msvc$|^clang$") + set(COMPILER gcc) + endif() + + set(OBJCACHE "" CACHE STRING "Path for ccache, auto-detected if empty") + option(OBJCACHE_ENABLED "Compile Verilator with ccache" ON) + + if(OBJCACHE_ENABLED) + if(OBJCACHE STREQUAL "") + find_program(OBJCACHE_PATH ccache) + if(OBJCACHE_PATH STREQUAL "OBJCACHE_PATH-NOTFOUND") + set(OBJCACHE_PATH "") + endif() + else() + set(OBJCACHE_PATH "${OBJCACHE}") + endif() + if(NOT OBJCACHE_PATH STREQUAL "") + execute_process( + COMMAND "${OBJCACHE_PATH}" --version + OUTPUT_VARIABLE objcache_version + ) + string( + REGEX MATCH + "[^\n\r]+" + objcache_version + "${objcache_version}" + ) + message( + STATUS + "Found ccache: ${OBJCACHE_PATH} (\"${objcache_version}\")" + ) + set(CMAKE_CXX_COMPILER_LAUNCHER "${OBJCACHE_PATH}") + endif() + endif() + + get_target_property(BINARY_DIR "${TARGET}" BINARY_DIR) + get_target_property(TARGET_NAME "${TARGET}" NAME) + set(VDIR + "${BINARY_DIR}/CMakeFiles/${TARGET_NAME}.dir/${VERILATE_PREFIX}.dir" + ) + + if(VERILATE_DIRECTORY) + set(VDIR "${VERILATE_DIRECTORY}") + endif() + + file(MAKE_DIRECTORY ${VDIR}) + + set(VERILATOR_COMMAND + "${CMAKE_COMMAND}" + -E + env + "VERILATOR_ROOT=${VERILATOR_ROOT}" + "${VERILATOR_BIN}" + --compiler + ${COMPILER} + --prefix + ${VERILATE_PREFIX} + --Mdir + ${VDIR} + --make + cmake + ${VERILATOR_ARGS} + ${VERILATE_VERILATOR_ARGS} + ${VERILATE_SOURCES} + ) + + set(VARGS_FILE "${VDIR}/verilator_args.txt") + set(VCMAKE "${VDIR}/${VERILATE_PREFIX}.cmake") + set(VCMAKE_COPY "${VDIR}/${VERILATE_PREFIX}_copy.cmake") + + if(NOT EXISTS "${VARGS_FILE}" OR NOT EXISTS "${VCMAKE_COPY}") + set(VERILATOR_OUTDATED ON) + else() + file(READ "${VARGS_FILE}" PREVIOUS_VERILATOR_COMMAND) + if(NOT VERILATOR_COMMAND STREQUAL PREVIOUS_VERILATOR_COMMAND) + set(VERILATOR_OUTDATED ON) + endif() + endif() + + if(VERILATOR_OUTDATED) + message(STATUS "Executing Verilator...") + execute_process( + COMMAND ${VERILATOR_COMMAND} + WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" + RESULT_VARIABLE _VERILATOR_RC + OUTPUT_VARIABLE _VERILATOR_OUTPUT + ERROR_VARIABLE _VERILATOR_OUTPUT + ) + if(_VERILATOR_RC) + string( + REPLACE + ";" + " " + VERILATOR_COMMAND_READABLE + "${VERILATOR_COMMAND}" + ) + message("Verilator command: \"${VERILATOR_COMMAND_READABLE}\"") + message("Output:\n${_VERILATOR_OUTPUT}") + message( + FATAL_ERROR + "Verilator command failed (return code=${_VERILATOR_RC})" + ) + endif() + execute_process( + COMMAND "${CMAKE_COMMAND}" -E copy "${VCMAKE}" "${VCMAKE_COPY}" + ) + endif() + file(WRITE "${VARGS_FILE}" "${VERILATOR_COMMAND}") + + include("${VCMAKE_COPY}") + + set(GENERATED_C_SOURCES + ${${VERILATE_PREFIX}_CLASSES_FAST} + ${${VERILATE_PREFIX}_CLASSES_SLOW} + ${${VERILATE_PREFIX}_SUPPORT_FAST} + ${${VERILATE_PREFIX}_SUPPORT_SLOW} + ) + # No need for .h's as the .cpp will get written same time + set(GENERATED_SOURCES ${GENERATED_C_SOURCES}) + + add_custom_command( + OUTPUT ${GENERATED_SOURCES} "${VCMAKE}" + COMMAND ${VERILATOR_COMMAND} + WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" + DEPENDS "${VERILATOR_BIN}" ${${VERILATE_PREFIX}_DEPS} + VERBATIM + ) + # Reconfigure if file list has changed + # (check contents rather than modified time to avoid unnecessary reconfiguration) + add_custom_command( + OUTPUT "${VCMAKE_COPY}" + COMMAND + "${CMAKE_COMMAND}" -E copy_if_different "${VCMAKE}" "${VCMAKE_COPY}" + DEPENDS "${VCMAKE}" + VERBATIM + ) + + if(${VERILATE_PREFIX}_COVERAGE) + # If any verilate() call specifies COVERAGE, define VM_COVERAGE in the final build + set_property(TARGET ${TARGET} PROPERTY VERILATOR_COVERAGE ON) + endif() + + if(${VERILATE_PREFIX}_TRACE_VCD) + # If any verilate() call specifies TRACE, define VM_TRACE in the final build + set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) + set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_VCD ON) + endif() + + if(${VERILATE_PREFIX}_TRACE_FST) + # If any verilate() call specifies TRACE_FST, define VM_TRACE_FST in the final build + set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) + set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_FST ON) + endif() + + if(${VERILATE_PREFIX}_SC) + # If any verilate() call specifies SYSTEMC, define VM_SC in the final build + set_property(TARGET ${TARGET} PROPERTY VERILATOR_SYSTEMC ON) + endif() + + if(${VERILATE_PREFIX}_TRACE_STRUCTS) + set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_STRUCTS ON) + endif() # Add the compile flags only on Verilated sources - target_include_directories(${TARGET} PUBLIC ${VDIR}) - target_sources(${TARGET} PRIVATE ${GENERATED_SOURCES} "${VCMAKE_COPY}" - ${${VERILATE_PREFIX}_GLOBAL} - ${${VERILATE_PREFIX}_USER_CLASSES}) - foreach(_VSOURCE ${VERILATE_SOURCES} ${${VERILATE_PREFIX}_DEPS}) - get_filename_component(_VSOURCE "${_VSOURCE}" ABSOLUTE BASE_DIR) - list(APPEND VHD_SOURCES "${_VSOURCE}") - endforeach() - target_sources(${TARGET} PRIVATE ${VHD_SOURCES}) - - # Add the compile flags only on Verilated sources - foreach(VSLOW ${${VERILATE_PREFIX}_CLASSES_SLOW} ${${VERILATE_PREFIX}_SUPPORT_SLOW}) - foreach(OPT_SLOW ${VERILATE_OPT_SLOW} ${${VERILATE_PREFIX}_USER_CFLAGS}) - set_property(SOURCE "${VSLOW}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_SLOW}") + target_include_directories(${TARGET} PUBLIC ${VDIR}) + target_sources( + ${TARGET} + PRIVATE + ${GENERATED_SOURCES} + "${VCMAKE_COPY}" + ${${VERILATE_PREFIX}_GLOBAL} + ${${VERILATE_PREFIX}_USER_CLASSES} + ) + foreach(_VSOURCE ${VERILATE_SOURCES} ${${VERILATE_PREFIX}_DEPS}) + get_filename_component(_VSOURCE "${_VSOURCE}" ABSOLUTE BASE_DIR) + list(APPEND VHD_SOURCES "${_VSOURCE}") endforeach() - endforeach() - foreach(VFAST ${${VERILATE_PREFIX}_CLASSES_FAST} ${${VERILATE_PREFIX}_SUPPORT_FAST}) - foreach(OPT_FAST ${VERILATE_OPT_FAST} ${${VERILATE_PREFIX}_USER_CFLAGS}) - set_property(SOURCE "${VFAST}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_FAST}") + target_sources(${TARGET} PRIVATE ${VHD_SOURCES}) + + # Add the compile flags only on Verilated sources + foreach( + VSLOW + ${${VERILATE_PREFIX}_CLASSES_SLOW} + ${${VERILATE_PREFIX}_SUPPORT_SLOW} + ) + foreach(OPT_SLOW ${VERILATE_OPT_SLOW} ${${VERILATE_PREFIX}_USER_CFLAGS}) + set_property( + SOURCE "${VSLOW}" + APPEND_STRING + PROPERTY COMPILE_FLAGS " ${OPT_SLOW}" + ) + endforeach() endforeach() - endforeach() - foreach(VGLOBAL ${${VERILATE_PREFIX}_GLOBAL}) - foreach(OPT_GLOBAL ${VERILATE_OPT_GLOBAL} ${${VERILATE_PREFIX}_USER_CFLAGS}) - set_property(SOURCE "${VGLOBAL}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_GLOBAL}") + foreach( + VFAST + ${${VERILATE_PREFIX}_CLASSES_FAST} + ${${VERILATE_PREFIX}_SUPPORT_FAST} + ) + foreach(OPT_FAST ${VERILATE_OPT_FAST} ${${VERILATE_PREFIX}_USER_CFLAGS}) + set_property( + SOURCE "${VFAST}" + APPEND_STRING + PROPERTY COMPILE_FLAGS " ${OPT_FAST}" + ) + endforeach() + endforeach() + foreach(VGLOBAL ${${VERILATE_PREFIX}_GLOBAL}) + foreach( + OPT_GLOBAL + ${VERILATE_OPT_GLOBAL} + ${${VERILATE_PREFIX}_USER_CFLAGS} + ) + set_property( + SOURCE "${VGLOBAL}" + APPEND_STRING + PROPERTY COMPILE_FLAGS " ${OPT_GLOBAL}" + ) + endforeach() endforeach() - endforeach() - target_include_directories(${TARGET} PUBLIC "${VERILATOR_ROOT}/include" - "${VERILATOR_ROOT}/include/vltstd") - target_compile_definitions(${TARGET} PRIVATE - VM_COVERAGE=$> - VM_SC=$> - VM_TRACE=$> - VM_TRACE_VCD=$> - VM_TRACE_FST=$> - ) + target_include_directories( + ${TARGET} + PUBLIC "${VERILATOR_ROOT}/include" "${VERILATOR_ROOT}/include/vltstd" + ) + target_compile_definitions( + ${TARGET} + PRIVATE + VM_COVERAGE=$> + VM_SC=$> + VM_TRACE=$> + VM_TRACE_VCD=$> + VM_TRACE_FST=$> + ) - target_link_libraries(${TARGET} PUBLIC - ${${VERILATE_PREFIX}_USER_LDLIBS} - ) + target_link_libraries(${TARGET} PUBLIC ${${VERILATE_PREFIX}_USER_LDLIBS}) - target_link_libraries(${TARGET} PUBLIC - ${VERILATOR_MT_CFLAGS} - ) + target_link_libraries(${TARGET} PUBLIC ${VERILATOR_MT_CFLAGS}) - target_compile_features(${TARGET} PRIVATE cxx_std_11) + target_compile_features(${TARGET} PRIVATE cxx_std_11) - if (${VERILATE_PREFIX}_TIMING) - check_cxx_compiler_flag(-fcoroutines-ts COROUTINES_TS_FLAG) - target_compile_options(${TARGET} PRIVATE $,-fcoroutines-ts,-fcoroutines>) - endif() + if(${VERILATE_PREFIX}_TIMING) + check_cxx_compiler_flag(-fcoroutines-ts COROUTINES_TS_FLAG) + target_compile_options( + ${TARGET} + PRIVATE + $,-fcoroutines-ts,-fcoroutines> + ) + endif() endfunction() function(_verilator_find_systemc) - if (NOT TARGET Verilator::systemc) - # Find SystemC include file "systemc.h" in the following order: - # 1. SYSTEMC_INCLUDE (environment) variable - # 2. SYSTEMC_ROOT (environment) variable - # 3. SYSTEMC (environment) variable - # 4. Use CMake module provided by SystemC installation - # (eventually requires CMAKE_PREFIX_PATH set) + if(NOT TARGET Verilator::systemc) + # Find SystemC include file "systemc.h" in the following order: + # 1. SYSTEMC_INCLUDE (environment) variable + # 2. SYSTEMC_ROOT (environment) variable + # 3. SYSTEMC (environment) variable + # 4. Use CMake module provided by SystemC installation + # (eventually requires CMAKE_PREFIX_PATH set) - find_path(SYSTEMC_INCLUDEDIR NAMES systemc.h - HINTS "${SYSTEMC_INCLUDE} " ENV SYSTEMC_INCLUDE) - find_path(SYSTEMC_INCLUDEDIR NAMES systemc.h - HINTS "${SYSTEMC_ROOT}" ENV SYSTEMC_ROOT - PATH_SUFFIXES include) - find_path(SYSTEMC_INCLUDEDIR NAMES systemc.h - HINTS "${SYSTEMC}" ENV SYSTEMC - PATH_SUFFIXES include) + find_path( + SYSTEMC_INCLUDEDIR + NAMES systemc.h + HINTS "${SYSTEMC_INCLUDE} " + ENV SYSTEMC_INCLUDE + ) + find_path( + SYSTEMC_INCLUDEDIR + NAMES systemc.h + HINTS "${SYSTEMC_ROOT}" + ENV SYSTEMC_ROOT + PATH_SUFFIXES include + ) + find_path( + SYSTEMC_INCLUDEDIR + NAMES systemc.h + HINTS "${SYSTEMC}" + ENV SYSTEMC + PATH_SUFFIXES include + ) - # Find SystemC library in the following order: - # 1. SYSTEMC_LIBDIR (environment) variable - # 2. SYSTEMC_ROOT (environment) variable - # 3. SYSTEMC (environment) variable - # 4. Use CMake module provided by SystemC installation - # (eventually requires CMAKE_PREFIX_PATH set) + # Find SystemC library in the following order: + # 1. SYSTEMC_LIBDIR (environment) variable + # 2. SYSTEMC_ROOT (environment) variable + # 3. SYSTEMC (environment) variable + # 4. Use CMake module provided by SystemC installation + # (eventually requires CMAKE_PREFIX_PATH set) - # Find SystemC using include and library paths - find_library(SYSTEMC_LIBRARY NAMES systemc - HINTS "${SYSTEMC_LIBDIR}" ENV SYSTEMC_LIBDIR) - find_library(SYSTEMC_LIBRARY NAMES systemc - HINTS "${SYSTEMC_ROOT}" ENV SYSTEMC_ROOT - PATH_SUFFIXES lib) - find_library(SYSTEMC_LIBRARY NAMES systemc - HINTS "${SYSTEMC}" ENV SYSTEMC - PATH_SUFFIXES lib) + # Find SystemC using include and library paths + find_library( + SYSTEMC_LIBRARY + NAMES systemc + HINTS "${SYSTEMC_LIBDIR}" + ENV SYSTEMC_LIBDIR + ) + find_library( + SYSTEMC_LIBRARY + NAMES systemc + HINTS "${SYSTEMC_ROOT}" + ENV SYSTEMC_ROOT + PATH_SUFFIXES lib + ) + find_library( + SYSTEMC_LIBRARY + NAMES systemc + HINTS "${SYSTEMC}" + ENV SYSTEMC + PATH_SUFFIXES lib + ) - if (SYSTEMC_INCLUDEDIR AND SYSTEMC_LIBRARY) - add_library(Verilator::systemc INTERFACE IMPORTED) - set_target_properties(Verilator::systemc - PROPERTIES - INTERFACE_INCLUDE_DIRECTORIES "${SYSTEMC_INCLUDEDIR}" - INTERFACE_LINK_LIBRARIES "${SYSTEMC_LIBRARY}") - return() + if(SYSTEMC_INCLUDEDIR AND SYSTEMC_LIBRARY) + add_library(Verilator::systemc INTERFACE IMPORTED) + set_target_properties( + Verilator::systemc + PROPERTIES + INTERFACE_INCLUDE_DIRECTORIES "${SYSTEMC_INCLUDEDIR}" + INTERFACE_LINK_LIBRARIES "${SYSTEMC_LIBRARY}" + ) + return() + endif() + + find_package(SystemCLanguage QUIET) + if(SystemCLanguage_FOUND) + add_library(Verilator::systemc INTERFACE IMPORTED) + set_target_properties( + Verilator::systemc + PROPERTIES INTERFACE_LINK_LIBRARIES "SystemC::systemc" + ) + return() + endif() + + message( + "SystemC not found. This can be fixed by doing either of the following steps:" + ) + message( + "- set the SYSTEMC_INCLUDE and SYSTEMC_LIBDIR (environment) variables; or" + ) + message("- set SYSTEMC_ROOT (environment) variable; or") + message("- set SYSTEMC (environment) variable; or") + message( + "- use the CMake module of your SystemC installation (may require CMAKE_PREFIX_PATH)" + ) + message(FATAL_ERROR "SystemC not found") endif() - - find_package(SystemCLanguage QUIET) - if (SystemCLanguage_FOUND) - add_library(Verilator::systemc INTERFACE IMPORTED) - set_target_properties(Verilator::systemc - PROPERTIES - INTERFACE_LINK_LIBRARIES "SystemC::systemc") - return() - endif() - - message("SystemC not found. This can be fixed by doing either of the following steps:") - message("- set the SYSTEMC_INCLUDE and SYSTEMC_LIBDIR (environment) variables; or") - message("- set SYSTEMC_ROOT (environment) variable; or") - message("- set SYSTEMC (environment) variable; or") - message("- use the CMake module of your SystemC installation (may require CMAKE_PREFIX_PATH)") - message(FATAL_ERROR "SystemC not found") - endif() endfunction() function(verilator_link_systemc TARGET) - _verilator_find_systemc() - target_link_libraries("${TARGET}" PUBLIC Verilator::systemc) - target_compile_options(${TARGET} PRIVATE $ENV{SYSTEMC_CXX_FLAGS} ${SYSTEMC_CXX_FLAGS}) + _verilator_find_systemc() + target_link_libraries("${TARGET}" PUBLIC Verilator::systemc) + target_compile_options( + ${TARGET} + PRIVATE $ENV{SYSTEMC_CXX_FLAGS} ${SYSTEMC_CXX_FLAGS} + ) endfunction() function(verilator_generate_key OUTPUT_VARIABLE) - execute_process(COMMAND ${VERILATOR_BIN} --generate-key - OUTPUT_VARIABLE KEY_VAL - RESULT_VARIABLE KEY_RET) - if (KEY_RET) - message(FATAL_ERROR "verilator --generate-key failed") - endif() - string(STRIP ${KEY_VAL} KEY_VAL) - set(${OUTPUT_VARIABLE} ${KEY_VAL} PARENT_SCOPE) + execute_process( + COMMAND ${VERILATOR_BIN} --generate-key + OUTPUT_VARIABLE KEY_VAL + RESULT_VARIABLE KEY_RET + ) + if(KEY_RET) + message(FATAL_ERROR "verilator --generate-key failed") + endif() + string(STRIP ${KEY_VAL} KEY_VAL) + set(${OUTPUT_VARIABLE} ${KEY_VAL} PARENT_SCOPE) endfunction()