diff --git a/Changes b/Changes
index ee05fe068..f8d31bf9e 100644
--- a/Changes
+++ b/Changes
@@ -14,6 +14,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix system compile flags injection. [Gianfranco Costamagna]
 
+****  Fix enum values not being sized based on parent, bug1442. [Dan Petrisko]
+
 
 * Verilator 4.016 2016-06-16
 
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index e133db637..f1d7ad678 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1406,8 +1406,8 @@ private:
         if (nodep->valuep()) {  // else the value will be assigned sequentially
             // Default type is int, but common to assign narrower values, so minwidth from value
             userIterateAndNext(nodep->valuep(), WidthVP(CONTEXT, PRELIM).p());
-            int mwidth = nodep->valuep()->widthMin();  // Value determines minwidth
-            nodep->dtypeChgWidth(nodep->width(), mwidth);
+            // Minwidth does not come from value, as spec says set based on parent
+            // and if we keep minwidth we'll consider it unsized which is incorrect
             iterateCheck(nodep, "Enum value", nodep->valuep(), CONTEXT, FINAL, nodep->dtypep(), EXTEND_EXP);
         }
     }
diff --git a/test_regress/t/t_enum_size.pl b/test_regress/t/t_enum_size.pl
new file mode 100755
index 000000000..6b3b15be5
--- /dev/null
+++ b/test_regress/t/t_enum_size.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_enum_size.v b/test_regress/t/t_enum_size.v
new file mode 100644
index 000000000..5fd56cae6
--- /dev/null
+++ b/test_regress/t/t_enum_size.v
@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   // verilator lint_off WIDTH
+   typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs;
+
+   typedef enum integer {UP=0, UW=1'b1} UNSIZED;
+   // verilator lint_on WIDTH
+
+   localparam LEN = 3;
+   localparam COL = 4;
+
+   localparam [59:0] SEQ = {LEN'(N), LEN'(E), LEN'(W), LEN'(P)
+                            ,LEN'(S), LEN'(E), LEN'(W), LEN'(P)
+                            ,LEN'(S), LEN'(N), LEN'(W), LEN'(P)
+                            ,LEN'(S), LEN'(N), LEN'(E), LEN'(P)
+                            ,LEN'(S), LEN'(N), LEN'(E), LEN'(W)};
+
+   bit [59:0] SE2 = {N, E, W, P
+                     ,S, E, W, P
+                     ,S, N, W, P
+                     ,S, N, E, P
+                     ,S, N, E, W};
+
+   initial begin
+      if (SEQ != 60'o32104210431043204321) $stop;
+      if (SE2 != 60'o32104210431043204321) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule