diff --git a/src/verilog.y b/src/verilog.y
index 08025f727..6af7811b6 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -325,7 +325,7 @@ int V3ParseGrammar::s_typeImpNum = 0;
 #define VARIO(type) \
     { GRAMMARP->m_varIO = VDirection::type; }
 // Set direction to default-input when detect inside an ANSI port list
-#define VARIOANSI(type) \
+#define VARIOANSI() \
     { \
         if (GRAMMARP->m_varIO == VDirection::NONE) VARIO(INPUT); \
     }