diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index f8c20a846..2196c9c2e 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -38,6 +38,7 @@ Jean Berniolles Jeremy Bennett John Coiner John Demme +Jonathan Drolet Josh Redford Julien Margetts Kaleb Barrett diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst index 53810b67e..d1231a314 100644 --- a/docs/guide/verilating.rst +++ b/docs/guide/verilating.rst @@ -360,7 +360,8 @@ Verilate in CMake verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name] [TRACE] [TRACE_FST] [SYSTEMC] [COVERAGE] [INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...] - [OPT_GLOBAL ..] [DIRECTORY dir] [VERILATOR_ARGS ...]) + [OPT_GLOBAL ..] [DIRECTORY dir] [THREADS num] + [TRACE_THREADS num] [VERILATOR_ARGS ...]) Lowercase and ... should be replaced with arguments, the uppercase parts delimit the arguments and can be passed in any order, or left out entirely @@ -429,6 +430,15 @@ SystemC include directories and link to the SystemC libraries. the SystemC library. This can be specified using the SYSTEMC_CXX_FLAGS environment variable. +.. describe:: THREADS + + Optional. Generated a multi-threaded model, same as "--threads". + +.. describe:: TRACE_THREADS + + Optional. Generated multi-threaded trace dumping, same as + "--trace-threads". + .. describe:: TOP_MODULE Optional. Sets the name of the top module. Defaults to the name of the diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp index e9097abde..288a576ec 100644 --- a/src/V3EmitCMake.cpp +++ b/src/V3EmitCMake.cpp @@ -113,6 +113,8 @@ class CMakeEmitter final { cmake_set_raw(*of, name + "_COVERAGE", v3Global.opt.coverage() ? "1" : "0"); *of << "# Threaded output mode? 0/1/N threads (from --threads)\n"; cmake_set_raw(*of, name + "_THREADS", cvtToStr(v3Global.opt.threads())); + *of << "# Threaded tracing output mode? 0/1/N threads (from --trace-threads)\n"; + cmake_set_raw(*of, name + "_TRACE_THREADS", cvtToStr(v3Global.opt.traceThreads())); *of << "# VCD Tracing output mode? 0/1 (from --trace)\n"; cmake_set_raw(*of, name + "_TRACE_VCD", (v3Global.opt.trace() && (v3Global.opt.traceFormat() == TraceFormat::VCD)) diff --git a/test_regress/CMakeLists.txt b/test_regress/CMakeLists.txt index 28a045961..413578a64 100644 --- a/test_regress/CMakeLists.txt +++ b/test_regress/CMakeLists.txt @@ -52,9 +52,10 @@ string(REGEX REPLACE "(^|;)--" "\\1-" getarg(TEST_VERILATOR_ARGS_NORM "-prefix" TEST_PREFIX) getarg(TEST_VERILATOR_ARGS_NORM "-threads" TEST_THREADS) +getarg(TEST_VERILATOR_ARGS_NORM "-trace-threads" TEST_TRACE_THREADS) # Strip unwanted args with 1 parameter -string(REGEX REPLACE "(^|;)--?(Mdir|make|prefix|threads);[^;]*" "" +string(REGEX REPLACE "(^|;)--?(Mdir|make|prefix|threads|trace-threads);[^;]*" "" TEST_VERILATOR_ARGS "${TEST_VERILATOR_ARGS}") # Strip unwanted args @@ -81,6 +82,9 @@ endif() if(TEST_THREADS) list(APPEND verilate_ARGS THREADS ${TEST_THREADS}) endif() +if(TEST_TRACE_THREADS) + list(APPEND verilate_ARGS TRACE_THREADS ${TEST_TRACE_THREADS}) +endif() if(TEST_SYSTEMC) list(APPEND verilate_ARGS SYSTEMC) endif() diff --git a/test_regress/t/t_trace_fst_cmake.out b/test_regress/t/t_trace_fst_cmake.out new file mode 100644 index 000000000..dde4f07e0 --- /dev/null +++ b/test_regress/t/t_trace_fst_cmake.out @@ -0,0 +1,1028 @@ +$date + Sun Apr 19 04:15:36 2020 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$var wire 1 ! clk $end +$var wire 5 " state $end +$scope module t $end +$var wire 1 ! clk $end +$var int 32 # cyc $end +$var logic 1 $ rstn $end +$var wire 5 " state $end +$var real_parameter 64 % fst_gparam_real $end +$var real_parameter 64 & fst_lparam_real $end +$var real 64 % fst_real $end +$var integer 32 ' fst_integer $end +$var bit 1 ( fst_bit $end +$var logic 1 ) fst_logic $end +$var int 32 * fst_int $end +$var shortint 16 + fst_shortint $end +$var longint 64 , fst_longint $end +$var byte 8 - fst_byte $end +$var parameter 32 . fst_parameter $end +$var parameter 32 / fst_lparam $end +$var supply0 1 0 fst_supply0 $end +$var supply1 1 1 fst_supply1 $end +$var tri0 1 2 fst_tri0 $end +$var tri1 1 3 fst_tri1 $end +$var tri 1 4 fst_tri $end +$var wire 1 5 fst_wire $end +$scope module test $end +$var wire 1 ! clk $end +$var wire 1 $ rstn $end +$var wire 5 " state $end +$var logic 5 6 state_w $end +$var logic 5 7 state_array(0) $end +$var logic 5 8 state_array(1) $end +$var logic 5 9 state_array(2) $end +$scope module unnamedblk2 $end +$var int 32 : i $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 ; i $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +b00000 " +b00000000000000000000000000000000 # +0$ +r1.23 % +r4.56 & +b00000000000000000000000000000000 ' +0( +0) +b00000000000000000000000000000000 * +b0000000000000000 + +b0000000000000000000000000000000000000000000000000000000000000000 , +b00000000 - +b00000000000000000000000001111011 . +b00000000000000000000000111001000 / +00 +11 +02 +13 +04 +05 +b00000 6 +b00000 7 +b00000 8 +b00000 9 +b00000000000000000000000000000000 : +b00000000000000000000000000000000 ; +#10 +b00000000000000000000000000000011 ; +b00001 9 +b00001 8 +b00001 7 +b10100 6 +b00000000000000000000000000000001 # +b00001 " +1! +#15 +0! +#20 +1! +b00000000000000000000000000000010 # +#25 +0! +#30 +1! +b00000000000000000000000000000011 # +#35 +0! +#40 +1! +b00000000000000000000000000000100 # +#45 +0! +#50 +1! +b00000000000000000000000000000101 # +#55 +0! +#60 +1! +b00000000000000000000000000000110 # +#65 +0! +#70 +1! +b00000000000000000000000000000111 # +#75 +0! +#80 +1! +b00000000000000000000000000001000 # +#85 +0! +#90 +1! +b00000000000000000000000000001001 # +#95 +0! +#100 +1! +b00000000000000000000000000001010 # +#105 +0! +#110 +1! +b00000000000000000000000000001011 # +1$ +#115 +0! +#120 +1! +b00000000000000000000000000001100 # +b01010 6 +b10100 9 +b00000000000000000000000000000010 : +#125 +0! +#130 +1! +b01010 9 +b00101 6 +b00000000000000000000000000001101 # +b10100 8 +#135 +0! +#140 +1! +b01010 8 +b00000000000000000000000000001110 # +b10110 6 +b00101 9 +b10100 " +b10100 7 +#145 +0! +#150 +1! +b01010 7 +b01010 " +b10110 9 +b01011 6 +b00000000000000000000000000001111 # +b00101 8 +#155 +0! +#160 +1! +b10110 8 +b00000000000000000000000000010000 # +b10001 6 +b01011 9 +b00101 " +b00101 7 +#165 +0! +#170 +1! +b10110 7 +b10110 " +b10001 9 +b11100 6 +b00000000000000000000000000010001 # +b01011 8 +#175 +0! +#180 +1! +b10001 8 +b00000000000000000000000000010010 # +b01110 6 +b11100 9 +b01011 " +b01011 7 +#185 +0! +#190 +1! +b10001 7 +b10001 " +b01110 9 +b00111 6 +b00000000000000000000000000010011 # +b11100 8 +#195 +0! +#200 +1! +b01110 8 +b00000000000000000000000000010100 # +b10111 6 +b00111 9 +b11100 " +b11100 7 +#205 +0! +#210 +1! +b01110 7 +b01110 " +b10111 9 +b11111 6 +b00000000000000000000000000010101 # +b00111 8 +#215 +0! +#220 +1! +b10111 8 +b00000000000000000000000000010110 # +b11011 6 +b11111 9 +b00111 " +b00111 7 +#225 +0! +#230 +1! +b10111 7 +b10111 " +b11011 9 +b11001 6 +b00000000000000000000000000010111 # +b11111 8 +#235 +0! +#240 +1! +b11011 8 +b00000000000000000000000000011000 # +b11000 6 +b11001 9 +b11111 " +b11111 7 +#245 +0! +#250 +1! +b11011 7 +b11011 " +b11000 9 +b01100 6 +b00000000000000000000000000011001 # +b11001 8 +#255 +0! +#260 +1! +b11000 8 +b00000000000000000000000000011010 # +b00110 6 +b01100 9 +b11001 " +b11001 7 +#265 +0! +#270 +1! +b11000 7 +b11000 " +b00110 9 +b00011 6 +b00000000000000000000000000011011 # +b01100 8 +#275 +0! +#280 +1! +b00110 8 +b00000000000000000000000000011100 # +b10101 6 +b00011 9 +b01100 " +b01100 7 +#285 +0! +#290 +1! +b00110 7 +b00110 " +b10101 9 +b11110 6 +b00000000000000000000000000011101 # +b00011 8 +#295 +0! +#300 +1! +b10101 8 +b00000000000000000000000000011110 # +b01111 6 +b11110 9 +b00011 " +b00011 7 +#305 +0! +#310 +1! +b10101 7 +b10101 " +b01111 9 +b10011 6 +b00000000000000000000000000011111 # +b11110 8 +#315 +0! +#320 +1! +b01111 8 +b00000000000000000000000000100000 # +b11101 6 +b10011 9 +b11110 " +b11110 7 +#325 +0! +#330 +1! +b01111 7 +b01111 " +b11101 9 +b11010 6 +b00000000000000000000000000100001 # +b10011 8 +#335 +0! +#340 +1! +b11101 8 +b00000000000000000000000000100010 # +b01101 6 +b11010 9 +b10011 " +b10011 7 +#345 +0! +#350 +1! +b11101 7 +b11101 " +b01101 9 +b10010 6 +b00000000000000000000000000100011 # +b11010 8 +#355 +0! +#360 +1! +b01101 8 +b00000000000000000000000000100100 # +b01001 6 +b10010 9 +b11010 " +b11010 7 +#365 +0! +#370 +1! +b01101 7 +b01101 " +b01001 9 +b10000 6 +b00000000000000000000000000100101 # +b10010 8 +#375 +0! +#380 +1! +b01001 8 +b00000000000000000000000000100110 # +b01000 6 +b10000 9 +b10010 " +b10010 7 +#385 +0! +#390 +1! +b01001 7 +b01001 " +b01000 9 +b00100 6 +b00000000000000000000000000100111 # +b10000 8 +#395 +0! +#400 +1! +b01000 8 +b00000000000000000000000000101000 # +b00010 6 +b00100 9 +b10000 " +b10000 7 +#405 +0! +#410 +1! +b01000 7 +b01000 " +b00010 9 +b00001 6 +b00000000000000000000000000101001 # +b00100 8 +#415 +0! +#420 +1! +b00010 8 +b00000000000000000000000000101010 # +b10100 6 +b00001 9 +b00100 " +b00100 7 +#425 +0! +#430 +1! +b00010 7 +b00010 " +b10100 9 +b01010 6 +b00000000000000000000000000101011 # +b00001 8 +#435 +0! +#440 +1! +b10100 8 +b00000000000000000000000000101100 # +b00101 6 +b01010 9 +b00001 " +b00001 7 +#445 +0! +#450 +1! +b10100 7 +b10100 " +b00101 9 +b10110 6 +b00000000000000000000000000101101 # +b01010 8 +#455 +0! +#460 +1! +b00101 8 +b00000000000000000000000000101110 # +b01011 6 +b10110 9 +b01010 " +b01010 7 +#465 +0! +#470 +1! +b00101 7 +b00101 " +b01011 9 +b10001 6 +b00000000000000000000000000101111 # +b10110 8 +#475 +0! +#480 +1! +b01011 8 +b00000000000000000000000000110000 # +b11100 6 +b10001 9 +b10110 " +b10110 7 +#485 +0! +#490 +1! +b01011 7 +b01011 " +b11100 9 +b01110 6 +b00000000000000000000000000110001 # +b10001 8 +#495 +0! +#500 +1! +b11100 8 +b00000000000000000000000000110010 # +b00111 6 +b01110 9 +b10001 " +b10001 7 +#505 +0! +#510 +1! +b11100 7 +b11100 " +b00111 9 +b10111 6 +b00000000000000000000000000110011 # +b01110 8 +#515 +0! +#520 +1! +b00111 8 +b00000000000000000000000000110100 # +b11111 6 +b10111 9 +b01110 " +b01110 7 +#525 +0! +#530 +1! +b00111 7 +b00111 " +b11111 9 +b11011 6 +b00000000000000000000000000110101 # +b10111 8 +#535 +0! +#540 +1! +b11111 8 +b00000000000000000000000000110110 # +b11001 6 +b11011 9 +b10111 " +b10111 7 +#545 +0! +#550 +1! +b11111 7 +b11111 " +b11001 9 +b11000 6 +b00000000000000000000000000110111 # +b11011 8 +#555 +0! +#560 +1! +b11001 8 +b00000000000000000000000000111000 # +b01100 6 +b11000 9 +b11011 " +b11011 7 +#565 +0! +#570 +1! +b11001 7 +b11001 " +b01100 9 +b00110 6 +b00000000000000000000000000111001 # +b11000 8 +#575 +0! +#580 +1! +b01100 8 +b00000000000000000000000000111010 # +b00011 6 +b00110 9 +b11000 " +b11000 7 +#585 +0! +#590 +1! +b01100 7 +b01100 " +b00011 9 +b10101 6 +b00000000000000000000000000111011 # +b00110 8 +#595 +0! +#600 +1! +b00011 8 +b00000000000000000000000000111100 # +b11110 6 +b10101 9 +b00110 " +b00110 7 +#605 +0! +#610 +1! +b00011 7 +b00011 " +b11110 9 +b01111 6 +b00000000000000000000000000111101 # +b10101 8 +#615 +0! +#620 +1! +b11110 8 +b00000000000000000000000000111110 # +b10011 6 +b01111 9 +b10101 " +b10101 7 +#625 +0! +#630 +1! +b11110 7 +b11110 " +b10011 9 +b11101 6 +b00000000000000000000000000111111 # +b01111 8 +#635 +0! +#640 +1! +b10011 8 +b00000000000000000000000001000000 # +b11010 6 +b11101 9 +b01111 " +b01111 7 +#645 +0! +#650 +1! +b10011 7 +b10011 " +b11010 9 +b01101 6 +b00000000000000000000000001000001 # +b11101 8 +#655 +0! +#660 +1! +b11010 8 +b00000000000000000000000001000010 # +b10010 6 +b01101 9 +b11101 " +b11101 7 +#665 +0! +#670 +1! +b11010 7 +b11010 " +b10010 9 +b01001 6 +b00000000000000000000000001000011 # +b01101 8 +#675 +0! +#680 +1! +b10010 8 +b00000000000000000000000001000100 # +b10000 6 +b01001 9 +b01101 " +b01101 7 +#685 +0! +#690 +1! +b10010 7 +b10010 " +b10000 9 +b01000 6 +b00000000000000000000000001000101 # +b01001 8 +#695 +0! +#700 +1! +b10000 8 +b00000000000000000000000001000110 # +b00100 6 +b01000 9 +b01001 " +b01001 7 +#705 +0! +#710 +1! +b10000 7 +b10000 " +b00100 9 +b00010 6 +b00000000000000000000000001000111 # +b01000 8 +#715 +0! +#720 +1! +b00100 8 +b00000000000000000000000001001000 # +b00001 6 +b00010 9 +b01000 " +b01000 7 +#725 +0! +#730 +1! +b00100 7 +b00100 " +b00001 9 +b10100 6 +b00000000000000000000000001001001 # +b00010 8 +#735 +0! +#740 +1! +b00001 8 +b00000000000000000000000001001010 # +b01010 6 +b10100 9 +b00010 " +b00010 7 +#745 +0! +#750 +1! +b00001 7 +b00001 " +b01010 9 +b00101 6 +b00000000000000000000000001001011 # +b10100 8 +#755 +0! +#760 +1! +b01010 8 +b00000000000000000000000001001100 # +b10110 6 +b00101 9 +b10100 " +b10100 7 +#765 +0! +#770 +1! +b01010 7 +b01010 " +b10110 9 +b01011 6 +b00000000000000000000000001001101 # +b00101 8 +#775 +0! +#780 +1! +b10110 8 +b00000000000000000000000001001110 # +b10001 6 +b01011 9 +b00101 " +b00101 7 +#785 +0! +#790 +1! +b10110 7 +b10110 " +b10001 9 +b11100 6 +b00000000000000000000000001001111 # +b01011 8 +#795 +0! +#800 +1! +b10001 8 +b00000000000000000000000001010000 # +b01110 6 +b11100 9 +b01011 " +b01011 7 +#805 +0! +#810 +1! +b10001 7 +b10001 " +b01110 9 +b00111 6 +b00000000000000000000000001010001 # +b11100 8 +#815 +0! +#820 +1! +b01110 8 +b00000000000000000000000001010010 # +b10111 6 +b00111 9 +b11100 " +b11100 7 +#825 +0! +#830 +1! +b01110 7 +b01110 " +b10111 9 +b11111 6 +b00000000000000000000000001010011 # +b00111 8 +#835 +0! +#840 +1! +b10111 8 +b00000000000000000000000001010100 # +b11011 6 +b11111 9 +b00111 " +b00111 7 +#845 +0! +#850 +1! +b10111 7 +b10111 " +b11011 9 +b11001 6 +b00000000000000000000000001010101 # +b11111 8 +#855 +0! +#860 +1! +b11011 8 +b00000000000000000000000001010110 # +b11000 6 +b11001 9 +b11111 " +b11111 7 +#865 +0! +#870 +1! +b11011 7 +b11011 " +b11000 9 +b01100 6 +b00000000000000000000000001010111 # +b11001 8 +#875 +0! +#880 +1! +b11000 8 +b00000000000000000000000001011000 # +b00110 6 +b01100 9 +b11001 " +b11001 7 +#885 +0! +#890 +1! +b11000 7 +b11000 " +b00110 9 +b00011 6 +b00000000000000000000000001011001 # +b01100 8 +#895 +0! +#900 +1! +b00110 8 +b00000000000000000000000001011010 # +b10101 6 +b00011 9 +b01100 " +b01100 7 +#905 +0! +#910 +1! +b00110 7 +b00110 " +b10101 9 +b11110 6 +b00000000000000000000000001011011 # +b00011 8 +#915 +0! +#920 +1! +b10101 8 +b00000000000000000000000001011100 # +b01111 6 +b11110 9 +b00011 " +b00011 7 +#925 +0! +#930 +1! +b10101 7 +b10101 " +b01111 9 +b10011 6 +b00000000000000000000000001011101 # +b11110 8 +#935 +0! +#940 +1! +b01111 8 +b00000000000000000000000001011110 # +b11101 6 +b10011 9 +b11110 " +b11110 7 +#945 +0! +#950 +1! +b01111 7 +b01111 " +b11101 9 +b11010 6 +b00000000000000000000000001011111 # +b10011 8 +#955 +0! +#960 +1! +b11101 8 +b00000000000000000000000001100000 # +b01101 6 +b11010 9 +b10011 " +b10011 7 +#965 +0! +#970 +1! +b11101 7 +b11101 " +b01101 9 +b10010 6 +b00000000000000000000000001100001 # +b11010 8 +#975 +0! +#980 +1! +b01101 8 +b00000000000000000000000001100010 # +b01001 6 +b10010 9 +b11010 " +b11010 7 +#985 +0! +#990 +1! +b01101 7 +b01101 " +b01001 9 +b10000 6 +b00000000000000000000000001100011 # +b10010 8 +#995 +0! +#1000 +1! +b01001 8 +b00000000000000000000000001100100 # +b01000 6 +b10000 9 +b10010 " +b10010 7 diff --git a/test_regress/t/t_trace_fst_cmake.pl b/test_regress/t/t_trace_fst_cmake.pl new file mode 100755 index 000000000..4a00d2fb6 --- /dev/null +++ b/test_regress/t/t_trace_fst_cmake.pl @@ -0,0 +1,27 @@ +#!/usr/bin/env perl +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } + +scenarios(vlt_all => 1); + +compile( + v_flags2 => ["--trace-fst"], + verilator_make_gmake => 0, + verilator_make_cmake => 1, +); + +execute( + check_finished => 1, +); + +fst_identical($Self->trace_filename, $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_trace_fst_cmake.v b/test_regress/t/t_trace_fst_cmake.v new file mode 100644 index 000000000..288ddadfc --- /dev/null +++ b/test_regress/t/t_trace_fst_cmake.v @@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + state, + // Inputs + clk + ); + + input clk; + + int cyc; + reg rstn; + output [4:0] state; + + parameter real fst_gparam_real = 1.23; + localparam real fst_lparam_real = 4.56; + real fst_real = 1.23; + integer fst_integer; + bit fst_bit; + logic fst_logic; + int fst_int; + shortint fst_shortint; + longint fst_longint; + byte fst_byte; + + parameter fst_parameter = 123; + localparam fst_lparam = 456; + supply0 fst_supply0; + supply1 fst_supply1; + tri0 fst_tri0; + tri1 fst_tri1; + tri fst_tri; + wire fst_wire; + + Test test (/*AUTOINST*/ + // Outputs + .state (state[4:0]), + // Inputs + .clk (clk), + .rstn (rstn)); + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + rstn <= ~'1; + end + else if (cyc<10) begin + rstn <= ~'1; + end + else if (cyc<90) begin + rstn <= ~'0; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + + +module Test ( + input clk, + input rstn, + output logic [4:0] state + ); + + logic [4:0] state_w; + logic [4:0] state_array [3]; + assign state = state_array[0]; + + always_comb begin + state_w[4] = state_array[2][0]; + state_w[3] = state_array[2][4]; + state_w[2] = state_array[2][3] ^ state_array[2][0]; + state_w[1] = state_array[2][2]; + state_w[0] = state_array[2][1]; + end + + always_ff @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 3; i++) + state_array[i] <= 'b1; + end + else begin + for (int i = 0; i < 2; i++) + state_array[i] <= state_array[i+1]; + state_array[2] <= state_w; + end + end + +endmodule diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in index cfd6ed2b2..f91fab2d1 100644 --- a/verilator-config.cmake.in +++ b/verilator-config.cmake.in @@ -83,6 +83,12 @@ define_property(TARGET FULL_DOCS "Verilator multithreading enabled" ) +define_property(TARGET + PROPERTY VERILATOR_TRACE_THREADED + BRIEF_DOCS "Verilator multithread tracing enabled" + FULL_DOCS "Verilator multithread tracing enabled" +) + define_property(TARGET PROPERTY VERILATOR_COVERAGE BRIEF_DOCS "Verilator coverage enabled" @@ -115,7 +121,7 @@ define_property(TARGET function(verilate TARGET) cmake_parse_arguments(VERILATE "COVERAGE;TRACE;TRACE_FST;SYSTEMC" - "PREFIX;TOP_MODULE;THREADS;DIRECTORY" + "PREFIX;TOP_MODULE;THREADS;TRACE_THREADS;DIRECTORY" "SOURCES;VERILATOR_ARGS;INCLUDE_DIRS;OPT_SLOW;OPT_FAST;OPT_GLOBAL" ${ARGN}) if (NOT VERILATE_SOURCES) @@ -136,6 +142,10 @@ function(verilate TARGET) list(APPEND VERILATOR_ARGS --threads ${VERILATE_THREADS}) endif() + if (VERILATE_TRACE_THREADS) + list(APPEND VERILATOR_ARGS --trace-threads ${VERILATE_TRACE_THREADS}) + endif() + if (VERILATE_COVERAGE) list(APPEND VERILATOR_ARGS --coverage) endif() @@ -240,6 +250,11 @@ function(verilate TARGET) set_property(TARGET ${TARGET} PROPERTY VERILATOR_THREADED ON) endif() + if (${VERILATE_PREFIX}_TRACE_THREADS) + # If any verilate() call specifies TRACE_THREADS, define VL_TRACE_THREADED in the final build + set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_THREADED ON) + endif() + if (${VERILATE_PREFIX}_COVERAGE) # If any verilate() call specifies COVERAGE, define VM_COVERAGE in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_COVERAGE ON) @@ -296,6 +311,7 @@ function(verilate TARGET) VM_COVERAGE=$> VM_SC=$> $<$>:VL_THREADED> + $<$>:VL_TRACE_THREADED> VM_TRACE=$> VM_TRACE_VCD=$> VM_TRACE_FST=$>