From 2bda43875de9adcfb7c992ae8e91cf82b65b8bc4 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 22 Mar 2012 21:02:38 -0400
Subject: [PATCH] Support += and -= in standard for loops, bug463.

---
 Changes                    |  2 ++
 src/verilog.y              |  8 ++------
 test_regress/t/t_gen_inc.v | 23 ++++++++++++++++++++++-
 3 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/Changes b/Changes
index f66ce5133..eed9bacd6 100644
--- a/Changes
+++ b/Changes
@@ -6,6 +6,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.833 devel
 
+***   Support += and -= in standard for loops, bug463. [Alex Solomatnikov]
+
 ****  Fix signed array warning, bug456. [Alex Solomatnikov]
 
 ****  Fix and document --gdb option, bug454. [Jeremy Bennett]
diff --git a/src/verilog.y b/src/verilog.y
index 427130742..4a7f8cb48 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2101,12 +2101,8 @@ for_stepE<nodep>:		// IEEE: for_step + empty
 	;
 
 for_step<nodep>:		// IEEE: for_step
-		varRefBase '=' expr			{ $$ = new AstAssign($2,$1,$3); }
-	|	yP_PLUSPLUS   varRefBase		{ $$ = new AstAssign($1,$2,new AstAdd ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))) }
-	|	yP_MINUSMINUS varRefBase		{ $$ = new AstAssign($1,$2,new AstSub ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))) }
-	|	varRefBase yP_PLUSPLUS			{ $$ = new AstAssign($2,$1,new AstAdd ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))) }
-	|	varRefBase yP_MINUSMINUS		{ $$ = new AstAssign($2,$1,new AstSub ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))) }
-	//UNSUP: List of steps
+	//UNSUP: List of steps, instead we keep it simple
+		genvar_iteration			{ $$ = $1; }
 	;
 
 //************************************************
diff --git a/test_regress/t/t_gen_inc.v b/test_regress/t/t_gen_inc.v
index e95644c9c..faa4d50d2 100644
--- a/test_regress/t/t_gen_inc.v
+++ b/test_regress/t/t_gen_inc.v
@@ -10,7 +10,10 @@ module t (/*AUTOARG*/
    input clk;
    integer 	cyc=0;
 
-   genvar g;
+   genvar 	g;
+   integer 	i;
+
+   reg [31:0] v;
 
    reg [31:0] gen_pre_PLUSPLUS = 32'h0;
    reg [31:0] gen_pre_MINUSMINUS = 32'h0;
@@ -85,6 +88,24 @@ module t (/*AUTOARG*/
 	 if (gen_SRIGHTEQ	!== 32'b00000000000000010000000000000000) $stop;
 	 if (gen_SSRIGHTEQ	!== 32'b00000000000000010000000000000000) $stop;
 `endif
+
+	 v=0; for (i=8; i<=16; ++i)  v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
+	 v=0; for (i=16; i>=8; --i)  v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
+	 v=0; for (i=8; i<=16; i++)  v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
+	 v=0; for (i=16; i>=8; i--)  v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
+	 v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
+	 v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
+`ifndef verilator //UNSUPPORTED
+	 v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
+	 v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
+	 v=0; for (i=15; i>8;  i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop;
+	 v=0; for (i=7; i>4;   i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop;
+	 v=0; for (i=1; i<=1;  i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop;
+	 v=0; for (i=7; i==7;  i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop;
+	 v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop;
+	 v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
+	 v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
+`endif
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end