diff --git a/src/verilog.y b/src/verilog.y
index bdf07ddb9..d11620541 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2209,7 +2209,7 @@ type_declaration<nodep>:	// ==IEEE: type_declaration
 			  AstNodeDType* dtp = GRAMMARP->createArray(refp, $4, true);
 			  $$ = GRAMMARP->createTypedef($<fl>5, *$5, $7, dtp, $6); }
 	//			//
-	|	yTYPEDEF id/*interface*/ '.' idAny/*type*/ idAny/*type*/ ';'
+	|	yTYPEDEF id/*interface*/ '.' idAny/*type*/ idAny/*type*/ dtypeAttrListE ';'
 			{ $$ = nullptr; BBUNSUP($1, "Unsupported: SystemVerilog 2005 typedef in this context"); }
 	//			// Allow redeclaring same typedef again
 	//			// Alternative is use of idAny below, but this will cause conflicts with ablve
diff --git a/test_regress/t/t_interface_typedef.out b/test_regress/t/t_interface_typedef.out
new file mode 100644
index 000000000..73fe2430f
--- /dev/null
+++ b/test_regress/t/t_interface_typedef.out
@@ -0,0 +1,7 @@
+%Error-UNSUPPORTED: t/t_interface_typedef.v:46:4: Unsupported: SystemVerilog 2005 typedef in this context
+   46 |    typedef ifc_if.struct_t struct_t;
+      |    ^~~~~~~
+%Error: t/t_interface_typedef.v:51:16: syntax error, unexpected IDENTIFIER
+   51 |       struct_t substruct;
+      |                ^~~~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_interface_typedef.pl b/test_regress/t/t_interface_typedef.pl
new file mode 100755
index 000000000..3a6c0a6d3
--- /dev/null
+++ b/test_regress/t/t_interface_typedef.pl
@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_typedef.v b/test_regress/t/t_interface_typedef.v
new file mode 100644
index 000000000..a8faecb9b
--- /dev/null
+++ b/test_regress/t/t_interface_typedef.v
@@ -0,0 +1,56 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+
+interface ifc
+  #(
+    parameter int unsigned WIDTH
+    ) ();
+   typedef struct {
+     logic [WIDTH-1:0] data;
+   } struct_t;
+endinterface
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   ifc #(10) i_ifc10();
+   ifc #(20) i_ifc20();
+
+   sub #(10) u_sub10 (.clk, .ifc_if(i_ifc10));
+   sub #(20) u_sub20 (.clk, .ifc_if(i_ifc20));
+
+   integer cyc = 1;
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==20) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule
+
+module sub #(
+     parameter int EXP_WIDTH)
+   (
+    input logic clk,
+    ifc ifc_if);
+   typedef ifc_if.struct_t struct_t;
+
+   wire [EXP_WIDTH-1:0] expval = '1;
+
+   initial begin
+      struct_t substruct;
+      substruct.data = '1;
+      `checkh(substruct.data, expval);
+   end
+
+endmodule