diff --git a/src/V3Ast.h b/src/V3Ast.h
index 32399dab9..9600daec7 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -1019,7 +1019,8 @@ public:
     static string encodeNumber(vlsint64_t numin);	// Encode number into internal C representation
     static string vcdName(const string& namein); // Name for printing out to vcd files
     string	prettyName() const { return prettyName(name()); }
-    string	prettyTypeName() const;			// "VARREF name" for error messages
+    string 	prettyTypeName() const;			// "VARREF" for error messages
+    virtual string prettyOperatorName() const { return "operator "+prettyTypeName(); }
     FileLine*	fileline() const { return m_fileline; }
     void	fileline(FileLine* fl) { m_fileline=fl; }
     bool	width1() const;
diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index 29354236c..8e11cf5b4 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -1003,6 +1003,8 @@ public:
     void	trace(bool flag) { m_trace=flag; }
     // METHODS
     virtual void name(const string& name) { m_name = name; }
+    virtual string directionName() const { return (isInout() ? "inout" : isInput() ? "input"
+						   : isOutput() ? "output" : varType().ascii()); }
     bool	isInput() const { return m_input; }
     bool	isOutput() const { return m_output; }
     bool	isInOnly() const { return m_input && !m_output; }
@@ -1294,6 +1296,9 @@ public:
     virtual const char* broken() const { BROKEN_RTN(m_modVarp && !m_modVarp->brokeExists()); return NULL; }
     virtual string name()	const { return m_name; }		// * = Pin name, ""=go by number
     virtual void name(const string& name) { m_name = name; }
+    virtual string prettyOperatorName() const { return modVarp()
+	    ? (modVarp()->directionName()+" port connection '"+modVarp()->prettyName()+"'")
+	    : "port connection"; }
     bool	dotStar()	const { return name() == ".*"; }	// Special fake name for .* connections until linked
     int		pinNum()	const { return m_pinNum; }
     void	exprp(AstNode* nodep) { addOp1p(nodep); }
@@ -2236,6 +2241,7 @@ struct AstFClose : public AstNodeStmt {
 };
 
 struct AstFOpen : public AstNodeStmt {
+    // Although a system function in IEEE, here a statement which sets the file pointer (MCD)
     AstFOpen(FileLine* fileline, AstNode* filep, AstNode* filenamep, AstNode* modep)
 	: AstNodeStmt (fileline) {
 	setOp1p(filep);
diff --git a/src/V3Error.h b/src/V3Error.h
index 8980c7282..c4b2349d3 100644
--- a/src/V3Error.h
+++ b/src/V3Error.h
@@ -272,12 +272,18 @@ template< class T> std::string cvtToStr (const T& t) {
 
 inline uint32_t cvtToHash(const void* vp) {
     // We can shove a 64 bit pointer into a 32 bit bucket
-    // On 32 bit systems, lower is always 0, but who cares?
+    // On 32-bit systems, lower is always 0, but who cares?
     union { const void* up; struct {uint32_t upper; uint32_t lower;} l;} u;
     u.l.upper=0; u.l.lower=0; u.up=vp;
     return u.l.upper^u.l.lower;
 }
 
+inline string ucfirst(const string& text) {
+    string out = text;
+    out[0] = toupper(out[0]);
+    return out;
+}
+
 //######################################################################
 
 class FileLine;
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index eb80833a2..2429561cb 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -196,11 +196,6 @@ public:
 	else if (nodep->castIface()) return "interface";
 	else return nodep->prettyTypeName();
     }
-    static string ucfirst(const string& text) {
-	string out = text;
-	out[0] = toupper(out[0]);
-	return out;
-    }
 
     VSymEnt* rootEntp() const { return m_syms.rootp(); }
     VSymEnt* dunitEntp() const { return m_dunitEntp; }
@@ -1467,9 +1462,9 @@ private:
 		    nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
 		    return;
 		}
-		nodep->v3error(LinkDotState::ucfirst(whatp)<<" not found: "<<nodep->prettyName());
+		nodep->v3error(ucfirst(whatp)<<" not found: "<<nodep->prettyName());
 	    } else if (!refp->isIO() && !refp->isParam() && !refp->isIfaceRef()) {
-		nodep->v3error(LinkDotState::ucfirst(whatp)<<" is not an in/out/inout/param/interface: "<<nodep->prettyName());
+		nodep->v3error(ucfirst(whatp)<<" is not an in/out/inout/param/interface: "<<nodep->prettyName());
 	    } else {
 		nodep->modVarp(refp);
 		if (refp->user5p() && refp->user5p()->castNode()!=nodep) {
diff --git a/src/V3Undriven.cpp b/src/V3Undriven.cpp
index 06636dfa8..36320fb0e 100644
--- a/src/V3Undriven.cpp
+++ b/src/V3Undriven.cpp
@@ -75,7 +75,7 @@ public:
 
 private:
     // METHODS
-    inline bool bitNumOk(int bit) const { return bit>=0 && (bit*FLAGS_PER_BIT < (int)m_flags.size()); }
+    inline bool bitNumOk(int bit) const { return (bit*FLAGS_PER_BIT < (int)m_flags.size()); }
     inline bool usedFlag(int bit) const { return m_usedWhole || m_flags[bit*FLAGS_PER_BIT + FLAG_USED]; }
     inline bool drivenFlag(int bit) const { return m_drivenWhole || m_flags[bit*FLAGS_PER_BIT + FLAG_DRIVEN]; }
     enum BitNamesWhich { BN_UNUSED, BN_UNDRIVEN, BN_BOTH };
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index abc6acee6..b97a0a7f4 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1765,7 +1765,7 @@ private:
 		} else {
 		    // Must be a error according to spec
 		    // (Because we need to know if to connect to one or all instants)
-		    nodep->v3error("Port connection "<<nodep->prettyName()<<" as part of a module instance array "
+		    nodep->v3error(ucfirst(nodep->prettyOperatorName())<<" as part of a module instance array"
 				   <<" requires "<<pinwidth<<" or "<<pinwidth*numInsts
 				   <<" bits, but connection's "<<nodep->exprp()->prettyTypeName()
 				   <<" generates "<<expwidth<<" bits.");
@@ -1774,8 +1774,8 @@ private:
 	    } else {
 		if (nodep->modVarp()->isTristate()) {
 		    if (pinwidth != expwidth) {
-			nodep->v3error("Unsupported: Port connection "<<nodep->prettyName()<<" to inout signal "
-				       <<" requires "<<pinwidth
+			nodep->v3error("Unsupported: "<<ucfirst(nodep->prettyOperatorName())
+				       <<" to inout signal requires "<<pinwidth
 				       <<" bits, but connection's "<<nodep->exprp()->prettyTypeName()
 				       <<" generates "<<expwidth<<" bits.");
 			// otherwise would need some mess to force both sides to proper size
@@ -1785,7 +1785,7 @@ private:
 		bool hiArray = nodep->exprp()->dtypep()->skipRefp()->castUnpackArrayDType();
 		bool loArray = nodep->modVarp()->dtypep()->skipRefp()->castUnpackArrayDType();
 		if (loArray != hiArray) {
-		    nodep->v3error("Illegal port connection '"<<nodep->prettyName()<<"',"
+		    nodep->v3error("Illegal "<<nodep->prettyOperatorName()<<","
 				   <<" mismatch between port which is"<<(hiArray?"":" not")<<" an array,"
 				   <<" and expression which is"<<(loArray?"":" not")<<" an array.");
 		    UINFO(1,"    Related lo: "<<nodep->exprp()->dtypep()->skipRefp()<<endl);
@@ -2500,7 +2500,7 @@ private:
 
 	if (bad && !ignoreWarn) {
 	    if (debug()>4) nodep->backp()->dumpTree(cout,"  back: ");
-	    nodep->v3warn(WIDTH,"Operator "<<nodep->prettyTypeName()
+	    nodep->v3warn(WIDTH,ucfirst(nodep->prettyOperatorName())
 			  <<" expects "<<expWidth
 			  <<(expWidth!=expWidthMin?" or "+cvtToStr(expWidthMin):"")
 			  <<" bits on the "<<side<<", but "<<side<<"'s "
@@ -2531,7 +2531,7 @@ private:
 	if (bad) {
 	    if (!ignoreWarn) {
 		if (debug()>4) nodep->backp()->dumpTree(cout,"  back: ");
-		nodep->v3warn(WIDTH,"Logical Operator "<<nodep->prettyTypeName()
+		nodep->v3warn(WIDTH,"Logical "<<nodep->prettyOperatorName()
 			      <<" expects 1 bit on the "<<side<<", but "<<side<<"'s "
 			      <<underp->prettyTypeName()<<" generates "<<underp->width()
 			      <<(underp->width()!=underp->widthMin()
@@ -2548,10 +2548,9 @@ private:
 	bool bad = widthBad(underp,expWidth,expWidth);
 	if (bad && fixAutoExtend(underp/*ref*/,expWidth)) bad=false;  // Changes underp
 	if (bad) {
-	    nodep->v3warn(WIDTH,(inputPin?"Input":"Output")
-			  <<" port connection "<<nodep->prettyName()
+	    nodep->v3warn(WIDTH,ucfirst(nodep->prettyOperatorName())
 			  <<" expects "<<expWidth
-			  <<" bits but connection's "
+			  <<" bits on the pin connection, but pin connection's "
 			  <<underp->prettyTypeName()<<" generates "<<underp->width()
 			  <<(underp->width()!=underp->widthMin()
 			     ?" or "+cvtToStr(underp->widthMin()):"")
diff --git a/test_regress/t/t_dist_fixme.pl b/test_regress/t/t_dist_fixme.pl
index 061f90226..bfd92c746 100755
--- a/test_regress/t/t_dist_fixme.pl
+++ b/test_regress/t/t_dist_fixme.pl
@@ -19,7 +19,7 @@ if (!-r "$root/.git") {
     my $files = `cd $root && git ls-files --exclude-standard`;
     print "ST $files\n" if $Debug;
     $files =~ s/\s+/ /g;
-    my $cmd = "cd $root && fgrep -n FIXME $files | sort | grep -v t_dist_fixme";
+    my $cmd = "cd $root && fgrep -n FIX"."ME $files | sort | grep -v t_dist_fixme";
     my $grep = `$cmd`;
     print "$grep\n";
     if ($grep ne "") {
@@ -27,7 +27,7 @@ if (!-r "$root/.git") {
 	foreach my $line (split /\n/, $grep) {
 	    $names{$1} = 1 if $line =~ /^([^:]+)/;
 	}
-	$Self->error("Files with FIXMEs: ",join(' ',sort keys %names));
+	$Self->error("Files with FIX"."MEs: ",join(' ',sort keys %names));
     }
 }
 
diff --git a/test_regress/t/t_inst_array_bad.pl b/test_regress/t/t_inst_array_bad.pl
index 7a5160b52..5e134d0ba 100755
--- a/test_regress/t/t_inst_array_bad.pl
+++ b/test_regress/t/t_inst_array_bad.pl
@@ -11,7 +11,7 @@ compile (
 	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
-q{%Error: t/t_inst_array_bad.v:\d+: Port connection __pinNumber2 as part of a module instance array  requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits.
+q{%Error: t/t_inst_array_bad.v:\d+: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits.
 %Error: Exiting due to.*},
 	 );
 
diff --git a/test_regress/t/t_inst_misarray_bad.pl b/test_regress/t/t_inst_misarray_bad.pl
index c5001a755..278edcd77 100755
--- a/test_regress/t/t_inst_misarray_bad.pl
+++ b/test_regress/t/t_inst_misarray_bad.pl
@@ -11,8 +11,8 @@ compile (
 	 verilator_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
-'%Error: t/t_inst_misarray_bad.v:\d+: Illegal port connection \'foo\', mismatch between port which is not an array, and expression which is an array.
-%Error: Exiting due to.*',
+q{%Error: t/t_inst_misarray_bad.v:\d+: Illegal input port connection 'foo', mismatch between port which is not an array, and expression which is an array.
+%Error: Exiting due to.*},
 	 );
 
 
diff --git a/test_regress/t/t_inst_overwide_bad.pl b/test_regress/t/t_inst_overwide_bad.pl
index d469afe72..4a2e845a6 100755
--- a/test_regress/t/t_inst_overwide_bad.pl
+++ b/test_regress/t/t_inst_overwide_bad.pl
@@ -16,11 +16,11 @@ compile (
 	 verilator_make_gcc=>0,
 	 fails=>$Self->{v3},
 	 expect=>
-q{%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection outy_w92 expects 92 bits but connection's VARREF 'outc_w30' generates 30 bits.
+q{%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits.
 %Warning-WIDTH: Use .* to disable this message.
-%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection outz_w22 expects 22 bits but connection's VARREF 'outd_w73' generates 73 bits.
-%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection inw_w31 expects 31 bits but connection's VARREF 'ina_w1' generates 1 bits.
-%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection inx_w11 expects 11 bits but connection's VARREF 'inb_w61' generates 61 bits.
+%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits.
+%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits.
+%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits.
 %Error: Exiting due to.*},
 	 );
 
diff --git a/test_regress/t/t_math_pow3.v b/test_regress/t/t_math_pow3.v
index 2ea68f740..be35aa254 100644
--- a/test_regress/t/t_math_pow3.v
+++ b/test_regress/t/t_math_pow3.v
@@ -3,14 +3,12 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2004 by Wilson Snyder.
 
-`ifdef VERILATOR
- `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
-`else
- `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
-`endif
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0)
 
 module t (/*AUTOARG*/);
 
+   bit fail;
+
    // IEEE says for ** the size is L(i).  Thus Icarus Verilog is wrong in sizing some of the below.
 
    initial begin
@@ -77,7 +75,8 @@ module t (/*AUTOARG*/);
       `checkh(( 8'sh3 ** -8'sh3),  8'h0 );  // 0  // NCVERILOG bug
 
 
-      $write("*-* All Finished *-*\n");
+      if (fail) $stop;
+      else $write("*-* All Finished *-*\n");
       $finish;
    end
 endmodule
diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_precedence.pl
index 94fb7ebdc..df1a10d7b 100755
--- a/test_regress/t/t_math_precedence.pl
+++ b/test_regress/t/t_math_precedence.pl
@@ -7,7 +7,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 
-!$Self->{vcs} or $Self->unsupported("VCS does ** wrong");
+#!$Self->{vcs} or $Self->unsupported("VCS does ** wrong, fixed in 2014");
 
 compile (
 	 );
diff --git a/test_regress/t/t_math_signed3.v b/test_regress/t/t_math_signed3.v
index 359d9b01a..c932ac376 100644
--- a/test_regress/t/t_math_signed3.v
+++ b/test_regress/t/t_math_signed3.v
@@ -35,6 +35,8 @@ module t (/*AUTOARG*/);
    reg signed [32:0] bug349_s;
    reg signed [32:0] bug349_u;
 
+   wire signed [1:0] sb11 = 2'sb11;
+
    wire [3:0] 	     subout_u;
    sub sub (.a(2'sb11), .z(subout_u));
    initial `checkh(subout_u, 4'b1111);
@@ -82,6 +84,11 @@ module t (/*AUTOARG*/);
 	default: $stop;
       endcase
 
+      case (sb11)
+	4'b1111: ;
+	default: $stop;
+      endcase
+
       $write("*-* All Finished *-*\n");
       $finish;
    end