From 2aa6a229ca8ac551e206c9efddc895987976975b Mon Sep 17 00:00:00 2001 From: Iztok Jeras Date: Tue, 21 Mar 2023 01:44:11 +0100 Subject: [PATCH] Change range order warning from LITENDIAN to ASCRANGE (#4010) --- docs/guide/exe_verilator.rst | 6 +- docs/guide/warnings.rst | 34 ++-- docs/spelling.txt | 1 + src/V3Ast.h | 12 +- src/V3AstInlines.h | 4 +- src/V3AstNodeDType.h | 6 +- src/V3AstNodeOther.h | 2 +- src/V3AstNodes.cpp | 2 +- src/V3Error.h | 15 +- src/V3Inst.cpp | 14 +- src/V3Slice.cpp | 13 +- src/V3SplitVar.cpp | 6 +- src/V3Undriven.cpp | 2 +- src/V3Width.cpp | 21 ++- src/V3WidthSel.cpp | 33 ++-- test_regress/t/t_array_backw_index_bad.out | 8 +- test_regress/t/t_array_packed_endian.v | 12 +- test_regress/t/t_array_packed_sysfunct.v | 108 +++++------ test_regress/t/t_array_packed_write_read.v | 168 +++++++++--------- test_regress/t/t_array_pattern_packed.v | 110 ++++++------ test_regress/t/t_array_pattern_unpacked.v | 2 +- test_regress/t/t_array_query.v | 4 +- test_regress/t/t_array_rev.v | 4 +- test_regress/t/t_clk_concat3.v | 2 +- test_regress/t/t_dist_warn_coverage.pl | 2 +- test_regress/t/t_foreach.v | 2 +- test_regress/t/t_inst_array_connect.v | 2 +- test_regress/t/t_interface_array_nocolon.v | 8 +- .../t/t_interface_array_nocolon_bad.out | 20 +-- .../t/t_interface_array_nocolon_bad.v | 2 +- test_regress/t/t_lib_prot.v | 4 +- test_regress/t/t_lib_prot_secret.v | 4 +- test_regress/t/t_lint_historical.v | 2 +- test_regress/t/t_mem_fifo.v | 4 +- test_regress/t/t_mem_first.v | 4 +- test_regress/t/t_mem_multidim.v | 4 +- test_regress/t/t_mem_multiwire.v | 4 +- test_regress/t/t_metacmt_onoff.out | 18 +- test_regress/t/t_metacmt_onoff.v | 2 +- test_regress/t/t_mod_interface_array1.v | 4 +- test_regress/t/t_mod_interface_array2.v | 2 +- test_regress/t/t_param_module.v | 2 +- test_regress/t/t_param_repl.v | 4 +- test_regress/t/t_select_ascending.pl | 21 +++ test_regress/t/t_select_ascending.v | 75 ++++++++ test_regress/t/t_select_bad_msb.out | 10 +- test_regress/t/t_select_bad_range4.out | 2 +- test_regress/t/t_select_little_pack.v | 2 +- test_regress/t/t_split_var_0.v | 24 +-- test_regress/t/t_struct_packed_sysfunct.v | 36 ++-- test_regress/t/t_struct_packed_value_list.v | 94 +++++----- test_regress/t/t_struct_packed_write_read.v | 106 +++++------ test_regress/t/t_sys_readmem.v | 4 +- ...tendian.out => t_trace_ascendingrange.out} | 0 ...litendian.pl => t_trace_ascendingrange.pl} | 2 +- ...e_litendian.v => t_trace_ascendingrange.v} | 0 ...fst.out => t_trace_ascendingrange_fst.out} | 0 ...n_fst.pl => t_trace_ascendingrange_fst.pl} | 4 +- ....out => t_trace_ascendingrange_fst_sc.out} | 0 ...sc.pl => t_trace_ascendingrange_fst_sc.pl} | 4 +- test_regress/t/t_trace_public.v | 4 +- test_regress/t/t_typedef_array.v | 4 +- test_regress/t/t_vpi_var.v | 4 +- test_regress/t/t_vpi_var2.v | 4 +- 64 files changed, 596 insertions(+), 487 deletions(-) create mode 100755 test_regress/t/t_select_ascending.pl create mode 100644 test_regress/t/t_select_ascending.v rename test_regress/t/{t_trace_litendian.out => t_trace_ascendingrange.out} (100%) rename test_regress/t/{t_trace_litendian.pl => t_trace_ascendingrange.pl} (92%) rename test_regress/t/{t_trace_litendian.v => t_trace_ascendingrange.v} (100%) rename test_regress/t/{t_trace_litendian_fst.out => t_trace_ascendingrange_fst.out} (100%) rename test_regress/t/{t_trace_litendian_fst.pl => t_trace_ascendingrange_fst.pl} (88%) rename test_regress/t/{t_trace_litendian_fst_sc.out => t_trace_ascendingrange_fst_sc.out} (100%) rename test_regress/t/{t_trace_litendian_fst_sc.pl => t_trace_ascendingrange_fst_sc.pl} (94%) diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 36ad7a6f4..604db0702 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -1514,9 +1514,9 @@ Summary: .. option:: -Wno-lint Disable all lint-related warning messages, and all style warnings. This is - equivalent to ``-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE + equivalent to ``-Wno-ALWCOMBORDER -Wno-ASCRANGE -Wno-BSSPACE -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASTCONST -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS - -Wno-IMPLICIT -Wno-IMPLICITSTATIC -Wno-LITENDIAN -Wno-PINCONNECTEMPTY + -Wno-IMPLICIT -Wno-IMPLICITSTATIC -Wno-PINCONNECTEMPTY -Wno-PINMISSING -Wno-STATICVAR -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSEDGENVAR -Wno-UNUSEDPARAM -Wno-UNUSEDSIGNAL -Wno-WIDTH`` plus the list shown for Wno-style. @@ -1554,7 +1554,7 @@ Summary: enabled), but do not affect style messages. This is equivalent to ``-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE -Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASTCONST -Wwarn-CASEWITHX -Wwarn-CMPCONST - -Wwarn-COLONPLUS -Wwarn-IMPLICIT -Wwarn-LITENDIAN + -Wwarn-COLONPLUS -Wwarn-IMPLICIT -Wwarn-ASCRANGE -Wwarn-PINMISSING -Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH``. .. option:: -Wwarn-style diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index 33763ec79..fe406c8a2 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -97,6 +97,24 @@ List Of Warnings simulate correctly. +.. option:: ASCRANGE + + .. TODO better example + + Warns that a packed vector is declared with ascending bit range + (i.e. [0:7]). Descending bit range is now the overwhelming standard, + and ascending ranges are now thus often due to simple oversight + instead of intent (a notable exception is the OpenPOWER code base). + + It also warns that an instance is declared with ascending range + (i.e. [0:7] or [7]) and is connected to an N-wide signal. + The bits will likely be in the reversed order from what people may expect + (i.e., instance [0] will connect to signal bit [N-1] not bit [0]). + + Ignoring this warning will only suppress the lint check; it will + simulate correctly. + + .. option:: ASSIGNDLY .. TODO better example @@ -850,18 +868,10 @@ List Of Warnings .. TODO better example - Warns that a packed vector is declared with big endian bit numbering - (i.e. [0:7]). Little endian bit numbering is now the overwhelming - standard, and big numbering is now thus often due to simple oversight - instead of intent. - - It also warns that an instance is declared with big endian range - (i.e. [0:7] or [7]) and is connected to an N-wide signal. - The bits will likely be backward from what people may expect - (i.e., instance [0] will connect to signal bit [N-1] not bit [0]). - - Ignoring this warning will only suppress the lint check; it will - simulate correctly. + The naming of this worning is in contradiction with the common + interpretation of little endian. It was therefore renamed to + :option:`ASCRANGE`. While :option:`LITENDIAN` remains for + backwards compatibility, new projects should use :option:`ASCRANGE`. .. option:: MINTYPMAX diff --git a/docs/spelling.txt b/docs/spelling.txt index 7d6a7c5d5..4f73b0a0e 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -532,6 +532,7 @@ endcelldefine endfunction endgenerate endian +endianness endif endmodule endprotect diff --git a/src/V3Ast.h b/src/V3Ast.h index cae837a51..ea3c1bb61 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -1097,21 +1097,21 @@ public: } // VNumRange() = default; - VNumRange(int hi, int lo, bool littleEndian) { init(hi, lo, littleEndian); } + VNumRange(int hi, int lo, bool ascending) { init(hi, lo, ascending); } VNumRange(int left, int right) : m_left{left} , m_right{right} , m_ranged{true} {} ~VNumRange() = default; // MEMBERS - void init(int hi, int lo, bool littleEndian) { + void init(int hi, int lo, bool ascending) { if (lo > hi) { const int t = hi; hi = lo; lo = t; } - m_left = littleEndian ? lo : hi; - m_right = littleEndian ? hi : lo; + m_left = ascending ? lo : hi; + m_right = ascending ? hi : lo; m_ranged = true; } int left() const { return m_left; } @@ -1122,10 +1122,10 @@ public: int lo() const VL_MT_SAFE { return m_left > m_right ? m_right : m_left; } // How to show a declaration - int leftToRightInc() const { return littleEndian() ? 1 : -1; } + int leftToRightInc() const { return ascending() ? 1 : -1; } int elements() const VL_MT_SAFE { return hi() - lo() + 1; } bool ranged() const { return m_ranged; } - bool littleEndian() const { return m_left < m_right; } + bool ascending() const { return m_left < m_right; } int hiMaxSelect() const { return (lo() < 0 ? hi() - lo() : hi()); } // Maximum value a [] select may index diff --git a/src/V3AstInlines.h b/src/V3AstInlines.h index 31bb603c9..9ca54f137 100644 --- a/src/V3AstInlines.h +++ b/src/V3AstInlines.h @@ -123,8 +123,8 @@ int AstBasicDType::lo() const { return (rangep() ? rangep()->loConst() : m.m_nra int AstBasicDType::elements() const { return (rangep() ? rangep()->elementsConst() : m.m_nrange.elements()); } -bool AstBasicDType::littleEndian() const { - return (rangep() ? rangep()->littleEndian() : m.m_nrange.littleEndian()); +bool AstBasicDType::ascending() const { + return (rangep() ? rangep()->ascending() : m.m_nrange.ascending()); } bool AstActive::hasClocked() const { return m_sensesp->hasClocked(); } diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h index 97eaacc5b..41c512617 100644 --- a/src/V3AstNodeDType.h +++ b/src/V3AstNodeDType.h @@ -468,9 +468,9 @@ public: inline int hi() const; inline int lo() const; inline int elements() const; - int left() const { return littleEndian() ? lo() : hi(); } // How to show a declaration - int right() const { return littleEndian() ? hi() : lo(); } - inline bool littleEndian() const; + int left() const { return ascending() ? lo() : hi(); } // How to show a declaration + int right() const { return ascending() ? hi() : lo(); } + inline bool ascending() const; bool implicit() const { return keyword() == VBasicDTypeKwd::LOGIC_IMPLICIT; } bool untyped() const { return keyword() == VBasicDTypeKwd::UNTYPED; } VNumRange declRange() const { return isRanged() ? VNumRange{left(), right()} : VNumRange{}; } diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index a37d2abe7..f137413fe 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -2349,7 +2349,7 @@ public: return l > r ? r : l; } int elementsConst() const VL_MT_STABLE { return hiConst() - loConst() + 1; } - bool littleEndian() const { return leftConst() < rightConst(); } + bool ascending() const { return leftConst() < rightConst(); } void dump(std::ostream& str) const override; virtual string emitC() { V3ERROR_NA_RETURN(""); } bool same(const AstNode* /*samep*/) const override { return true; } diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 0e09698e0..d9b8146ab 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -1759,7 +1759,7 @@ void AstTypedef::dump(std::ostream& str) const { void AstNodeRange::dump(std::ostream& str) const { this->AstNode::dump(str); } void AstRange::dump(std::ostream& str) const { this->AstNodeRange::dump(str); - if (littleEndian()) str << " [LITTLE]"; + if (ascending()) str << " [ASCENDING]"; } void AstParamTypeDType::dump(std::ostream& str) const { this->AstNodeDType::dump(str); diff --git a/src/V3Error.h b/src/V3Error.h index 43ab1b696..b63dfdf2d 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -70,6 +70,7 @@ public: EC_FIRST_WARN, // Just a code so the program knows where to start warnings // ALWCOMBORDER, // Always_comb with unordered statements + ASCRANGE, // Ascending bit range vector ASSIGNDLY, // Assignment delays ASSIGNIN, // Assigning to input BADSTDPRAGMA, // Any error related to pragmas @@ -109,7 +110,7 @@ public: INITIALDLY, // Initial delayed statement INSECURE, // Insecure options LATCH, // Latch detected outside of always_latch block - LITENDIAN, // Little bit endian vector + LITENDIAN, // Little endian, renamed to ASCRANGE MINTYPMAXDLY, // Unsupported: min/typ/max delay expressions MODDUP, // Duplicate module MULTIDRIVEN, // Driven from multiple blocks @@ -183,7 +184,7 @@ public: "PORTSHORT", "UNSUPPORTED", "TASKNSVAR", "NEEDTIMINGOPT", "NOTIMING", // Warnings " EC_FIRST_WARN", - "ALWCOMBORDER", "ASSIGNDLY", "ASSIGNIN", "BADSTDPRAGMA", + "ALWCOMBORDER", "ASCRANGE", "ASSIGNDLY", "ASSIGNIN", "BADSTDPRAGMA", "BLKANDNBLK", "BLKLOOPINIT", "BLKSEQ", "BSSPACE", "CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CASTCONST", "CDCRSTLOGIC", "CLKDATA", "CMPCONST", "COLONPLUS", "COMBDLY", "CONTASSREG", @@ -228,12 +229,12 @@ public: } // Warnings that are lint only bool lintError() const VL_MT_SAFE { - return (m_e == ALWCOMBORDER || m_e == BSSPACE || m_e == CASEINCOMPLETE + return (m_e == ALWCOMBORDER || m_e == ASCRANGE || m_e == BSSPACE || m_e == CASEINCOMPLETE || m_e == CASEOVERLAP || m_e == CASEWITHX || m_e == CASEX || m_e == CASTCONST || m_e == CMPCONST || m_e == COLONPLUS || m_e == IMPLICIT || m_e == IMPLICITSTATIC - || m_e == LATCH || m_e == LITENDIAN || m_e == PINMISSING || m_e == REALCVT - || m_e == STATICVAR || m_e == UNSIGNED || m_e == WIDTH || m_e == WIDTHTRUNC - || m_e == WIDTHEXPAND || m_e == WIDTHXZEXPAND); + || m_e == LATCH || m_e == PINMISSING || m_e == REALCVT || m_e == STATICVAR + || m_e == UNSIGNED || m_e == WIDTH || m_e == WIDTHTRUNC || m_e == WIDTHEXPAND + || m_e == WIDTHXZEXPAND); } // Warnings that are style only bool styleError() const VL_MT_SAFE { @@ -251,7 +252,7 @@ public: V3ErrorCode renamedTo() const { // Return a new error this error has been renamed to - // e.g. if (m_e == LITENDIAN) return V3ErrorCode{RANGEASC}; + if (m_e == LITENDIAN) return V3ErrorCode{ASCRANGE}; return V3ErrorCode{EC_MIN}; // Not renamed; see isRenamed() } bool isRenamed() const { return renamedTo() != V3ErrorCode{EC_MIN}; } diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index 02db2fd98..74fe5d504 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -252,7 +252,7 @@ private: // Make all of the required clones for (int i = 0; i < m_cellRangep->elementsConst(); i++) { m_instSelNum - = m_cellRangep->littleEndian() ? (m_cellRangep->elementsConst() - 1 - i) : i; + = m_cellRangep->ascending() ? (m_cellRangep->elementsConst() - 1 - i) : i; const int instNum = m_cellRangep->loConst() + i; AstCell* const newp = nodep->cloneTree(false); @@ -331,7 +331,7 @@ private: // Connection to array, where array dimensions match the instant dimension const AstRange* const rangep = VN_AS(nodep->exprp()->dtypep(), UnpackArrayDType)->rangep(); - const int arraySelNum = rangep->littleEndian() + const int arraySelNum = rangep->ascending() ? (rangep->elementsConst() - 1 - m_instSelNum) : m_instSelNum; AstNodeExpr* exprp = VN_AS(nodep->exprp(), NodeExpr)->unlinkFrBack(); @@ -342,11 +342,11 @@ private: } else if (expwidth == modwidth * m_cellRangep->elementsConst()) { // Arrayed instants: one bit for each of the instants (each // assign is 1 modwidth wide) - if (m_cellRangep->littleEndian()) { - nodep->exprp()->v3warn(LITENDIAN, "Big endian instance range connecting to " - "vector: left < right of instance range: [" - << m_cellRangep->leftConst() << ":" - << m_cellRangep->rightConst() << "]"); + if (m_cellRangep->ascending()) { + nodep->exprp()->v3warn(ASCRANGE, "Ascending instance range connecting to " + "vector: left < right of instance range: [" + << m_cellRangep->leftConst() << ":" + << m_cellRangep->rightConst() << "]"); } AstNodeExpr* exprp = VN_AS(nodep->exprp(), NodeExpr)->unlinkFrBack(); const bool inputPin = nodep->modVarp()->isNonOutput(); diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp index 17ad58852..4c5a392cd 100644 --- a/src/V3Slice.cpp +++ b/src/V3Slice.cpp @@ -90,7 +90,7 @@ class SliceVisitor final : public VNVisitor { AstNodeExpr* newp; if (const AstInitArray* const initp = VN_CAST(nodep, InitArray)) { UINFO(9, " cloneInitArray(" << elements << "," << offset << ") " << nodep << endl); - const int leOffset = !arrayp->rangep()->littleEndian() + const int leOffset = !arrayp->rangep()->ascending() ? arrayp->rangep()->elementsConst() - 1 - offset : offset; AstNodeExpr* const itemp = initp->getIndexDefaultedValuep(leOffset); @@ -107,14 +107,14 @@ class SliceVisitor final : public VNVisitor { } else if (const AstSliceSel* const snodep = VN_CAST(nodep, SliceSel)) { UINFO(9, " cloneSliceSel(" << elements << "," << offset << ") " << nodep << endl); const int leOffset = (snodep->declRange().lo() - + (!snodep->declRange().littleEndian() + + (!snodep->declRange().ascending() ? snodep->declRange().elements() - 1 - offset : offset)); newp = new AstArraySel{nodep->fileline(), snodep->fromp()->cloneTree(false), leOffset}; } else if (VN_IS(nodep, ArraySel) || VN_IS(nodep, NodeVarRef) || VN_IS(nodep, NodeSel) || VN_IS(nodep, CMethodHard) || VN_IS(nodep, MemberSel)) { UINFO(9, " cloneSel(" << elements << "," << offset << ") " << nodep << endl); - const int leOffset = !arrayp->rangep()->littleEndian() + const int leOffset = !arrayp->rangep()->ascending() ? arrayp->rangep()->elementsConst() - 1 - offset : offset; newp = new AstArraySel{nodep->fileline(), VN_AS(nodep, NodeExpr)->cloneTree(false), @@ -139,9 +139,10 @@ class SliceVisitor final : public VNVisitor { if (debug() >= 9) nodep->dumpTree("- Deslice-In: "); AstNodeDType* const dtp = nodep->lhsp()->dtypep()->skipRefp(); if (const AstUnpackArrayDType* const arrayp = VN_CAST(dtp, UnpackArrayDType)) { - // Left and right could have different msb/lsbs/endianness, but #elements is common - // and all variables are realigned to start at zero - // Assign of a little endian'ed slice to a big endian one must reverse the elements + // Left and right could have different ascending/descending range, + // but #elements is common and all variables are realigned to start at zero + // Assign of an ascending range slice to a descending range one must reverse the + // elements AstNodeAssign* newlistp = nullptr; const int elements = arrayp->rangep()->elementsConst(); for (int offset = 0; offset < elements; ++offset) { diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp index 43af5a4a2..4550ee310 100644 --- a/src/V3SplitVar.cpp +++ b/src/V3SplitVar.cpp @@ -591,7 +591,7 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl { // restore the original decl range here. const VNumRange selRange{nodep->declRange().hi() + dtypep->declRange().lo(), nodep->declRange().lo() + dtypep->declRange().lo(), - nodep->declRange().littleEndian()}; + nodep->declRange().ascending()}; UASSERT_OBJ(dtypep->lo() <= selRange.lo() && selRange.hi() <= dtypep->hi(), nodep, "Range check for AstSliceSel must have been finished in V3Width.cpp"); UINFO(4, "add " << nodep << " for " << refp->varp()->prettyName() << "\n"); @@ -1071,7 +1071,7 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl { for (SplitNewVar& newvar : vars) { int left = newvar.msb(); int right = newvar.lsb(); - if (basicp->littleEndian()) std::swap(left, right); + if (basicp->ascending()) std::swap(left, right); const std::string name = (left == right) ? varp->name() + "__BRA__" + AstNode::encodeNumber(left) + "__KET__" @@ -1091,7 +1091,7 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl { default: UASSERT_OBJ(false, basicp, "Only bit and logic are allowed"); } dtypep->rangep(new AstRange{ - varp->fileline(), VNumRange{newvar.msb(), newvar.lsb(), basicp->littleEndian()}}); + varp->fileline(), VNumRange{newvar.msb(), newvar.lsb(), basicp->ascending()}}); newvar.varp(new AstVar{varp->fileline(), VVarType::VAR, name, dtypep}); newvar.varp()->propagateAttrFrom(varp); newvar.varp()->funcLocal(varp->isFuncLocal() || varp->isFuncReturn()); diff --git a/src/V3Undriven.cpp b/src/V3Undriven.cpp index af60b39a0..84e7aba35 100644 --- a/src/V3Undriven.cpp +++ b/src/V3Undriven.cpp @@ -101,7 +101,7 @@ private: if (lsb == msb) { bits += cvtToStr(lsb + bdtypep->lo()); } else { - if (bdtypep->littleEndian()) { + if (bdtypep->ascending()) { bits += cvtToStr(lsb + bdtypep->lo()) + ":" + cvtToStr(msb + bdtypep->lo()); } else { diff --git a/src/V3Width.cpp b/src/V3Width.cpp index d6fde7ff4..726b209a4 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -858,11 +858,11 @@ private: << std::hex << width); } // Note width() not set on range; use elementsConst() - if (nodep->littleEndian() && !VN_IS(nodep->backp(), UnpackArrayDType) + if (nodep->ascending() && !VN_IS(nodep->backp(), UnpackArrayDType) && !VN_IS(nodep->backp(), Cell)) { // For cells we warn in V3Inst - nodep->v3warn(LITENDIAN, "Big bit endian vector: left < right of bit range: [" - << nodep->leftConst() << ":" << nodep->rightConst() - << "]"); + nodep->v3warn(ASCRANGE, "Ascending bit range vector: left < right of bit range: [" + << nodep->leftConst() << ":" << nodep->rightConst() + << "]"); } } } @@ -1101,18 +1101,18 @@ private: // Add subtracted value to get the original range const VNumRange declRange{nodep->declRange().hi() + subtracted, nodep->declRange().lo() + subtracted, - nodep->declRange().littleEndian()}; + nodep->declRange().ascending()}; if ((declRange.hi() > adtypep->declRange().hi()) || declRange.lo() < adtypep->declRange().lo()) { // Other simulators warn too nodep->v3error("Slice selection index '" << declRange << "'" << " outside data type's '" << adtypep->declRange() << "'"); - } else if ((declRange.littleEndian() != adtypep->declRange().littleEndian()) + } else if ((declRange.ascending() != adtypep->declRange().ascending()) && declRange.hi() != declRange.lo()) { nodep->v3error("Slice selection '" << declRange << "'" - << " has backward indexing versus data type's '" + << " has reversed range order versus data type's '" << adtypep->declRange() << "'"); } } @@ -6351,9 +6351,8 @@ private: constp->fileline(), lhsDTypep, new AstConst{constp->fileline(), AstConst::WidthedValue{}, 8, 0}}; for (int aindex = arrayp->lo(); aindex <= arrayp->hi(); ++aindex) { - int cindex = arrayp->declRange().littleEndian() - ? (arrayp->hi() - aindex) - : (aindex - arrayp->lo()); + int cindex = arrayp->declRange().ascending() ? (arrayp->hi() - aindex) + : (aindex - arrayp->lo()); V3Number selected{constp, 8}; selected.opSel(constp->num(), cindex * 8 + 7, cindex * 8); UINFO(0, " aindex=" << aindex << " cindex=" << cindex @@ -6970,7 +6969,7 @@ private: case VAttrType::DIM_LOW: val = !declRange.ranged() ? 0 : declRange.lo(); break; case VAttrType::DIM_RIGHT: val = !declRange.ranged() ? 0 : declRange.right(); break; case VAttrType::DIM_INCREMENT: - val = (declRange.ranged() && declRange.littleEndian()) ? -1 : 1; + val = (declRange.ranged() && declRange.ascending()) ? -1 : 1; break; case VAttrType::DIM_SIZE: val = !declRange.ranged() ? 0 : declRange.elements(); break; default: nodep->v3fatalSrc("Missing DIM ATTR type case"); break; diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp index 20b2741b7..a4a1628b3 100644 --- a/src/V3WidthSel.cpp +++ b/src/V3WidthSel.cpp @@ -19,7 +19,7 @@ // Replace SELEXTRACT with SEL // Replace SELBIT with SEL or ARRAYSEL // -// This code was once in V3LinkResolve, but little endian bit vectors won't +// This code was once in V3LinkResolve, but ascending bit range vectors won't // work that early. It was considered for V3Width and V3Param, but is // fairly ugly both places as the nodes change in too strongly // interconnected ways. @@ -162,7 +162,7 @@ private: // vector without range, or 0 lsb is ok, for example a INTEGER x; y = x[21:0]; return underp; } else { - if (fromRange.littleEndian()) { + if (fromRange.ascending()) { // reg [1:3] was swapped to [3:1] (lsbEndianedp==3) and needs a SUB(3,under) return newSubNeg(fromRange.hi(), underp); } else { @@ -180,7 +180,7 @@ private: } else { // Need a slice data type, which is an array of the extracted // type, but with (presumably) different size - const VNumRange newRange{msb, lsb, nodep->declRange().littleEndian()}; + const VNumRange newRange{msb, lsb, nodep->declRange().ascending()}; AstNodeDType* const vardtypep = new AstPackArrayDType{nodep->fileline(), nodep->subDTypep(), // Need to strip off array reference @@ -227,7 +227,7 @@ private: } else if (const AstPackArrayDType* const adtypep = VN_CAST(ddtypep, PackArrayDType)) { // SELBIT(array, index) -> SEL(array, index*width-of-subindex, width-of-subindex) AstNodeExpr* subp = rhsp; - if (fromRange.littleEndian()) { + if (fromRange.ascending()) { subp = newSubNeg(fromRange.hi(), subp); } else { subp = newSubNeg(subp, fromRange.lo()); @@ -375,8 +375,8 @@ private: adtypep, "Array extraction with width miscomputed " << adtypep->width() << "/" << fromRange.elements()); - if (fromRange.littleEndian()) { - // Below code assumes big bit endian; just works out if we swap + if (fromRange.ascending()) { + // Below code assumes descending bit range; just works out if we swap const int x = msb; msb = lsb; lsb = x; @@ -385,7 +385,7 @@ private: nodep->v3warn( SELRANGE, "[" << msb << ":" << lsb - << "] Range extract has backward bit ordering, perhaps you wanted [" << lsb + << "] Slice range has ascending bit ordering, perhaps you wanted [" << lsb << ":" << msb << "]"); const int x = msb; msb = lsb; @@ -405,8 +405,8 @@ private: nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); } else if (VN_IS(ddtypep, BasicDType)) { - if (fromRange.littleEndian()) { - // Below code assumes big bit endian; just works out if we swap + if (fromRange.ascending()) { + // Below code assumes descending bit range; just works out if we swap const int x = msb; msb = lsb; lsb = x; @@ -415,7 +415,7 @@ private: nodep->v3warn( SELRANGE, "[" << msb << ":" << lsb - << "] Range extract has backward bit ordering, perhaps you wanted [" << lsb + << "] Slice range has ascending bit ordering, perhaps you wanted [" << lsb << ":" << msb << "]"); const int x = msb; msb = lsb; @@ -432,12 +432,12 @@ private: nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); } else if (VN_IS(ddtypep, NodeUOrStructDType)) { - // Classes aren't little endian + // Classes don't have an ascending range if (lsb > msb) { nodep->v3warn( SELRANGE, "[" << msb << ":" << lsb - << "] Range extract has backward bit ordering, perhaps you wanted [" << lsb + << "] Slice range has ascending bit ordering, perhaps you wanted [" << lsb << ":" << msb << "]"); const int x = msb; msb = lsb; @@ -485,7 +485,8 @@ private: V3Width::widthParamsEdit(nodep->rhsp()); // constifyEdit doesn't ensure widths finished V3Const::constifyEdit(nodep->rhsp()); // May relink pointed to node, ok if not const V3Const::constifyParamsEdit(nodep->thsp()); // May relink pointed to node - checkConstantOrReplace(nodep->thsp(), "Width of :+ or :- bit extract isn't a constant"); + checkConstantOrReplace(nodep->thsp(), + "Width of :+ or :- bit slice range isn't a constant"); if (debug() >= 9) nodep->dumpTree("- SELPM3: "); // Now replace it with an AstSel AstNodeExpr* const fromp = nodep->fromp()->unlinkFrBack(); @@ -521,7 +522,7 @@ private: const int32_t msb = VN_IS(nodep, SelPlus) ? rhs + width - 1 : rhs; const int32_t lsb = VN_IS(nodep, SelPlus) ? rhs : rhs - width + 1; AstSliceSel* const newp = new AstSliceSel{ - nodep->fileline(), fromp, VNumRange{msb, lsb, fromRange.littleEndian()}}; + nodep->fileline(), fromp, VNumRange{msb, lsb, fromRange.ascending()}}; nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); } else { @@ -539,7 +540,7 @@ private: } AstNodeExpr* newlsbp = nullptr; if (VN_IS(nodep, SelPlus)) { - if (fromRange.littleEndian()) { + if (fromRange.ascending()) { // SELPLUS(from,lsb,width) -> SEL(from, (vector_msb-width+1)-sel, width) newlsbp = newSubNeg((fromRange.hi() - width + 1), rhsp); } else { @@ -547,7 +548,7 @@ private: newlsbp = newSubNeg(rhsp, fromRange.lo()); } } else if (VN_IS(nodep, SelMinus)) { - if (fromRange.littleEndian()) { + if (fromRange.ascending()) { // SELMINUS(from,msb,width) -> SEL(from, msb-[bit]) newlsbp = newSubNeg(fromRange.hi(), rhsp); } else { diff --git a/test_regress/t/t_array_backw_index_bad.out b/test_regress/t/t_array_backw_index_bad.out index 83ee4b870..f49d74019 100644 --- a/test_regress/t/t_array_backw_index_bad.out +++ b/test_regress/t/t_array_backw_index_bad.out @@ -1,16 +1,16 @@ -%Error: t/t_array_backw_index_bad.v:17:19: Slice selection '[1:3]' has backward indexing versus data type's '[3:0]' +%Error: t/t_array_backw_index_bad.v:17:19: Slice selection '[1:3]' has reversed range order versus data type's '[3:0]' : ... In instance t 17 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; | ^ -%Error: t/t_array_backw_index_bad.v:18:20: Slice selection '[3:1]' has backward indexing versus data type's '[0:3]' +%Error: t/t_array_backw_index_bad.v:18:20: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]' : ... In instance t 18 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; | ^ -%Error: t/t_array_backw_index_bad.v:19:20: Slice selection '[4:6]' has backward indexing versus data type's '[6:3]' +%Error: t/t_array_backw_index_bad.v:19:20: Slice selection '[4:6]' has reversed range order versus data type's '[6:3]' : ... In instance t 19 | array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; | ^ -%Error: t/t_array_backw_index_bad.v:20:21: Slice selection '[6:4]' has backward indexing versus data type's '[3:6]' +%Error: t/t_array_backw_index_bad.v:20:21: Slice selection '[6:4]' has reversed range order versus data type's '[3:6]' : ... In instance t 20 | larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; | ^ diff --git a/test_regress/t/t_array_packed_endian.v b/test_regress/t/t_array_packed_endian.v index 5a4fa03f0..a0f3300ff 100644 --- a/test_regress/t/t_array_packed_endian.v +++ b/test_regress/t/t_array_packed_endian.v @@ -12,27 +12,27 @@ typedef struct packed { } tb_t; typedef struct packed { - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE logic [0:7] a; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE } tl_t; typedef struct packed { logic [7:0] bb; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE tb_t [0:1] cbl; tb_t [1:0] cbb; tl_t [0:1] cll; tl_t [1:0] clb; logic [0:7] dl; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE } t2; logic [2:0][31:0] test2l; -// verilator lint_off LITENDIAN +// verilator lint_off ASCRANGE logic [0:2][31:0] test2b; logic [0:2][31:0] test1b; -// verilator lint_on LITENDIAN +// verilator lint_on ASCRANGE logic [2:0][31:0] test1l; module t; diff --git a/test_regress/t/t_array_packed_sysfunct.v b/test_regress/t/t_array_packed_sysfunct.v index 2c3c7520f..4a8ce3f9a 100644 --- a/test_regress/t/t_array_packed_sysfunct.v +++ b/test_regress/t/t_array_packed_sysfunct.v @@ -19,10 +19,10 @@ module t (/*AUTOARG*/ localparam WC = 8; // 2D packed arrays - logic [WA+1:2] [WB+1:2] [WC+1:2] array_bg; // big endian array - /* verilator lint_off LITENDIAN */ - logic [2:WA+1] [2:WB+1] [2:WC+1] array_lt; // little endian array - /* verilator lint_on LITENDIAN */ + logic [WA+1:2] [WB+1:2] [WC+1:2] array_dsc; // descending range array + /* verilator lint_off ASCRANGE */ + logic [2:WA+1] [2:WB+1] [2:WC+1] array_asc; // ascending range array + /* verilator lint_on ASCRANGE */ logic [1:0] array_unpk [3:2][1:0]; @@ -83,84 +83,84 @@ module t (/*AUTOARG*/ $write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt); `endif if (cnt[30:4]==1) begin - // big endian + // descending range if (slc==0) begin // full array - `checkh($dimensions (array_bg), 3); - `checkh($bits (array_bg), WA*WB*WC); + `checkh($dimensions (array_dsc), 3); + `checkh($bits (array_dsc), WA*WB*WC); if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_bg, dim), wdt+1); - `checkh($right (array_bg, dim), 2 ); - `checkh($low (array_bg, dim), 2 ); - `checkh($high (array_bg, dim), wdt+1); - `checkh($increment (array_bg, dim), 1 ); - `checkh($size (array_bg, dim), wdt ); + `checkh($left (array_dsc, dim), wdt+1); + `checkh($right (array_dsc, dim), 2 ); + `checkh($low (array_dsc, dim), 2 ); + `checkh($high (array_dsc, dim), wdt+1); + `checkh($increment (array_dsc, dim), 1 ); + `checkh($size (array_dsc, dim), wdt ); end end else if (slc==1) begin // single array element - `checkh($dimensions (array_bg[2]), 2); - `checkh($bits (array_bg[2]), WB*WC); + `checkh($dimensions (array_dsc[2]), 2); + `checkh($bits (array_dsc[2]), WB*WC); if ((dim>=2)&&(dim<=3)) begin - `checkh($left (array_bg[2], dim-1), wdt+1); - `checkh($right (array_bg[2], dim-1), 2 ); - `checkh($low (array_bg[2], dim-1), 2 ); - `checkh($high (array_bg[2], dim-1), wdt+1); - `checkh($increment (array_bg[2], dim-1), 1 ); - `checkh($size (array_bg[2], dim-1), wdt ); + `checkh($left (array_dsc[2], dim-1), wdt+1); + `checkh($right (array_dsc[2], dim-1), 2 ); + `checkh($low (array_dsc[2], dim-1), 2 ); + `checkh($high (array_dsc[2], dim-1), wdt+1); + `checkh($increment (array_dsc[2], dim-1), 1 ); + `checkh($size (array_dsc[2], dim-1), wdt ); end `ifndef VERILATOR // Unsupported slices don't maintain size correctly end else if (slc==2) begin // half array - `checkh($dimensions (array_bg[WA/2+1:2]), 3); - `checkh($bits (array_bg[WA/2+1:2]), WA/2*WB*WC); + `checkh($dimensions (array_dsc[WA/2+1:2]), 3); + `checkh($bits (array_dsc[WA/2+1:2]), WA/2*WB*WC); if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_bg[WA/2+1:2], dim), wdt+1); - `checkh($right (array_bg[WA/2+1:2], dim), 2 ); - `checkh($low (array_bg[WA/2+1:2], dim), 2 ); - `checkh($high (array_bg[WA/2+1:2], dim), wdt+1); - `checkh($increment (array_bg[WA/2+1:2], dim), 1 ); - `checkh($size (array_bg[WA/2+1:2], dim), wdt); + `checkh($left (array_dsc[WA/2+1:2], dim), wdt+1); + `checkh($right (array_dsc[WA/2+1:2], dim), 2 ); + `checkh($low (array_dsc[WA/2+1:2], dim), 2 ); + `checkh($high (array_dsc[WA/2+1:2], dim), wdt+1); + `checkh($increment (array_dsc[WA/2+1:2], dim), 1 ); + `checkh($size (array_dsc[WA/2+1:2], dim), wdt); end `endif end end else if (cnt[30:4]==2) begin - // little endian + // ascending range if (slc==0) begin // full array - `checkh($dimensions (array_lt), 3); - `checkh($bits (array_lt), WA*WB*WC); + `checkh($dimensions (array_asc), 3); + `checkh($bits (array_asc), WA*WB*WC); if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_lt, dim), 2 ); - `checkh($right (array_lt, dim), wdt+1); - `checkh($low (array_lt, dim), 2 ); - `checkh($high (array_lt, dim), wdt+1); - `checkh($increment (array_lt, dim), -1 ); - `checkh($size (array_lt, dim), wdt ); + `checkh($left (array_asc, dim), 2 ); + `checkh($right (array_asc, dim), wdt+1); + `checkh($low (array_asc, dim), 2 ); + `checkh($high (array_asc, dim), wdt+1); + `checkh($increment (array_asc, dim), -1 ); + `checkh($size (array_asc, dim), wdt ); end end else if (slc==1) begin // single array element - `checkh($dimensions (array_lt[2]), 2); - `checkh($bits (array_lt[2]), WB*WC); + `checkh($dimensions (array_asc[2]), 2); + `checkh($bits (array_asc[2]), WB*WC); if ((dim>=2)&&(dim<=3)) begin - `checkh($left (array_lt[2], dim-1), 2 ); - `checkh($right (array_lt[2], dim-1), wdt+1); - `checkh($low (array_lt[2], dim-1), 2 ); - `checkh($high (array_lt[2], dim-1), wdt+1); - `checkh($increment (array_lt[2], dim-1), -1 ); - `checkh($size (array_lt[2], dim-1), wdt ); + `checkh($left (array_asc[2], dim-1), 2 ); + `checkh($right (array_asc[2], dim-1), wdt+1); + `checkh($low (array_asc[2], dim-1), 2 ); + `checkh($high (array_asc[2], dim-1), wdt+1); + `checkh($increment (array_asc[2], dim-1), -1 ); + `checkh($size (array_asc[2], dim-1), wdt ); end `ifndef VERILATOR // Unsupported slices don't maintain size correctly end else if (slc==2) begin // half array - `checkh($dimensions (array_lt[2:WA/2+1]), 3); - `checkh($bits (array_lt[2:WA/2+1]), WA/2*WB*WC); + `checkh($dimensions (array_asc[2:WA/2+1]), 3); + `checkh($bits (array_asc[2:WA/2+1]), WA/2*WB*WC); if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_lt[2:WA/2+1], dim), 2 ); - `checkh($right (array_lt[2:WA/2+1], dim), wdt+1); - `checkh($low (array_lt[2:WA/2+1], dim), 2 ); - `checkh($high (array_lt[2:WA/2+1], dim), wdt+1); - `checkh($increment (array_lt[2:WA/2+1], dim), -1 ); - `checkh($size (array_lt[2:WA/2+1], dim), wdt ); + `checkh($left (array_asc[2:WA/2+1], dim), 2 ); + `checkh($right (array_asc[2:WA/2+1], dim), wdt+1); + `checkh($low (array_asc[2:WA/2+1], dim), 2 ); + `checkh($high (array_asc[2:WA/2+1], dim), wdt+1); + `checkh($increment (array_asc[2:WA/2+1], dim), -1 ); + `checkh($size (array_asc[2:WA/2+1], dim), wdt ); end `endif end diff --git a/test_regress/t/t_array_packed_write_read.v b/test_regress/t/t_array_packed_write_read.v index 0da8351b4..1e2bf3d15 100644 --- a/test_regress/t/t_array_packed_write_read.v +++ b/test_regress/t/t_array_packed_write_read.v @@ -18,10 +18,10 @@ module t (/*AUTOARG*/ localparam NO = 10; // number of access events // 2D packed arrays - logic [WA-1:0] [WB-1:0] array_bg; // big endian array - /* verilator lint_off LITENDIAN */ - logic [0:WA-1] [0:WB-1] array_lt; // little endian array - /* verilator lint_on LITENDIAN */ + logic [WA-1:0] [WB-1:0] array_dsc; // descending range array + /* verilator lint_off ASCRANGE */ + logic [0:WA-1] [0:WB-1] array_asc; // ascending range array + /* verilator lint_on ASCRANGE */ integer cnt = 0; @@ -41,108 +41,108 @@ module t (/*AUTOARG*/ $finish; end - // big endian + // descending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) - if (cnt[30:2]==0) array_bg <= '0; - else if (cnt[30:2]==1) array_bg <= '0; - else if (cnt[30:2]==2) array_bg <= '0; - else if (cnt[30:2]==3) array_bg <= '0; - else if (cnt[30:2]==4) array_bg <= '0; - else if (cnt[30:2]==5) array_bg <= '0; - else if (cnt[30:2]==6) array_bg <= '0; - else if (cnt[30:2]==7) array_bg <= '0; - else if (cnt[30:2]==8) array_bg <= '0; - else if (cnt[30:2]==9) array_bg <= '0; + if (cnt[30:2]==0) array_dsc <= '0; + else if (cnt[30:2]==1) array_dsc <= '0; + else if (cnt[30:2]==2) array_dsc <= '0; + else if (cnt[30:2]==3) array_dsc <= '0; + else if (cnt[30:2]==4) array_dsc <= '0; + else if (cnt[30:2]==5) array_dsc <= '0; + else if (cnt[30:2]==6) array_dsc <= '0; + else if (cnt[30:2]==7) array_dsc <= '0; + else if (cnt[30:2]==8) array_dsc <= '0; + else if (cnt[30:2]==9) array_dsc <= '0; end else if (cnt[1:0]==2'd1) begin // write value to array if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) array_bg <= {WA *WB +0{1'b1}}; - else if (cnt[30:2]==2) array_bg [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==3) array_bg [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==4) array_bg [ 0 ] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==5) array_bg [WA -1 ] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==6) array_bg [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==7) array_bg [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==8) array_bg [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; - else if (cnt[30:2]==9) array_bg [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2]==1) array_dsc <= {WA *WB +0{1'b1}}; + else if (cnt[30:2]==2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2]==9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; end else if (cnt[1:0]==2'd2) begin // check array value - if (cnt[30:2]==0) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==1) begin if (array_bg !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==2) begin if (array_bg !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==3) begin if (array_bg !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==4) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==5) begin if (array_bg !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==6) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==7) begin if (array_bg !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==8) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]==9) begin if (array_bg !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end + if (cnt[30:2]==0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]==1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]==2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]==3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]==4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]==5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]==6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]==7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]==8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]==9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from array (not a very good test for now) - if (cnt[30:2]==0) begin if (array_bg !== {WA *WB {1'b0}}) $stop(); end - else if (cnt[30:2]==1) begin if (array_bg !== {WA *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (array_bg [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (array_bg [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (array_bg [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (array_bg [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==6) begin if (array_bg [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==7) begin if (array_bg [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==8) begin if (array_bg [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end - else if (cnt[30:2]==9) begin if (array_bg [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end + if (cnt[30:2]==0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end + else if (cnt[30:2]==1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2]==9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end end - // little endian + // ascending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) - if (cnt[30:2]==0) array_lt <= '0; - else if (cnt[30:2]==1) array_lt <= '0; - else if (cnt[30:2]==2) array_lt <= '0; - else if (cnt[30:2]==3) array_lt <= '0; - else if (cnt[30:2]==4) array_lt <= '0; - else if (cnt[30:2]==5) array_lt <= '0; - else if (cnt[30:2]==6) array_lt <= '0; - else if (cnt[30:2]==7) array_lt <= '0; - else if (cnt[30:2]==8) array_lt <= '0; - else if (cnt[30:2]==9) array_lt <= '0; + if (cnt[30:2]==0) array_asc <= '0; + else if (cnt[30:2]==1) array_asc <= '0; + else if (cnt[30:2]==2) array_asc <= '0; + else if (cnt[30:2]==3) array_asc <= '0; + else if (cnt[30:2]==4) array_asc <= '0; + else if (cnt[30:2]==5) array_asc <= '0; + else if (cnt[30:2]==6) array_asc <= '0; + else if (cnt[30:2]==7) array_asc <= '0; + else if (cnt[30:2]==8) array_asc <= '0; + else if (cnt[30:2]==9) array_asc <= '0; end else if (cnt[1:0]==2'd1) begin // write value to array if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) array_lt <= {WA *WB +0{1'b1}}; - else if (cnt[30:2]==2) array_lt [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==3) array_lt [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==4) array_lt [0 ] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==5) array_lt [ WA -1] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==6) array_lt [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==7) array_lt [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==8) array_lt [0 ][0 ] <= {1 *1 +0{1'b1}}; - else if (cnt[30:2]==9) array_lt [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2]==1) array_asc <= {WA *WB +0{1'b1}}; + else if (cnt[30:2]==2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==4) array_asc [0 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==5) array_asc [ WA -1] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2]==9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; end else if (cnt[1:0]==2'd2) begin // check array value - if (cnt[30:2]==0) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==1) begin if (array_lt !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==2) begin if (array_lt !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==3) begin if (array_lt !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==4) begin if (array_lt !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==5) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==6) begin if (array_lt !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==7) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==8) begin if (array_lt !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==9) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_lt); $stop(); end end + if (cnt[30:2]==0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from array (not a very good test for now) - if (cnt[30:2]==0) begin if (array_lt !== {WA *WB {1'b0}}) $stop(); end - else if (cnt[30:2]==1) begin if (array_lt !== {WA *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (array_lt [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (array_lt [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (array_lt [0 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (array_lt [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==6) begin if (array_lt [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==7) begin if (array_lt [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==8) begin if (array_lt [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end - else if (cnt[30:2]==9) begin if (array_lt [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end + if (cnt[30:2]==0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end + else if (cnt[30:2]==1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2]==9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end end endmodule diff --git a/test_regress/t/t_array_pattern_packed.v b/test_regress/t/t_array_pattern_packed.v index 8023dae9f..0c3eff320 100644 --- a/test_regress/t/t_array_pattern_packed.v +++ b/test_regress/t/t_array_pattern_packed.v @@ -11,7 +11,7 @@ module t (/*AUTOARG*/ input clk; - logic [1:0] [3:0] [3:0] array_simp; // big endian array + logic [1:0] [3:0] [3:0] array_simp; // descending range array logic [3:0] array_oned; @@ -61,10 +61,10 @@ module t (/*AUTOARG*/ localparam NO = 11; // number of access events // 2D packed arrays - logic [WA-1:0] [WB-1:0] array_bg; // big endian array - /* verilator lint_off LITENDIAN */ - logic [0:WA-1] [0:WB-1] array_lt; // little endian array - /* verilator lint_on LITENDIAN */ + logic [WA-1:0] [WB-1:0] array_dsc; // descending range array + /* verilator lint_off ASCRANGE */ + logic [0:WA-1] [0:WB-1] array_asc; // ascending range array + /* verilator lint_on ASCRANGE */ integer cnt = 0; @@ -80,74 +80,74 @@ module t (/*AUTOARG*/ $finish; end - // big endian + // descending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) - if (cnt[30:2]== 0) array_bg <= '0; - else if (cnt[30:2]== 1) array_bg <= '0; - else if (cnt[30:2]== 2) array_bg <= '0; - else if (cnt[30:2]== 3) array_bg <= '0; - else if (cnt[30:2]== 4) array_bg <= '0; - else if (cnt[30:2]== 5) array_bg <= '0; - else if (cnt[30:2]== 6) array_bg <= '0; - else if (cnt[30:2]== 7) array_bg <= '0; - else if (cnt[30:2]== 8) array_bg <= '0; - else if (cnt[30:2]== 9) array_bg <= '0; - else if (cnt[30:2]==10) array_bg <= '0; + if (cnt[30:2]== 0) array_dsc <= '0; + else if (cnt[30:2]== 1) array_dsc <= '0; + else if (cnt[30:2]== 2) array_dsc <= '0; + else if (cnt[30:2]== 3) array_dsc <= '0; + else if (cnt[30:2]== 4) array_dsc <= '0; + else if (cnt[30:2]== 5) array_dsc <= '0; + else if (cnt[30:2]== 6) array_dsc <= '0; + else if (cnt[30:2]== 7) array_dsc <= '0; + else if (cnt[30:2]== 8) array_dsc <= '0; + else if (cnt[30:2]== 9) array_dsc <= '0; + else if (cnt[30:2]==10) array_dsc <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]== 0) begin end - else if (cnt[30:2]== 1) array_bg <= '{ 3 ,2 ,1, 0 }; - else if (cnt[30:2]== 2) array_bg <= '{default:13}; - else if (cnt[30:2]== 3) array_bg <= '{0:4, 1:5, 2:6, 3:7}; - else if (cnt[30:2]== 4) array_bg <= '{2:15, default:13}; - else if (cnt[30:2]== 5) array_bg <= '{WA { {WB/2 {2'b10}} }}; - else if (cnt[30:2]== 6) array_bg <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; + else if (cnt[30:2]== 1) array_dsc <= '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]== 2) array_dsc <= '{default:13}; + else if (cnt[30:2]== 3) array_dsc <= '{0:4, 1:5, 2:6, 3:7}; + else if (cnt[30:2]== 4) array_dsc <= '{2:15, default:13}; + else if (cnt[30:2]== 5) array_dsc <= '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]== 6) array_dsc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; end else if (cnt[1:0]==2'd2) begin // chack array agains expected value - if (cnt[30:2]== 0) begin if (array_bg !== 16'b0000000000000000) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]== 1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]== 2) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]== 3) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]== 4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]== 5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end - else if (cnt[30:2]== 6) begin if (array_bg !== 16'b1001101010111100) begin $display("%b", array_bg); $stop(); end end + if (cnt[30:2]== 0) begin if (array_dsc !== 16'b0000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 1) begin if (array_dsc !== 16'b0011001000010000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 2) begin if (array_dsc !== 16'b1101110111011101) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 3) begin if (array_dsc !== 16'b0111011001010100) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 4) begin if (array_dsc !== 16'b1101111111011101) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 5) begin if (array_dsc !== 16'b1010101010101010) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 6) begin if (array_dsc !== 16'b1001101010111100) begin $display("%b", array_dsc); $stop(); end end end - // little endian + // ascending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) - if (cnt[30:2]== 0) array_lt <= '0; - else if (cnt[30:2]== 1) array_lt <= '0; - else if (cnt[30:2]== 2) array_lt <= '0; - else if (cnt[30:2]== 3) array_lt <= '0; - else if (cnt[30:2]== 4) array_lt <= '0; - else if (cnt[30:2]== 5) array_lt <= '0; - else if (cnt[30:2]== 6) array_lt <= '0; - else if (cnt[30:2]== 7) array_lt <= '0; - else if (cnt[30:2]== 8) array_lt <= '0; - else if (cnt[30:2]== 9) array_lt <= '0; - else if (cnt[30:2]==10) array_lt <= '0; + if (cnt[30:2]== 0) array_asc <= '0; + else if (cnt[30:2]== 1) array_asc <= '0; + else if (cnt[30:2]== 2) array_asc <= '0; + else if (cnt[30:2]== 3) array_asc <= '0; + else if (cnt[30:2]== 4) array_asc <= '0; + else if (cnt[30:2]== 5) array_asc <= '0; + else if (cnt[30:2]== 6) array_asc <= '0; + else if (cnt[30:2]== 7) array_asc <= '0; + else if (cnt[30:2]== 8) array_asc <= '0; + else if (cnt[30:2]== 9) array_asc <= '0; + else if (cnt[30:2]==10) array_asc <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]== 0) begin end - else if (cnt[30:2]== 1) array_lt <= '{ 3 ,2 ,1, 0 }; - else if (cnt[30:2]== 2) array_lt <= '{default:13}; - else if (cnt[30:2]== 3) array_lt <= '{3:4, 2:5, 1:6, 0:7}; - else if (cnt[30:2]== 4) array_lt <= '{1:15, default:13}; - else if (cnt[30:2]== 5) array_lt <= '{WA { {WB/2 {2'b10}} }}; - else if (cnt[30:2]==10) array_lt <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; + else if (cnt[30:2]== 1) array_asc <= '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]== 2) array_asc <= '{default:13}; + else if (cnt[30:2]== 3) array_asc <= '{3:4, 2:5, 1:6, 0:7}; + else if (cnt[30:2]== 4) array_asc <= '{1:15, default:13}; + else if (cnt[30:2]== 5) array_asc <= '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]==10) array_asc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; end else if (cnt[1:0]==2'd2) begin // chack array agains expected value - if (cnt[30:2]== 0) begin if (array_lt !== 16'b0000000000000000) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]== 1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]== 2) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]== 3) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]== 4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]== 5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end - else if (cnt[30:2]==10) begin if (array_lt !== 16'b1001101010111100) begin $display("%b", array_lt); $stop(); end end + if (cnt[30:2]== 0) begin if (array_asc !== 16'b0000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 1) begin if (array_asc !== 16'b0011001000010000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 2) begin if (array_asc !== 16'b1101110111011101) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 3) begin if (array_asc !== 16'b0111011001010100) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 4) begin if (array_asc !== 16'b1101111111011101) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 5) begin if (array_asc !== 16'b1010101010101010) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==10) begin if (array_asc !== 16'b1001101010111100) begin $display("%b", array_asc); $stop(); end end end endmodule diff --git a/test_regress/t/t_array_pattern_unpacked.v b/test_regress/t/t_array_pattern_unpacked.v index aaf1db6c4..60e710d92 100644 --- a/test_regress/t/t_array_pattern_unpacked.v +++ b/test_regress/t/t_array_pattern_unpacked.v @@ -6,7 +6,7 @@ module t (/*AUTOARG*/); - logic [3:0] array_simp [1:0] [3:0]; // big endian array + logic [3:0] array_simp [1:0] [3:0]; // descending range array int irep[1:2][1:6]; diff --git a/test_regress/t/t_array_query.v b/test_regress/t/t_array_query.v index b57a10494..963495080 100644 --- a/test_regress/t/t_array_query.v +++ b/test_regress/t/t_array_query.v @@ -40,9 +40,9 @@ module array_test input clk; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE reg [7:0] a [LEFT:RIGHT]; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE typedef reg [7:0] r_t; diff --git a/test_regress/t/t_array_rev.v b/test_regress/t/t_array_rev.v index 47594bf5f..6d06bbd9d 100644 --- a/test_regress/t/t_array_rev.v +++ b/test_regress/t/t_array_rev.v @@ -12,9 +12,9 @@ module t (/*AUTOARG*/ input clk; integer cyc = 0; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE logic arrd [0:1] = '{ 1'b1, 1'b0 }; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE logic y0, y1; logic localbkw [1:0]; diff --git a/test_regress/t/t_clk_concat3.v b/test_regress/t/t_clk_concat3.v index 87fb40db8..fe68657cb 100644 --- a/test_regress/t/t_clk_concat3.v +++ b/test_regress/t/t_clk_concat3.v @@ -4,7 +4,7 @@ // without warranty. // SPDX-License-Identifier: CC0-1.0 -/* verilator lint_off LITENDIAN */ +/* verilator lint_off ASCRANGE */ module some_module ( input wrclk ); diff --git a/test_regress/t/t_dist_warn_coverage.pl b/test_regress/t/t_dist_warn_coverage.pl index 7fb44afc5..349fd4737 100755 --- a/test_regress/t/t_dist_warn_coverage.pl +++ b/test_regress/t/t_dist_warn_coverage.pl @@ -31,7 +31,7 @@ foreach my $s ( 'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error # Not yet analyzed ' is not an in/out/inout/param/interface: ', - 'Big endian instance range connecting to ', + 'Descending instance range connecting to ', ' loading non-variable', '--pipe-filter protocol error, unexpected: ', '/*verilator sformat*/ can only be applied to last argument of ', diff --git a/test_regress/t/t_foreach.v b/test_regress/t/t_foreach.v index e7f75f0a5..4cdf96180 100644 --- a/test_regress/t/t_foreach.v +++ b/test_regress/t/t_foreach.v @@ -8,7 +8,7 @@ module t (/*AUTOARG*/); - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE // verilator lint_off WIDTH reg [63:0] sum; // Checked not in objects diff --git a/test_regress/t/t_inst_array_connect.v b/test_regress/t/t_inst_array_connect.v index 48d5af727..af08f7c30 100644 --- a/test_regress/t/t_inst_array_connect.v +++ b/test_regress/t/t_inst_array_connect.v @@ -20,7 +20,7 @@ module t (/*AUTOARG*/ assign inc = 4'b0001; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE COUNTER UCOUNTER1[N-1:0] ( diff --git a/test_regress/t/t_interface_array_nocolon.v b/test_regress/t/t_interface_array_nocolon.v index 7536b49ce..370ca35fd 100644 --- a/test_regress/t/t_interface_array_nocolon.v +++ b/test_regress/t/t_interface_array_nocolon.v @@ -22,13 +22,13 @@ module t (); wire [2:0] X = 3'b110; - // Should not cause LITENDIAN warning, as no harm in array selections. - // verilator lint_on LITENDIAN + // Should not cause ASCRANGE warning, as no harm in array selections. + // verilator lint_on ASCRANGE foo_intf foo1 [N] (.x(1'b1)); foo_subm sub1 [N] (.x(1'b1)); - // Will cause LITENDIAN warning? - // verilator lint_off LITENDIAN + // Will cause ASCRANGE warning? + // verilator lint_off ASCRANGE foo_intf foos [N] (.x(X)); foo_intf fool [1:3] (.x(X)); foo_intf foom [3:1] (.x(X)); diff --git a/test_regress/t/t_interface_array_nocolon_bad.out b/test_regress/t/t_interface_array_nocolon_bad.out index b189edec7..744b81d20 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.out +++ b/test_regress/t/t_interface_array_nocolon_bad.out @@ -1,19 +1,19 @@ -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26:26: Big endian instance range connecting to vector: left < right of instance range: [0:2] - : ... In instance t +%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:26:26: Ascending instance range connecting to vector: left < right of instance range: [0:2] + : ... In instance t 26 | foo_intf foos [N] (.x(X)); | ^ - ... For warning description see https://verilator.org/warn/LITENDIAN?v=latest - ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Big endian instance range connecting to vector: left < right of instance range: [1:3] - : ... In instance t + ... For warning description see https://verilator.org/warn/ASCRANGE?v=latest + ... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message. +%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:27:28: Ascending instance range connecting to vector: left < right of instance range: [1:3] + : ... In instance t 27 | foo_intf fool [1:3] (.x(X)); | ^ -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30:26: Big endian instance range connecting to vector: left < right of instance range: [0:2] - : ... In instance t +%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:30:26: Ascending instance range connecting to vector: left < right of instance range: [0:2] + : ... In instance t 30 | foo_subm subs [N] (.x(X)); | ^ -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:31:28: Big endian instance range connecting to vector: left < right of instance range: [1:3] - : ... In instance t +%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:31:28: Ascending instance range connecting to vector: left < right of instance range: [1:3] + : ... In instance t 31 | foo_subm subl [1:3] (.x(X)); | ^ %Error: Exiting due to diff --git a/test_regress/t/t_interface_array_nocolon_bad.v b/test_regress/t/t_interface_array_nocolon_bad.v index 94431d640..088f38ef1 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.v +++ b/test_regress/t/t_interface_array_nocolon_bad.v @@ -22,7 +22,7 @@ module t (); wire [2:0] X = 3'b110; - // Will cause LITENDIAN warning? + // Will cause ASCRANGE warning? foo_intf foos [N] (.x(X)); // bad foo_intf fool [1:3] (.x(X)); // bad foo_intf foom [3:1] (.x(X)); // ok diff --git a/test_regress/t/t_lib_prot.v b/test_regress/t/t_lib_prot.v index 7fa639835..464f91426 100644 --- a/test_regress/t/t_lib_prot.v +++ b/test_regress/t/t_lib_prot.v @@ -57,10 +57,10 @@ module t #(parameter GATED_CLK = 0) (/*AUTOARG*/ logic [128:0] s129_out; logic [3:0] [31:0] s4x32_in; logic [3:0] [31:0] s4x32_out; - /*verilator lint_off LITENDIAN*/ + /*verilator lint_off ASCRANGE*/ logic [0:15] s6x16up_in[0:1][2:0]; logic [0:15] s6x16up_out[0:1][2:0]; - /*verilator lint_on LITENDIAN*/ + /*verilator lint_on ASCRANGE*/ logic [15:0] s8x16up_in[1:0][0:3]; logic [15:0] s8x16up_out[1:0][0:3]; logic [15:0] s8x16up_3d_in[1:0][0:1][0:1]; diff --git a/test_regress/t/t_lib_prot_secret.v b/test_regress/t/t_lib_prot_secret.v index 1ed4dae83..44e055cfe 100644 --- a/test_regress/t/t_lib_prot_secret.v +++ b/test_regress/t/t_lib_prot_secret.v @@ -27,10 +27,10 @@ module secret #(parameter GATED_CLK = 0) output logic [128:0] s129_out, input [3:0] [31:0] s4x32_in, output logic [3:0] [31:0] s4x32_out, - /*verilator lint_off LITENDIAN*/ + /*verilator lint_off ASCRANGE*/ input [0:15] s6x16up_in[0:1][2:0], output logic [0:15] s6x16up_out[0:1][2:0], - /*verilator lint_on LITENDIAN*/ + /*verilator lint_on ASCRANGE*/ input [15:0] s8x16up_in[1:0][0:3], output logic [15:0] s8x16up_out[1:0][0:3], input [15:0] s8x16up_3d_in[1:0][0:1][0:1], diff --git a/test_regress/t/t_lint_historical.v b/test_regress/t/t_lint_historical.v index 8647a070c..b1c1caf24 100644 --- a/test_regress/t/t_lint_historical.v +++ b/test_regress/t/t_lint_historical.v @@ -45,7 +45,7 @@ module t; // verilator lint_off INITIALDLY // verilator lint_off INSECURE // verilator lint_off LATCH - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE // verilator lint_off MODDUP // verilator lint_off MULTIDRIVEN // verilator lint_off MULTITOP diff --git a/test_regress/t/t_mem_fifo.v b/test_regress/t/t_mem_fifo.v index e76ec783a..ca1e13940 100644 --- a/test_regress/t/t_mem_fifo.v +++ b/test_regress/t/t_mem_fifo.v @@ -89,9 +89,9 @@ module fifo (/*AUTOARG*/ reg [65:0] outData; // verilator lint_off VARHIDDEN - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE reg [65:0] fifo[0:fifoDepth-1]; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE // verilator lint_on VARHIDDEN //reg [65:0] temp; diff --git a/test_regress/t/t_mem_first.v b/test_regress/t/t_mem_first.v index 372032a77..dfda7d9cb 100644 --- a/test_regress/t/t_mem_first.v +++ b/test_regress/t/t_mem_first.v @@ -12,13 +12,13 @@ module t (/*AUTOARG*/ input clk; integer _mode; initial _mode = 0; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [77:0] mem_wide [1024:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [7:0] mem_dly_narrow [0:1]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [77:0] mem_dly_wide [1:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [34:0] vec_wide; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE reg [31:0] wrd0 [15:0]; wire [3:0] sel = 4'h3; diff --git a/test_regress/t/t_mem_multidim.v b/test_regress/t/t_mem_multidim.v index 9f68b4d5d..a81d5319d 100644 --- a/test_regress/t/t_mem_multidim.v +++ b/test_regress/t/t_mem_multidim.v @@ -11,7 +11,7 @@ module t (/*AUTOARG*/ input clk; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE // verilator lint_off BLKANDNBLK // 3 3 4 reg [71:0] memw [2:0][1:3][5:2]; @@ -29,7 +29,7 @@ module t (/*AUTOARG*/ integer imem[2:0][1:3]; reg [2:0] cstyle[2]; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE initial begin for (i0=0; i0<3; i0=i0+1) begin diff --git a/test_regress/t/t_mem_multiwire.v b/test_regress/t/t_mem_multiwire.v index 24a53f502..15569e2f7 100644 --- a/test_regress/t/t_mem_multiwire.v +++ b/test_regress/t/t_mem_multiwire.v @@ -11,10 +11,10 @@ module t (/*AUTOARG*/ input clk; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE wire [7:0] array [2:0][1:3]; wire [7:0] arrayNoColon [2][3]; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE integer cyc; initial cyc = 0; integer i0,i1,i2; diff --git a/test_regress/t/t_metacmt_onoff.out b/test_regress/t/t_metacmt_onoff.out index 4c6ca3bf2..7b912780c 100644 --- a/test_regress/t/t_metacmt_onoff.out +++ b/test_regress/t/t_metacmt_onoff.out @@ -1,11 +1,11 @@ -%Warning-LITENDIAN: t/t_metacmt_onoff.v:8:8: Big bit endian vector: left < right of bit range: [0:1] - : ... In instance t - 8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; +%Warning-ASCRANGE: t/t_metacmt_onoff.v:8:8: Ascending bit range vector: left < right of bit range: [0:1] + : ... In instance t + 8 | reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; | ^ - ... For warning description see https://verilator.org/warn/LITENDIAN?v=latest - ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. -%Warning-LITENDIAN: t/t_metacmt_onoff.v:8:109: Big bit endian vector: left < right of bit range: [0:3] - : ... In instance t - 8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; - | ^ + ... For warning description see https://verilator.org/warn/ASCRANGE?v=latest + ... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message. +%Warning-ASCRANGE: t/t_metacmt_onoff.v:8:107: Ascending bit range vector: left < right of bit range: [0:3] + : ... In instance t + 8 | reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_metacmt_onoff.v b/test_regress/t/t_metacmt_onoff.v index 7b7c5735e..91dc5eeae 100644 --- a/test_regress/t/t_metacmt_onoff.v +++ b/test_regress/t/t_metacmt_onoff.v @@ -5,7 +5,7 @@ module t; // Test turning on and off a message on the same line; only middle reg shouldn't warn - reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; + reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; initial begin $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_mod_interface_array1.v b/test_regress/t/t_mod_interface_array1.v index bd497af90..f16a65b41 100644 --- a/test_regress/t/t_mod_interface_array1.v +++ b/test_regress/t/t_mod_interface_array1.v @@ -44,9 +44,9 @@ module t logic [N-1:0] a_in; logic [N-1:0] a_out; logic [N-1:0] ack_out; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE a_if #(.PARAM(1)) tl_intf [N] (); - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE intf_source source(a_in, tl_intf); intf_sink sink(a_out, tl_intf); diff --git a/test_regress/t/t_mod_interface_array2.v b/test_regress/t/t_mod_interface_array2.v index b7f7647f8..b2f15dc04 100644 --- a/test_regress/t/t_mod_interface_array2.v +++ b/test_regress/t/t_mod_interface_array2.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 parameter N = 4; -// verilator lint_off LITENDIAN +// verilator lint_off ASCRANGE interface a_if #(parameter PARAM = 0) (); logic long_name; diff --git a/test_regress/t/t_param_module.v b/test_regress/t/t_param_module.v index 18369db2c..c83a8e805 100644 --- a/test_regress/t/t_param_module.v +++ b/test_regress/t/t_param_module.v @@ -7,7 +7,7 @@ // used in the test module to set the value of MSB. A number of warnings and // errors follow, starting with: // -// %Warning-LITENDIAN: t/t_param_module.v:42: Big bit endian vector: MSB +// %Warning-ASCRANGE: t/t_param_module.v:42: Ascending bit range vector: MSB // < LSB of bit range: -17:0 // // This file ONLY is placed into the Public Domain, for any use, without diff --git a/test_regress/t/t_param_repl.v b/test_regress/t/t_param_repl.v index 0cc2c107a..cc7b04d40 100644 --- a/test_regress/t/t_param_repl.v +++ b/test_regress/t/t_param_repl.v @@ -21,9 +21,9 @@ module t (/*AUTOARG*/ parameter DWORDS_LOG2 = 7; parameter DWORDS = (1< 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_select_ascending.v b/test_regress/t/t_select_ascending.v new file mode 100644 index 000000000..0f37470d9 --- /dev/null +++ b/test_regress/t/t_select_ascending.v @@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; + + // verilator lint_off ASCRANGE + wire [10:41] sel2 = crc[31:0]; + wire [10:100] sel3 = {crc[26:0],crc}; + + wire out20 = sel2[{1'b0,crc[3:0]} + 11]; + wire [3:0] out21 = sel2[13 : 16]; + wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; + wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; + + wire out30 = sel3[{2'b0,crc[3:0]} + 11]; + wire [3:0] out31 = sel3[13 : 16]; + wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; + wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; + + // Aggregate outputs into a single result vector + wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; + + reg [19:50] sel1; + initial begin + // Path clearing + // 122333445 + // 826048260 + sel1 = 32'h12345678; + if (sel1 != 32'h12345678) $stop; + if (sel1[47 : 50] != 4'h8) $stop; + if (sel1[31 : 34] != 4'h4) $stop; + if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20] + if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24] + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n", $time, out20,out21,out22,out23, out30,out31,out32,out33); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; +`define EXPECTED_SUM 64'h28bf65439eb12c00 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_select_bad_msb.out b/test_regress/t/t_select_bad_msb.out index 1ec1c350e..84e30c325 100644 --- a/test_regress/t/t_select_bad_msb.out +++ b/test_regress/t/t_select_bad_msb.out @@ -1,10 +1,10 @@ -%Warning-LITENDIAN: t/t_select_bad_msb.v:12:8: Big bit endian vector: left < right of bit range: [0:22] - : ... In instance t +%Warning-ASCRANGE: t/t_select_bad_msb.v:12:8: Ascending bit range vector: left < right of bit range: [0:22] + : ... In instance t 12 | reg [0:22] backwd; | ^ - ... For warning description see https://verilator.org/warn/LITENDIAN?v=latest - ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. -%Warning-SELRANGE: t/t_select_bad_msb.v:16:16: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1] + ... For warning description see https://verilator.org/warn/ASCRANGE?v=latest + ... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message. +%Warning-SELRANGE: t/t_select_bad_msb.v:16:16: [1:4] Slice range has ascending bit ordering, perhaps you wanted [4:1] : ... In instance t 16 | sel2 = mi[1:4]; | ^ diff --git a/test_regress/t/t_select_bad_range4.out b/test_regress/t/t_select_bad_range4.out index 302b44d6e..cff72fd9a 100644 --- a/test_regress/t/t_select_bad_range4.out +++ b/test_regress/t/t_select_bad_range4.out @@ -36,7 +36,7 @@ : ... In instance t 22 | sel2 = mi[44 +: nonconst]; | ^~~~~~~~ -%Error: t/t_select_bad_range4.v:22:23: Width of :+ or :- bit extract isn't a constant +%Error: t/t_select_bad_range4.v:22:23: Width of :+ or :- bit slice range isn't a constant : ... In instance t 22 | sel2 = mi[44 +: nonconst]; | ^~~~~~~~ diff --git a/test_regress/t/t_select_little_pack.v b/test_regress/t/t_select_little_pack.v index e265f3b1f..3f7492a84 100644 --- a/test_regress/t/t_select_little_pack.v +++ b/test_regress/t/t_select_little_pack.v @@ -10,7 +10,7 @@ module t (/*AUTOARG*/ ); input clk; - // No endian warning here + // No ascending range warning here reg [7:0] pack [3:0]; initial begin diff --git a/test_regress/t/t_split_var_0.v b/test_regress/t/t_split_var_0.v index ee3db8562..6b316d6f3 100644 --- a/test_regress/t/t_split_var_0.v +++ b/test_regress/t/t_split_var_0.v @@ -175,9 +175,9 @@ module barshift_2d_packed_array #(parameter DEPTH = 2, localparam WIDTH = 2**DEP (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = -2; - /*verilator lint_off LITENDIAN*/ + /*verilator lint_off ASCRANGE*/ reg [OFFSET:DEPTH+OFFSET][WIDTH-1:0] tmp /*verilator split_var*/; - /*verilator lint_on LITENDIAN*/ + /*verilator lint_on ASCRANGE*/ generate for(genvar i = 0; i < DEPTH; ++i) begin @@ -201,9 +201,9 @@ module barshift_2d_packed_array_le #(parameter DEPTH = 2, localparam WIDTH = 2** (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = -2; - /*verilator lint_off LITENDIAN*/ + /*verilator lint_off ASCRANGE*/ reg [OFFSET:DEPTH+OFFSET][OFFSET:WIDTH-1+OFFSET] tmp /*verilator split_var*/; - /*verilator lint_on LITENDIAN*/ + /*verilator lint_on ASCRANGE*/ generate for(genvar i = 0; i < DEPTH; ++i) begin @@ -245,9 +245,9 @@ endmodule module barshift_bitslice #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); - /*verilator lint_off LITENDIAN*/ + /*verilator lint_off ASCRANGE*/ wire [0:WIDTH*(DEPTH+1) - 1] tmp /*verilator split_var*/; - /*verilator lint_on LITENDIAN*/ + /*verilator lint_on ASCRANGE*/ generate for(genvar i = 0; i < DEPTH; ++i) begin @@ -267,10 +267,10 @@ endmodule module var_decl_with_init(); - /*verilator lint_off LITENDIAN*/ + /*verilator lint_off ASCRANGE*/ logic [-1:30] var0 /* verilator split_var */ = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7}; logic [-1:30] var2 /* verilator split_var */; - /*verilator lint_on LITENDIAN*/ + /*verilator lint_on ASCRANGE*/ logic [30:-1] var1 /* verilator split_var */ = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7}; logic [30:-1] var3 /* verilator split_var */; @@ -290,9 +290,9 @@ module t_array_rev(clk); // from t_array_rev.v input clk; integer cyc = 0; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE logic arrd [0:1] /*verilator split_var*/ = '{ 1'b1, 1'b0 }; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE logic y0, y1; logic localbkw [1:0]/*verilator split_var*/ ; @@ -442,11 +442,11 @@ module t(/*AUTOARG*/ clk); t_array_rev i_t_array_rev(clk); assign in = 8'b10001110; - /*verilator lint_off LITENDIAN*/ + /*verilator lint_off ASCRANGE*/ logic [7:0] [7:0] expc = {8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001, 8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101}; - /*verilator lint_on LITENDIAN*/ + /*verilator lint_on ASCRANGE*/ always @(posedge clk) begin : always_block automatic bit failed = 0; $display("in:%b shift:%d expc:%b", in, shift, expc[7-shift]); diff --git a/test_regress/t/t_struct_packed_sysfunct.v b/test_regress/t/t_struct_packed_sysfunct.v index acbe00291..540f27dcb 100644 --- a/test_regress/t/t_struct_packed_sysfunct.v +++ b/test_regress/t/t_struct_packed_sysfunct.v @@ -17,15 +17,15 @@ module t (/*AUTOARG*/ logic [1:0] e1; logic [3:0] e2; logic [7:0] e3; - } struct_bg; // big endian structure - /* verilator lint_off LITENDIAN */ + } struct_dsc; // descendng range structure + /* verilator lint_off ASCRANGE */ struct packed { logic e0; logic [0:1] e1; logic [0:3] e2; logic [0:7] e3; - } struct_lt; // little endian structure - /* verilator lint_on LITENDIAN */ + } struct_asc; // ascending range structure + /* verilator lint_on ASCRANGE */ integer cnt = 0; @@ -44,20 +44,20 @@ module t (/*AUTOARG*/ always @ (posedge clk) if (cnt==1) begin - // big endian - if ($bits (struct_bg ) != 15) $stop; - if ($bits (struct_bg.e0) != 1) $stop; - if ($bits (struct_bg.e1) != 2) $stop; - if ($bits (struct_bg.e2) != 4) $stop; - if ($bits (struct_bg.e3) != 8) $stop; - if ($increment (struct_bg, 1) != 1) $stop; - // little endian - if ($bits (struct_lt ) != 15) $stop; - if ($bits (struct_lt.e0) != 1) $stop; - if ($bits (struct_lt.e1) != 2) $stop; - if ($bits (struct_lt.e2) != 4) $stop; - if ($bits (struct_lt.e3) != 8) $stop; - if ($increment (struct_lt, 1) != 1) $stop; // Structure itself always big numbered + // descending range + if ($bits (struct_dsc ) != 15) $stop; + if ($bits (struct_dsc.e0) != 1) $stop; + if ($bits (struct_dsc.e1) != 2) $stop; + if ($bits (struct_dsc.e2) != 4) $stop; + if ($bits (struct_dsc.e3) != 8) $stop; + if ($increment (struct_dsc, 1) != 1) $stop; + // ascending range + if ($bits (struct_asc ) != 15) $stop; + if ($bits (struct_asc.e0) != 1) $stop; + if ($bits (struct_asc.e1) != 2) $stop; + if ($bits (struct_asc.e2) != 4) $stop; + if ($bits (struct_asc.e3) != 8) $stop; + if ($increment (struct_asc, 1) != 1) $stop; // Structure itself always big numbered end endmodule diff --git a/test_regress/t/t_struct_packed_value_list.v b/test_regress/t/t_struct_packed_value_list.v index 41c84d3b9..3321d3d9e 100644 --- a/test_regress/t/t_struct_packed_value_list.v +++ b/test_regress/t/t_struct_packed_value_list.v @@ -19,17 +19,17 @@ module t (/*AUTOARG*/ logic [1:0] e1; logic [3:0] e2; logic [7:0] e3; - } struct_bg; // big endian structure - /* verilator lint_off LITENDIAN */ + } struct_dsc; // descending range structure + /* verilator lint_off ASCRANGE */ struct packed { logic e0; logic [0:1] e1; logic [0:3] e2; logic [0:7] e3; - } struct_lt; // little endian structure - /* verilator lint_on LITENDIAN */ + } struct_asc; // ascending range structure + /* verilator lint_on ASCRANGE */ - localparam WS = 15; // $bits(struct_bg) + localparam WS = 15; // $bits(struct_dsc) integer cnt = 0; @@ -46,70 +46,70 @@ module t (/*AUTOARG*/ $finish; end - // big endian + // descending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) - if (cnt[30:2]==0) struct_bg <= '0; - else if (cnt[30:2]==1) struct_bg <= '0; - else if (cnt[30:2]==2) struct_bg <= '0; - else if (cnt[30:2]==3) struct_bg <= '0; - else if (cnt[30:2]==4) struct_bg <= '0; - else if (cnt[30:2]==5) struct_bg <= '0; - else if (cnt[30:2]==6) struct_bg <= '0; + if (cnt[30:2]==0) struct_dsc <= '0; + else if (cnt[30:2]==1) struct_dsc <= '0; + else if (cnt[30:2]==2) struct_dsc <= '0; + else if (cnt[30:2]==3) struct_dsc <= '0; + else if (cnt[30:2]==4) struct_dsc <= '0; + else if (cnt[30:2]==5) struct_dsc <= '0; + else if (cnt[30:2]==6) struct_dsc <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) struct_bg <= '{0 ,1 , 2, 3}; - else if (cnt[30:2]==2) struct_bg <= '{e0:1, e1:2, e2:3, e3:4}; - else if (cnt[30:2]==3) struct_bg <= '{e3:6, e2:4, e1:2, e0:0}; + else if (cnt[30:2]==1) struct_dsc <= '{0 ,1 , 2, 3}; + else if (cnt[30:2]==2) struct_dsc <= '{e0:1, e1:2, e2:3, e3:4}; + else if (cnt[30:2]==3) struct_dsc <= '{e3:6, e2:4, e1:2, e0:0}; // verilator lint_off WIDTH - else if (cnt[30:2]==4) struct_bg <= '{default:13}; - else if (cnt[30:2]==5) struct_bg <= '{e2:8'haa, default:1}; - else if (cnt[30:2]==6) struct_bg <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; + else if (cnt[30:2]==4) struct_dsc <= '{default:13}; + else if (cnt[30:2]==5) struct_dsc <= '{e2:8'haa, default:1}; + else if (cnt[30:2]==6) struct_dsc <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; // verilator lint_on WIDTH end else if (cnt[1:0]==2'd2) begin // chack array agains expected value - if (cnt[30:2]==0) begin if (struct_bg !== 15'b0_00_0000_00000000) begin $display("%b", struct_bg); $stop(); end end - else if (cnt[30:2]==1) begin if (struct_bg !== 15'b0_01_0010_00000011) begin $display("%b", struct_bg); $stop(); end end - else if (cnt[30:2]==2) begin if (struct_bg !== 15'b1_10_0011_00000100) begin $display("%b", struct_bg); $stop(); end end - else if (cnt[30:2]==3) begin if (struct_bg !== 15'b0_10_0100_00000110) begin $display("%b", struct_bg); $stop(); end end - else if (cnt[30:2]==4) begin if (struct_bg !== 15'b1_01_1101_00001101) begin $display("%b", struct_bg); $stop(); end end - else if (cnt[30:2]==5) begin if (struct_bg !== 15'b1_01_1010_00000001) begin $display("%b", struct_bg); $stop(); end end - else if (cnt[30:2]==6) begin if (struct_bg !== 15'b1_10_1011_00011100) begin $display("%b", struct_bg); $stop(); end end + if (cnt[30:2]==0) begin if (struct_dsc !== 15'b0_00_0000_00000000) begin $display("%b", struct_dsc); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_dsc !== 15'b0_01_0010_00000011) begin $display("%b", struct_dsc); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_dsc !== 15'b1_10_0011_00000100) begin $display("%b", struct_dsc); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_dsc !== 15'b0_10_0100_00000110) begin $display("%b", struct_dsc); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_dsc !== 15'b1_01_1101_00001101) begin $display("%b", struct_dsc); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_dsc !== 15'b1_01_1010_00000001) begin $display("%b", struct_dsc); $stop(); end end + else if (cnt[30:2]==6) begin if (struct_dsc !== 15'b1_10_1011_00011100) begin $display("%b", struct_dsc); $stop(); end end end - // little endian + // ascending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) - if (cnt[30:2]==0) struct_lt <= '0; - else if (cnt[30:2]==1) struct_lt <= '0; - else if (cnt[30:2]==2) struct_lt <= '0; - else if (cnt[30:2]==3) struct_lt <= '0; - else if (cnt[30:2]==4) struct_lt <= '0; - else if (cnt[30:2]==5) struct_lt <= '0; - else if (cnt[30:2]==6) struct_lt <= '0; + if (cnt[30:2]==0) struct_asc <= '0; + else if (cnt[30:2]==1) struct_asc <= '0; + else if (cnt[30:2]==2) struct_asc <= '0; + else if (cnt[30:2]==3) struct_asc <= '0; + else if (cnt[30:2]==4) struct_asc <= '0; + else if (cnt[30:2]==5) struct_asc <= '0; + else if (cnt[30:2]==6) struct_asc <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) struct_lt <= '{0 ,1 , 2, 3}; - else if (cnt[30:2]==2) struct_lt <= '{e0:1, e1:2, e2:3, e3:4}; - else if (cnt[30:2]==3) struct_lt <= '{e3:6, e2:4, e1:2, e0:0}; + else if (cnt[30:2]==1) struct_asc <= '{0 ,1 , 2, 3}; + else if (cnt[30:2]==2) struct_asc <= '{e0:1, e1:2, e2:3, e3:4}; + else if (cnt[30:2]==3) struct_asc <= '{e3:6, e2:4, e1:2, e0:0}; // verilator lint_off WIDTH - else if (cnt[30:2]==4) struct_lt <= '{default:13}; - else if (cnt[30:2]==5) struct_lt <= '{e2:8'haa, default:1}; - else if (cnt[30:2]==6) struct_lt <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; + else if (cnt[30:2]==4) struct_asc <= '{default:13}; + else if (cnt[30:2]==5) struct_asc <= '{e2:8'haa, default:1}; + else if (cnt[30:2]==6) struct_asc <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; // verilator lint_on WIDTH end else if (cnt[1:0]==2'd2) begin // chack array agains expected value - if (cnt[30:2]==0) begin if (struct_lt !== 15'b0_00_0000_00000000) begin $display("%b", struct_lt); $stop(); end end - else if (cnt[30:2]==1) begin if (struct_lt !== 15'b0_01_0010_00000011) begin $display("%b", struct_lt); $stop(); end end - else if (cnt[30:2]==2) begin if (struct_lt !== 15'b1_10_0011_00000100) begin $display("%b", struct_lt); $stop(); end end - else if (cnt[30:2]==3) begin if (struct_lt !== 15'b0_10_0100_00000110) begin $display("%b", struct_lt); $stop(); end end - else if (cnt[30:2]==4) begin if (struct_lt !== 15'b1_01_1101_00001101) begin $display("%b", struct_lt); $stop(); end end - else if (cnt[30:2]==5) begin if (struct_lt !== 15'b1_01_1010_00000001) begin $display("%b", struct_lt); $stop(); end end - else if (cnt[30:2]==6) begin if (struct_lt !== 15'b1_10_1011_00011100) begin $display("%b", struct_lt); $stop(); end end + if (cnt[30:2]==0) begin if (struct_asc !== 15'b0_00_0000_00000000) begin $display("%b", struct_asc); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_asc !== 15'b0_01_0010_00000011) begin $display("%b", struct_asc); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_asc !== 15'b1_10_0011_00000100) begin $display("%b", struct_asc); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_asc !== 15'b0_10_0100_00000110) begin $display("%b", struct_asc); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_asc !== 15'b1_01_1101_00001101) begin $display("%b", struct_asc); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_asc !== 15'b1_01_1010_00000001) begin $display("%b", struct_asc); $stop(); end end + else if (cnt[30:2]==6) begin if (struct_asc !== 15'b1_10_1011_00011100) begin $display("%b", struct_asc); $stop(); end end end endmodule diff --git a/test_regress/t/t_struct_packed_write_read.v b/test_regress/t/t_struct_packed_write_read.v index 7616b1593..fa7761d7d 100644 --- a/test_regress/t/t_struct_packed_write_read.v +++ b/test_regress/t/t_struct_packed_write_read.v @@ -19,17 +19,17 @@ module t (/*AUTOARG*/ logic [1:0] e1; logic [3:0] e2; logic [7:0] e3; - } struct_bg; // big endian structure - /* verilator lint_off LITENDIAN */ + } struct_dsc; // descending range structure + /* verilator lint_off ASCRANGE */ struct packed { logic e0; logic [0:1] e1; logic [0:3] e2; logic [0:7] e3; - } struct_lt; // little endian structure - /* verilator lint_on LITENDIAN */ + } struct_asc; // ascending range structure + /* verilator lint_on ASCRANGE */ - localparam WS = 15; // $bits(struct_bg) + localparam WS = 15; // $bits(struct_dsc) integer cnt = 0; @@ -46,76 +46,76 @@ module t (/*AUTOARG*/ $finish; end - // big endian + // descending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) - if (cnt[30:2]==0) struct_bg <= '0; - else if (cnt[30:2]==1) struct_bg <= '0; - else if (cnt[30:2]==2) struct_bg <= '0; - else if (cnt[30:2]==3) struct_bg <= '0; - else if (cnt[30:2]==4) struct_bg <= '0; - else if (cnt[30:2]==5) struct_bg <= '0; + if (cnt[30:2]==0) struct_dsc <= '0; + else if (cnt[30:2]==1) struct_dsc <= '0; + else if (cnt[30:2]==2) struct_dsc <= '0; + else if (cnt[30:2]==3) struct_dsc <= '0; + else if (cnt[30:2]==4) struct_dsc <= '0; + else if (cnt[30:2]==5) struct_dsc <= '0; end else if (cnt[1:0]==2'd1) begin // write value to structure if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) struct_bg <= '1; - else if (cnt[30:2]==2) struct_bg.e0 <= '1; - else if (cnt[30:2]==3) struct_bg.e1 <= '1; - else if (cnt[30:2]==4) struct_bg.e2 <= '1; - else if (cnt[30:2]==5) struct_bg.e3 <= '1; + else if (cnt[30:2]==1) struct_dsc <= '1; + else if (cnt[30:2]==2) struct_dsc.e0 <= '1; + else if (cnt[30:2]==3) struct_dsc.e1 <= '1; + else if (cnt[30:2]==4) struct_dsc.e2 <= '1; + else if (cnt[30:2]==5) struct_dsc.e3 <= '1; end else if (cnt[1:0]==2'd2) begin // check structure value - if (cnt[30:2]==0) begin if (struct_bg !== 15'b000000000000000) begin $display("%b", struct_bg); $stop(); end end - else if (cnt[30:2]==1) begin if (struct_bg !== 15'b111111111111111) begin $display("%b", struct_bg); $stop(); end end - else if (cnt[30:2]==2) begin if (struct_bg !== 15'b100000000000000) begin $display("%b", struct_bg); $stop(); end end - else if (cnt[30:2]==3) begin if (struct_bg !== 15'b011000000000000) begin $display("%b", struct_bg); $stop(); end end - else if (cnt[30:2]==4) begin if (struct_bg !== 15'b000111100000000) begin $display("%b", struct_bg); $stop(); end end - else if (cnt[30:2]==5) begin if (struct_bg !== 15'b000000011111111) begin $display("%b", struct_bg); $stop(); end end + if (cnt[30:2]==0) begin if (struct_dsc !== 15'b000000000000000) begin $display("%b", struct_dsc); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_dsc !== 15'b111111111111111) begin $display("%b", struct_dsc); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_dsc !== 15'b100000000000000) begin $display("%b", struct_dsc); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_dsc !== 15'b011000000000000) begin $display("%b", struct_dsc); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_dsc !== 15'b000111100000000) begin $display("%b", struct_dsc); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_dsc !== 15'b000000011111111) begin $display("%b", struct_dsc); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from structure (not a very good test for now) - if (cnt[30:2]==0) begin if (struct_bg !== {WS{1'b0}}) $stop(); end - else if (cnt[30:2]==1) begin if (struct_bg !== {WS{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (struct_bg.e0 !== { 1{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (struct_bg.e1 !== { 2{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (struct_bg.e2 !== { 4{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (struct_bg.e3 !== { 8{1'b1}}) $stop(); end + if (cnt[30:2]==0) begin if (struct_dsc !== {WS{1'b0}}) $stop(); end + else if (cnt[30:2]==1) begin if (struct_dsc !== {WS{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (struct_dsc.e0 !== { 1{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (struct_dsc.e1 !== { 2{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (struct_dsc.e2 !== { 4{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (struct_dsc.e3 !== { 8{1'b1}}) $stop(); end end - // little endian + // ascending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) - if (cnt[30:2]==0) struct_lt <= '0; - else if (cnt[30:2]==1) struct_lt <= '0; - else if (cnt[30:2]==2) struct_lt <= '0; - else if (cnt[30:2]==3) struct_lt <= '0; - else if (cnt[30:2]==4) struct_lt <= '0; - else if (cnt[30:2]==5) struct_lt <= '0; + if (cnt[30:2]==0) struct_asc <= '0; + else if (cnt[30:2]==1) struct_asc <= '0; + else if (cnt[30:2]==2) struct_asc <= '0; + else if (cnt[30:2]==3) struct_asc <= '0; + else if (cnt[30:2]==4) struct_asc <= '0; + else if (cnt[30:2]==5) struct_asc <= '0; end else if (cnt[1:0]==2'd1) begin // write value to structure if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) struct_lt <= '1; - else if (cnt[30:2]==2) struct_lt.e0 <= '1; - else if (cnt[30:2]==3) struct_lt.e1 <= '1; - else if (cnt[30:2]==4) struct_lt.e2 <= '1; - else if (cnt[30:2]==5) struct_lt.e3 <= '1; + else if (cnt[30:2]==1) struct_asc <= '1; + else if (cnt[30:2]==2) struct_asc.e0 <= '1; + else if (cnt[30:2]==3) struct_asc.e1 <= '1; + else if (cnt[30:2]==4) struct_asc.e2 <= '1; + else if (cnt[30:2]==5) struct_asc.e3 <= '1; end else if (cnt[1:0]==2'd2) begin // check structure value - if (cnt[30:2]==0) begin if (struct_lt !== 15'b000000000000000) begin $display("%b", struct_lt); $stop(); end end - else if (cnt[30:2]==1) begin if (struct_lt !== 15'b111111111111111) begin $display("%b", struct_lt); $stop(); end end - else if (cnt[30:2]==2) begin if (struct_lt !== 15'b100000000000000) begin $display("%b", struct_lt); $stop(); end end - else if (cnt[30:2]==3) begin if (struct_lt !== 15'b011000000000000) begin $display("%b", struct_lt); $stop(); end end - else if (cnt[30:2]==4) begin if (struct_lt !== 15'b000111100000000) begin $display("%b", struct_lt); $stop(); end end - else if (cnt[30:2]==5) begin if (struct_lt !== 15'b000000011111111) begin $display("%b", struct_lt); $stop(); end end + if (cnt[30:2]==0) begin if (struct_asc !== 15'b000000000000000) begin $display("%b", struct_asc); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_asc !== 15'b111111111111111) begin $display("%b", struct_asc); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_asc !== 15'b100000000000000) begin $display("%b", struct_asc); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_asc !== 15'b011000000000000) begin $display("%b", struct_asc); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_asc !== 15'b000111100000000) begin $display("%b", struct_asc); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_asc !== 15'b000000011111111) begin $display("%b", struct_asc); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from structure (not a very good test for now) - if (cnt[30:2]==0) begin if (struct_lt !== {WS{1'b0}}) $stop(); end - else if (cnt[30:2]==1) begin if (struct_lt !== {WS{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (struct_lt.e0 !== { 1{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (struct_lt.e1 !== { 2{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (struct_lt.e2 !== { 4{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (struct_lt.e3 !== { 8{1'b1}}) $stop(); end + if (cnt[30:2]==0) begin if (struct_asc !== {WS{1'b0}}) $stop(); end + else if (cnt[30:2]==1) begin if (struct_asc !== {WS{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (struct_asc.e0 !== { 1{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (struct_asc.e1 !== { 2{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (struct_asc.e2 !== { 4{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (struct_asc.e3 !== { 8{1'b1}}) $stop(); end end endmodule diff --git a/test_regress/t/t_sys_readmem.v b/test_regress/t/t_sys_readmem.v index ca79d8b0c..98a025ee8 100644 --- a/test_regress/t/t_sys_readmem.v +++ b/test_regress/t/t_sys_readmem.v @@ -14,7 +14,7 @@ module t; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE reg [5:0] binary_string [2:15]; reg [5:0] binary_nostart [2:15]; reg [5:0] binary_start [0:15]; @@ -30,7 +30,7 @@ module t; reg [(32*6)-1:0] hex_align_tmp [0:15]; string fns_tmp; `endif - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE integer i; diff --git a/test_regress/t/t_trace_litendian.out b/test_regress/t/t_trace_ascendingrange.out similarity index 100% rename from test_regress/t/t_trace_litendian.out rename to test_regress/t/t_trace_ascendingrange.out diff --git a/test_regress/t/t_trace_litendian.pl b/test_regress/t/t_trace_ascendingrange.pl similarity index 92% rename from test_regress/t/t_trace_litendian.pl rename to test_regress/t/t_trace_ascendingrange.pl index 3ecfa6bc6..aedb9ce36 100755 --- a/test_regress/t/t_trace_litendian.pl +++ b/test_regress/t/t_trace_ascendingrange.pl @@ -14,7 +14,7 @@ scenarios(simulator => 1); # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # Strangely, asking for more threads makes it go away. compile( - verilator_flags2 => ['--cc --trace --trace-params -Wno-LITENDIAN'], + verilator_flags2 => ['--cc --trace --trace-params -Wno-ASCRANGE'], threads => $Self->{vltmt} ? 6 : 1 ); diff --git a/test_regress/t/t_trace_litendian.v b/test_regress/t/t_trace_ascendingrange.v similarity index 100% rename from test_regress/t/t_trace_litendian.v rename to test_regress/t/t_trace_ascendingrange.v diff --git a/test_regress/t/t_trace_litendian_fst.out b/test_regress/t/t_trace_ascendingrange_fst.out similarity index 100% rename from test_regress/t/t_trace_litendian_fst.out rename to test_regress/t/t_trace_ascendingrange_fst.out diff --git a/test_regress/t/t_trace_litendian_fst.pl b/test_regress/t/t_trace_ascendingrange_fst.pl similarity index 88% rename from test_regress/t/t_trace_litendian_fst.pl rename to test_regress/t/t_trace_ascendingrange_fst.pl index 754bea6fd..54e75cec9 100755 --- a/test_regress/t/t_trace_litendian_fst.pl +++ b/test_regress/t/t_trace_ascendingrange_fst.pl @@ -10,13 +10,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(simulator => 1); -top_filename("t/t_trace_litendian.v"); +top_filename("t/t_trace_ascendingrange.v"); # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # Strangely, asking for more threads makes it go away. compile( - verilator_flags2 => ['--cc --trace-fst --trace-params -Wno-LITENDIAN'], + verilator_flags2 => ['--cc --trace-fst --trace-params -Wno-ASCRANGE'], threads => $Self->{vltmt} ? 6 : 1 ); diff --git a/test_regress/t/t_trace_litendian_fst_sc.out b/test_regress/t/t_trace_ascendingrange_fst_sc.out similarity index 100% rename from test_regress/t/t_trace_litendian_fst_sc.out rename to test_regress/t/t_trace_ascendingrange_fst_sc.out diff --git a/test_regress/t/t_trace_litendian_fst_sc.pl b/test_regress/t/t_trace_ascendingrange_fst_sc.pl similarity index 94% rename from test_regress/t/t_trace_litendian_fst_sc.pl rename to test_regress/t/t_trace_ascendingrange_fst_sc.pl index 40366a231..864a69b97 100755 --- a/test_regress/t/t_trace_litendian_fst_sc.pl +++ b/test_regress/t/t_trace_ascendingrange_fst_sc.pl @@ -14,13 +14,13 @@ if (!$Self->have_sc) { skip("No SystemC installed"); } else { - top_filename("t/t_trace_litendian.v"); + top_filename("t/t_trace_ascendingrange.v"); # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # Strangely, asking for more threads makes it go away. compile( - verilator_flags2 => ['--sc --trace-fst --trace-params -Wno-LITENDIAN'], + verilator_flags2 => ['--sc --trace-fst --trace-params -Wno-ASCRANGE'], threads => $Self->{vltmt} ? 6 : 1 ); diff --git a/test_regress/t/t_trace_public.v b/test_regress/t/t_trace_public.v index c3d0c9603..e6ea04953 100644 --- a/test_regress/t/t_trace_public.v +++ b/test_regress/t/t_trace_public.v @@ -68,11 +68,11 @@ module little ( input clk ); - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE reg [0:7] i8; initial i8 = '0; reg [1:49] i48; initial i48 = '0; reg [63:190] i128; initial i128 = '0; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE always @ (posedge clk) begin i8 <= ~i8; diff --git a/test_regress/t/t_typedef_array.v b/test_regress/t/t_typedef_array.v index 018d6abbd..8fe08ffcc 100644 --- a/test_regress/t/t_typedef_array.v +++ b/test_regress/t/t_typedef_array.v @@ -8,9 +8,9 @@ typedef logic logic_alias_t; module t; logic_alias_t [6:1] signal; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE logic_alias_t [1:6] signal2; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE initial begin signal[6:1] = 'b100001; diff --git a/test_regress/t/t_vpi_var.v b/test_regress/t/t_vpi_var.v index ebc707eb3..80188af11 100644 --- a/test_regress/t/t_vpi_var.v +++ b/test_regress/t/t_vpi_var.v @@ -30,9 +30,9 @@ extern "C" int mon_check(); reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND /*verilator public_flat_rw*/; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE reg [31:0] count /*verilator public_flat_rd */; reg [31:0] half_count /*verilator public_flat_rd */; diff --git a/test_regress/t/t_vpi_var2.v b/test_regress/t/t_vpi_var2.v index ca24c06f2..dc04a1c7f 100644 --- a/test_regress/t/t_vpi_var2.v +++ b/test_regress/t/t_vpi_var2.v @@ -39,11 +39,11 @@ extern "C" int mon_check(); reg [2:1] twoone; reg [2:1] fourthreetwoone[4:3]; reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; - // verilator lint_off LITENDIAN + // verilator lint_off ASCRANGE reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk)*/; /*verilator public_off*/ reg invisible1; - // verilator lint_on LITENDIAN + // verilator lint_on ASCRANGE /*verilator public_flat_rd_on*/ reg [31:0] count;