From 28e19cef90aea3c4f2ee241a3266220c4db8f392 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 23 Feb 2020 19:33:37 -0500 Subject: [PATCH] Fix undeclared VL_SHIFTR_WWQ, #2114. --- Changes | 8 +- include/verilated.h | 11 +++ test_regress/t/t_math_shift.v | 159 +++++++++++++++++----------------- 3 files changed, 98 insertions(+), 80 deletions(-) diff --git a/Changes b/Changes index cf3e97ac0..b54ee2cb8 100644 --- a/Changes +++ b/Changes @@ -5,8 +5,12 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 4.029 devel -*** Add assertOn check for assert. [Tobias Wölfel] -*** Add +verilator+noassert flag to disable assert checking. [Tobias Wölfel] +*** Add +verilator+noassert flag to disable assertion checking. [Tobias Wölfel] + +*** Add check for assertOn for asserts, #2162. [Tobias Wölfel] + +**** Fix undeclared VL_SHIFTR_WWQ, #2114. [Alex Solomatnikov] + * Verilator 4.028 2020-02-08 diff --git a/include/verilated.h b/include/verilated.h index 3c0b0f9d4..c039d3878 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -2013,6 +2013,12 @@ static inline WDataOutP VL_SHIFTR_WWW(int obits, int lbits, int rbits, } return VL_SHIFTR_WWI(obits, lbits, 32, owp, lwp, rwp[0]); } +static inline WDataOutP VL_SHIFTR_WWQ(int obits, int lbits, int rbits, + WDataOutP owp, WDataInP lwp, QData rd) VL_MT_SAFE { + WData rwp[VL_WQ_WORDS_E]; VL_SET_WQ(rwp, rd); + return VL_SHIFTR_WWW(obits, lbits, rbits, owp, lwp, rwp); +} + static inline IData VL_SHIFTR_IIW(int obits, int, int rbits, IData lhs, WDataInP rwp) VL_MT_SAFE { for (int i = 1; i < VL_WORDS_I(rbits); ++i) { if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more @@ -2098,6 +2104,11 @@ static inline WDataOutP VL_SHIFTRS_WWW(int obits, int lbits, int rbits, } return VL_SHIFTRS_WWI(obits, lbits, 32, owp, lwp, rwp[0]); } +static inline WDataOutP VL_SHIFTRS_WWQ(int obits, int lbits, int rbits, + WDataOutP owp, WDataInP lwp, QData rd) VL_MT_SAFE { + WData rwp[VL_WQ_WORDS_E]; VL_SET_WQ(rwp, rd); + return VL_SHIFTRS_WWW(obits, lbits, rbits, owp, lwp, rwp); +} static inline IData VL_SHIFTRS_IIW(int obits, int lbits, int rbits, IData lhs, WDataInP rwp) VL_MT_SAFE { EData overshift = 0; // Huge shift 1>>32 or more diff --git a/test_regress/t/t_math_shift.v b/test_regress/t/t_math_shift.v index 12de70145..dfc282320 100644 --- a/test_regress/t/t_math_shift.v +++ b/test_regress/t/t_math_shift.v @@ -5,7 +5,7 @@ module t (/*AUTOARG*/ // Outputs - ign, ign2, ign3, + ign, ign2, ign3, ign4, ign4s, // Inputs clk ); @@ -23,21 +23,24 @@ module t (/*AUTOARG*/ localparam [3:0] PBIG29 = 4'b1 << 33'h100000000; // verilator lint_on WIDTH - reg [31:0] right; - reg [31:0] left; - reg [P64-1:0] qright; - reg [P64-1:0] qleft; - reg [31:0] amt; + reg [31:0] right; + reg [31:0] left; + reg [P64-1:0] qright; + reg [P64-1:0] qleft; + reg [31:0] amt; assign ign = {31'h0, clk} >>> 4'bx; // bug760 assign ign2 = {amt[1:0] >> {22{amt[5:2]}}, amt[1:0] << (0 <<< amt[5:2])}; // bug1174 assign ign3 = {amt[1:0] >> {22{amt[5:2]}}, - amt[1:0] >> {11{amt[5:2]}}, - $signed(amt[1:0]) >>> {22{amt[5:2]}}, - $signed(amt[1:0]) >>> {11{amt[5:2]}}, - amt[1:0] << {22{amt[5:2]}}, + amt[1:0] >> {11{amt[5:2]}}, + $signed(amt[1:0]) >>> {22{amt[5:2]}}, + $signed(amt[1:0]) >>> {11{amt[5:2]}}, + amt[1:0] << {22{amt[5:2]}}, amt[1:0] << {11{amt[5:2]}}}; + wire [95:0] wamt = {amt,amt,amt}; + output wire [95:0] ign4 = wamt >> {11{amt[5:2]}}; + output wire signed [95:0] ign4s = $signed(wamt) >>> {11{amt[5:2]}}; always @* begin right = 32'h819b018a >> amt; @@ -49,76 +52,76 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("%d %x %x %x %x\n", cyc, left, right, qleft, qright); + $write("%d %x %x %x %x\n", cyc, left, right, qleft, qright); `endif - if (cyc==1) begin - amt <= 32'd0; - if (P64 != 64) $stop; - if (5'b10110>>2 != 5'b00101) $stop; - if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness - if (5'b10110<<2 != 5'b11000) $stop; - if (5'b10110<<<2 != 5'b11000) $stop; - if (5'sb10110>>2 != 5'sb00101) $stop; - if (5'sb10110>>>2 != 5'sb11101) $stop; - if (5'sb10110<<2 != 5'sb11000) $stop; - if (5'sb10110<<<2 != 5'sb11000) $stop; - // Allow >64 bit shifts if the shift amount is a constant - if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; - end - if (cyc==2) begin - amt <= 32'd28; - if (left != 32'h819b018a) $stop; - if (right != 32'h819b018a) $stop; - if (qleft != 64'hf784bf8f_12734089) $stop; - if (qright != 64'hf784bf8f_12734089) $stop; - end - if (cyc==3) begin - amt <= 32'd31; - if (left != 32'ha0000000) $stop; - if (right != 32'h8) $stop; - if (qleft != 64'h0000000f784bf8f1) $stop; - if (qright != 64'h0000000f784bf8f1) $stop; - end - if (cyc==4) begin - amt <= 32'd32; - if (left != 32'h0) $stop; - if (right != 32'h1) $stop; - if (qleft != 64'h00000001ef097f1e) $stop; - if (qright != 64'h00000001ef097f1e) $stop; - end - if (cyc==5) begin - amt <= 32'd33; - if (left != 32'h0) $stop; - if (right != 32'h0) $stop; - if (qleft != 64'h00000000f784bf8f) $stop; - if (qright != 64'h00000000f784bf8f) $stop; - end - if (cyc==6) begin - amt <= 32'd64; - if (left != 32'h0) $stop; - if (right != 32'h0) $stop; - if (qleft != 64'h000000007bc25fc7) $stop; - if (qright != 64'h000000007bc25fc7) $stop; - end - if (cyc==7) begin - amt <= 32'd128; - if (left != 32'h0) $stop; - if (right != 32'h0) $stop; - if (qleft != 64'h0) $stop; - if (qright != 64'h0) $stop; - end - if (cyc==8) begin - if (left != 32'h0) $stop; - if (right != 32'h0) $stop; - if (qleft != 64'h0) $stop; - if (qright != 64'h0) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc==1) begin + amt <= 32'd0; + if (P64 != 64) $stop; + if (5'b10110>>2 != 5'b00101) $stop; + if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness + if (5'b10110<<2 != 5'b11000) $stop; + if (5'b10110<<<2 != 5'b11000) $stop; + if (5'sb10110>>2 != 5'sb00101) $stop; + if (5'sb10110>>>2 != 5'sb11101) $stop; + if (5'sb10110<<2 != 5'sb11000) $stop; + if (5'sb10110<<<2 != 5'sb11000) $stop; + // Allow >64 bit shifts if the shift amount is a constant + if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; + end + if (cyc==2) begin + amt <= 32'd28; + if (left != 32'h819b018a) $stop; + if (right != 32'h819b018a) $stop; + if (qleft != 64'hf784bf8f_12734089) $stop; + if (qright != 64'hf784bf8f_12734089) $stop; + end + if (cyc==3) begin + amt <= 32'd31; + if (left != 32'ha0000000) $stop; + if (right != 32'h8) $stop; + if (qleft != 64'h0000000f784bf8f1) $stop; + if (qright != 64'h0000000f784bf8f1) $stop; + end + if (cyc==4) begin + amt <= 32'd32; + if (left != 32'h0) $stop; + if (right != 32'h1) $stop; + if (qleft != 64'h00000001ef097f1e) $stop; + if (qright != 64'h00000001ef097f1e) $stop; + end + if (cyc==5) begin + amt <= 32'd33; + if (left != 32'h0) $stop; + if (right != 32'h0) $stop; + if (qleft != 64'h00000000f784bf8f) $stop; + if (qright != 64'h00000000f784bf8f) $stop; + end + if (cyc==6) begin + amt <= 32'd64; + if (left != 32'h0) $stop; + if (right != 32'h0) $stop; + if (qleft != 64'h000000007bc25fc7) $stop; + if (qright != 64'h000000007bc25fc7) $stop; + end + if (cyc==7) begin + amt <= 32'd128; + if (left != 32'h0) $stop; + if (right != 32'h0) $stop; + if (qleft != 64'h0) $stop; + if (qright != 64'h0) $stop; + end + if (cyc==8) begin + if (left != 32'h0) $stop; + if (right != 32'h0) $stop; + if (qleft != 64'h0) $stop; + if (qright != 64'h0) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule