From 28901261106ddfdaf28f86b4f8dce6241640718c Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Mon, 9 Sep 2024 14:09:29 +0100
Subject: [PATCH] Remove out of range Sel in V3Unknown (#5443)

Fixes #5393
---
 src/V3DfgPeephole.cpp                |  2 +-
 src/V3Unknown.cpp                    |  6 ++++--
 test_regress/t/t_out_of_range_sel.py | 16 ++++++++++++++++
 test_regress/t/t_out_of_range_sel.v  | 25 +++++++++++++++++++++++++
 4 files changed, 46 insertions(+), 3 deletions(-)
 create mode 100755 test_regress/t/t_out_of_range_sel.py
 create mode 100644 test_regress/t/t_out_of_range_sel.v

diff --git a/src/V3DfgPeephole.cpp b/src/V3DfgPeephole.cpp
index 649545c5e..531d5c35b 100644
--- a/src/V3DfgPeephole.cpp
+++ b/src/V3DfgPeephole.cpp
@@ -750,7 +750,7 @@ class V3DfgPeephole final : public DfgVisitor {
 
         // Full width select, replace with the source.
         if (fromp->width() == width) {
-            UASSERT_OBJ(lsb == 0, fromp, "OOPS");
+            UASSERT_OBJ(lsb == 0, fromp, "Out of range select should have been fixed up earlier");
             APPLYING(REMOVE_FULL_WIDTH_SEL) {
                 replace(vtxp, fromp);
                 return;
diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp
index 632793693..0b89d02e4 100644
--- a/src/V3Unknown.cpp
+++ b/src/V3Unknown.cpp
@@ -410,8 +410,10 @@ class UnknownVisitor final : public VNVisitor {
                 nodep->unlinkFrBack(&replaceHandle);
                 V3Number xnum{nodep, nodep->width()};
                 xnum.setAllBitsX();
-                AstNode* const newp = new AstCondBound{nodep->fileline(), condp, nodep,
-                                                       new AstConst{nodep->fileline(), xnum}};
+                AstNodeExpr* const xexprp = new AstConst{nodep->fileline(), xnum};
+                AstNodeExpr* const newp
+                    = condp->isZero() ? xexprp
+                                      : new AstCondBound{nodep->fileline(), condp, nodep, xexprp};
                 if (debug() >= 9) newp->dumpTree("-        _new: ");
                 // Link in conditional
                 replaceHandle.relink(newp);
diff --git a/test_regress/t/t_out_of_range_sel.py b/test_regress/t/t_out_of_range_sel.py
new file mode 100755
index 000000000..9fff37b43
--- /dev/null
+++ b/test_regress/t/t_out_of_range_sel.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=["-Wno-SELRANGE"])
+
+test.passes()
diff --git a/test_regress/t/t_out_of_range_sel.v b/test_regress/t/t_out_of_range_sel.v
new file mode 100644
index 000000000..7ecbbe6fa
--- /dev/null
+++ b/test_regress/t/t_out_of_range_sel.v
@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module serial_adder(
+  input  cin,
+  output cout
+);
+    localparam WIDTH = 8;
+
+    wire [WIDTH:0] c;
+
+    generate for (genvar i = 0; i < WIDTH; i++)
+        full_adder fa(c[i+1]);
+    endgenerate
+
+    assign c[0] = cin;
+    assign cout = c[WIDTH+1]; // intentional out-of-range
+
+endmodule
+
+module full_adder (output cout);
+endmodule