diff --git a/src/V3MemberMap.h b/src/V3MemberMap.h
index 2a9561a12..63e847d1b 100644
--- a/src/V3MemberMap.h
+++ b/src/V3MemberMap.h
@@ -37,6 +37,9 @@ class VMemberMap final {
     using MemberMap = std::map<std::string, AstNode*>;
     using NodeMap = std::map<const AstNode*, MemberMap>;
     NodeMap m_map;  // Map of nodes being tracked
+
+    VL_DEFINE_DEBUG_FUNCTIONS;
+
 public:
     void clear() { m_map.clear(); }
     // Find 'name' under 'nodep', caching nodep's children if needed
@@ -80,7 +83,7 @@ private:
                     for (AstNode* blockp = scopep->blocksp(); blockp; blockp = blockp->nextp()) {
                         memberInsert(mmapr, blockp);
                     }
-                } else {
+                } else if (!VN_IS(itemp, Always)) {
                     memberInsert(mmapr, itemp);
                 }
             }
diff --git a/test_regress/t/t_interface_ndup_member.py b/test_regress/t/t_interface_ndup_member.py
new file mode 100755
index 000000000..cca4c9e73
--- /dev/null
+++ b/test_regress/t/t_interface_ndup_member.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint()
+
+test.passes()
diff --git a/test_regress/t/t_interface_ndup_member.v b/test_regress/t/t_interface_ndup_member.v
new file mode 100644
index 000000000..05371c9a9
--- /dev/null
+++ b/test_regress/t/t_interface_ndup_member.v
@@ -0,0 +1,40 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+interface backdoor_if;
+  logic [15:0] signal1;
+  logic [15:0] signal2;
+  assign signal1 = t.child1.sub1.signal3;
+  assign signal2 = t.child2.sub2.signal3;
+  function int get_size_signal1();
+    return $bits(signal1);
+  endfunction
+endinterface
+
+module sub #(
+    parameter DELAY = 10
+) ();
+  logic [15:0] signal3;
+endmodule
+
+package tests_pkg;
+  class signal1_backdoor;
+    virtual backdoor_if vif;
+    virtual function int get_signal_size();
+      return vif.get_size_signal1();
+    endfunction
+  endclass
+endpackage
+
+module child ();
+  sub #(10) sub1 ();
+  sub #(25) sub2 ();
+endmodule
+
+module t;
+  child child1 ();
+  child child2 ();
+endmodule