From 27953e26b6af1a580ada6c160531a560b407337b Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 8 May 2020 07:35:54 -0400
Subject: [PATCH] Backout example change.

---
 test_regress/t/t_EXAMPLE.v | 88 ++++++++++++++++++++++++++++++++------
 1 file changed, 75 insertions(+), 13 deletions(-)

diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v
index c3667e195..4e1051614 100644
--- a/test_regress/t/t_EXAMPLE.v
+++ b/test_regress/t/t_EXAMPLE.v
@@ -16,20 +16,82 @@
 // any use, without warranty, 2020 ____YOUR_NAME_HERE____.
 // SPDX-License-Identifier: CC0-1.0
 
-module t(/*AUTOARG*/);
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
 
-   initial begin
-      // verilator lint_off WIDTH
-      parameter [3:0] val0 = 32'b000x;
-      parameter [3:0] val1 = 32'b000z;
-      parameter [3:0] val2 = 32'b00xz;
-      parameter [3:0] val3 = 32'b0000;
-      $display(":assert: (%d == 1)", $isunknown(val0));
-      $display(":assert: (%d == 1)", $isunknown(val1));
-      $display(":assert: (%d == 1)", $isunknown(val2));
-      $display(":assert: (%d == 0)", $isunknown(val3));
-      $write("*-* All Finished *-*\n");
-      $finish;
+   integer cyc=0;
+   reg [63:0] crc;
+   reg [63:0] sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [31:0] in = crc[31:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0]          out;                    // From test of Test.v
+   // End of automatics
+
+   Test test(/*AUTOINST*/
+             // Outputs
+             .out                       (out[31:0]),
+             // Inputs
+             .clk                       (clk),
+             .in                        (in[31:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {32'h0, out};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc == 0) begin
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
+         sum <= '0;
+      end
+      else if (cyc < 10) begin
+         sum <= '0;
+      end
+      else if (cyc < 90) begin
+      end
+      else if (cyc == 99) begin
+         $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h4afe43fb79d7b71e
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
    end
 
 endmodule
+
+module Test(/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in
+   );
+
+   // Replace this module with the device under test.
+   //
+   // Change the code in the t module to apply values to the inputs and
+   // merge the output values into the result vector.
+
+   input clk;
+   input [31:0] in;
+   output reg [31:0] out;
+
+   always @(posedge clk) begin
+      out <= in;
+   end
+endmodule