diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 77ff135ed..86bee331e 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -688,6 +688,7 @@ sub new {
         $self->{top_shell_filename} = "$self->{obj_dir}/$self->{VM_PREFIX}__top.v";
     }
     $self->{pli_filename} ||= $self->{name} . ".cpp";
+
     return $self;
 }
 
@@ -964,6 +965,11 @@ sub compile {
 
     compile_vlt_cmd(%param);
 
+    my $define_opt = defineOpt($self->{xsim});
+    if (join(' ', @{$self->{v_flags}}) !~ /TEST_DUMPFILE/) {
+        push @{$self->{v_flags}}, ($define_opt . "TEST_DUMPFILE=" . $self->trace_filename);
+    }
+
     if (!$param{make_top_shell}) {
         $param{top_shell_filename}
         = $self->{top_shell_filename} = "";
diff --git a/test_regress/t/t_gen_intdot2.v b/test_regress/t/t_gen_intdot2.v
index b496c4f05..785d9dd13 100644
--- a/test_regress/t/t_gen_intdot2.v
+++ b/test_regress/t/t_gen_intdot2.v
@@ -36,7 +36,7 @@ module t (/*AUTOARG*/
 //`define WAVES
 `ifdef WAVES
    initial begin
-      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+      $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
       $dumpvars(12, t);
    end
 `endif
diff --git a/test_regress/t/t_preproc_defines.out b/test_regress/t/t_preproc_defines.out
index e410899bc..58f7d85b4 100644
--- a/test_regress/t/t_preproc_defines.out
+++ b/test_regress/t/t_preproc_defines.out
@@ -16,6 +16,7 @@
 `define SV_COV_STOP 1
 `define SV_COV_TOGGLE 23
 `define SYSTEMVERILOG 1
+`define TEST_DUMPFILE obj_vlt/t_preproc_defines/simx.vcd
 `define TEST_OBJ_DIR obj_vlt/t_preproc_defines
 `define VERILATOR 1
 `define WITH_ARG(a) (a)(a)
diff --git a/test_regress/t/t_timing_trace.v b/test_regress/t/t_timing_trace.v
index 25782e267..af789dbeb 100644
--- a/test_regress/t/t_timing_trace.v
+++ b/test_regress/t/t_timing_trace.v
@@ -18,7 +18,7 @@ module t;
     logic d;
 
     initial begin
-        $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+        $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
         $dumpvars;
         forever clk = #CLK_HALF_PERIOD ~clk;
     end
diff --git a/test_regress/t/t_trace_binary.v b/test_regress/t/t_trace_binary.v
index 445c2b375..b25c30841 100644
--- a/test_regress/t/t_trace_binary.v
+++ b/test_regress/t/t_trace_binary.v
@@ -10,7 +10,7 @@ module t(/*AUTOARG*/);
    int sig;
    initial begin
       sig = 10;
-      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+      $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
       $dumpvars();
       #20;
       sig = 20;
diff --git a/test_regress/t/t_trace_param_override.v b/test_regress/t/t_trace_param_override.v
index 072e94e33..fb5798f0a 100644
--- a/test_regress/t/t_trace_param_override.v
+++ b/test_regress/t/t_trace_param_override.v
@@ -12,7 +12,7 @@ module t #(
            ) (/*AUTOARG*/);
 
    initial begin
-      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+      $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
       $dumpvars;
 
       $write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_trace_timing1.v b/test_regress/t/t_trace_timing1.v
index 26aef7ea9..57afab182 100644
--- a/test_regress/t/t_trace_timing1.v
+++ b/test_regress/t/t_trace_timing1.v
@@ -14,7 +14,7 @@ module t(/*AUTOARG*/);
    logic clk;
 
    initial begin
-      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+      $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
       $dumpvars;
    end