diff --git a/Changes b/Changes index ef7c31fde..1156d9d9b 100644 --- a/Changes +++ b/Changes @@ -31,6 +31,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix first clock edge and --x-initial-edge, bug1327. [Rupert Swarbrick] +**** Fix compile error on tracing of string arrays, bug1338. [Iztok Jeras]. + * Verilator 3.926 2018-08-22 diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index 256133592..d75428222 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -198,7 +198,11 @@ private: && m_traVscp->dtypep()->skipRefp() == nodep) { // Nothing above this array // Simple 1-D array, use exising V3EmitC runtime loop rather than unrolling // This will put "(index)" at end of signal name for us - addTraceDecl(nodep->declRange(), 0); + if (m_traVscp->dtypep()->skipRefp()->isString()) { + addIgnore("Unsupported: strings"); + } else { + addTraceDecl(nodep->declRange(), 0); + } } else { // Unroll now, as have no other method to get right signal names AstNodeDType* subtypep = nodep->subDTypep()->skipRefp(); @@ -278,7 +282,7 @@ private: } virtual void visit(AstBasicDType* nodep) { if (m_traVscp) { - if (nodep->keyword()==AstBasicDTypeKwd::STRING) { + if (nodep->isString()) { addIgnore("Unsupported: strings"); } else { addTraceDecl(VNumRange(), 0); diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v index da3fd399f..732e813a4 100644 --- a/test_regress/t/t_trace_complex.v +++ b/test_regress/t/t_trace_complex.v @@ -68,7 +68,7 @@ module t (clk); v_arrp <= ~v_arrp; v_arrp_arrp <= ~v_arrp_arrp; v_real <= v_real + 0.1; - v_string <= "foo"; + v_string <= cyc[0] ? "foo" : "bar"; v_arr_real[0] <= v_arr_real[0] + 0.2; v_arr_real[1] <= v_arr_real[1] + 0.3; for (integer b=3; b<=4; b++) begin diff --git a/test_regress/t/t_trace_string.pl b/test_regress/t/t_trace_string.pl new file mode 100755 index 000000000..b6ba517f5 --- /dev/null +++ b/test_regress/t/t_trace_string.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ['--cc --trace'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_trace_string.v b/test_regress/t/t_trace_string.v new file mode 100644 index 000000000..c72b05099 --- /dev/null +++ b/test_regress/t/t_trace_string.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/); + + localparam string SVEC [0:7] = '{"zero", "one", "two", "three", "four", "five", "six", "seven"}; + + initial begin + $display("%s", SVEC[3'd1]); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_trace_string_lxt2.pl b/test_regress/t/t_trace_string_lxt2.pl new file mode 100755 index 000000000..2a4758cc9 --- /dev/null +++ b/test_regress/t/t_trace_string_lxt2.pl @@ -0,0 +1,23 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(simulator => 1); + +top_filename("t/t_trace_string.v"); + +compile( + verilator_flags2 => ['--cc --trace'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1;