From 2491f25da7ef8bec61963e52ec58ad1f8b72dd3a Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Thu, 22 May 2025 11:42:09 +0200 Subject: [PATCH] Add filtering type option in verilator_coverage (#6030) --- bin/verilator_coverage | 1 + docs/guide/exe_verilator_coverage.rst | 6 + include/verilated_cov.cpp | 4 + src/VlcMain.cpp | 1 + src/VlcOptions.h | 5 + src/VlcPoint.h | 31 +- src/VlcTop.cpp | 2 + test_regress/t/t_assert_ctl_arg.dat.out | 304 ++++++++-------- test_regress/t/t_cover_lib__1.out | 12 +- .../t/t_cover_lib__1_per_instance.out | 14 +- test_regress/t/t_cover_lib__2.out | 4 +- test_regress/t/t_cover_lib__3.out | 4 +- test_regress/t/t_cover_main.out | 2 +- test_regress/t/t_vlcov_data_e.dat | 226 ++++++++++++ test_regress/t/t_vlcov_data_f.dat | 157 ++++++++ test_regress/t/t_vlcov_opt_branch.info.out | 127 +++++++ test_regress/t/t_vlcov_opt_branch.py | 22 ++ test_regress/t/t_vlcov_opt_expr.info.out | 23 ++ test_regress/t/t_vlcov_opt_expr.py | 22 ++ test_regress/t/t_vlcov_opt_line.info.out | 87 +++++ test_regress/t/t_vlcov_opt_line.py | 22 ++ test_regress/t/t_vlcov_opt_toggle.info.out | 116 ++++++ test_regress/t/t_vlcov_opt_toggle.py | 22 ++ test_regress/t/t_vlcov_opt_user.info.out | 182 ++++++++++ test_regress/t/t_vlcov_opt_user.py | 22 ++ test_regress/t/t_vlcov_opt_wild.info.out | 334 ++++++++++++++++++ test_regress/t/t_vlcov_opt_wild.py | 22 ++ .../t/t_wrapper_context__top0.dat.out | 162 ++++----- .../t/t_wrapper_context__top1.dat.out | 162 ++++----- 29 files changed, 1755 insertions(+), 343 deletions(-) create mode 100644 test_regress/t/t_vlcov_data_e.dat create mode 100644 test_regress/t/t_vlcov_data_f.dat create mode 100644 test_regress/t/t_vlcov_opt_branch.info.out create mode 100755 test_regress/t/t_vlcov_opt_branch.py create mode 100644 test_regress/t/t_vlcov_opt_expr.info.out create mode 100755 test_regress/t/t_vlcov_opt_expr.py create mode 100644 test_regress/t/t_vlcov_opt_line.info.out create mode 100755 test_regress/t/t_vlcov_opt_line.py create mode 100644 test_regress/t/t_vlcov_opt_toggle.info.out create mode 100755 test_regress/t/t_vlcov_opt_toggle.py create mode 100644 test_regress/t/t_vlcov_opt_user.info.out create mode 100755 test_regress/t/t_vlcov_opt_user.py create mode 100644 test_regress/t/t_vlcov_opt_wild.info.out create mode 100755 test_regress/t/t_vlcov_opt_wild.py diff --git a/bin/verilator_coverage b/bin/verilator_coverage index e7f1f6be2..476da1b1a 100755 --- a/bin/verilator_coverage +++ b/bin/verilator_coverage @@ -170,6 +170,7 @@ L. --annotate-all All files should be shown. --annotate-min Minimum occurrence count for uncovered. --annotate-points Annotates info from each coverage point. + --filter-type Skips records of coverage types different than . --help Displays this message and version and exits. --rank Compute relative importance of tests. --unlink With --write, unlink all inputs diff --git a/docs/guide/exe_verilator_coverage.rst b/docs/guide/exe_verilator_coverage.rst index 11cd6e52a..c7db059c2 100644 --- a/docs/guide/exe_verilator_coverage.rst +++ b/docs/guide/exe_verilator_coverage.rst @@ -124,6 +124,12 @@ verilator_coverage Arguments This option should be used together with :option:`--annotate`. +.. option:: --filter-type + + Skips records of coverage types that matches with + Possible values are `toggle`, `line`, `branch`, `expr`, `user` and + a wildcard with `\*` or `?`. The default value is `\*`. + .. option:: --help Displays a help summary, the program version, and exits. diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index a9bc7c1cd..d81742199 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -390,6 +390,10 @@ public: hier = val; } else { // Print it + if (key == "page") { + const std::string type = val.substr(2, val.find('/') - 2); + name += keyValueFormatter(VL_CIK_TYPE, type); + } name += keyValueFormatter(key, val); } } diff --git a/src/VlcMain.cpp b/src/VlcMain.cpp index fbabc9b07..328359b25 100644 --- a/src/VlcMain.cpp +++ b/src/VlcMain.cpp @@ -68,6 +68,7 @@ void VlcOptions::parseOptsList(int argc, char** argv) { DECL_OPTION("-annotate-points", OnOff, &m_annotatePoints); DECL_OPTION("-debug", CbCall, []() { V3Error::debugDefault(3); }); DECL_OPTION("-debugi", CbVal, [](int v) { V3Error::debugDefault(v); }); + DECL_OPTION("-filter-type", Set, &m_filterType); DECL_OPTION("-rank", OnOff, &m_rank); DECL_OPTION("-unlink", OnOff, &m_unlink); DECL_OPTION("-V", CbCall, []() { diff --git a/src/VlcOptions.h b/src/VlcOptions.h index edd889957..21e06090b 100644 --- a/src/VlcOptions.h +++ b/src/VlcOptions.h @@ -20,6 +20,7 @@ #include "config_build.h" #include "verilatedos.h" +#include "VlcPoint.h" #include "config_rev.h" #include @@ -38,6 +39,7 @@ class VlcOptions final { bool m_annotateAll = false; // main switch: --annotate-all int m_annotateMin = 10; // main switch: --annotate-min I bool m_annotatePoints = false; // main switch: --annotate-points + string m_filterType = "*"; // main switch: --filter-type VlStringSet m_readFiles; // main switch: --read bool m_rank = false; // main switch: --rank bool m_unlink = false; // main switch: --unlink @@ -69,6 +71,9 @@ public: bool unlink() const { return m_unlink; } string writeFile() const { return m_writeFile; } string writeInfoFile() const { return m_writeInfoFile; } + bool isTypeMatch(const char* name) const { + return VString::wildmatch(VlcPoint::typeExtract(name), m_filterType); + } // METHODS (from main) static string version() VL_MT_DISABLED; diff --git a/src/VlcPoint.h b/src/VlcPoint.h index afb546f46..f26d10dde 100644 --- a/src/VlcPoint.h +++ b/src/VlcPoint.h @@ -61,20 +61,29 @@ public: return m_count >= threshi; } // KEY ACCESSORS - string filename() const { return keyExtract(VL_CIK_FILENAME); } - string comment() const { return keyExtract(VL_CIK_COMMENT); } - string hier() const { return keyExtract(VL_CIK_HIER); } - string type() const { return keyExtract(VL_CIK_TYPE); } - string thresh() const { return keyExtract(VL_CIK_THRESH); } // string as maybe "" - string linescov() const { return keyExtract(VL_CIK_LINESCOV); } - int lineno() const { return std::atoi(keyExtract(VL_CIK_LINENO).c_str()); } - int column() const { return std::atoi(keyExtract(VL_CIK_COLUMN).c_str()); } + string filename() const { return keyExtract(VL_CIK_FILENAME, m_name.c_str()); } + string comment() const { return keyExtract(VL_CIK_COMMENT, m_name.c_str()); } + string hier() const { return keyExtract(VL_CIK_HIER, m_name.c_str()); } + string type() const { return typeExtract(m_name.c_str()); } + string thresh() const { + // string as maybe "" + return keyExtract(VL_CIK_THRESH, m_name.c_str()); + } + string linescov() const { return keyExtract(VL_CIK_LINESCOV, m_name.c_str()); } + int lineno() const { + const string lineStr = keyExtract(VL_CIK_LINENO, m_name.c_str()); + return std::atoi(lineStr.c_str()); + } + int column() const { + const string columnStr = keyExtract(VL_CIK_COLUMN, m_name.c_str()); + return std::atoi(columnStr.c_str()); + } // METHODS - string keyExtract(const char* shortKey) const { + static string typeExtract(const char* name) { return keyExtract(VL_CIK_TYPE, name); } + static string keyExtract(const char* shortKey, const char* name) { // Hot function const size_t shortLen = std::strlen(shortKey); - const string namestr = name(); - for (const char* cp = namestr.c_str(); *cp; ++cp) { + for (const char* cp = name; *cp; ++cp) { if (*cp == '\001') { if (0 == std::strncmp(cp + 1, shortKey, shortLen) && cp[shortLen + 1] == '\002') { cp += shortLen + 2; // Skip \001+short+\002 diff --git a/src/VlcTop.cpp b/src/VlcTop.cpp index e16edfab3..c4930f349 100644 --- a/src/VlcTop.cpp +++ b/src/VlcTop.cpp @@ -51,6 +51,8 @@ void VlcTop::readCoverage(const string& filename, bool nonfatal) { if (line[secspace] == '\'' && line[secspace + 1] == ' ') break; } const string point = line.substr(3, secspace - 3); + if (!opt.isTypeMatch(point.c_str())) continue; + const uint64_t hits = std::atoll(line.c_str() + secspace + 1); // UINFO(9," point '"< 0htop.t.cond1' 7 +C 'ft/t_cover_line.vl331n20texprpagev_expr/condo(((cyc %25 32'sh3) == 32'sh0)==1) => 1htop.t.cond1' 3 +C 'ft/t_cover_line.vl331n26tbranchpagev_branch/condocond_thenS331htop.t.cond1' 3 +C 'ft/t_cover_line.vl331n27tbranchpagev_branch/condocond_elseS331htop.t.cond1' 7 +C 'ft/t_cover_line.vl332n34tbranchpagev_branch/condocond_thenS332htop.t.cond1' 0 +C 'ft/t_cover_line.vl332n35tbranchpagev_branch/condocond_elseS332htop.t.cond1' 10 +C 'ft/t_cover_line.vl334n30tbranchpagev_branch/condocond_thenS334htop.t.cond1' 12 +C 'ft/t_cover_line.vl334n31tbranchpagev_branch/condocond_elseS334htop.t.cond1' 19 +C 'ft/t_cover_line.vl334n37tbranchpagev_branch/condocond_thenS334htop.t.cond1' 7 +C 'ft/t_cover_line.vl334n38tbranchpagev_branch/condocond_elseS334htop.t.cond1' 5 +C 'ft/t_cover_line.vl337n34tbranchpagev_branch/condocond_thenS337htop.t.cond1' 11 +C 'ft/t_cover_line.vl337n35tbranchpagev_branch/condocond_elseS337htop.t.cond1' 0 +C 'ft/t_cover_line.vl343n22tbranchpagev_branch/condocond_thenS343htop.t.cond1' 10 +C 'ft/t_cover_line.vl343n23tbranchpagev_branch/condocond_elseS343htop.t.cond1' 11 +C 'ft/t_cover_line.vl346n4tlinepagev_line/condoblockS346,350,353,356htop.t.cond1' 11 +C 'ft/t_cover_line.vl347n29texprpagev_expr/condo((cyc > 32'sh5)==0) => 0htop.t.cond1' 1 +C 'ft/t_cover_line.vl347n29texprpagev_expr/condo((cyc > 32'sh5)==1) => 1htop.t.cond1' 0 +C 'ft/t_cover_line.vl347n33tbranchpagev_branch/condocond_thenS347htop.t.cond1' 0 +C 'ft/t_cover_line.vl347n34tbranchpagev_branch/condocond_elseS347htop.t.cond1' 1 +C 'ft/t_cover_line.vl347n7tbranchpagev_branch/condoifS347htop.t.cond1' 1 +C 'ft/t_cover_line.vl347n8tbranchpagev_branch/condoelseS348htop.t.cond1' 10 +C 'ft/t_cover_line.vl350n22texprpagev_expr/condo((cyc == 32'sh2)==0) => 0htop.t.cond1' 10 +C 'ft/t_cover_line.vl350n22texprpagev_expr/condo((cyc == 32'sh2)==1) => 1htop.t.cond1' 1 +C 'ft/t_cover_line.vl350n28tbranchpagev_branch/condocond_thenS350htop.t.cond1' 1 +C 'ft/t_cover_line.vl350n29tbranchpagev_branch/condocond_elseS350htop.t.cond1' 10 +C 'ft/t_cover_line.vl353n26texprpagev_expr/condo((i < 32'sh5)==0) => 0htop.t.cond1' 11 +C 'ft/t_cover_line.vl353n26texprpagev_expr/condo((i < 32'sh5)==1) => 1htop.t.cond1' 0 +C 'ft/t_cover_line.vl353n7tlinepagev_line/condoblockS353-354htop.t.cond1' 55 +C 'ft/t_cover_line.vl356n37texprpagev_expr/condo((i > 32'sh4)==0) => 0htop.t.cond1' 0 +C 'ft/t_cover_line.vl356n37texprpagev_expr/condo((i > 32'sh4)==1) => 1htop.t.cond1' 11 +C 'ft/t_cover_line.vl356n7tlinepagev_line/condoblockS356-357htop.t.cond1' 44 +C 'ft/t_cover_line.vl360n11texprpagev_expr/condo(k==0) => 0htop.t.cond1' 11 +C 'ft/t_cover_line.vl360n11texprpagev_expr/condo(k==1) => 1htop.t.cond1' 0 +C 'ft/t_cover_line.vl360n7tbranchpagev_branch/condoifS360htop.t.cond1' 0 +C 'ft/t_cover_line.vl360n8tbranchpagev_branch/condoelseS361htop.t.cond1' 11 +C 'ft/t_cover_line.vl55n4tlinepagev_line/toblockS55htop.t' 10 +C 'ft/t_cover_line.vl56n7tbranchpagev_branch/toifS56-58,105-106htop.t' 10 +C 'ft/t_cover_line.vl56n8tbranchpagev_branch/toelsehtop.t' 0 +C 'ft/t_cover_line.vl60n10tbranchpagev_branch/toifS60htop.t' 1 +C 'ft/t_cover_line.vl60n11tbranchpagev_branch/toelsehtop.t' 9 +C 'ft/t_cover_line.vl61n10tbranchpagev_branch/toifS61-63htop.t' 1 +C 'ft/t_cover_line.vl61n11tbranchpagev_branch/toelsehtop.t' 9 +C 'ft/t_cover_line.vl66n10tbranchpagev_branch/toifS66htop.t' 1 +C 'ft/t_cover_line.vl66n11tbranchpagev_branch/toelseS66htop.t' 9 +C 'ft/t_cover_line.vl67n10tbranchpagev_branch/toifS67htop.t' 1 +C 'ft/t_cover_line.vl67n11tbranchpagev_branch/toelseS69-70htop.t' 9 +C 'ft/t_cover_line.vl73n10tbranchpagev_branch/toifS73htop.t' 1 +C 'ft/t_cover_line.vl73n11tbranchpagev_branch/toelseS73htop.t' 9 +C 'ft/t_cover_line.vl74n10tbranchpagev_branch/toifS74-76htop.t' 1 +C 'ft/t_cover_line.vl74n11tbranchpagev_branch/toelseS79-80htop.t' 9 +C 'ft/t_cover_line.vl83n10tlinepagev_line/toelsifS83-85htop.t' 1 +C 'ft/t_cover_line.vl87n15tlinepagev_line/toelsifS87-89htop.t' 1 +C 'ft/t_cover_line.vl91n15tlinepagev_line/toifS91-93htop.t' 1 +C 'ft/t_cover_line.vl91n16tlinepagev_line/toelseS96-97htop.t' 7 diff --git a/test_regress/t/t_vlcov_data_f.dat b/test_regress/t/t_vlcov_data_f.dat new file mode 100644 index 000000000..7ef9e4d1d --- /dev/null +++ b/test_regress/t/t_vlcov_data_f.dat @@ -0,0 +1,157 @@ +# SystemC::Coverage-3 +C 'ft/t_assert_ctl_arg.vl100n32tuserpagev_user/tocover_simple_immediate_100S100htop.t.cover_simple_immediate_100' 1 +C 'ft/t_assert_ctl_arg.vl100n37tuserpagev_user/tocover_simple_immediate_stmt_100S100htop.t.cover_simple_immediate_stmt_100' 1 +C 'ft/t_assert_ctl_arg.vl100n40tuserpagev_user/tocover_final_deferred_immediate_100S100htop.t.cover_final_deferred_immediate_100' 1 +C 'ft/t_assert_ctl_arg.vl100n43tuserpagev_user/tocover_observed_deferred_immediate_100S100htop.t.cover_observed_deferred_immediate_100' 1 +C 'ft/t_assert_ctl_arg.vl100n45tuserpagev_user/tocover_final_deferred_immediate_stmt_100S100htop.t.cover_final_deferred_immediate_stmt_100' 1 +C 'ft/t_assert_ctl_arg.vl100n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_100S100htop.t.cover_observed_deferred_immediate_stmt_100' 1 +C 'ft/t_assert_ctl_arg.vl103n32tuserpagev_user/tocover_simple_immediate_103S103htop.t.cover_simple_immediate_103' 0 +C 'ft/t_assert_ctl_arg.vl103n37tuserpagev_user/tocover_simple_immediate_stmt_103S103htop.t.cover_simple_immediate_stmt_103' 0 +C 'ft/t_assert_ctl_arg.vl103n40tuserpagev_user/tocover_final_deferred_immediate_103S103htop.t.cover_final_deferred_immediate_103' 0 +C 'ft/t_assert_ctl_arg.vl103n43tuserpagev_user/tocover_observed_deferred_immediate_103S103htop.t.cover_observed_deferred_immediate_103' 0 +C 'ft/t_assert_ctl_arg.vl103n45tuserpagev_user/tocover_final_deferred_immediate_stmt_103S103htop.t.cover_final_deferred_immediate_stmt_103' 0 +C 'ft/t_assert_ctl_arg.vl103n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_103S103htop.t.cover_observed_deferred_immediate_stmt_103' 0 +C 'ft/t_assert_ctl_arg.vl106n32tuserpagev_user/tocover_simple_immediate_106S106htop.t.cover_simple_immediate_106' 1 +C 'ft/t_assert_ctl_arg.vl106n37tuserpagev_user/tocover_simple_immediate_stmt_106S106htop.t.cover_simple_immediate_stmt_106' 1 +C 'ft/t_assert_ctl_arg.vl106n40tuserpagev_user/tocover_final_deferred_immediate_106S106htop.t.cover_final_deferred_immediate_106' 1 +C 'ft/t_assert_ctl_arg.vl106n43tuserpagev_user/tocover_observed_deferred_immediate_106S106htop.t.cover_observed_deferred_immediate_106' 1 +C 'ft/t_assert_ctl_arg.vl106n45tuserpagev_user/tocover_final_deferred_immediate_stmt_106S106htop.t.cover_final_deferred_immediate_stmt_106' 1 +C 'ft/t_assert_ctl_arg.vl106n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_106S106htop.t.cover_observed_deferred_immediate_stmt_106' 1 +C 'ft/t_assert_ctl_arg.vl108n32tuserpagev_user/tocover_simple_immediate_108S108htop.t.cover_simple_immediate_108' 1 +C 'ft/t_assert_ctl_arg.vl108n37tuserpagev_user/tocover_simple_immediate_stmt_108S108htop.t.cover_simple_immediate_stmt_108' 1 +C 'ft/t_assert_ctl_arg.vl108n40tuserpagev_user/tocover_final_deferred_immediate_108S108htop.t.cover_final_deferred_immediate_108' 1 +C 'ft/t_assert_ctl_arg.vl108n43tuserpagev_user/tocover_observed_deferred_immediate_108S108htop.t.cover_observed_deferred_immediate_108' 1 +C 'ft/t_assert_ctl_arg.vl108n45tuserpagev_user/tocover_final_deferred_immediate_stmt_108S108htop.t.cover_final_deferred_immediate_stmt_108' 1 +C 'ft/t_assert_ctl_arg.vl108n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_108S108htop.t.cover_observed_deferred_immediate_stmt_108' 1 +C 'ft/t_assert_ctl_arg.vl110n32tuserpagev_user/tocover_simple_immediate_110S110htop.t.cover_simple_immediate_110' 0 +C 'ft/t_assert_ctl_arg.vl110n37tuserpagev_user/tocover_simple_immediate_stmt_110S110htop.t.cover_simple_immediate_stmt_110' 0 +C 'ft/t_assert_ctl_arg.vl110n40tuserpagev_user/tocover_final_deferred_immediate_110S110htop.t.cover_final_deferred_immediate_110' 0 +C 'ft/t_assert_ctl_arg.vl110n43tuserpagev_user/tocover_observed_deferred_immediate_110S110htop.t.cover_observed_deferred_immediate_110' 0 +C 'ft/t_assert_ctl_arg.vl110n45tuserpagev_user/tocover_final_deferred_immediate_stmt_110S110htop.t.cover_final_deferred_immediate_stmt_110' 0 +C 'ft/t_assert_ctl_arg.vl110n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_110S110htop.t.cover_observed_deferred_immediate_stmt_110' 0 +C 'ft/t_assert_ctl_arg.vl112n32tuserpagev_user/tocover_simple_immediate_112S112htop.t.cover_simple_immediate_112' 1 +C 'ft/t_assert_ctl_arg.vl112n37tuserpagev_user/tocover_simple_immediate_stmt_112S112htop.t.cover_simple_immediate_stmt_112' 1 +C 'ft/t_assert_ctl_arg.vl112n40tuserpagev_user/tocover_final_deferred_immediate_112S112htop.t.cover_final_deferred_immediate_112' 1 +C 'ft/t_assert_ctl_arg.vl112n43tuserpagev_user/tocover_observed_deferred_immediate_112S112htop.t.cover_observed_deferred_immediate_112' 0 +C 'ft/t_assert_ctl_arg.vl112n45tuserpagev_user/tocover_final_deferred_immediate_stmt_112S112htop.t.cover_final_deferred_immediate_stmt_112' 1 +C 'ft/t_assert_ctl_arg.vl112n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_112S112htop.t.cover_observed_deferred_immediate_stmt_112' 0 +C 'ft/t_assert_ctl_arg.vl177n25ttogglepagev_toggle/concurrentoclkhtop.t.concurrent' 21 +C 'ft/t_assert_ctl_arg.vl178n13tlinepagev_line/concurrentoblockS178-179htop.t.concurrent' 0 +C 'ft/t_assert_ctl_arg.vl192n22tuserpagev_user/concurrentocover_concurrentS192htop.t.concurrent.cover_concurrent' 0 +C 'ft/t_assert_ctl_arg.vl193n27tuserpagev_user/concurrentocover_concurrent_stmtS193htop.t.concurrent.cover_concurrent_stmt' 0 +C 'ft/t_assert_ctl_arg.vl26n10ttogglepagev_toggle/toclkhtop.t' 21 +C 'ft/t_assert_ctl_arg.vl45n4tlinepagev_line/toblockS28-30,32-35,37,39-41,45,47-51,54-58,61-65,68-73,75-92,95-113,116-122,124-125htop.t' 1 +C 'ft/t_assert_ctl_arg.vl49n31tuserpagev_user/tocover_simple_immediate_49S49htop.t.cover_simple_immediate_49' 1 +C 'ft/t_assert_ctl_arg.vl49n36tuserpagev_user/tocover_simple_immediate_stmt_49S49htop.t.cover_simple_immediate_stmt_49' 1 +C 'ft/t_assert_ctl_arg.vl49n39tuserpagev_user/tocover_final_deferred_immediate_49S49htop.t.cover_final_deferred_immediate_49' 0 +C 'ft/t_assert_ctl_arg.vl49n42tuserpagev_user/tocover_observed_deferred_immediate_49S49htop.t.cover_observed_deferred_immediate_49' 0 +C 'ft/t_assert_ctl_arg.vl49n44tuserpagev_user/tocover_final_deferred_immediate_stmt_49S49htop.t.cover_final_deferred_immediate_stmt_49' 0 +C 'ft/t_assert_ctl_arg.vl49n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_49S49htop.t.cover_observed_deferred_immediate_stmt_49' 0 +C 'ft/t_assert_ctl_arg.vl51n31tuserpagev_user/tocover_simple_immediate_51S51htop.t.cover_simple_immediate_51' 0 +C 'ft/t_assert_ctl_arg.vl51n36tuserpagev_user/tocover_simple_immediate_stmt_51S51htop.t.cover_simple_immediate_stmt_51' 0 +C 'ft/t_assert_ctl_arg.vl51n39tuserpagev_user/tocover_final_deferred_immediate_51S51htop.t.cover_final_deferred_immediate_51' 0 +C 'ft/t_assert_ctl_arg.vl51n42tuserpagev_user/tocover_observed_deferred_immediate_51S51htop.t.cover_observed_deferred_immediate_51' 0 +C 'ft/t_assert_ctl_arg.vl51n44tuserpagev_user/tocover_final_deferred_immediate_stmt_51S51htop.t.cover_final_deferred_immediate_stmt_51' 0 +C 'ft/t_assert_ctl_arg.vl51n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_51S51htop.t.cover_observed_deferred_immediate_stmt_51' 0 +C 'ft/t_assert_ctl_arg.vl56n31tuserpagev_user/tocover_simple_immediate_56S56htop.t.cover_simple_immediate_56' 0 +C 'ft/t_assert_ctl_arg.vl56n36tuserpagev_user/tocover_simple_immediate_stmt_56S56htop.t.cover_simple_immediate_stmt_56' 0 +C 'ft/t_assert_ctl_arg.vl56n39tuserpagev_user/tocover_final_deferred_immediate_56S56htop.t.cover_final_deferred_immediate_56' 0 +C 'ft/t_assert_ctl_arg.vl56n42tuserpagev_user/tocover_observed_deferred_immediate_56S56htop.t.cover_observed_deferred_immediate_56' 1 +C 'ft/t_assert_ctl_arg.vl56n44tuserpagev_user/tocover_final_deferred_immediate_stmt_56S56htop.t.cover_final_deferred_immediate_stmt_56' 0 +C 'ft/t_assert_ctl_arg.vl56n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_56S56htop.t.cover_observed_deferred_immediate_stmt_56' 1 +C 'ft/t_assert_ctl_arg.vl58n31tuserpagev_user/tocover_simple_immediate_58S58htop.t.cover_simple_immediate_58' 0 +C 'ft/t_assert_ctl_arg.vl58n36tuserpagev_user/tocover_simple_immediate_stmt_58S58htop.t.cover_simple_immediate_stmt_58' 0 +C 'ft/t_assert_ctl_arg.vl58n39tuserpagev_user/tocover_final_deferred_immediate_58S58htop.t.cover_final_deferred_immediate_58' 0 +C 'ft/t_assert_ctl_arg.vl58n42tuserpagev_user/tocover_observed_deferred_immediate_58S58htop.t.cover_observed_deferred_immediate_58' 0 +C 'ft/t_assert_ctl_arg.vl58n44tuserpagev_user/tocover_final_deferred_immediate_stmt_58S58htop.t.cover_final_deferred_immediate_stmt_58' 0 +C 'ft/t_assert_ctl_arg.vl58n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_58S58htop.t.cover_observed_deferred_immediate_stmt_58' 0 +C 'ft/t_assert_ctl_arg.vl63n31tuserpagev_user/tocover_simple_immediate_63S63htop.t.cover_simple_immediate_63' 0 +C 'ft/t_assert_ctl_arg.vl63n36tuserpagev_user/tocover_simple_immediate_stmt_63S63htop.t.cover_simple_immediate_stmt_63' 0 +C 'ft/t_assert_ctl_arg.vl63n39tuserpagev_user/tocover_final_deferred_immediate_63S63htop.t.cover_final_deferred_immediate_63' 1 +C 'ft/t_assert_ctl_arg.vl63n42tuserpagev_user/tocover_observed_deferred_immediate_63S63htop.t.cover_observed_deferred_immediate_63' 0 +C 'ft/t_assert_ctl_arg.vl63n44tuserpagev_user/tocover_final_deferred_immediate_stmt_63S63htop.t.cover_final_deferred_immediate_stmt_63' 1 +C 'ft/t_assert_ctl_arg.vl63n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_63S63htop.t.cover_observed_deferred_immediate_stmt_63' 0 +C 'ft/t_assert_ctl_arg.vl65n31tuserpagev_user/tocover_simple_immediate_65S65htop.t.cover_simple_immediate_65' 0 +C 'ft/t_assert_ctl_arg.vl65n36tuserpagev_user/tocover_simple_immediate_stmt_65S65htop.t.cover_simple_immediate_stmt_65' 0 +C 'ft/t_assert_ctl_arg.vl65n39tuserpagev_user/tocover_final_deferred_immediate_65S65htop.t.cover_final_deferred_immediate_65' 0 +C 'ft/t_assert_ctl_arg.vl65n42tuserpagev_user/tocover_observed_deferred_immediate_65S65htop.t.cover_observed_deferred_immediate_65' 0 +C 'ft/t_assert_ctl_arg.vl65n44tuserpagev_user/tocover_final_deferred_immediate_stmt_65S65htop.t.cover_final_deferred_immediate_stmt_65' 0 +C 'ft/t_assert_ctl_arg.vl65n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_65S65htop.t.cover_observed_deferred_immediate_stmt_65' 0 +C 'ft/t_assert_ctl_arg.vl69n31tuserpagev_user/tocover_simple_immediate_69S69htop.t.cover_simple_immediate_69' 0 +C 'ft/t_assert_ctl_arg.vl69n36tuserpagev_user/tocover_simple_immediate_stmt_69S69htop.t.cover_simple_immediate_stmt_69' 0 +C 'ft/t_assert_ctl_arg.vl69n39tuserpagev_user/tocover_final_deferred_immediate_69S69htop.t.cover_final_deferred_immediate_69' 0 +C 'ft/t_assert_ctl_arg.vl69n42tuserpagev_user/tocover_observed_deferred_immediate_69S69htop.t.cover_observed_deferred_immediate_69' 0 +C 'ft/t_assert_ctl_arg.vl69n44tuserpagev_user/tocover_final_deferred_immediate_stmt_69S69htop.t.cover_final_deferred_immediate_stmt_69' 0 +C 'ft/t_assert_ctl_arg.vl69n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_69S69htop.t.cover_observed_deferred_immediate_stmt_69' 0 +C 'ft/t_assert_ctl_arg.vl71n31tuserpagev_user/tocover_simple_immediate_71S71htop.t.cover_simple_immediate_71' 1 +C 'ft/t_assert_ctl_arg.vl71n36tuserpagev_user/tocover_simple_immediate_stmt_71S71htop.t.cover_simple_immediate_stmt_71' 1 +C 'ft/t_assert_ctl_arg.vl71n39tuserpagev_user/tocover_final_deferred_immediate_71S71htop.t.cover_final_deferred_immediate_71' 1 +C 'ft/t_assert_ctl_arg.vl71n42tuserpagev_user/tocover_observed_deferred_immediate_71S71htop.t.cover_observed_deferred_immediate_71' 1 +C 'ft/t_assert_ctl_arg.vl71n44tuserpagev_user/tocover_final_deferred_immediate_stmt_71S71htop.t.cover_final_deferred_immediate_stmt_71' 1 +C 'ft/t_assert_ctl_arg.vl71n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_71S71htop.t.cover_observed_deferred_immediate_stmt_71' 1 +C 'ft/t_assert_ctl_arg.vl73n31tuserpagev_user/tocover_simple_immediate_73S73htop.t.cover_simple_immediate_73' 0 +C 'ft/t_assert_ctl_arg.vl73n36tuserpagev_user/tocover_simple_immediate_stmt_73S73htop.t.cover_simple_immediate_stmt_73' 0 +C 'ft/t_assert_ctl_arg.vl73n39tuserpagev_user/tocover_final_deferred_immediate_73S73htop.t.cover_final_deferred_immediate_73' 0 +C 'ft/t_assert_ctl_arg.vl73n42tuserpagev_user/tocover_observed_deferred_immediate_73S73htop.t.cover_observed_deferred_immediate_73' 0 +C 'ft/t_assert_ctl_arg.vl73n44tuserpagev_user/tocover_final_deferred_immediate_stmt_73S73htop.t.cover_final_deferred_immediate_stmt_73' 0 +C 'ft/t_assert_ctl_arg.vl73n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_73S73htop.t.cover_observed_deferred_immediate_stmt_73' 0 +C 'ft/t_assert_ctl_arg.vl76n31tuserpagev_user/tocover_simple_immediate_76S76htop.t.cover_simple_immediate_76' 1 +C 'ft/t_assert_ctl_arg.vl76n36tuserpagev_user/tocover_simple_immediate_stmt_76S76htop.t.cover_simple_immediate_stmt_76' 1 +C 'ft/t_assert_ctl_arg.vl76n39tuserpagev_user/tocover_final_deferred_immediate_76S76htop.t.cover_final_deferred_immediate_76' 0 +C 'ft/t_assert_ctl_arg.vl76n42tuserpagev_user/tocover_observed_deferred_immediate_76S76htop.t.cover_observed_deferred_immediate_76' 1 +C 'ft/t_assert_ctl_arg.vl76n44tuserpagev_user/tocover_final_deferred_immediate_stmt_76S76htop.t.cover_final_deferred_immediate_stmt_76' 0 +C 'ft/t_assert_ctl_arg.vl76n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_76S76htop.t.cover_observed_deferred_immediate_stmt_76' 1 +C 'ft/t_assert_ctl_arg.vl78n31tuserpagev_user/tocover_simple_immediate_78S78htop.t.cover_simple_immediate_78' 1 +C 'ft/t_assert_ctl_arg.vl78n36tuserpagev_user/tocover_simple_immediate_stmt_78S78htop.t.cover_simple_immediate_stmt_78' 1 +C 'ft/t_assert_ctl_arg.vl78n39tuserpagev_user/tocover_final_deferred_immediate_78S78htop.t.cover_final_deferred_immediate_78' 1 +C 'ft/t_assert_ctl_arg.vl78n42tuserpagev_user/tocover_observed_deferred_immediate_78S78htop.t.cover_observed_deferred_immediate_78' 1 +C 'ft/t_assert_ctl_arg.vl78n44tuserpagev_user/tocover_final_deferred_immediate_stmt_78S78htop.t.cover_final_deferred_immediate_stmt_78' 1 +C 'ft/t_assert_ctl_arg.vl78n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_78S78htop.t.cover_observed_deferred_immediate_stmt_78' 1 +C 'ft/t_assert_ctl_arg.vl80n31tuserpagev_user/tocover_simple_immediate_80S80htop.t.cover_simple_immediate_80' 1 +C 'ft/t_assert_ctl_arg.vl80n36tuserpagev_user/tocover_simple_immediate_stmt_80S80htop.t.cover_simple_immediate_stmt_80' 1 +C 'ft/t_assert_ctl_arg.vl80n39tuserpagev_user/tocover_final_deferred_immediate_80S80htop.t.cover_final_deferred_immediate_80' 0 +C 'ft/t_assert_ctl_arg.vl80n42tuserpagev_user/tocover_observed_deferred_immediate_80S80htop.t.cover_observed_deferred_immediate_80' 0 +C 'ft/t_assert_ctl_arg.vl80n44tuserpagev_user/tocover_final_deferred_immediate_stmt_80S80htop.t.cover_final_deferred_immediate_stmt_80' 0 +C 'ft/t_assert_ctl_arg.vl80n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_80S80htop.t.cover_observed_deferred_immediate_stmt_80' 0 +C 'ft/t_assert_ctl_arg.vl82n31tuserpagev_user/tocover_simple_immediate_82S82htop.t.cover_simple_immediate_82' 1 +C 'ft/t_assert_ctl_arg.vl82n36tuserpagev_user/tocover_simple_immediate_stmt_82S82htop.t.cover_simple_immediate_stmt_82' 1 +C 'ft/t_assert_ctl_arg.vl82n39tuserpagev_user/tocover_final_deferred_immediate_82S82htop.t.cover_final_deferred_immediate_82' 0 +C 'ft/t_assert_ctl_arg.vl82n42tuserpagev_user/tocover_observed_deferred_immediate_82S82htop.t.cover_observed_deferred_immediate_82' 0 +C 'ft/t_assert_ctl_arg.vl82n44tuserpagev_user/tocover_final_deferred_immediate_stmt_82S82htop.t.cover_final_deferred_immediate_stmt_82' 0 +C 'ft/t_assert_ctl_arg.vl82n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_82S82htop.t.cover_observed_deferred_immediate_stmt_82' 0 +C 'ft/t_assert_ctl_arg.vl84n31tuserpagev_user/tocover_simple_immediate_84S84htop.t.cover_simple_immediate_84' 0 +C 'ft/t_assert_ctl_arg.vl84n36tuserpagev_user/tocover_simple_immediate_stmt_84S84htop.t.cover_simple_immediate_stmt_84' 0 +C 'ft/t_assert_ctl_arg.vl84n39tuserpagev_user/tocover_final_deferred_immediate_84S84htop.t.cover_final_deferred_immediate_84' 0 +C 'ft/t_assert_ctl_arg.vl84n42tuserpagev_user/tocover_observed_deferred_immediate_84S84htop.t.cover_observed_deferred_immediate_84' 0 +C 'ft/t_assert_ctl_arg.vl84n44tuserpagev_user/tocover_final_deferred_immediate_stmt_84S84htop.t.cover_final_deferred_immediate_stmt_84' 0 +C 'ft/t_assert_ctl_arg.vl84n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_84S84htop.t.cover_observed_deferred_immediate_stmt_84' 0 +C 'ft/t_assert_ctl_arg.vl86n31tuserpagev_user/tocover_simple_immediate_86S86htop.t.cover_simple_immediate_86' 1 +C 'ft/t_assert_ctl_arg.vl86n36tuserpagev_user/tocover_simple_immediate_stmt_86S86htop.t.cover_simple_immediate_stmt_86' 1 +C 'ft/t_assert_ctl_arg.vl86n39tuserpagev_user/tocover_final_deferred_immediate_86S86htop.t.cover_final_deferred_immediate_86' 0 +C 'ft/t_assert_ctl_arg.vl86n42tuserpagev_user/tocover_observed_deferred_immediate_86S86htop.t.cover_observed_deferred_immediate_86' 0 +C 'ft/t_assert_ctl_arg.vl86n44tuserpagev_user/tocover_final_deferred_immediate_stmt_86S86htop.t.cover_final_deferred_immediate_stmt_86' 0 +C 'ft/t_assert_ctl_arg.vl86n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_86S86htop.t.cover_observed_deferred_immediate_stmt_86' 0 +C 'ft/t_assert_ctl_arg.vl88n31tuserpagev_user/tocover_simple_immediate_88S88htop.t.cover_simple_immediate_88' 0 +C 'ft/t_assert_ctl_arg.vl88n36tuserpagev_user/tocover_simple_immediate_stmt_88S88htop.t.cover_simple_immediate_stmt_88' 0 +C 'ft/t_assert_ctl_arg.vl88n39tuserpagev_user/tocover_final_deferred_immediate_88S88htop.t.cover_final_deferred_immediate_88' 0 +C 'ft/t_assert_ctl_arg.vl88n42tuserpagev_user/tocover_observed_deferred_immediate_88S88htop.t.cover_observed_deferred_immediate_88' 0 +C 'ft/t_assert_ctl_arg.vl88n44tuserpagev_user/tocover_final_deferred_immediate_stmt_88S88htop.t.cover_final_deferred_immediate_stmt_88' 0 +C 'ft/t_assert_ctl_arg.vl88n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_88S88htop.t.cover_observed_deferred_immediate_stmt_88' 0 +C 'ft/t_assert_ctl_arg.vl90n31tuserpagev_user/tocover_simple_immediate_90S90htop.t.cover_simple_immediate_90' 1 +C 'ft/t_assert_ctl_arg.vl90n36tuserpagev_user/tocover_simple_immediate_stmt_90S90htop.t.cover_simple_immediate_stmt_90' 1 +C 'ft/t_assert_ctl_arg.vl90n39tuserpagev_user/tocover_final_deferred_immediate_90S90htop.t.cover_final_deferred_immediate_90' 1 +C 'ft/t_assert_ctl_arg.vl90n42tuserpagev_user/tocover_observed_deferred_immediate_90S90htop.t.cover_observed_deferred_immediate_90' 1 +C 'ft/t_assert_ctl_arg.vl90n44tuserpagev_user/tocover_final_deferred_immediate_stmt_90S90htop.t.cover_final_deferred_immediate_stmt_90' 1 +C 'ft/t_assert_ctl_arg.vl90n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_90S90htop.t.cover_observed_deferred_immediate_stmt_90' 1 +C 'ft/t_assert_ctl_arg.vl92n31tuserpagev_user/tocover_simple_immediate_92S92htop.t.cover_simple_immediate_92' 0 +C 'ft/t_assert_ctl_arg.vl92n36tuserpagev_user/tocover_simple_immediate_stmt_92S92htop.t.cover_simple_immediate_stmt_92' 0 +C 'ft/t_assert_ctl_arg.vl92n39tuserpagev_user/tocover_final_deferred_immediate_92S92htop.t.cover_final_deferred_immediate_92' 0 +C 'ft/t_assert_ctl_arg.vl92n42tuserpagev_user/tocover_observed_deferred_immediate_92S92htop.t.cover_observed_deferred_immediate_92' 0 +C 'ft/t_assert_ctl_arg.vl92n44tuserpagev_user/tocover_final_deferred_immediate_stmt_92S92htop.t.cover_final_deferred_immediate_stmt_92' 0 +C 'ft/t_assert_ctl_arg.vl92n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_92S92htop.t.cover_observed_deferred_immediate_stmt_92' 0 +C 'ft/t_assert_ctl_arg.vl97n31tuserpagev_user/tocover_simple_immediate_97S97htop.t.cover_simple_immediate_97' 0 +C 'ft/t_assert_ctl_arg.vl97n36tuserpagev_user/tocover_simple_immediate_stmt_97S97htop.t.cover_simple_immediate_stmt_97' 0 +C 'ft/t_assert_ctl_arg.vl97n39tuserpagev_user/tocover_final_deferred_immediate_97S97htop.t.cover_final_deferred_immediate_97' 0 +C 'ft/t_assert_ctl_arg.vl97n42tuserpagev_user/tocover_observed_deferred_immediate_97S97htop.t.cover_observed_deferred_immediate_97' 0 +C 'ft/t_assert_ctl_arg.vl97n44tuserpagev_user/tocover_final_deferred_immediate_stmt_97S97htop.t.cover_final_deferred_immediate_stmt_97' 0 +C 'ft/t_assert_ctl_arg.vl97n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_97S97htop.t.cover_observed_deferred_immediate_stmt_97' 0 diff --git a/test_regress/t/t_vlcov_opt_branch.info.out b/test_regress/t/t_vlcov_opt_branch.info.out new file mode 100644 index 000000000..45d5b4627 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_branch.info.out @@ -0,0 +1,127 @@ +TN:verilator_coverage +SF:t/t_cover_line.v +DA:56,10 +BRDA:56,0,0,10 +BRDA:56,0,1,0 +DA:57,10 +DA:58,10 +DA:60,9 +BRDA:60,0,0,1 +BRDA:60,0,1,9 +DA:61,9 +BRDA:61,0,0,1 +BRDA:61,0,1,9 +DA:62,1 +DA:63,1 +DA:66,9 +BRDA:66,0,0,1 +BRDA:66,0,1,9 +DA:67,9 +BRDA:67,0,0,1 +BRDA:67,0,1,9 +DA:69,9 +DA:70,9 +DA:73,9 +BRDA:73,0,0,1 +BRDA:73,0,1,9 +DA:74,9 +BRDA:74,0,0,1 +BRDA:74,0,1,9 +DA:75,1 +DA:76,1 +DA:79,9 +DA:80,9 +DA:105,10 +DA:106,10 +DA:120,7 +BRDA:120,0,0,1 +BRDA:120,0,1,7 +DA:121,1 +DA:122,1 +DA:141,18 +BRDA:141,0,0,2 +BRDA:141,0,1,18 +DA:142,2 +DA:166,20 +BRDA:166,0,0,0 +BRDA:166,0,1,20 +DA:168,0 +DA:170,18 +BRDA:170,0,0,2 +BRDA:170,0,1,18 +DA:172,2 +DA:190,1 +BRDA:190,0,0,1 +BRDA:190,0,1,0 +DA:191,1 +DA:195,11 +BRDA:195,0,0,11 +BRDA:195,0,1,0 +DA:196,11 +DA:200,11 +BRDA:200,0,0,11 +BRDA:200,0,1,0 +DA:201,11 +DA:222,10 +BRDA:222,0,0,1 +BRDA:222,0,1,10 +DA:223,1 +DA:225,10 +BRDA:225,0,0,1 +BRDA:225,0,1,10 +DA:226,1 +DA:253,9 +BRDA:253,0,0,1 +BRDA:253,0,1,9 +DA:255,1 +DA:256,1 +BRDA:256,0,0,0 +BRDA:256,0,1,1 +DA:288,0 +BRDA:288,0,0,0 +BRDA:288,0,1,0 +DA:289,0 +DA:291,0 +DA:292,0 +DA:327,31 +BRDA:327,0,0,0 +BRDA:327,0,1,31 +DA:328,28 +BRDA:328,0,0,3 +BRDA:328,0,1,28 +DA:329,21 +BRDA:329,0,0,21 +BRDA:329,0,1,0 +DA:331,7 +BRDA:331,0,0,3 +BRDA:331,0,1,7 +DA:332,10 +BRDA:332,0,0,0 +BRDA:332,0,1,10 +DA:334,19 +BRDA:334,0,0,12 +BRDA:334,0,1,19 +BRDA:334,0,2,7 +BRDA:334,0,3,5 +DA:337,11 +BRDA:337,0,0,11 +BRDA:337,0,1,0 +DA:343,11 +BRDA:343,0,0,10 +BRDA:343,0,1,11 +DA:347,10 +BRDA:347,0,0,0 +BRDA:347,0,1,1 +BRDA:347,0,2,1 +BRDA:347,0,3,10 +DA:348,10 +DA:350,10 +BRDA:350,0,0,1 +BRDA:350,0,1,10 +DA:360,11 +BRDA:360,0,0,0 +BRDA:360,0,1,11 +DA:361,11 +BRF:64 +BRH:20 +end_of_record diff --git a/test_regress/t/t_vlcov_opt_branch.py b/test_regress/t/t_vlcov_opt_branch.py new file mode 100755 index 000000000..d784b9006 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_branch.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "--filter-type branch", "t/t_vlcov_data_e.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_vlcov_opt_expr.info.out b/test_regress/t/t_vlcov_opt_expr.info.out new file mode 100644 index 000000000..33c3c1c89 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_expr.info.out @@ -0,0 +1,23 @@ +TN:verilator_coverage +SF:t/t_cover_line.v +DA:331,7 +BRDA:331,0,0,7 +BRDA:331,0,1,3 +DA:347,1 +BRDA:347,0,0,1 +BRDA:347,0,1,0 +DA:350,10 +BRDA:350,0,0,10 +BRDA:350,0,1,1 +DA:353,11 +BRDA:353,0,0,11 +BRDA:353,0,1,0 +DA:356,11 +BRDA:356,0,0,0 +BRDA:356,0,1,11 +DA:360,11 +BRDA:360,0,0,11 +BRDA:360,0,1,0 +BRF:12 +BRH:4 +end_of_record diff --git a/test_regress/t/t_vlcov_opt_expr.py b/test_regress/t/t_vlcov_opt_expr.py new file mode 100755 index 000000000..4fa8200d2 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_expr.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "--filter-type expr", "t/t_vlcov_data_e.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_vlcov_opt_line.info.out b/test_regress/t/t_vlcov_opt_line.info.out new file mode 100644 index 000000000..eaba1df5d --- /dev/null +++ b/test_regress/t/t_vlcov_opt_line.info.out @@ -0,0 +1,87 @@ +TN:verilator_coverage +SF:t/t_cover_line.v +DA:15,1 +DA:18,1 +DA:55,10 +DA:83,1 +DA:84,1 +DA:85,1 +DA:87,1 +DA:88,1 +DA:89,1 +DA:91,7 +BRDA:91,0,0,1 +BRDA:91,0,1,7 +DA:92,1 +DA:93,1 +DA:96,7 +DA:97,7 +DA:100,0 +DA:101,0 +DA:102,0 +DA:104,0 +DA:105,0 +DA:106,0 +DA:107,0 +DA:110,1 +DA:111,1 +DA:113,1 +DA:115,1 +DA:127,1 +DA:129,1 +DA:140,20 +DA:145,18 +DA:164,20 +DA:165,20 +DA:174,18 +DA:188,1 +DA:189,1 +DA:194,11 +DA:199,11 +DA:215,10 +DA:216,10 +DA:219,11 +DA:221,11 +DA:229,11 +DA:230,1 +DA:231,11 +DA:232,11 +DA:252,10 +DA:265,10 +DA:266,10 +DA:267,1 +DA:268,1 +DA:269,1 +DA:270,1 +DA:271,1 +DA:272,5 +DA:276,10 +DA:277,10 +DA:287,0 +DA:294,0 +DA:300,1 +DA:303,1 +DA:304,20 +DA:305,20 +DA:314,1 +DA:317,21 +DA:318,21 +DA:319,21 +DA:322,10 +DA:324,10 +DA:330,10 +DA:331,10 +DA:332,10 +DA:346,11 +DA:350,11 +DA:353,55 +BRDA:353,0,0,11 +BRDA:353,0,1,55 +DA:354,55 +DA:356,44 +BRDA:356,0,0,11 +BRDA:356,0,1,44 +DA:357,44 +BRF:6 +BRH:4 +end_of_record diff --git a/test_regress/t/t_vlcov_opt_line.py b/test_regress/t/t_vlcov_opt_line.py new file mode 100755 index 000000000..f5f4b8195 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_line.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "--filter-type line", "t/t_vlcov_data_e.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_vlcov_opt_toggle.info.out b/test_regress/t/t_vlcov_opt_toggle.info.out new file mode 100644 index 000000000..7740e44dc --- /dev/null +++ b/test_regress/t/t_vlcov_opt_toggle.info.out @@ -0,0 +1,116 @@ +TN:verilator_coverage +SF:t/t_cover_line.v +DA:12,19 +DA:14,2 +DA:20,11 +BRDA:20,0,0,11 +BRDA:20,0,1,5 +BRDA:20,0,2,2 +BRDA:20,0,3,1 +BRDA:20,0,4,0 +BRDA:20,0,5,0 +BRDA:20,0,6,0 +BRDA:20,0,7,0 +DA:138,38 +DA:139,4 +DA:159,38 +DA:160,4 +DA:210,19 +DA:211,2 +DA:241,19 +DA:242,2 +DA:261,19 +DA:262,10 +BRDA:262,0,0,10 +BRDA:262,0,1,5 +BRDA:262,0,2,2 +BRDA:262,0,3,1 +DA:309,19 +BRDA:309,0,0,19 +BRDA:309,0,1,11 +BRDA:309,0,2,0 +BRDA:309,0,3,0 +BRDA:309,0,4,0 +BRDA:309,0,5,0 +BRDA:309,0,6,0 +BRDA:309,0,7,0 +BRDA:309,0,8,0 +BRDA:309,0,9,0 +BRDA:309,0,10,0 +BRDA:309,0,11,0 +BRDA:309,0,12,5 +BRDA:309,0,13,0 +BRDA:309,0,14,0 +BRDA:309,0,15,0 +BRDA:309,0,16,0 +BRDA:309,0,17,0 +BRDA:309,0,18,0 +BRDA:309,0,19,0 +BRDA:309,0,20,0 +BRDA:309,0,21,0 +BRDA:309,0,22,0 +BRDA:309,0,23,2 +BRDA:309,0,24,0 +BRDA:309,0,25,0 +BRDA:309,0,26,1 +BRDA:309,0,27,0 +BRDA:309,0,28,0 +BRDA:309,0,29,0 +BRDA:309,0,30,0 +BRDA:309,0,31,0 +BRDA:309,0,32,0 +DA:310,19 +BRDA:310,0,0,0 +BRDA:310,0,1,2 +BRDA:310,0,2,19 +BRDA:310,0,3,6 +BRDA:310,0,4,7 +BRDA:310,0,5,1 +BRDA:310,0,6,19 +BRDA:310,0,7,3 +BRDA:310,0,8,0 +BRDA:310,0,9,0 +BRDA:310,0,10,0 +DA:311,1 +BRDA:311,0,0,1 +BRDA:311,0,1,1 +BRDA:311,0,2,0 +BRDA:311,0,3,0 +BRDA:311,0,4,0 +BRDA:311,0,5,0 +DA:313,2 +BRDA:313,0,0,0 +BRDA:313,0,1,2 +BRDA:313,0,2,0 +BRDA:313,0,3,0 +BRDA:313,0,4,0 +BRDA:313,0,5,0 +BRDA:313,0,6,0 +BRDA:313,0,7,0 +BRDA:313,0,8,2 +BRDA:313,0,9,0 +BRDA:313,0,10,0 +BRDA:313,0,11,0 +BRDA:313,0,12,0 +BRDA:313,0,13,0 +BRDA:313,0,14,0 +BRDA:313,0,15,0 +BRDA:313,0,16,0 +BRDA:313,0,17,0 +BRDA:313,0,18,0 +BRDA:313,0,19,0 +BRDA:313,0,20,0 +BRDA:313,0,21,0 +BRDA:313,0,22,0 +BRDA:313,0,23,0 +BRDA:313,0,24,0 +BRDA:313,0,25,0 +BRDA:313,0,26,0 +BRDA:313,0,27,0 +BRDA:313,0,28,0 +BRDA:313,0,29,0 +BRDA:313,0,30,0 +BRDA:313,0,31,0 +BRF:94 +BRH:6 +end_of_record diff --git a/test_regress/t/t_vlcov_opt_toggle.py b/test_regress/t/t_vlcov_opt_toggle.py new file mode 100755 index 000000000..49da6830d --- /dev/null +++ b/test_regress/t/t_vlcov_opt_toggle.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "--filter-type toggle", "t/t_vlcov_data_e.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_vlcov_opt_user.info.out b/test_regress/t/t_vlcov_opt_user.info.out new file mode 100644 index 000000000..e1b47061b --- /dev/null +++ b/test_regress/t/t_vlcov_opt_user.info.out @@ -0,0 +1,182 @@ +TN:verilator_coverage +SF:t/t_assert_ctl_arg.v +DA:49,1 +BRDA:49,0,0,1 +BRDA:49,0,1,1 +BRDA:49,0,2,0 +BRDA:49,0,3,0 +BRDA:49,0,4,0 +BRDA:49,0,5,0 +DA:51,0 +BRDA:51,0,0,0 +BRDA:51,0,1,0 +BRDA:51,0,2,0 +BRDA:51,0,3,0 +BRDA:51,0,4,0 +BRDA:51,0,5,0 +DA:56,1 +BRDA:56,0,0,0 +BRDA:56,0,1,0 +BRDA:56,0,2,0 +BRDA:56,0,3,1 +BRDA:56,0,4,0 +BRDA:56,0,5,1 +DA:58,0 +BRDA:58,0,0,0 +BRDA:58,0,1,0 +BRDA:58,0,2,0 +BRDA:58,0,3,0 +BRDA:58,0,4,0 +BRDA:58,0,5,0 +DA:63,1 +BRDA:63,0,0,0 +BRDA:63,0,1,0 +BRDA:63,0,2,1 +BRDA:63,0,3,0 +BRDA:63,0,4,1 +BRDA:63,0,5,0 +DA:65,0 +BRDA:65,0,0,0 +BRDA:65,0,1,0 +BRDA:65,0,2,0 +BRDA:65,0,3,0 +BRDA:65,0,4,0 +BRDA:65,0,5,0 +DA:69,0 +BRDA:69,0,0,0 +BRDA:69,0,1,0 +BRDA:69,0,2,0 +BRDA:69,0,3,0 +BRDA:69,0,4,0 +BRDA:69,0,5,0 +DA:71,1 +BRDA:71,0,0,1 +BRDA:71,0,1,1 +BRDA:71,0,2,1 +BRDA:71,0,3,1 +BRDA:71,0,4,1 +BRDA:71,0,5,1 +DA:73,0 +BRDA:73,0,0,0 +BRDA:73,0,1,0 +BRDA:73,0,2,0 +BRDA:73,0,3,0 +BRDA:73,0,4,0 +BRDA:73,0,5,0 +DA:76,1 +BRDA:76,0,0,1 +BRDA:76,0,1,1 +BRDA:76,0,2,0 +BRDA:76,0,3,1 +BRDA:76,0,4,0 +BRDA:76,0,5,1 +DA:78,1 +BRDA:78,0,0,1 +BRDA:78,0,1,1 +BRDA:78,0,2,1 +BRDA:78,0,3,1 +BRDA:78,0,4,1 +BRDA:78,0,5,1 +DA:80,1 +BRDA:80,0,0,1 +BRDA:80,0,1,1 +BRDA:80,0,2,0 +BRDA:80,0,3,0 +BRDA:80,0,4,0 +BRDA:80,0,5,0 +DA:82,1 +BRDA:82,0,0,1 +BRDA:82,0,1,1 +BRDA:82,0,2,0 +BRDA:82,0,3,0 +BRDA:82,0,4,0 +BRDA:82,0,5,0 +DA:84,0 +BRDA:84,0,0,0 +BRDA:84,0,1,0 +BRDA:84,0,2,0 +BRDA:84,0,3,0 +BRDA:84,0,4,0 +BRDA:84,0,5,0 +DA:86,1 +BRDA:86,0,0,1 +BRDA:86,0,1,1 +BRDA:86,0,2,0 +BRDA:86,0,3,0 +BRDA:86,0,4,0 +BRDA:86,0,5,0 +DA:88,0 +BRDA:88,0,0,0 +BRDA:88,0,1,0 +BRDA:88,0,2,0 +BRDA:88,0,3,0 +BRDA:88,0,4,0 +BRDA:88,0,5,0 +DA:90,1 +BRDA:90,0,0,1 +BRDA:90,0,1,1 +BRDA:90,0,2,1 +BRDA:90,0,3,1 +BRDA:90,0,4,1 +BRDA:90,0,5,1 +DA:92,0 +BRDA:92,0,0,0 +BRDA:92,0,1,0 +BRDA:92,0,2,0 +BRDA:92,0,3,0 +BRDA:92,0,4,0 +BRDA:92,0,5,0 +DA:97,0 +BRDA:97,0,0,0 +BRDA:97,0,1,0 +BRDA:97,0,2,0 +BRDA:97,0,3,0 +BRDA:97,0,4,0 +BRDA:97,0,5,0 +DA:100,1 +BRDA:100,0,0,1 +BRDA:100,0,1,1 +BRDA:100,0,2,1 +BRDA:100,0,3,1 +BRDA:100,0,4,1 +BRDA:100,0,5,1 +DA:103,0 +BRDA:103,0,0,0 +BRDA:103,0,1,0 +BRDA:103,0,2,0 +BRDA:103,0,3,0 +BRDA:103,0,4,0 +BRDA:103,0,5,0 +DA:106,1 +BRDA:106,0,0,1 +BRDA:106,0,1,1 +BRDA:106,0,2,1 +BRDA:106,0,3,1 +BRDA:106,0,4,1 +BRDA:106,0,5,1 +DA:108,1 +BRDA:108,0,0,1 +BRDA:108,0,1,1 +BRDA:108,0,2,1 +BRDA:108,0,3,1 +BRDA:108,0,4,1 +BRDA:108,0,5,1 +DA:110,0 +BRDA:110,0,0,0 +BRDA:110,0,1,0 +BRDA:110,0,2,0 +BRDA:110,0,3,0 +BRDA:110,0,4,0 +BRDA:110,0,5,0 +DA:112,1 +BRDA:112,0,0,1 +BRDA:112,0,1,1 +BRDA:112,0,2,1 +BRDA:112,0,3,0 +BRDA:112,0,4,1 +BRDA:112,0,5,0 +DA:192,0 +DA:193,0 +BRF:150 +BRH:0 +end_of_record diff --git a/test_regress/t/t_vlcov_opt_user.py b/test_regress/t/t_vlcov_opt_user.py new file mode 100755 index 000000000..805813778 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_user.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "--filter-type user", "t/t_vlcov_data_f.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_vlcov_opt_wild.info.out b/test_regress/t/t_vlcov_opt_wild.info.out new file mode 100644 index 000000000..efcf737f6 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_wild.info.out @@ -0,0 +1,334 @@ +TN:verilator_coverage +SF:t/t_cover_line.v +DA:12,19 +DA:14,2 +DA:15,1 +DA:18,1 +DA:20,11 +BRDA:20,0,0,11 +BRDA:20,0,1,5 +BRDA:20,0,2,2 +BRDA:20,0,3,1 +BRDA:20,0,4,0 +BRDA:20,0,5,0 +BRDA:20,0,6,0 +BRDA:20,0,7,0 +DA:55,10 +DA:56,10 +BRDA:56,0,0,10 +BRDA:56,0,1,0 +DA:57,10 +DA:58,10 +DA:60,9 +BRDA:60,0,0,1 +BRDA:60,0,1,9 +DA:61,9 +BRDA:61,0,0,1 +BRDA:61,0,1,9 +DA:62,1 +DA:63,1 +DA:66,9 +BRDA:66,0,0,1 +BRDA:66,0,1,9 +DA:67,9 +BRDA:67,0,0,1 +BRDA:67,0,1,9 +DA:69,9 +DA:70,9 +DA:73,9 +BRDA:73,0,0,1 +BRDA:73,0,1,9 +DA:74,9 +BRDA:74,0,0,1 +BRDA:74,0,1,9 +DA:75,1 +DA:76,1 +DA:79,9 +DA:80,9 +DA:83,1 +DA:84,1 +DA:85,1 +DA:87,1 +DA:88,1 +DA:89,1 +DA:91,7 +BRDA:91,0,0,1 +BRDA:91,0,1,7 +DA:92,1 +DA:93,1 +DA:96,7 +DA:97,7 +DA:100,0 +DA:101,0 +DA:102,0 +DA:104,0 +DA:105,10 +BRDA:105,0,0,0 +BRDA:105,0,1,10 +DA:106,10 +BRDA:106,0,0,0 +BRDA:106,0,1,10 +DA:107,0 +DA:110,1 +DA:111,1 +DA:113,1 +DA:115,1 +DA:120,7 +BRDA:120,0,0,1 +BRDA:120,0,1,7 +DA:121,1 +DA:122,1 +DA:127,1 +DA:129,1 +DA:138,38 +DA:139,4 +DA:140,20 +DA:141,18 +BRDA:141,0,0,2 +BRDA:141,0,1,18 +DA:142,2 +DA:145,18 +DA:159,38 +DA:160,4 +DA:164,20 +DA:165,20 +DA:166,20 +BRDA:166,0,0,0 +BRDA:166,0,1,20 +DA:168,0 +DA:170,18 +BRDA:170,0,0,2 +BRDA:170,0,1,18 +DA:172,2 +DA:174,18 +DA:188,1 +DA:189,1 +DA:190,1 +BRDA:190,0,0,1 +BRDA:190,0,1,0 +DA:191,1 +DA:194,11 +DA:195,11 +BRDA:195,0,0,11 +BRDA:195,0,1,0 +DA:196,11 +DA:199,11 +DA:200,11 +BRDA:200,0,0,11 +BRDA:200,0,1,0 +DA:201,11 +DA:210,19 +DA:211,2 +DA:215,10 +DA:216,10 +DA:219,11 +DA:221,11 +DA:222,10 +BRDA:222,0,0,1 +BRDA:222,0,1,10 +DA:223,1 +DA:225,10 +BRDA:225,0,0,1 +BRDA:225,0,1,10 +DA:226,1 +DA:229,11 +DA:230,1 +DA:231,11 +DA:232,11 +DA:241,19 +DA:242,2 +DA:252,10 +DA:253,9 +BRDA:253,0,0,1 +BRDA:253,0,1,9 +DA:255,1 +DA:256,1 +BRDA:256,0,0,0 +BRDA:256,0,1,1 +DA:261,19 +DA:262,10 +BRDA:262,0,0,10 +BRDA:262,0,1,5 +BRDA:262,0,2,2 +BRDA:262,0,3,1 +DA:265,10 +DA:266,10 +DA:267,1 +DA:268,1 +DA:269,1 +DA:270,1 +DA:271,1 +DA:272,5 +DA:276,10 +DA:277,10 +DA:287,0 +DA:288,0 +BRDA:288,0,0,0 +BRDA:288,0,1,0 +DA:289,0 +DA:291,0 +DA:292,0 +DA:294,0 +DA:300,1 +DA:303,1 +DA:304,20 +DA:305,20 +DA:309,19 +BRDA:309,0,0,19 +BRDA:309,0,1,11 +BRDA:309,0,2,0 +BRDA:309,0,3,0 +BRDA:309,0,4,0 +BRDA:309,0,5,0 +BRDA:309,0,6,0 +BRDA:309,0,7,0 +BRDA:309,0,8,0 +BRDA:309,0,9,0 +BRDA:309,0,10,0 +BRDA:309,0,11,0 +BRDA:309,0,12,5 +BRDA:309,0,13,0 +BRDA:309,0,14,0 +BRDA:309,0,15,0 +BRDA:309,0,16,0 +BRDA:309,0,17,0 +BRDA:309,0,18,0 +BRDA:309,0,19,0 +BRDA:309,0,20,0 +BRDA:309,0,21,0 +BRDA:309,0,22,0 +BRDA:309,0,23,2 +BRDA:309,0,24,0 +BRDA:309,0,25,0 +BRDA:309,0,26,1 +BRDA:309,0,27,0 +BRDA:309,0,28,0 +BRDA:309,0,29,0 +BRDA:309,0,30,0 +BRDA:309,0,31,0 +BRDA:309,0,32,0 +DA:310,19 +BRDA:310,0,0,0 +BRDA:310,0,1,2 +BRDA:310,0,2,19 +BRDA:310,0,3,6 +BRDA:310,0,4,7 +BRDA:310,0,5,1 +BRDA:310,0,6,19 +BRDA:310,0,7,3 +BRDA:310,0,8,0 +BRDA:310,0,9,0 +BRDA:310,0,10,0 +DA:311,1 +BRDA:311,0,0,1 +BRDA:311,0,1,1 +BRDA:311,0,2,0 +BRDA:311,0,3,0 +BRDA:311,0,4,0 +BRDA:311,0,5,0 +DA:313,2 +BRDA:313,0,0,0 +BRDA:313,0,1,2 +BRDA:313,0,2,0 +BRDA:313,0,3,0 +BRDA:313,0,4,0 +BRDA:313,0,5,0 +BRDA:313,0,6,0 +BRDA:313,0,7,0 +BRDA:313,0,8,2 +BRDA:313,0,9,0 +BRDA:313,0,10,0 +BRDA:313,0,11,0 +BRDA:313,0,12,0 +BRDA:313,0,13,0 +BRDA:313,0,14,0 +BRDA:313,0,15,0 +BRDA:313,0,16,0 +BRDA:313,0,17,0 +BRDA:313,0,18,0 +BRDA:313,0,19,0 +BRDA:313,0,20,0 +BRDA:313,0,21,0 +BRDA:313,0,22,0 +BRDA:313,0,23,0 +BRDA:313,0,24,0 +BRDA:313,0,25,0 +BRDA:313,0,26,0 +BRDA:313,0,27,0 +BRDA:313,0,28,0 +BRDA:313,0,29,0 +BRDA:313,0,30,0 +BRDA:313,0,31,0 +DA:314,1 +DA:317,21 +DA:318,21 +DA:319,21 +DA:322,10 +DA:324,10 +DA:327,31 +BRDA:327,0,0,0 +BRDA:327,0,1,31 +DA:328,28 +BRDA:328,0,0,3 +BRDA:328,0,1,28 +DA:329,21 +BRDA:329,0,0,21 +BRDA:329,0,1,0 +DA:330,10 +DA:331,10 +BRDA:331,0,0,10 +BRDA:331,0,1,7 +BRDA:331,0,2,3 +BRDA:331,0,3,3 +BRDA:331,0,4,7 +DA:332,10 +BRDA:332,0,0,10 +BRDA:332,0,1,0 +BRDA:332,0,2,10 +DA:334,19 +BRDA:334,0,0,12 +BRDA:334,0,1,19 +BRDA:334,0,2,7 +BRDA:334,0,3,5 +DA:337,11 +BRDA:337,0,0,11 +BRDA:337,0,1,0 +DA:343,11 +BRDA:343,0,0,10 +BRDA:343,0,1,11 +DA:346,11 +DA:347,10 +BRDA:347,0,0,1 +BRDA:347,0,1,0 +BRDA:347,0,2,0 +BRDA:347,0,3,1 +BRDA:347,0,4,1 +BRDA:347,0,5,10 +DA:348,10 +DA:350,11 +BRDA:350,0,0,11 +BRDA:350,0,1,10 +BRDA:350,0,2,1 +BRDA:350,0,3,1 +BRDA:350,0,4,10 +DA:353,55 +BRDA:353,0,0,11 +BRDA:353,0,1,11 +BRDA:353,0,2,0 +BRDA:353,0,3,55 +DA:354,55 +DA:356,44 +BRDA:356,0,0,11 +BRDA:356,0,1,0 +BRDA:356,0,2,11 +BRDA:356,0,3,44 +DA:357,44 +DA:360,11 +BRDA:360,0,0,11 +BRDA:360,0,1,0 +BRDA:360,0,2,0 +BRDA:360,0,3,11 +DA:361,11 +BRF:183 +BRH:39 +end_of_record diff --git a/test_regress/t/t_vlcov_opt_wild.py b/test_regress/t/t_vlcov_opt_wild.py new file mode 100755 index 000000000..7fea40269 --- /dev/null +++ b/test_regress/t/t_vlcov_opt_wild.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "--filter-type '*'", "t/t_vlcov_data_e.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_wrapper_context__top0.dat.out b/test_regress/t/t_wrapper_context__top0.dat.out index 74af3f696..d4620c660 100644 --- a/test_regress/t/t_wrapper_context__top0.dat.out +++ b/test_regress/t/t_wrapper_context__top0.dat.out @@ -1,82 +1,82 @@ # SystemC::Coverage-3 -C 'ft/t_wrapper_context.vl14n22pagev_toggle/topoclkhtop0.top' 21 -C 'ft/t_wrapper_context.vl15n22pagev_toggle/toporsthtop0.top' 2 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[0]htop0.top' 1 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[10]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[11]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[12]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[13]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[14]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[15]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[16]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[17]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[18]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[19]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[1]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[20]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[21]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[22]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[23]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[24]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[25]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[26]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[27]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[28]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[29]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[2]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[30]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[31]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[3]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[4]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[5]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[6]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[7]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[8]htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[9]htop0.top' 0 -C 'ft/t_wrapper_context.vl17n22pagev_toggle/topostophtop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[0]htop0.top' 10 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[10]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[11]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[12]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[13]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[14]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[15]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[16]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[17]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[18]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[19]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[1]htop0.top' 5 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[20]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[21]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[22]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[23]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[24]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[25]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[26]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[27]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[28]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[29]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[2]htop0.top' 2 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[30]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[31]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[3]htop0.top' 1 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[4]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[5]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[6]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[7]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[8]htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[9]htop0.top' 0 -C 'ft/t_wrapper_context.vl19n22pagev_toggle/topodone_ohtop0.top' 1 -C 'ft/t_wrapper_context.vl22n4pagev_line/topoblockS22,25-29htop0.top' 1 -C 'ft/t_wrapper_context.vl32n4pagev_line/topoblockS32htop0.top' 11 -C 'ft/t_wrapper_context.vl33n7pagev_branch/topoifS33-34htop0.top' 1 -C 'ft/t_wrapper_context.vl33n8pagev_branch/topoelseS36htop0.top' 10 -C 'ft/t_wrapper_context.vl38n4pagev_line/topoblockS38-39htop0.top' 34 -C 'ft/t_wrapper_context.vl40n7pagev_branch/topoifS40htop0.top' 0 -C 'ft/t_wrapper_context.vl40n8pagev_branch/topoelseS46htop0.top' 34 -C 'ft/t_wrapper_context.vl41n11pagev_line/topoelsehtop0.top' 0 -C 'ft/t_wrapper_context.vl41n27pagev_expr/topo((counter >= 32'sh5)==0) => 0htop0.top' 0 -C 'ft/t_wrapper_context.vl41n27pagev_expr/topo((counter >= 32'sh5)==1 && stop==1) => 1htop0.top' 0 -C 'ft/t_wrapper_context.vl41n27pagev_expr/topo(stop==0) => 0htop0.top' 0 -C 'ft/t_wrapper_context.vl47n10pagev_branch/topoifS47-49htop0.top' 1 -C 'ft/t_wrapper_context.vl47n11pagev_branch/topoelsehtop0.top' 33 +C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclkhtop0.top' 21 +C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporsthtop0.top' 2 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]htop0.top' 1 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]htop0.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]htop0.top' 0 +C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostophtop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]htop0.top' 10 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]htop0.top' 5 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]htop0.top' 2 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]htop0.top' 1 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]htop0.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]htop0.top' 0 +C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_ohtop0.top' 1 +C 'ft/t_wrapper_context.vl22n4tlinepagev_line/topoblockS22,25-29htop0.top' 1 +C 'ft/t_wrapper_context.vl32n4tlinepagev_line/topoblockS32htop0.top' 11 +C 'ft/t_wrapper_context.vl33n7tbranchpagev_branch/topoifS33-34htop0.top' 1 +C 'ft/t_wrapper_context.vl33n8tbranchpagev_branch/topoelseS36htop0.top' 10 +C 'ft/t_wrapper_context.vl38n4tlinepagev_line/topoblockS38-39htop0.top' 34 +C 'ft/t_wrapper_context.vl40n7tbranchpagev_branch/topoifS40htop0.top' 0 +C 'ft/t_wrapper_context.vl40n8tbranchpagev_branch/topoelseS46htop0.top' 34 +C 'ft/t_wrapper_context.vl41n11tlinepagev_line/topoelsehtop0.top' 0 +C 'ft/t_wrapper_context.vl41n27texprpagev_expr/topo((counter >= 32'sh5)==0) => 0htop0.top' 0 +C 'ft/t_wrapper_context.vl41n27texprpagev_expr/topo((counter >= 32'sh5)==1 && stop==1) => 1htop0.top' 0 +C 'ft/t_wrapper_context.vl41n27texprpagev_expr/topo(stop==0) => 0htop0.top' 0 +C 'ft/t_wrapper_context.vl47n10tbranchpagev_branch/topoifS47-49htop0.top' 1 +C 'ft/t_wrapper_context.vl47n11tbranchpagev_branch/topoelsehtop0.top' 33 diff --git a/test_regress/t/t_wrapper_context__top1.dat.out b/test_regress/t/t_wrapper_context__top1.dat.out index f7fab4025..4b335614e 100644 --- a/test_regress/t/t_wrapper_context__top1.dat.out +++ b/test_regress/t/t_wrapper_context__top1.dat.out @@ -1,82 +1,82 @@ # SystemC::Coverage-3 -C 'ft/t_wrapper_context.vl14n22pagev_toggle/topoclkhtop1.top' 11 -C 'ft/t_wrapper_context.vl15n22pagev_toggle/toporsthtop1.top' 2 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[0]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[10]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[11]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[12]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[13]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[14]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[15]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[16]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[17]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[18]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[19]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[1]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[20]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[21]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[22]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[23]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[24]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[25]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[26]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[27]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[28]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[29]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[2]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[30]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[31]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[3]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[4]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[5]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[6]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[7]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[8]htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22pagev_toggle/topotrace_number[9]htop1.top' 0 -C 'ft/t_wrapper_context.vl17n22pagev_toggle/topostophtop1.top' 1 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[0]htop1.top' 5 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[10]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[11]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[12]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[13]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[14]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[15]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[16]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[17]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[18]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[19]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[1]htop1.top' 2 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[20]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[21]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[22]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[23]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[24]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[25]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[26]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[27]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[28]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[29]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[2]htop1.top' 1 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[30]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[31]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[3]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[4]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[5]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[6]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[7]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[8]htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22pagev_toggle/topocounter[9]htop1.top' 0 -C 'ft/t_wrapper_context.vl19n22pagev_toggle/topodone_ohtop1.top' 1 -C 'ft/t_wrapper_context.vl22n4pagev_line/topoblockS22,25-29htop1.top' 1 -C 'ft/t_wrapper_context.vl32n4pagev_line/topoblockS32htop1.top' 6 -C 'ft/t_wrapper_context.vl33n7pagev_branch/topoifS33-34htop1.top' 1 -C 'ft/t_wrapper_context.vl33n8pagev_branch/topoelseS36htop1.top' 5 -C 'ft/t_wrapper_context.vl38n4pagev_line/topoblockS38-39htop1.top' 19 -C 'ft/t_wrapper_context.vl40n7pagev_branch/topoifS40htop1.top' 19 -C 'ft/t_wrapper_context.vl40n8pagev_branch/topoelseS46htop1.top' 0 -C 'ft/t_wrapper_context.vl41n11pagev_line/topoelsehtop1.top' 18 -C 'ft/t_wrapper_context.vl41n27pagev_expr/topo((counter >= 32'sh5)==0) => 0htop1.top' 18 -C 'ft/t_wrapper_context.vl41n27pagev_expr/topo((counter >= 32'sh5)==1 && stop==1) => 1htop1.top' 1 -C 'ft/t_wrapper_context.vl41n27pagev_expr/topo(stop==0) => 0htop1.top' 0 -C 'ft/t_wrapper_context.vl47n10pagev_branch/topoifS47-49htop1.top' 0 -C 'ft/t_wrapper_context.vl47n11pagev_branch/topoelsehtop1.top' 0 +C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclkhtop1.top' 11 +C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporsthtop1.top' 2 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]htop1.top' 0 +C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]htop1.top' 0 +C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostophtop1.top' 1 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]htop1.top' 5 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]htop1.top' 2 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]htop1.top' 1 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]htop1.top' 0 +C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]htop1.top' 0 +C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_ohtop1.top' 1 +C 'ft/t_wrapper_context.vl22n4tlinepagev_line/topoblockS22,25-29htop1.top' 1 +C 'ft/t_wrapper_context.vl32n4tlinepagev_line/topoblockS32htop1.top' 6 +C 'ft/t_wrapper_context.vl33n7tbranchpagev_branch/topoifS33-34htop1.top' 1 +C 'ft/t_wrapper_context.vl33n8tbranchpagev_branch/topoelseS36htop1.top' 5 +C 'ft/t_wrapper_context.vl38n4tlinepagev_line/topoblockS38-39htop1.top' 19 +C 'ft/t_wrapper_context.vl40n7tbranchpagev_branch/topoifS40htop1.top' 19 +C 'ft/t_wrapper_context.vl40n8tbranchpagev_branch/topoelseS46htop1.top' 0 +C 'ft/t_wrapper_context.vl41n11tlinepagev_line/topoelsehtop1.top' 18 +C 'ft/t_wrapper_context.vl41n27texprpagev_expr/topo((counter >= 32'sh5)==0) => 0htop1.top' 18 +C 'ft/t_wrapper_context.vl41n27texprpagev_expr/topo((counter >= 32'sh5)==1 && stop==1) => 1htop1.top' 1 +C 'ft/t_wrapper_context.vl41n27texprpagev_expr/topo(stop==0) => 0htop1.top' 0 +C 'ft/t_wrapper_context.vl47n10tbranchpagev_branch/topoifS47-49htop1.top' 0 +C 'ft/t_wrapper_context.vl47n11tbranchpagev_branch/topoelsehtop1.top' 0