From 23fe5c1b9386228afe80a42b95e91cde8462d1c4 Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Mon, 10 Jul 2023 18:58:54 +0200 Subject: [PATCH] Fix string concatenations (#4354) --- src/V3Width.cpp | 8 +++++--- test_regress/t/t_concat_string.pl | 21 +++++++++++++++++++++ test_regress/t/t_concat_string.v | 24 ++++++++++++++++++++++++ test_regress/t/t_xml_debugcheck.out | 22 ++++++++++++---------- 4 files changed, 62 insertions(+), 13 deletions(-) create mode 100755 test_regress/t/t_concat_string.pl create mode 100644 test_regress/t/t_concat_string.v diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 1a0d899b2..f57c272cb 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -617,9 +617,11 @@ private: } if (m_vup->final()) { if (nodep->lhsp()->isString() || nodep->rhsp()->isString()) { - AstNode* const newp - = new AstConcatN{nodep->fileline(), nodep->lhsp()->unlinkFrBack(), - nodep->rhsp()->unlinkFrBack()}; + AstNodeExpr* lhsp = nodep->lhsp()->unlinkFrBack(); + AstNodeExpr* rhsp = nodep->rhsp()->unlinkFrBack(); + if (!lhsp->isString()) lhsp = new AstCvtPackString{lhsp->fileline(), lhsp}; + if (!rhsp->isString()) rhsp = new AstCvtPackString{rhsp->fileline(), rhsp}; + AstNode* const newp = new AstConcatN{nodep->fileline(), lhsp, rhsp}; nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); return; diff --git a/test_regress/t/t_concat_string.pl b/test_regress/t/t_concat_string.pl new file mode 100755 index 000000000..1aa73f80a --- /dev/null +++ b/test_regress/t/t_concat_string.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_concat_string.v b/test_regress/t/t_concat_string.v new file mode 100644 index 000000000..680dc8caa --- /dev/null +++ b/test_regress/t/t_concat_string.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +typedef enum {efgh} en; + +module t (/*AUTOARG*/); + initial begin + en e; + string s; + + s = {"a", "b"}; + if (s != "ab") $stop; + + e = efgh; + s = {"abcd", e.name(), "ijkl"}; + if (s != "abcdefghijkl") $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_xml_debugcheck.out b/test_regress/t/t_xml_debugcheck.out index 11a9f8501..9e7447c4c 100644 --- a/test_regress/t/t_xml_debugcheck.out +++ b/test_regress/t/t_xml_debugcheck.out @@ -543,15 +543,17 @@ - - - - - - - - - + + + + + + + + + + + @@ -578,7 +580,7 @@ - +