From 23ea3d7f11aa922d6b2bdff520d00393489accd5 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 21 Apr 2026 00:33:40 -0400 Subject: [PATCH] Commentary: Changes update --- Changes | 12 ++++++++++-- docs/guide/verilating.rst | 2 +- docs/spelling.txt | 3 +++ test_regress/t/t_assert_consec_rep_unsup.out | 4 ++-- test_regress/t/t_assert_consec_rep_unsup.v | 4 +++- test_regress/t/t_param_type_struct_member.v | 10 ++++++++-- test_regress/t/t_param_type_struct_member2.v | 12 +++++------- 7 files changed, 32 insertions(+), 15 deletions(-) diff --git a/Changes b/Changes index 85e13e2c3..a63de82f7 100644 --- a/Changes +++ b/Changes @@ -65,9 +65,11 @@ Verilator 5.047 devel * Improve assignment-compatibility type check (#2843) (#5666) (#7052). [Pawel Kojma, Antmicro Ltd.] * Improve error message when variable used as data type (#7318). [Ryszard Rozak, Antmicro Ltd.] * Improve E_UNSUPPORTED warning messages (#7329). [Eunseo Song] +* Improve NFA-based multi-cycle SVA evaluation engine (#7430). [Yilou Wang] * Change array tracing to dump left index to right index (#7205). [Geza Lore, Testorrent USA, Inc.] * Change `--converge-limit` default to 10000 (#7209). * Remove DFG extract optimization pass (#7394). [Geza Lore, Testorrent USA, Inc.] +* Remove multi-threaded FST tracing (#7443). [Geza Lore, Testorrent USA, Inc.] * Optimize trace code for faster compiles on repeated types (#6707) (#6832). [Todd Strader] * Optimize size of trace declaration object code (#7150). [Szymon Gizler, Antmicro Ltd.] * Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.] @@ -80,11 +82,15 @@ Verilator 5.047 devel * Optimize more patterns in DfgPeephole (#7332). [Geza Lore, Testorrent USA, Inc.] * Optimize read references in DFG (#7354). [Geza Lore, Testorrent USA, Inc.] * Optimize DFG only once, after scoping (#7362). [Geza Lore, Testorrent USA, Inc.] -* Optimize more DFG peephole patterns (#7423). [Geza Lore, Testorrent USA, Inc.] +* Optimize more DFG peephole patterns (#7423) (#7452). [Geza Lore, Testorrent USA, Inc.] +* Optimize DfgBreakCycles IndependentBits analysis ordering (#7446). [Geza Lore, Testorrent USA, Inc.] +* Optimize select patterns in DfgPeephole. [Geza Lore, Testorrent USA, Inc.] +* Optimize temporary insertion in DfgPeephole. [Geza Lore, Testorrent USA, Inc.] +* Optimize arithmetic right shift (>>>) in DfgBreakCycles (#7447). [Geza Lore, Testorrent USA, Inc.] * Fix recursive default assignment for sub-arrays (#4589) (#7202). [Julian Carrier] * Fix virtual interface member trigger convergence (#5116) (#7323). [Yilou Wang] * Fix shift width mismatch in constraint solver SMT emission (#5420) (#7265). [Yilou Wang] -* Fix returning wrong type from static function in parameterized class (#5479) (#7387) (#7411) (#7418). [em2machine] +* Fix returning wrong type from static function in parameterized class (#5479) (#7387) (#7411) (#7418) (#7445) (#7450). [em2machine] * Fix randomize size+element queue constraints (#5582) (#7225). [Rahul Behl, Testorrent USA, Inc.] * Fix null assignment to virtual interfaces (#5974) (#5990). [Maxim Fonarev] * Fix typedef scope resolution for parameterized class aliases (#5977) (#7319). [Nick Brereton] @@ -151,8 +157,10 @@ Verilator 5.047 devel * Fix delete inside foreach skipping elements (#7407) (#7410) * Fix std::randomize in parameterized-derived class (#7409) (#7416). [Yilou Wang] * Fix virtual interface implied comparison with null (#7421). [Alex Solomatnikov] +* Fix uvm_hdl_release_and_read to release value and check success (#7425). [Christian Hecken, Heidelberg University] * Fix inline constraint on array-indexed randomize target (#7431) (#7434). [Yilou Wang] * Fix modification of members of object with const handle (#7433). [Kamil Danecki, Antmicro Ltd.] +* Fix `dist` under implication in constraints (#7440) (#7442). [Alex Solomatnikov] [Yilou Wang] Verilator 5.046 2026-02-28 diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst index a91eb66b9..80de09f58 100644 --- a/docs/guide/verilating.rst +++ b/docs/guide/verilating.rst @@ -505,7 +505,7 @@ include directories and link to the SystemC libraries. Deprecated and has no effect. - Before Verialtor 5.048: Optional. Enable multithreaded FST trace; see + In versions before 5.048: Optional. Enable multithreaded FST trace; see :vlopt:`--trace-threads`. .. describe:: TRACE_VCD diff --git a/docs/spelling.txt b/docs/spelling.txt index 7e86ffdad..80b6c176f 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -333,6 +333,7 @@ Muhlestein Multithreaded Multithreading Mykyta +NFA NOUNOPTFLAT NaN Nalbantis @@ -837,6 +838,7 @@ gotFinish goto gprof gtkwave +hdl hdr hdzhangdoc hh @@ -1211,6 +1213,7 @@ upcasting urandom uselib utimes +uvm uwire uwires valgrind diff --git a/test_regress/t/t_assert_consec_rep_unsup.out b/test_regress/t/t_assert_consec_rep_unsup.out index 9129daa7f..69a178932 100644 --- a/test_regress/t/t_assert_consec_rep_unsup.out +++ b/test_regress/t/t_assert_consec_rep_unsup.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_assert_consec_rep_unsup.v:11:45: Unsupported: multi-cycle sequence expression inside consecutive repetition (IEEE 1800-2023 16.9.2) +%Error-UNSUPPORTED: t/t_assert_consec_rep_unsup.v:13:45: Unsupported: multi-cycle sequence expression inside consecutive repetition (IEEE 1800-2023 16.9.2) : ... note: In instance 't' - 11 | assert property (@(posedge clk) (a ##1 b) [* 2] |-> a); + 13 | assert property (@(posedge clk) (a ##1 b) [* 2] |-> a); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assert_consec_rep_unsup.v b/test_regress/t/t_assert_consec_rep_unsup.v index 3fe3fba7a..d7dd174db 100644 --- a/test_regress/t/t_assert_consec_rep_unsup.v +++ b/test_regress/t/t_assert_consec_rep_unsup.v @@ -4,7 +4,9 @@ // SPDX-FileCopyrightText: 2026 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 -module t (input clk); +module t ( + input clk +); logic a, b; // Unsupported: multi-cycle sequence expression inside consecutive repetition diff --git a/test_regress/t/t_param_type_struct_member.v b/test_regress/t/t_param_type_struct_member.v index a493b99a6..2d678c756 100644 --- a/test_regress/t/t_param_type_struct_member.v +++ b/test_regress/t/t_param_type_struct_member.v @@ -25,13 +25,19 @@ module mid #( parameter type interrupts_t = logic, parameter interrupts_t INTERRUPTS = '0 ) (); - leaf #(.interrupts_t(interrupts_t), .INTERRUPTS(INTERRUPTS)) l(); + leaf #( + .interrupts_t(interrupts_t), + .INTERRUPTS(INTERRUPTS) + ) l (); endmodule module t; localparam type irq_t = my_irq_t; localparam irq_t IRQ = '{S_TIMER: 8'hAA, M_TIMER: 8'h55, M_EXT: 8'hCC}; - mid #(.interrupts_t(irq_t), .INTERRUPTS(IRQ)) m(); + mid #( + .interrupts_t(irq_t), + .INTERRUPTS(IRQ) + ) m (); initial begin #1; if (m.l.observed !== 8'h55) begin diff --git a/test_regress/t/t_param_type_struct_member2.v b/test_regress/t/t_param_type_struct_member2.v index cf2173583..acaf67a9a 100644 --- a/test_regress/t/t_param_type_struct_member2.v +++ b/test_regress/t/t_param_type_struct_member2.v @@ -10,15 +10,13 @@ // verilog_format: on package pkg; - typedef struct packed { - logic [1:0][31:0] bar; - } T; + typedef struct packed {logic [1:0][31:0] bar;} T; localparam T t = 64'h87654321_deadbeef; endpackage module foo #( - parameter type T = int, - parameter T t = 0 + parameter type T = int, + parameter T t = 0 ) (); initial begin `checkh(t.bar[0], 32'hdeadbeef); @@ -30,7 +28,7 @@ endmodule module top; foo #( - .T(pkg::T), - .t(pkg::t) + .T(pkg::T), + .t(pkg::t) ) u_foo (); endmodule