From 232d3ecc0cb1a8ac98dc0a34ce6e23f8585dc635 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 21 Sep 2026 08:06:30 -0400 Subject: [PATCH] Commentary: Changes update --- Changes | 7 +++++++ README.rst | 18 +++++++++--------- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/Changes b/Changes index 2713443ad..5282ce5bd 100644 --- a/Changes +++ b/Changes @@ -29,6 +29,7 @@ Verilator 5.053 devel * Support logic and set operations on binsof (#8306). [Marco Bartoli] * Support `illegal_bins` and `ignore_bins` for cross bins (#8372). [Marco Bartoli] * Support `iff` in covergroup bins (#8406) (#8407). [Marco Bartoli] +* Support enclosing cross identifiers in bin selections (#8416). [Marco Bartoli] * Optimize NBA shadow copies for partial writes (#8266). [Artur Bieniek, Antmicro Ltd.] * Optimize recursion depth in DFG circular driver tracing (#8272). [Drew Risinger] * Optimize DFG synthesis symbol table ordering (#8282). [Geza Lore, Testorrent USA, Inc.] @@ -47,6 +48,7 @@ Verilator 5.053 devel * Optimize wide four-state constant operations in V3Number (#8333). [CatalpaEel] * Optimize split pass (#8385). [Geza Lore, Testorrent USA, Inc.] * Optimize covergroup bin metadata lookup (#8404). [Marco Bartoli] +* Optimize away dead ports (#8426). [Geza Lore, Testorrent USA, Inc.] * Fix array slice crash when used as a bare value (#5132) (#8262). [Marco Frank] * Fix pattern type matching against nested aggregates (#7304). * Fix covergroup-internal references multi-threaded ordering (#7779) (#8255). [Matthew Ballance] @@ -59,6 +61,7 @@ Verilator 5.053 devel * Fix assignment pattern default fill of an array of unpacked structs (#8289). [Nick Brereton] * Fix escape strings in pattern formatting (#8297). [Marco Bartoli] * Fix DECLFILENAME warning on nested declarations (#8302). [Martijn Wobbes] +* Fix cache of boundary vertices in DFG cycle-breaking (#8308). [Shriyans Sahoo] * Fix property and sequence line coverage (#8314). [Andrii, Antmicro Ltd.] * Fix wide typed pattern formatting primitives (#8325). [Marco Bartoli] * Fix parameterized class nested in a parameterized interface (#8328) (#8329). [Kristof Marien] @@ -82,6 +85,10 @@ Verilator 5.053 devel * Fix compile-time blowup forcing large unpacked arrays (#8395). [Jonathan Drolet] * Fix covergroup constructor initialization (#8410). [Marco Bartoli] * Fix issues with configuring flex during build on MacOS (#8412). [Kaleb Barrett] +* Fix interface modport resolution against non-scope symbol tables (#8420). [Geza Lore, Testorrent USA, Inc.] +* Fix FSM coverage hierarchy being emitted as an absolute path (#8421). [Geza Lore, Testorrent USA, Inc.] +* Fix MSYS header include search to be after toolchain headers (#8422). [Kaleb Barrett] +* Fix losing coverage declarations if first in a module body (#8425). [Geza Lore, Testorrent USA, Inc.] Verilator 5.052 2026-09-05 diff --git a/README.rst b/README.rst index 490c3b798..6dd983c0d 100644 --- a/README.rst +++ b/README.rst @@ -35,7 +35,7 @@ Welcome to Verilator .. list-table:: - - **Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.** - - Accepts Verilog or SystemVerilog + - Accepts Verilog or SystemVerilog, including UVM - Performs lint code-quality checks - Compiles into multithreaded C++, or SystemC - Creates JSON to front-end your own tools @@ -75,14 +75,14 @@ instantiate the model. The resulting Verilated executable performs the design simulation. Verilator also supports linking Verilator-generated libraries, optionally encrypted, into other simulators. -Verilator supports all design constructs, most verification constructs, -intra-assignment delays (e.g, `#10`), and events. Tristate-bus (`z`) and -unknowns (`x`) are handled in limited contexts, in a special manor for -performance. It currently may not be the best choice if you are expecting a -full-featured replacement for a closed-source Verilog simulator, performing -SDF annotation, or mixed-signal simulation. However, if you are looking for -a path to migrate SystemVerilog to C++/SystemC, or want high-speed -simulation, Verilator is the tool for you. +Verilator supports all design constructs, most verification constructs +including UVM, intra-assignment delays (e.g, `#10`), and events. +Tristate-bus (`z`) and unknowns (`x`) are handled in limited contexts, in a +special manor for performance. It currently may not be the best choice if +you are expecting a full-featured replacement for a closed-source Verilog +simulator, performing SDF annotation, or mixed-signal simulation. However, +if you are looking for a path to migrate SystemVerilog to C++/SystemC, or +want high-speed simulation, Verilator is the tool for you. Performance ===========