From 230ce772c2742faf2c4d036e8af0e156572e1f94 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 28 Feb 2026 18:19:34 -0500
Subject: [PATCH] Tests: Verilog format; rename test

---
 test_regress/t/t_array_sel_short.v            | 12 +--
 test_regress/t/t_coroutine_lambda.v           | 78 ++++++++++---------
 .../t/{t_lift_expr.py => t_opt_lift_expr.py}  |  0
 .../t/{t_lift_expr.v => t_opt_lift_expr.v}    |  0
 4 files changed, 46 insertions(+), 44 deletions(-)
 rename test_regress/t/{t_lift_expr.py => t_opt_lift_expr.py} (100%)
 rename test_regress/t/{t_lift_expr.v => t_opt_lift_expr.v} (100%)

diff --git a/test_regress/t/t_array_sel_short.v b/test_regress/t/t_array_sel_short.v
index aa669f231..8c5fabd21 100644
--- a/test_regress/t/t_array_sel_short.v
+++ b/test_regress/t/t_array_sel_short.v
@@ -6,12 +6,12 @@
 
 module t;
 
-   logic [15:0] foo [8];
+  logic [15:0] foo[8];
 
-   initial begin
-      if (foo[1] != foo[1]) $stop;
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  initial begin
+    if (foo[1] != foo[1]) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 
 endmodule
diff --git a/test_regress/t/t_coroutine_lambda.v b/test_regress/t/t_coroutine_lambda.v
index c0a7eb6c0..28b3b8433 100644
--- a/test_regress/t/t_coroutine_lambda.v
+++ b/test_regress/t/t_coroutine_lambda.v
@@ -5,51 +5,53 @@
 // or the Perl Artistic License Version 2.0.
 // SPDX-FileCopyrightText: 2026 Wilson Snyder
 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-interface cpu_if(input logic clk);
+interface cpu_if (
+    input logic clk
+);
 endinterface
 
 package p;
 
-virtual class WriterIf;
-  virtual function void write(input int t);
-  endfunction
-endclass
+  virtual class WriterIf;
+    virtual function void write(input int t);
+    endfunction
+  endclass
 
-class BlockingWriter;
-  virtual cpu_if vif;
-  task write(int t);
-    @(posedge vif.clk);
-  endtask
-endclass
+  class BlockingWriter;
+    virtual cpu_if vif;
+    task write(int t);
+      @(posedge vif.clk);
+    endtask
+  endclass
 
-class WriterAdapter extends WriterIf;
-  BlockingWriter m_impl;
-  function new(BlockingWriter impl);
-    m_impl = impl;
-  endfunction
-  function void write(input int t);
-    m_impl.write(t);  // function -> task path
-  endfunction
-endclass
+  class WriterAdapter extends WriterIf;
+    BlockingWriter m_impl;
+    function new(BlockingWriter impl);
+      m_impl = impl;
+    endfunction
+    function void write(input int t);
+      m_impl.write(t);  // function -> task path
+    endfunction
+  endclass
 
-class QueueLike;
-  WriterIf sink;
-  mailbox #(int) m;
-  function bit try_get(output int t);
-    if (!m.try_get(t)) begin
-    end
-    sink.write(t);  // can become coroutine call
-  endfunction
-endclass
+  class QueueLike;
+    WriterIf sink;
+    mailbox #(int) m;
+    function bit try_get(output int t);
+      if (!m.try_get(t)) begin
+      end
+      sink.write(t);  // can become coroutine call
+    endfunction
+  endclass
 
-class DriverLike;
-  QueueLike reqq;
-  function void item_done();
-    int t;
-    if (reqq.try_get(t) == 0) begin
-    end
-  endfunction
-endclass
+  class DriverLike;
+    QueueLike reqq;
+    function void item_done();
+      int t;
+      if (reqq.try_get(t) == 0) begin
+      end
+    endfunction
+  endclass
 
 endpackage
 
@@ -57,7 +59,7 @@ module t;
   import p::*;
 
   logic clk = 0;
-  cpu_if vif(clk);
+  cpu_if vif (clk);
 
   always #1 clk = ~clk;
 
diff --git a/test_regress/t/t_lift_expr.py b/test_regress/t/t_opt_lift_expr.py
similarity index 100%
rename from test_regress/t/t_lift_expr.py
rename to test_regress/t/t_opt_lift_expr.py
diff --git a/test_regress/t/t_lift_expr.v b/test_regress/t/t_opt_lift_expr.v
similarity index 100%
rename from test_regress/t/t_lift_expr.v
rename to test_regress/t/t_opt_lift_expr.v