From 2207217df3839ad9b17b34115548ab2694e57341 Mon Sep 17 00:00:00 2001 From: Tobias Rosenkranz Date: Mon, 27 Jan 2020 22:29:53 +0100 Subject: [PATCH] Added unittest for unsupported arguments --- test_regress/t/t_enum_type_methods_bad.out | 5 ++++ test_regress/t/t_enum_type_methods_bad.pl | 18 ++++++++++++++ test_regress/t/t_enum_type_methods_bad.v | 28 ++++++++++++++++++++++ 3 files changed, 51 insertions(+) create mode 100644 test_regress/t/t_enum_type_methods_bad.out create mode 100755 test_regress/t/t_enum_type_methods_bad.pl create mode 100644 test_regress/t/t_enum_type_methods_bad.v diff --git a/test_regress/t/t_enum_type_methods_bad.out b/test_regress/t/t_enum_type_methods_bad.out new file mode 100644 index 000000000..e4e984915 --- /dev/null +++ b/test_regress/t/t_enum_type_methods_bad.out @@ -0,0 +1,5 @@ +%Error: Internal Error: t/t_enum_type_methods_bad.v:24: ../V3Width.cpp:#: Unsupported: enum next/prev with non-const argument + : ... In instance t + e.next(increment); + ^~~~ + ... See the manual and https://verilator.org for more assistance. diff --git a/test_regress/t/t_enum_type_methods_bad.pl b/test_regress/t/t_enum_type_methods_bad.pl new file mode 100755 index 000000000..45ec8147c --- /dev/null +++ b/test_regress/t/t_enum_type_methods_bad.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(simulator => 1); + +compile( + fails => 1, + expect_filename => $Self->{golden_filename} + ); + +ok(1); +1; diff --git a/test_regress/t/t_enum_type_methods_bad.v b/test_regress/t/t_enum_type_methods_bad.v new file mode 100644 index 000000000..9f0a2623f --- /dev/null +++ b/test_regress/t/t_enum_type_methods_bad.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk, + increment + ); + input clk; + input [1:0] increment; + + typedef enum [3:0] { + E01 = 1, + E03 = 3, + E04 = 4, + E05 = 5 + } my_t; + + my_t e; + + always @ (posedge clk) begin + e.next(increment); + $finish; + end + +endmodule