diff --git a/Changes b/Changes
index e214c0496..6ecc68aba 100644
--- a/Changes
+++ b/Changes
@@ -19,7 +19,9 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix $signed casts under generates, bug999. [Clifford Wolf]
 
-****  Fix genvar constant propagation from package, bug1004. [Johan Bjork]
+****  Fix genvar constant propagation, bug1003. [Johan Bjork]
+
+****  Fix parameter constant propagation from package, bug1004. [Johan Bjork]
 
 
 * Verilator 3.878 2015-11-01
diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp
index 915c74799..00df5504c 100644
--- a/src/V3Unroll.cpp
+++ b/src/V3Unroll.cpp
@@ -51,7 +51,6 @@ private:
     AstVarScope*	m_forVscp;		// Iterator variable scope (NULL for generate pass)
     AstConst*		m_varValuep;		// Current value of loop
     AstNode*		m_ignoreIncp;		// Increment node to ignore
-    AstAttrOf*		m_attrp;		// Current attribute
     bool		m_varModeCheck;		// Just checking RHS assignments
     bool		m_varModeReplace;	// Replacing varrefs
     bool		m_varAssignHit;		// Assign var hit
@@ -401,12 +400,6 @@ private:
 	    nodep->v3error("V3Begin should have removed standard FORs");
 	}
     }
-    virtual void visit(AstAttrOf* nodep, AstNUser*) {
-	AstAttrOf* oldAttr = m_attrp;
-	m_attrp = nodep;
-	nodep->iterateChildren(*this);
-	m_attrp = oldAttr;
-    }
 
     virtual void visit(AstVarRef* nodep, AstNUser*) {
 	if (m_varModeCheck
@@ -416,11 +409,11 @@ private:
 	    UINFO(8,"   Itervar assigned to: "<<nodep<<endl);
 	    m_varAssignHit = true;
 	}
+
 	if (m_varModeReplace
 	    && nodep->varp() == m_forVarp
 	    && nodep->varScopep() == m_forVscp
-	    && !nodep->lvalue()
-	    && !m_attrp) {  // Most likely under a select
+	    && !nodep->lvalue()) {
 	    AstNode* newconstp = m_varValuep->cloneTree(false);
 	    nodep->replaceWith(newconstp);
 	    pushDeletep(nodep);
@@ -447,7 +440,6 @@ public:
 	m_varModeReplace = false;
 	m_generate = generate;
 	m_beginName = beginName;
-	m_attrp = NULL;
 	//
 	nodep->accept(*this);
     }
diff --git a/test_regress/t/t_gen_for2.pl b/test_regress/t/t_gen_for2.pl
new file mode 100755
index 000000000..f91289753
--- /dev/null
+++ b/test_regress/t/t_gen_for2.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gen_for2.v b/test_regress/t/t_gen_for2.v
new file mode 100644
index 000000000..f4f83a8cb
--- /dev/null
+++ b/test_regress/t/t_gen_for2.v
@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Johan Bjork.
+
+parameter N = 5;
+
+interface intf;
+   logic [N-1:0] data;
+endinterface
+
+module t (
+   input logic clk
+   );
+   intf localinterface [N-1:0]();
+
+   generate
+      genvar   i,j;
+      for(i = 0; i  < N; i++) begin
+         logic [N-1:0] dummy;
+         for(j = 0; j < N; j++) begin
+            assign dummy[j] = localinterface[j].data[i];
+         end
+      end
+   endgenerate
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule