diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp
index 3d8a270fd..ce67691ed 100644
--- a/src/V3LinkResolve.cpp
+++ b/src/V3LinkResolve.cpp
@@ -376,6 +376,7 @@ class LinkResolveVisitor final : public VNVisitor {
         expectFormat(nodep, nodep->text(), nodep->exprsp(), true);
     }
     void visit(AstSFormatF* nodep) override {
+        if (nodep->user2SetOnce()) return;
         iterateChildren(nodep);
         // Cleanup old-school displays without format arguments
         if (!nodep->hasFormat()) {
diff --git a/test_regress/t/t_initial_assign_sformatf.pl b/test_regress/t/t_initial_assign_sformatf.pl
new file mode 100755
index 000000000..b46d46042
--- /dev/null
+++ b/test_regress/t/t_initial_assign_sformatf.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_initial_assign_sformatf.v b/test_regress/t/t_initial_assign_sformatf.v
new file mode 100644
index 000000000..7ff94eaba
--- /dev/null
+++ b/test_regress/t/t_initial_assign_sformatf.v
@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: SystemVerilog interface test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Iztok Jeras.
+// SPDX-License-Identifier: CC0-1.0
+
+interface intf();
+
+   function automatic string get_scope;
+      string the_scope = $sformatf("%m");
+      return the_scope;
+   endfunction
+
+   initial $display(get_scope());
+endinterface
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   // finish report
+   always @ (posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   intf the_intf();
+
+endmodule
diff --git a/test_regress/t/t_initial_assign_sformatf_debug.pl b/test_regress/t/t_initial_assign_sformatf_debug.pl
new file mode 100755
index 000000000..281cd4b10
--- /dev/null
+++ b/test_regress/t/t_initial_assign_sformatf_debug.pl
@@ -0,0 +1,24 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+top_filename("t/t_initial_assign_sformatf.v");
+
+compile(
+    verilator_flags2 => ['--debug'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;