diff --git a/src/verilog.y b/src/verilog.y
index 627e457e9..513d2ff07 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -6564,9 +6564,11 @@ property_port_itemFront:  // IEEE: part of property_port_item/sequence_port_item
 
 property_port_itemAssignment<nodep>:  // IEEE: part of property_port_item/sequence_port_item
                 id variable_dimensionListE
-                        { $$ = VARDONEA($<fl>1, *$1, $2, nullptr); }
+                        { VARDECL(VAR);
+                          $$ = VARDONEA($<fl>1, *$1, $2, nullptr); }
         |       id variable_dimensionListE '=' property_actual_arg
-                        { $$ = VARDONEA($<fl>1, *$1, $2, $4);
+                        { VARDECL(VAR);
+                          $$ = VARDONEA($<fl>1, *$1, $2, $4);
                           BBUNSUP($3, "Unsupported: property variable default value"); }
         ;
 
diff --git a/test_regress/t/t_property_arg_type.py b/test_regress/t/t_property_arg_type.py
new file mode 100755
index 000000000..8e271fdb8
--- /dev/null
+++ b/test_regress/t/t_property_arg_type.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.passes()
diff --git a/test_regress/t/t_property_arg_type.v b/test_regress/t/t_property_arg_type.v
new file mode 100644
index 000000000..a0acc8bfb
--- /dev/null
+++ b/test_regress/t/t_property_arg_type.v
@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+// Test to assert that property argument type is not retained from
+// the previous variable and is not causing errors
+
+module t(input clk);
+  genvar i;
+  property prop(prop_arg);
+    @(posedge clk)
+    (prop_arg |-> prop_arg);
+  endproperty
+
+  wire w;
+  property prop2(prop_arg);
+    @(posedge clk)
+    (prop_arg |-> prop_arg);
+  endproperty
+
+  initial begin
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule