From 1f6796a804ee9a3ae2f84fda3bc46d23694eee0a Mon Sep 17 00:00:00 2001
From: Mateusz Gancarz <mgancarz@antmicro.com>
Date: Mon, 17 Feb 2025 15:10:39 +0100
Subject: [PATCH] [#72179] wip: add SAIF file parser for testing backend

---
 test_regress/vcd_to_saif.py | 85 ++++++++++++++++++++++++++-----------
 1 file changed, 61 insertions(+), 24 deletions(-)

diff --git a/test_regress/vcd_to_saif.py b/test_regress/vcd_to_saif.py
index bc62c57a5..6994a9ef8 100644
--- a/test_regress/vcd_to_saif.py
+++ b/test_regress/vcd_to_saif.py
@@ -1,10 +1,11 @@
 import re
 from collections import defaultdict
 
-class SignalBit:
+class SAIFSignalBit:
     def __init__(self):
         self.last_val = 0
         self.high_time = 0
+        self.low_time = 0
         self.transitions = 0
 
     def aggregate(self, dt, new_val):
@@ -16,19 +17,24 @@ class SignalBit:
 
         self.last_val = new_val
 
-class Signal:
+class SAIFSignal:
     def __init__(self, signal_name, signal_width):
         self.name = signal_name
         self.width = signal_width
+        self.last_time = 0
 
         self.bits = []
         for _ in range(self.width):
-            self.bits.append(SignalBit())
+            self.bits.append(SAIFSignalBit())
 
+    def __init__(self, signal_name):
+        self.name = signal_name
+        self.bits = []
         self.last_time = 0
+        self.width = 0
 
 
-class VCDParser:
+class VCDToSAIFParser:
     def __init__(self):
         self.signal_definitions = {}
         self.current_time = 0
@@ -43,7 +49,7 @@ class VCDParser:
                 match = re.match(r'\$var\s+(\w+)\s+(\d+)\s+(\S+)\s+(\S+)\s*(\S*)\s*\$end', line)
                 if match:
                     _, signal_width, signal_id, signal_name, _ = match.groups()
-                    self.signal_definitions[signal_id] = Signal(signal_name, int(signal_width))
+                    self.signal_definitions[signal_id] = SAIFSignal(signal_name, int(signal_width))
                     continue
 
                 match = re.match(r'\#(\d+)', line)
@@ -75,29 +81,60 @@ class VCDParser:
 
                     self.signal_definitions[signal_id].bits[0].aggregate(dt, int(value))
 
+            for _, signal in self.signal_definitions.items():
+                for i in range(signal.width):
+                    if signal.bits[i].last_val == 1:
+                        signal.bits[i].high_time += self.current_time - signal.last_time
 
-def generate_saif(vcd_parser, saif_filename):
-    with open(saif_filename, 'w') as saif_file:
-        for _, activity in vcd_parser.signal_definitions.items():
-            index = 0
-            for activity_bit in activity.bits:
-                if activity_bit.transitions <= 0:
-                    index += 1
+
+class SAIFParser:
+    def __init__(self):
+        self.signal_definitions = {}
+
+    def parse(self, saif_filename):
+        with open(saif_filename, 'r') as saif_file:
+            for line in saif_file:
+                line = line.strip()
+                if not line:
                     continue
 
-                if activity_bit.last_val == 1:
-                    activity_bit.high_time += vcd_parser.current_time - activity.last_time
+                match = re.search(r'(\w+)\[*(\d*)\]*\s+(\(T(.+)\))+', line)
+                if match:
+                    signal_name, bit_index, bit_values, _ = match.groups()
 
-                if activity.width <= 1:
-                    saif_file.write(f"{activity.name} (T0 {vcd_parser.current_time - activity_bit.high_time}) (T1 {activity_bit.high_time}) (TZ 0) (TX 0) (TB 0) (TC {activity_bit.transitions})\n")
-                else:    
-                    saif_file.write(f"{activity.name}[{index}] (T0 {vcd_parser.current_time - activity_bit.high_time}) (T1 {activity_bit.high_time}) (TZ 0) (TX 0) (TB 0) (TC {activity_bit.transitions})\n")
-                index += 1
+                    if bit_index == '':
+                        bit_index = 0
 
-def vcd_to_saif(vcd_filename, saif_filename):
-    vcd_parser = VCDParser()
+                    if signal_name not in self.signal_definitions:
+                        self.signal_definitions[signal_name] = SAIFSignal(signal_name)
 
-    vcd_parser.parse(vcd_filename)
-    generate_saif(vcd_parser, saif_filename)
+                    for _ in range(0, int(bit_index) - self.signal_definitions[signal_name].width + 1):
+                        self.signal_definitions[signal_name].bits.append(SAIFSignalBit())
+                        
+                    self.signal_definitions[signal_name].width = int(bit_index) + 1
 
-vcd_to_saif('input.vcd', 'output.saif')
\ No newline at end of file
+                    match = re.search(r'T0 (\d+)', bit_values)
+                    if match:
+                        low_time = match.groups()[0]
+
+                        self.signal_definitions[signal_name].bits[int(bit_index)].low_time = low_time
+
+                    match = re.search(r'T1 (\d+)', bit_values)
+                    if match:
+                        high_time = match.groups()[0]
+                        
+                        self.signal_definitions[signal_name].bits[int(bit_index)].high_time = high_time
+
+                    match = re.search(r'TC (\d+)', bit_values)
+                    if match:
+                        toggle_count = match.groups()[0]
+                        
+                        self.signal_definitions[signal_name].bits[int(bit_index)].transitions = toggle_count
+
+
+saif_parser = SAIFParser()
+saif_parser.parse("simx.saif")
+
+for signal_name, signal in saif_parser.signal_definitions.items():
+    for bit in range(signal.width):
+        print(f"{signal.name}[{bit}] (T0 {signal.bits[bit].low_time}) (T1 {signal.bits[bit].high_time}) (TC {signal.bits[bit].transitions})")
\ No newline at end of file