From 1f19e8e2064658f5e0949c644b4ad2b3889343cd Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 6 Jun 2021 09:17:56 -0400
Subject: [PATCH] Tests: Add test case for #2895.

---
 test_regress/t/t_unpacked_str_init2.pl | 20 +++++++++++++
 test_regress/t/t_unpacked_str_init2.v  | 39 ++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)
 create mode 100755 test_regress/t/t_unpacked_str_init2.pl
 create mode 100644 test_regress/t/t_unpacked_str_init2.v

diff --git a/test_regress/t/t_unpacked_str_init2.pl b/test_regress/t/t_unpacked_str_init2.pl
new file mode 100755
index 000000000..235ca326a
--- /dev/null
+++ b/test_regress/t/t_unpacked_str_init2.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+# TODO change to compile()
+lint(
+    );
+
+# No execute, not self-checking
+
+ok(1);
+1;
diff --git a/test_regress/t/t_unpacked_str_init2.v b/test_regress/t/t_unpacked_str_init2.v
new file mode 100644
index 000000000..9481aafb8
--- /dev/null
+++ b/test_regress/t/t_unpacked_str_init2.v
@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2018 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// issue2895
+
+module t (/*AUTOARG*/);
+
+   localparam string REG_X [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0",
+                                      "t1", "t2", "s0/fp", "s1", "a0", "a1",
+                                      "a2", "a3", "a4", "a5", "a6", "a7", "s2",
+                                      "s3", "s4", "s5", "s6", "s7", "s8", "s9",
+                                      "s10", "s11", "t3", "t4", "t5", "t6"};
+
+   function string reg_x (logic [4:0] r, bit abi=1'b0);
+      reg_x = abi ? REG_X[r] : $sformatf("x%0d", r);
+   endfunction
+
+   // the issue is triggered by a second function containing a case statement
+   function string f2 (logic [4:0] r, bit abi=0);
+      case (r)
+        5'd0:    f2 = $sformatf("nop");
+        5'd1:    f2 = $sformatf("reg %s", reg_x(r[4:0], abi));
+        default: f2 = $sformatf("ILLEGAL");
+      endcase
+   endfunction
+
+   initial begin
+      for (int unsigned i = 0; i < 32; ++i) begin
+         $display("REGX: %s", reg_x(i[4:0], 1'b1));
+      end
+      $display("OP: %s", f2(5'd7));
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule