From 1e283875414265e39909b3d8a828989eb93106ff Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 2 Mar 2023 20:29:42 -0500
Subject: [PATCH] Tests: Add nettype test

---
 test_regress/t/t_nettype.out | 17 ++++++++++++
 test_regress/t/t_nettype.pl  | 19 ++++++++++++++
 test_regress/t/t_nettype.v   | 50 ++++++++++++++++++++++++++++++++++++
 3 files changed, 86 insertions(+)
 create mode 100644 test_regress/t/t_nettype.out
 create mode 100755 test_regress/t/t_nettype.pl
 create mode 100644 test_regress/t/t_nettype.v

diff --git a/test_regress/t/t_nettype.out b/test_regress/t/t_nettype.out
new file mode 100644
index 000000000..878eda2aa
--- /dev/null
+++ b/test_regress/t/t_nettype.out
@@ -0,0 +1,17 @@
+%Error-UNSUPPORTED: t/t_nettype.v:24:4: Unsupported: SystemVerilog 2012 reserved word not implemented: 'nettype'
+   24 |    nettype real real1_n with Pkg::resolver;
+      |    ^~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: t/t_nettype.v:24:25: syntax error, unexpected with, expecting ',' or ';'
+   24 |    nettype real real1_n with Pkg::resolver;
+      |                         ^~~~
+%Error-UNSUPPORTED: t/t_nettype.v:28:4: Unsupported: SystemVerilog 2012 reserved word not implemented: 'nettype'
+   28 |    nettype real real2_n with local_resolver;
+      |    ^~~~~~~
+%Error: t/t_nettype.v:28:25: syntax error, unexpected with, expecting ',' or ';'
+   28 |    nettype real real2_n with local_resolver;
+      |                         ^~~~
+%Error-UNSUPPORTED: t/t_nettype.v:33:4: Unsupported: SystemVerilog 2012 reserved word not implemented: 'nettype'
+   33 |    nettype real2_n real3_n;
+      |    ^~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_nettype.pl b/test_regress/t/t_nettype.pl
new file mode 100755
index 000000000..376c2d2ee
--- /dev/null
+++ b/test_regress/t/t_nettype.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_nettype.v b/test_regress/t/t_nettype.v
new file mode 100644
index 000000000..312a5960f
--- /dev/null
+++ b/test_regress/t/t_nettype.v
@@ -0,0 +1,50 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+package Pkg;
+   real last_resolve;
+
+   function automatic real resolver(input real drivers[]);
+      resolver = 0.0;
+      foreach (drivers[i]) resolver += drivers[i];
+      last_resolve = resolver;
+   endfunction
+endpackage
+
+module t(/*AUTOARG*/);
+
+   function automatic real local_resolver(input real drivers[]);
+      local_resolver = 0.0;
+      foreach (drivers[i]) local_resolver += drivers[i];
+   endfunction
+
+   nettype real real1_n with Pkg::resolver;
+   real1_n real1;
+   assign real1 = 1.23;
+
+   nettype real real2_n with local_resolver;
+   real2_n real2;
+   assign real2 = 1.23;
+
+   // Create alias using new name
+   nettype real2_n real3_n;
+   real3_n real3;
+   assign real3 = 1.23;
+
+   // TODO when implement net types need to check multiple driver cases, across
+   // submodules
+
+   initial begin
+      #10;
+      if (real1 != 1.23) $stop;
+      if (real2 != 1.23) $stop;
+      if (real3 != 1.23) $stop;
+      if (Pkg::last_resolve != 1.23) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule